CN109817715A - 半导体器件栅极间隔件结构及其方法 - Google Patents

半导体器件栅极间隔件结构及其方法 Download PDF

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CN109817715A
CN109817715A CN201810449654.0A CN201810449654A CN109817715A CN 109817715 A CN109817715 A CN 109817715A CN 201810449654 A CN201810449654 A CN 201810449654A CN 109817715 A CN109817715 A CN 109817715A
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side wall
layer
gate
substrate
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CN109817715B (zh
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黄国长
卢富鹏
刘峻昌
黄镇球
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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Abstract

一种半导体器件包括：衬底，具有沟道区；栅极堆叠件，位于沟道区上方；密封间隔件，覆盖栅极堆叠件的侧壁，密封间隔件包括氮化硅；栅极间隔件，覆盖密封间隔件的侧壁，栅极间隔件包括氧化硅，栅极间隔件具有第一垂直部分和第一水平部分；以及第一介电层，覆盖栅极间隔件的侧壁，第一介电层包括氮化硅。本发明的实施例还涉及半导体器件栅极间隔件结构及其方法。

Description

半导体器件栅极间隔件结构及其方法
技术领域
本发明的实施例涉及半导体器件栅极间隔件结构及其方法。
背景技术
半导体集成电路(IC)产业经历了指数式的发展。IC材料和设计的技术进步产生了多代IC，其中，每一代都具有比先前一代更小且更复杂的电路。在IC演进的过程中，功能密度(即，单位芯片面积中的互连器件的数量)通常已经增加，同时几何尺寸(即，可使用制造工艺创建的最小组件(或线))却已减小。这种按比例缩小通常通过增加生产效率和降低相关成本来提供很多益处。这种按比例缩小也增加了处理和制造IC的复杂性，并且为了实现这些进步，需要IC处理和制造的类似发展。
例如，为了增加开关速度、降低开关功率损耗和/或降低晶体管的耦合噪声，通常期望降低场效应晶体管的部件之间的寄生电容，诸如栅极结构与源极/漏极接触件之间的电容。已经提出了用作围绕栅极结构的绝缘材料的某些低k材料，以提供较低的介电常数(或相对介电常数)并降低寄生电容。然而，随着半导体技术发展至更小的几何结构，栅极结构与源极/漏极接触件之间的距离进一步减小，导致仍然存在大的寄生电容。因此，虽然晶体管形成的现有方法通常对于其预期目的已经足够，但它们不是在所有方面都完全令人满意。
发明内容
本发明的实施例提供了一种半导体器件，包括：衬底，具有沟道区；栅极堆叠件，位于所述沟道区上方；密封间隔件，覆盖所述栅极堆叠件的侧壁，所述密封间隔件包括氮化硅；栅极间隔件，覆盖所述密封间隔件的侧壁，所述栅极间隔件包括氧化硅，所述栅极间隔件具有第一垂直部分和第一水平部分；以及第一介电层，覆盖所述栅极间隔件的侧壁，所述第一介电层包括氮化硅。
本发明的另一实施例提供了一种半导体器件，包括：衬底，具有源极/漏极(S/D)区域和介于源极/漏极区域之间的沟道区；栅极堆叠件，位于所述沟道区上方；介电层，覆盖所述栅极堆叠件的侧壁，所述介电层包括氮化物；间隔件层，覆盖所述介电层的侧壁，所述间隔件层包括氧化物，其中，所述间隔件层的侧壁包括上侧壁、水平表面和下侧壁，从而形成台阶轮廓；以及接触蚀刻停止(CES)层，覆盖所述间隔件层的侧壁，所述接触蚀刻停止层包括氮化物。
本发明的又一实施例提供了一种形成半导体器件的方法，包括：在衬底上方形成栅极结构；形成覆盖所述栅极结构的密封间隔件；通过原子层沉积(ALD)工艺形成覆盖所述密封间隔件的栅极间隔件，所述栅极间隔件具有第一垂直部分和第一水平部分；形成覆盖所述栅极间隔件的硬掩模层，所述硬掩模层具有第二垂直部分和第二水平部分；去除所述硬掩模层的所述第二水平部分以及位于所述硬掩模层的所述第二水平部分下方的所述栅极间隔件的所述第一水平部分的一部分；以及形成覆盖栅极间隔件的接触蚀刻停止(CES)层。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A、图1B和图1C示出了根据本公开的各个方面的形成半导体器件的方法的流程图。
图2、图3、图4、图5、图6、图7、图8、图9、图10、图11、图12、图13、图14、图15、图16和图17是根据一些实施例的根据图1A、图1B和图1C的方法的制造工艺期间的半导体器件的一部分的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述符可以同样地作相应的解释。
本公开大体上涉及半导体器件及其形成方法。更具体地，本公开涉及提供低k栅极间隔件结构及其方法，以用于降低半导体制造中的场效应晶体管(FET)的栅极结构与源极/漏极接触件之间的寄生电容。当形成FET时，希望提高开关速度，降低开关功率损耗，并降低耦合噪声。寄生电容通常会对这些参数产生负面影响，特别是栅极结构和源极/漏极接触件之间的寄生电容。随着半导体技术发展至更小的几何结构，栅极与源极/漏极接触件之间的距离缩小，导致更大的寄生电容。因此，FET中的寄生电容更加成为问题。本公开提供了形成围绕栅极堆叠件(诸如多晶硅栅极或金属栅极)的低k栅极间隔件结构的解决方案。与通常由氮化硅(例如，Si3N4)制成的栅极间隔件相比，低k栅极间隔件结构降低了栅极堆叠件与源极/漏极接触件之间的介电常数(或相对介电常数)，从而降低了它们之间的寄生电容。此外，低k栅极间隔件结构有助于降低栅极堆叠件与源极/漏极区域之间的界面应力，从而改善沟道载流子迁移率。
图1A、图1B和图1C示出了根据本公开的形成半导体器件的方法100的流程图。方法100是一个示例，并不意在限定本公开超出权利要求明确记载的范围。可在方法100之前、期间和之后提供额外的操作，对于方法100的其他实施例，可将描述的一些步骤替换、去除或重排。下面结合图2至图16描述方法100，图2至图16示出了根据方法100的一些实施例的各个制造步骤期间的半导体器件200的截面图。
器件200可以是集成电路(IC)或IC的一部分的工艺期间制造的中间器件，器件200可以包括：静态随机存取存储器(SRAM)和/或逻辑电路，诸如电阻器、电容器和电感器的无源部件以及诸如p型FET(pFET)、n型FET(nFET)、FinFET、金属-氧化物半导体场效应晶体管(MOSFET)和互补金属-氧化物半导体(CMOS)晶体管的有源部件，双极晶体管，高压晶体管，高频晶体管，其他存储器单元以及它们的组合。此外，本公开的各个实施例提供的各个部件(包括晶体管、栅极堆叠件、有源区、隔离结构以及其他部件)是为了简明和容易理解，并不必然地将实施例限定于器件的任何类型、器件的任何数量、区域的任何数量，或者结构或区域的任何配置。
在操作102处，方法100(图1A)提供器件结构200(图2)。为了便于讨论，器件结构200也被称为器件200。器件200可以包括衬底202以及形成在衬底202中或衬底202上的各个部件。在示出的实施例中，衬底202是硅衬底。可选的，衬底202可以包括：诸如锗的另一种元素半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体，或它们的组合。另一可选的，衬底202是绝缘体上半导体(SOI)。在一些实施例中，衬底202包括用于形成FinFET的鳍状半导体区域(“鳍”)。可以通过任何合适的方法来图案化鳍。例如，可以使用包括双重图案化或多重图案化工艺的一种或多种光刻工艺来图案化鳍。通常，双重图案化或多重图案化工艺结合了光刻和自对准工艺，例如允许创建的图案具有比使用单一、直接光刻工艺获得的间距更小的间距。例如，在一个实施例中，在衬底202上形成牺牲层并使用光刻工艺图案化牺牲层。使用自对准工艺在图案化的牺牲层旁边形成间隔件。然后去除牺牲层，随后可使用剩余的间隔件或心轴来图案化衬底202以形成鳍。在一些实施例中，鳍可以包括一个或多个外延生长的半导体材料层。
在一些实施例中，衬底202包括绝缘体(或隔离结构)，绝缘体可以由氧化硅、氮化硅、氮氧化硅，氟掺杂硅酸盐玻璃(FSG)、低k介电材料和/或其它合适的绝缘材料形成。绝缘体可以是浅沟槽隔离(STI)部件。在一个实施例中，通过在衬底202中蚀刻沟槽(例如，以上讨论的鳍形成工艺的一部分)、用绝缘材料填充沟槽、并且对包括绝缘材料的衬底202执行化学机械抛光(CMP)工艺来形成绝缘体。衬底202可以包括诸如场氧化物和硅的局部氧化(LOCOS)的其他隔离结构。衬底202可以包括多层隔离结构。
在操作104处，方法100(图1A)在衬底202上形成栅极堆叠件208(图2)。在多个实施例中，栅极堆叠件208是多层结构。在一些实施例中，栅极堆叠件208是多晶硅栅极结构，多晶硅栅极结构包括具有氧化硅或氮氧化硅的界面层210和具有多晶硅的电极层212。相应地，在一些实施例中，形成栅极堆叠件208包括：通过化学氧化、热氧化、原子层沉积(ALD)、化学气相沉积(CVD)或其他合适的方法在衬底202上沉积界面层210；通过低压化学气相沉积(LPCVD)或其他合适的方法在界面层210上沉积电极层212；以及随后在光刻工艺中图案化界面层210和电极层212以形成栅极堆叠件208。栅极堆叠件208限定了位于其下方的衬底202中或衬底202的鳍中的沟道区215。在示出的实施例中，沟道区215具有约5nm至约180nm范围内的沟道长度D。
在一个具体的实施例中，方法100包括将在后面进一步详细描述的替换栅极工艺。在替换栅极工艺中，栅极堆叠件208是临时栅极结构。界面层210可以是具有氧化硅或氮氧化硅的临时界面层，电极层212可以是具有多晶硅的临时电极层。
操作104可以进一步包括形成覆盖器件200的密封间隔件层214。在示出的实施例中，密封间隔件层214作为毯状层沉积在栅极堆叠件208的顶部和侧壁上以及衬底202的顶面上。进一步的，对于示出的实施例，密封间隔件层214包括氮化硅(例如，Si3N4)，并且可以使用等离子体增强化学气相沉积(PECVD)、LPCVD、ALD或其他合适的方法来沉积密封间隔件层214。密封间隔件层214可以沉积为约0.5nm至约10nm的厚度，诸如约3nm。
在操作106处，方法100(图1A)对密封间隔件层214施加各向异性蚀刻工艺(图3)。各向异性蚀刻工艺设计为选择性地蚀刻密封间隔件层214，但不蚀刻衬底202。操作106从衬底202的顶面去除部分密封间隔件层214，从而暴露衬底202的顶面。由于高度地定向蚀刻，所以栅极堆叠件208的侧壁上的部分密封间隔件层214保持基本未被蚀刻。此外，通过这种各向异性蚀刻工艺，可以暴露或者可以不暴露栅极堆叠件208的顶面。在一个实施例中，其中，密封间隔件层214包括氮化硅，操作106可以采用远程O2/N2放电，远程O2/N2放电具有诸如CF4、NF3或SF6的含氟气体、并且可以另外包括氢气(H2)或CH4。选择性蚀刻密封间隔件层214的各种其他方法是可能的。为了简明，图案化的密封间隔件层214可以表示为密封间隔件214。在具体的实施例中，密封间隔件214与栅极堆叠件208的侧壁共形，并且具有邻近栅极堆叠件208底部的锥形轮廓。因此，可以认为密封间隔件214包括由于锥形轮廓而形成的水平部分214a和垂直部分214b。水平部分214a连接至垂直部分214b的底部并且在远离栅极堆叠件208的方向上横向地延伸。水平部分214a可以具有约0.5nm至约5nm的宽度(沿着X轴)，诸如约3nm。
在操作108处，方法100(图1A)通过执行离子注入工艺218在衬底202中形成轻掺杂源极/漏极(LDD)区域216(图4)。离子注入工艺218可以使用诸如磷(P)或砷(As)的用于NFET的n型掺杂剂、或者使用诸如硼(B)或铟(In)的用于PFET的p型掺杂剂。LDD区域216与栅极堆叠件208和密封间隔件214自对准。当LDD区域216经历离子注入工艺218时，可以使用掩模层(未示出)来覆盖衬底202的其他区域。在一些实施例中，掩模层是图案化的光刻胶。在一些实施例中，掩模层是诸如氧化硅、氮化硅、氮氧化硅或其组合的材料的图案化的硬掩模。当LDD区域216中的LDD注入完成之后，去除掩模层。在图4所示的实施例中，操作108在操作106之后执行。在可选的实施例中，操作108在操作106之前执行。
在操作110处，方法100(图1A)形成覆盖器件200的栅极间隔件层220(图5)。在示出的实施例中，栅极间隔件层220作为毯状层沉积在密封间隔件214的侧壁上、栅极堆叠件208的顶部上以及衬底202的顶面上。在一些器件中，使用氮化硅作为用于半导体制造中的栅极间隔件的材料。然而，氮化硅具有通常在6.8-8.3范围内(诸如约7.5)的相对高的介电常数，这导致栅极堆叠件与源极/漏极接触件和/或一些实例中的其他FET部件之间的高寄生电容。为了降低寄生电容，需要使用除氮化硅之外的介电常数相对低的材料作为栅极间隔件。在一个实施例中，栅极间隔件层220包括氧化硅(例如，SiO2)。氧化硅具有比氮化硅低的通常在3.4-4.2的范围内(诸如约3.9)的介电常数。在一些实施例中，沉积栅极间隔件层220包括引入发生反应的含硅化合物和含氧化合物以形成介电材料。栅极间隔件层220可以包括未掺杂硅酸盐玻璃(USG)、氟化物掺杂硅酸盐玻璃(FSG)、磷硅酸盐玻璃(PSG)或硼磷硅酸盐玻璃(BPSG)。在另一个实施例中，栅极间隔件层220包括氧化锗(例如，GeO2)。可以通过包括PECVD、LPCVD和ALD的任何合适的技术形成栅极间隔件层220。在示出的实施例中，栅极间隔件层220包括二氧化硅，并且通过诸如ALD工艺的共形沉积技术来沉积栅极间隔件层220。可以沉积栅极间隔件层220至厚度T1，T1在沟道区215的长度D的大约10％至大约70％的比率内。在一些实施例中，厚度T1在约3nm至约20nm的范围内，诸如约5nm。
在操作112处，方法100(图1A)形成覆盖栅极间隔件层220的硬掩模层224(图6)。硬掩模层224可以包括介电材料，诸如氮化硅、氧化硅、氮氧化硅、碳氮化硅、碳氧氮化硅、其他介电材料或它们的组合。对硬掩模层224的组成进行选择，使得硬掩模层224相对于栅极间隔件层220具有一些蚀刻选择性。在一些实施例中，硬掩模层224包括氮化硅(例如，Si3N4)。可以通过包括PECVD、LPCVD和ALD的任何合适的技术形成硬掩模层224。在示出的实施例中，通过LPCVD工艺沉积硬掩模层224。可以沉积硬掩模层224至厚度T2，T2在沟道区215的长度D的约10％至约70％的比率内。在一些实施例中，厚度T2在约3nm至约20nm的范围内，诸如约4nm。在一些实施例中，硬掩模层224比栅极间隔件层220更薄(T2<T1)，诸如薄多达1nm。
在操作114处，方法100(图1A)对硬掩模层224和栅极间隔件层220应用蚀刻工艺(图7)。在一个实施例中，蚀刻工艺包括各向异性蚀刻。如图7所示，由于高度地定向蚀刻，所以栅极间隔件层220的侧壁上的部分硬掩模层224保持基本未被蚀刻。在一个实施例中，其中，硬掩模层224包括氮化硅，操作114可以采用远程O2/N2放电，远程O2/N2放电具有诸如CF4、NF3或SF6的含氟气体、并且可以另外包括氢气(H2)或CH4。各向异性蚀刻可以进一步蚀刻在去除部分硬掩模层224之后暴露的栅极间隔件层220。可选地，蚀刻工艺可以包括具有不同蚀刻化学组成的多个蚀刻步骤，诸如以硬掩模层224的具体材料为目标的各向异性蚀刻、以及随后的以栅极间隔物层220为目标并且用未蚀刻的硬掩模层224作为蚀刻掩模的湿蚀刻或干蚀刻。通过这样的蚀刻工艺，可以暴露或者可以不暴露栅极堆叠件208的顶面。
仍然参考图7，为了简明，图案化的栅极间隔件层220可以表示为栅极间隔件220，同时图案化的硬掩模层224可以表示为硬掩模224。栅极间隔件220包括直接位于硬掩模224下方的水平部分220a和覆盖密封间隔件214的侧壁的垂直部分220b。垂直部分220b包括侧壁225。硬掩模224覆盖侧壁225。在一些实施例中，侧壁225基本上垂直于(即，沿着Z轴)衬底202的顶面。水平部分220a包括顶面226和侧壁228。侧壁228可以基本上垂直于(即，沿着Z轴)衬底202的顶面。侧壁225、顶面226和侧壁228形成台阶轮廓。硬掩模224直接设置在顶面226上。在一个实施例中，硬掩模224完全覆盖顶面226。在另一个实施例中，诸如由于操作114期间的硬掩模224的较高的侧壁蚀刻损失，使得硬掩模224比水平部分220a的宽度W1更薄(T2<W1)。因此，暴露出与侧壁228相邻的顶面226的一部分，并且顶面226的一部分沿着X轴可具有约0.5nm至约2nm的宽度。顶面226与侧壁225相交，在顶面226和侧壁225之间形成角度θ。在一些实施例中，角度θ在约85度至约95度的范围内，并且可以认为顶面226基本上垂直于侧壁225。在各个实施例中，水平部分220a的高度H1在沟道区215的长度D的约10％至约70％的比率内。在具体的实施例中，高度H1与垂直部分220b的厚度T1相同(H1＝T1)。在一个实施例中，高度H1与垂直部分220b的厚度T1不同(H1≠T1)，诸如H1比厚度T1小或大1nm。水平部分220a的最高点可以高于密封间隔件214的水平部分214a的最高点。
在操作118处，方法100(图1B)在衬底202中形成重掺杂源极/漏极(HDD)区域230(图8)。HDD区域230可以是用于形成有源器件的n型掺杂区域和/或p型掺杂区域。HDD区域230和LDD区域216共同视为源极/漏极(S/D)区域。HDD区域230比LDD区域216更加重掺杂。可以通过执行离子注入工艺232形成HDD区域230。离子注入工艺232可以使用诸如磷(P)或砷(As)的用于NFET的n型掺杂剂，或使用诸如硼(B)或铟(In)的用于PFET的p型掺杂剂。HDD区域230与栅极堆叠件208和栅极间隔件220自对准。当HDD区域230经历离子注入工艺232时，可以使用掩模层(未示出)覆盖衬底202的其他区域。在一些实施例中，掩模层是图案化的光刻胶。在一些实施例中，掩模层是诸如氧化硅、氮化硅、氮氧化硅或其组合的材料的图案化的硬掩模。当HDD区域230中的HDD注入完成后，去除掩模层。
形成HDD区域230还可以包括首先在衬底202中蚀刻S/D凹槽，然后在各个凹槽中外延生长HDD区域230。在一些实施例中，其中，栅极堆叠件208和栅极间隔件220比期望的更厚，HDD区域230可以形成为具有基本上菱形的轮廓，诸如图9中的HDD区域230。参考图9，HDD区域230的一些侧壁在栅极间隔件220的下方(诸如在垂直部分220b下方)向栅极堆叠件208延伸。在一个实例中，HDD区域230进一步在密封间隔件214的水平部分214a下延伸，但不在其垂直部分214b下延伸。在另一个实例中，HDD区域230进一步在栅极堆叠件208下延伸。在一个实例中，使用包括干刻蚀和湿刻蚀工艺的蚀刻工艺形成S/D凹槽，其中，对蚀刻参数(诸如使用的蚀刻剂、蚀刻温度、蚀刻溶液浓度、蚀刻压力、源功率、射频(RF)偏置电压、RF偏置功率，蚀刻剂流量和其他合适的参数)进行调整以实现期望的凹陷轮廓。HDD区域230可以包括顶面上的自对准硅化物部分231。部分硅化物部分231可以由栅极间隔件220的水平部分220a和/或垂直部分220b覆盖。由于硅化物部分231的升高的高度，所以水平部分220a的底面可以高于垂直部分220b的底面。为了便于讨论，具有图8所示形状的HDD区域的器件200用作后续操作的示例。本领域的普通技术人员应该认识到，具有图9所示形状的HDD区域的器件200也可以用于后续的操作。
回到图8所示，在一个实施例中，HDD区域230还包括硅化或硅锗化(未示出)。例如，硅化可以通过包括沉积金属层、退火金属层使得金属层与硅反应以形成硅化物、然后除去未反应的金属层的工艺来形成。操作118还可以包括一个或多个退火工艺以激活S/D区域。在激活之后，LDD区域216可以在密封间隔件214下朝向栅极堆叠件208延伸，并且HDD区域230可以部分地在栅极间隔件220的水平部分220a下延伸。换句话说，密封间隔件214和栅极间隔件220的垂直部分220b可以与LDD区域216物理接触，并且栅极间隔件220的水平部分220a可以与LDD区域216和HDD区域230都物理接触。栅极间隔件220的材料组成的低介电常数有助于减小栅极堆叠件与源极/漏极区域之间的界面应力，从而改善沟道载流子迁移率。在一个实施例中，器件200包括用于形成多栅极FET(诸如FinFET)的鳍状有源区。进一步地，在这样的实施例中，S/D区域和沟道区215可以形成在鳍内或者鳍上。沟道区215位于栅极堆叠件208下方并且介于一对LDD区域216之间。当半导体器件200导通(诸如通过偏置栅电极层212)时，沟道区215在各个S/D区域之间传导电流。
在操作120处，方法100(图1B)形成覆盖器件200的接触蚀刻停止(CES)层246(图10)。在示出的实施例中，CES层246作为毯状层沉积在栅极间隔件220、硬掩模224、密封间隔件214、栅极堆叠件208的侧壁和顶部上、以及HDD区域230的顶面上。CES层246可以包括介电材料，诸如氮化硅、氧化硅、氮氧化硅、碳氮化硅、碳氮氧化硅、其它介电材料或它们的组合。可以通过等离子体增强CVD(PECVD)工艺和/或其他合适的沉积或氧化工艺形成CES层246。在示出的实施例中，硬掩模224和CES层246都包括氮化硅(例如，Si3N4)，同时通过LPCVD形成硬掩模224并通过PECVD形成CES层246，因此硬掩模224和CES层246中的氮化硅材料具有不同的晶体结构(例如，不同的晶格常数)。在一个具体的实施例中，由于CES层246下的水平部分220a和硬掩模224的侧壁轮廓，所以CES层246沿着其垂直侧壁具有台阶轮廓248。
在操作122处，方法100(图1B)在CES层246上形成层间介电质(ILD)层252(图11)。ILD层252可以包括诸如氧化硅、掺杂氧化硅(诸如硼磷硅酸盐玻璃(BPSG)、原硅酸四乙酯(TEOS)氧化物、未掺杂硅酸盐玻璃、熔凝石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂硅玻璃(BSG))的材料、低k介电材料和/或其他合适的介电材料。可以通过PECVD工艺、可流动CVD(FCVD)工艺或其他合适的沉积技术沉积ILD层252。对CES层246和ILD层252的组成进行选择，使得CES层246相对于ILD层252具有一些蚀刻选择性。
在操作124处，方法100(图1B)执行一个或多个化学机械抛光(CMP)工艺来抛光ILD层252以暴露栅极堆叠件208(图12)。在一些实施例中，如虚线253所示，诸如由于相对较低的材料密度，所以在抛光期间ILD层252比栅极堆叠件208具有更高的表面损失，且ILD层252的顶面具有凹面轮廓。ILD层252的顶面的最底部可以比栅极堆叠件208的顶面低约0.1nm至约25nm的范围内。
在操作126处，为了完成器件200的制造，方法100(图1B)继续进行进一步处理。例如，方法100可以在替换栅极工艺中形成金属栅极堆叠件。
在替换栅极工艺中，栅极堆叠件208是临时栅极结构。可以通过沉积和蚀刻工艺形成临时栅极结构。随后，操作126去除临时栅极结构以在密封间隔件214之间形成栅极沟槽(未示出)，并在栅极沟槽中沉积高k金属栅极堆叠件290(图13)。高k金属栅极堆叠件290可以包括高k介电层292和位于高k介电层292上的导电层294。高k金属栅极堆叠件290可以进一步包括位于高k介电层292和沟道区215之间的界面层(例如SiO2)(未示出)。可以使用化学氧化、热氧化、ALD、CVD和/或其他合适的方法形成界面层。
高k介电层292可以包括一种或多种高k介电材料(或者一个或多个高k介电材料层)，诸如氧化铪硅(HfSiO)、氧化铪(HfO2)、氧化铝(Al2O3)、氧化锆(ZrO2)、氧化镧(La2O3)、氧化钛(TiO2)、氧化钇(Y2O3)、钛酸锶(SrTiO3)或它们的组合。可以使用CVD、ALD和/或其他合适的方法来沉积高k介电层292。
导电层294可以包括诸如功函数金属层、导电阻挡层和金属填充层的一个或多个金属层。根据晶体管的类型(p型或n型)，功函数金属层可以是p型或n型功函数层。p型功函数层包括但不限于选自氮化钛(TiN)、氮化钽(TaN)、钌(Ru)、钼(Mo)、钨(W)、铂(Pt)、或它们的组合的金属。n型功函数层包括但不限于选自钛(Ti)、铝(Al)、碳化钽(TaC)、碳氮化钽(TaCN)、氮化钽硅(TaSiN)、氮化钛硅(TiSiN)或它们的组合的金属。金属填充层可以包括铝(Al)、钨(W)、钴(Co)和/或其他合适的材料。可以使用诸如CVD、PVD、镀和/或其他合适的工艺的方法来沉积导电层294。
为了完成器件200的制造，操作126可以包括其他的处理。例如，操作126可以形成S/D接触件(未示出)并形成多层互连结构，多层互连结构将栅极堆叠件和S/D接触件与器件200的其他部分连接以形成完整的IC。
方法100可以具有多个实施例。例如，如图14所示，方法100可以在操作114和操作118之间具有可选的操作116(图1C)，以从栅极间隔件220的侧壁去除硬掩模224。在示出的实施例中，硬掩模224包括氮化硅，氮化硅具有比栅极间隔件220的材料组成更高的介电常数。通过去除硬掩模224，进一步减小了栅极堆叠件208和源极/漏极接触件(未示出)之间的绝缘材料的整体介电常数，结果FET部件之间的寄生电容更低。
去除硬掩模224可以包括任何合适的蚀刻技术，诸如湿蚀刻、干蚀刻、RIE、灰化和/或其他的蚀刻工艺。在一些实施例中，对蚀刻剂进行选择，使得硬掩模224和栅极间隔件220具有高蚀刻选择性。例如，硬掩模224和栅极间隔件220之间的蚀刻选择性具有约5:1或更大的比值，诸如5:1至20:1的范围。蚀刻工艺还可以修整栅极间隔件220的水平部分220a的轮廓。在一个实施例中，顶面226缩短至沟道区215的长度D的约3％至约30％的比率，诸如约1nm至约8nm(例如，2nm)，并且相对于侧壁225，侧壁228以小于45度的角度β(诸如约20度)变得锥化。如图15所示，为了形成装置200的其他部件，方法100可以随后进行如上的操作118、操作120、操作122、操作124和操作126，包括：使用修整的栅极间隔件220作为掩模来形成HDD区域230、直接在修整的栅极间隔件220的侧壁上沉积CES层246、以及在器件200上形成ILD层252。如图16所示，在另一个实施例中，操作116(图1C)修整去掉水平部分220a的顶面226，使得侧壁228以小于45度的角度β(诸如约20度)直接与侧壁225相交。如图17所示，为了形成设备200的其他部件，方法100可以随后进行到操作118、操作120、操作122、操作124和操作126，为了简明此处不再重复。
虽然不旨在进行限定，但本公开的一个或多个实施例为包括鳍式场效应晶体管(FinFET)的半导体器件及其形成提供了许多益处。例如，上述公开内容非常适合于，可对鳍进行图案化以在部件之间产生相对紧密的间隔。根据以上的公开，可以对用于形成FinFET的鳍的栅极间隔件进行处理。例如，本公开的实施例提供了一种形成围绕栅极堆叠件的低k栅极间隔件的方法。降低了栅极堆叠件与源极/漏极接触件之间的隔离材料的介电常数，这降低了互连件之间的干扰、噪声和寄生耦合电容。另外，低k栅极间隔件结构有助于降低栅极堆叠件与源极/漏极区域之间的界面应力，从而改善沟道载流子迁移率。此外，所公开的方法可以容易地集成到现有的半导体制造工艺中。
在一个示例性的方面，本公开涉及一种半导体器件。在一个实施例中，半导体器件包括：衬底，具有沟道区；栅极堆叠件，位于沟道区上方；密封间隔件，覆盖栅极堆叠件的侧壁，密封间隔件包括氮化硅；栅极间隔件，覆盖密封间隔件的侧壁，栅极间隔件包括氧化硅，栅极间隔件具有第一垂直部分和第一水平部分；以及第一介电层，覆盖栅极间隔件的侧壁，第一介电层包括氮化硅。在一个实施例中，密封间隔件包括第二垂直部分和第二水平部分；以及第一介电层包括第三垂直部分和第三水平部分。在一个实施例中，第一水平部分、第二水平部分和第三水平部分中的每一个与衬底的顶面物理接触。在一个实施例中，第二水平部分的最高点低于第一水平部分的最高点。在一个实施例中，衬底具有源极/漏极(S/D)区域，S/D区域具有与沟道区相邻的第一掺杂S/D区域和与第一掺杂S/D区域相邻的第二掺杂S/D区域，其中，第二掺杂S/D区域比第一掺杂S/D区域更重掺杂；第一垂直部分从第二掺杂S/D区域偏移并且与第一掺杂S/D区域物理接触；以及第一水平部分与第一掺杂S/D区域和第二掺杂S/D区域均物理接触。在一个实施例中，第一水平部分的高度与第一垂直部分的宽度基本相同。在一个实施例中，第一垂直部分具有第一侧壁，第一侧壁基本上垂直于衬底的顶面；以及第一水平部分具有第二侧壁，第二侧壁与第一侧壁以小于45度的角度相交。在一个实施例中，第一垂直部分具有第一侧壁，第一侧壁基本上垂直于衬底的顶面；以及第一水平部分具有第二侧壁以及介于第一侧壁和第二侧壁之间的第一顶面，第一顶面基本上垂直于第一侧壁。在一个实施例中，半导体器件还包括：介于栅极间隔件与第一介电层之间的第二介电层，第二介电层位于第一水平部分上方，第二介电层与栅极间隔件具有不同的材料组成。在一个实施例中，第二介电质层部分地覆盖第一顶面。在一个实施例中，第二侧壁基本上垂直于衬底的顶面。在一个实施例中，栅极堆叠件包括多晶硅栅极或金属栅极。
在另一个示例性的方面，本公开涉及一种半导体器件。在一个实施例中，半导体器件包括：衬底，具有源极/漏极(S/D)区域和介于S/D区域之间的沟道区；栅极堆叠件，位于沟道区上方；介电层，覆盖栅极堆叠件的侧壁，介电层包括氮化物；间隔件层，覆盖介电层的侧壁，间隔件层包括氧化物，其中，间隔件层的侧壁包括上侧壁、水平表面和下侧壁，从而形成台阶轮廓；以及接触蚀刻停止(CES)层，覆盖间隔件层的侧壁，CES层包括氮化物。在一个实施例中，上侧壁与水平表面相交，限定上侧壁与水平表面之间的角度，角度在85度至95度的范围内。在一个实施例中，半导体器件还包括：硬掩模层，设置在间隔件层与CES层之间，硬掩模层的介电常数高于间隔件层的介电常数。在一个实施例中，S/D区域包括第一掺杂S/D区域以及比第一掺杂S/D区域更重掺杂的第二掺杂S/D区域，其中，上侧壁直接位于第一掺杂S/D区域上方，并且下侧壁直接位于第二掺杂S/D区域上方。在一个实施例中，间隔件层的厚度在沟道区的长度的10％至70％的范围内。
在一个示例性的方面，本公开涉及一种方法。在一个实施例中，方法包括：在衬底上方形成栅极结构；形成覆盖栅极结构的密封间隔件；通过原子层沉积(ALD)工艺形成覆盖密封间隔件的栅极间隔件，栅极间隔件具有第一垂直部分和第一水平部分；形成覆盖栅极间隔件的硬掩模层，硬掩模层具有第二垂直部分和第二水平部分；去除硬掩模层的第二水平部分以及位于硬掩模层的第二水平部分下方的栅极间隔件的第一水平部分的一部分；以及形成覆盖栅极间隔件的接触蚀刻停止(CES)层。在一个实施例中，方法还包括：在形成CES层之前，去除硬掩模层的第二垂直部分。在一个实施例中，在密封间隔件、栅极间隔件、硬掩模层、以及CES层的组中，栅极间隔件具有最低的介电常数。在一个实施例中，密封间隔件包括氮化硅；栅极间隔件包括氧化硅；以及CES层包括氮化硅。在一个实施例中，方法还包括在形成密封间隔件之后并且在形成栅极间隔件之前，通过离子注入工艺形成第一源极/漏极区域；并且在去除硬掩模层的第二水平部分之后以及在形成CES层之前，形成与第一源极/漏极区域相邻的第二源极/漏极区域，其中，第二源极/漏极区域比第一源极/漏极区更重掺杂。在一个实施例中，栅极结构是多晶硅栅极结构或金属栅极结构。
上面论述了若干实施例的部件，使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种半导体器件，包括：
衬底，具有沟道区；
栅极堆叠件，位于所述沟道区上方；
密封间隔件，覆盖所述栅极堆叠件的侧壁，所述密封间隔件包括氮化硅；
栅极间隔件，覆盖所述密封间隔件的侧壁，所述栅极间隔件包括氧化硅，所述栅极间隔件具有第一垂直部分和第一水平部分；以及
第一介电层，覆盖所述栅极间隔件的侧壁，所述第一介电层包括氮化硅。
2.根据权利要求1所述的半导体器件，其中，
所述密封间隔件包括第二垂直部分和第二水平部分；以及
所述第一介电层包括第三垂直部分和第三水平部分。
3.根据权利要求2所述的半导体器件，其中，所述第一水平部分、所述第二水平部分和所述第三水平部分中的每一个均与所述衬底的顶面物理接触。
4.根据权利要求2所述的半导体器件，其中，所述第二水平部分的最高点低于所述第一水平部分的最高点。
5.根据权利要求1所述的半导体器件，其中：
所述衬底具有源极/漏极(S/D)区域，所述源极/漏极区域具有与所述沟道区相邻的第一掺杂源极/漏极区域和与所述第一掺杂源极/漏极区域相邻的第二掺杂源极/漏极区域，其中，所述第二掺杂源极/漏极区域比所述第一掺杂源极/漏极区域更重掺杂；
所述第一垂直部分从所述第二掺杂源极/漏极区域偏移并且与所述第一掺杂源极/漏极区域物理接触；以及
所述第一水平部分与所述第一掺杂源极/漏极区域和所述第二掺杂源极/漏极区域均物理接触。
6.根据权利要求1所述的半导体器件，其中，所述第一水平部分的高度与所述第一垂直部分的宽度相同。
7.根据权利要求1所述的半导体器件，其中：
所述第一垂直部分具有第一侧壁，所述第一侧壁垂直于所述衬底的顶面；以及
所述第一水平部分具有第二侧壁，所述第二侧壁与所述第一侧壁以小于45度的角度相交。
8.根据权利要求1所述的半导体器件，其中：
所述第一垂直部分具有第一侧壁，所述第一侧壁垂直于所述衬底的顶面；以及
所述第一水平部分具有第二侧壁以及介于所述第一侧壁和所述第二侧壁之间的第一顶面，所述第一顶面垂直于所述第一侧壁。
9.一种半导体器件，包括：
衬底，具有源极/漏极(S/D)区域和介于源极/漏极区域之间的沟道区；
栅极堆叠件，位于所述沟道区上方；
介电层，覆盖所述栅极堆叠件的侧壁，所述介电层包括氮化物；
间隔件层，覆盖所述介电层的侧壁，所述间隔件层包括氧化物，其中，所述间隔件层的侧壁包括上侧壁、水平表面和下侧壁，从而形成台阶轮廓；以及接触蚀刻停止(CES)层，覆盖所述间隔件层的侧壁，所述接触蚀刻停止层包括氮化物。
10.一种形成半导体器件的方法，包括：
在衬底上方形成栅极结构；
形成覆盖所述栅极结构的密封间隔件；
通过原子层沉积(ALD)工艺形成覆盖所述密封间隔件的栅极间隔件，所述栅极间隔件具有第一垂直部分和第一水平部分；
形成覆盖所述栅极间隔件的硬掩模层，所述硬掩模层具有第二垂直部分和第二水平部分；
去除所述硬掩模层的所述第二水平部分以及位于所述硬掩模层的所述第二水平部分下方的所述栅极间隔件的所述第一水平部分的一部分；以及
形成覆盖栅极间隔件的接触蚀刻停止(CES)层。
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