TW201911513A - 內連線結構的製造方法 - Google Patents
內連線結構的製造方法 Download PDFInfo
- Publication number
- TW201911513A TW201911513A TW106127797A TW106127797A TW201911513A TW 201911513 A TW201911513 A TW 201911513A TW 106127797 A TW106127797 A TW 106127797A TW 106127797 A TW106127797 A TW 106127797A TW 201911513 A TW201911513 A TW 201911513A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- interconnect structure
- manufacturing
- forming
- metal
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 72
- 229910052751 metal Inorganic materials 0.000 claims abstract description 64
- 239000002184 metal Substances 0.000 claims abstract description 64
- 230000004888 barrier function Effects 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims description 26
- 229910052732 germanium Inorganic materials 0.000 claims description 21
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 21
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 claims description 19
- 239000004020 conductor Substances 0.000 claims description 13
- 238000005240 physical vapour deposition Methods 0.000 claims description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 6
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- IAOQICOCWPKKMH-UHFFFAOYSA-N dithieno[3,2-a:3',2'-d]thiophene Chemical compound C1=CSC2=C1C(C=CS1)=C1S2 IAOQICOCWPKKMH-UHFFFAOYSA-N 0.000 claims description 4
- NZIHMSYSZRFUQJ-UHFFFAOYSA-N 6-chloro-1h-benzimidazole-2-carboxylic acid Chemical compound C1=C(Cl)C=C2NC(C(=O)O)=NC2=C1 NZIHMSYSZRFUQJ-UHFFFAOYSA-N 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- CXXKWLMXEDWEJW-UHFFFAOYSA-N tellanylidenecobalt Chemical compound [Te]=[Co] CXXKWLMXEDWEJW-UHFFFAOYSA-N 0.000 claims description 3
- 238000005496 tempering Methods 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052710 silicon Inorganic materials 0.000 abstract 4
- 239000010703 silicon Substances 0.000 abstract 4
- 229910021332 silicide Inorganic materials 0.000 abstract 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 6
- 229910052707 ruthenium Inorganic materials 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 229910052715 tantalum Inorganic materials 0.000 description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 229910001507 metal halide Inorganic materials 0.000 description 2
- 150000005309 metal halides Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 150000002978 peroxides Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- -1 titanium hydride Chemical compound 0.000 description 1
- 229910000048 titanium hydride Inorganic materials 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
一種內連線結構的製造方法,包括以下步驟。在矽層上形成介電層,其中在介電層中具有暴露出矽層的開口。在開口的表面上形成金屬層。在金屬層上形成應力調整層。進行熱製程,使金屬層與矽層反應,而在矽層上形成金屬矽化物層。在進行熱製程之後,移除應力調整層。在開口的表面上形成阻障層。
Description
本發明是有關於一種半導體結構的製造方法,且特別是有關於一種內連線結構的製造方法。
隨著半導體元件積集度的增加,半導體元件的圖案與線寬亦逐漸縮小,因而導致半導體元件中的電極與內連線之間的接觸電阻增高,產生較大的電阻-電容延遲(RC Delay),進而影響半導體元件的操作速度。
由於金屬矽化物的電阻較低,所以藉由金屬矽化物能夠降低半導體元件中的電極與內連線之間的接觸電阻。
然而,如何進一步地降低金屬矽化物的接觸電阻為目前業界持續努力的目標。
本發明提出一種內連線結構的製造方法,其可使得金屬矽化物層具有較低的接觸電阻與較高的導通電流(Ion
)。
本發明提供一種內連線結構的製造方法,包括以下步驟。在矽層上形成介電層,其中在介電層中具有暴露出矽層的開口。在開口的表面上形成金屬層。在金屬層上形成應力調整層。進行熱製程,使金屬層與矽層反應,而在矽層上形成金屬矽化物層。在進行熱製程之後,移除應力調整層。在開口的表面上形成阻障層。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,應力調整層與阻障層例如是使用不同沉積方法所形成。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,矽層例如是矽基底或磊晶矽層。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,介電層的形成方法例如是化學氣相沉積法(CVD)。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,金屬層的材料例如是鈦(Ti)、鎳(Ni)或鈷(Co)。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,金屬層的形成方法例如是物理氣相沉積法(PVD)或化學氣相沉積法。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,應力調整層的材料例如是氮化鈦(TiN)、氮化矽(SiN)或其組合。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,應力調整層的形成方法例如是射頻物理氣相沉積法(radio frequency physical vapor deposition,RF-PVD)。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,應力調整層的應力可藉由設定沉積機台的可變電容值來進行調整。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,應力調整層更可填滿開口。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,熱製程例如是回火製程。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,金屬矽化物層的材料例如是矽化鈦(TiSi)、矽化鎳(NiSi)或矽化鈷(CoSi)。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,更包括在移除應力調整層時,可同時移除未與矽層反應的金屬層。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,應力調整層的移除方法例如是濕式蝕刻法。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,濕式蝕刻法的蝕刻劑例如是稀釋氫氟酸(diluted hydrofluoric acid,DHF)或是硫酸與過氧化氫的混合溶液(sulfuric peroxide mixture,SPM)。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,阻障層的材料例如是氮化鈦(TiN)。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,阻障層的形成方法例如是化學氣相沉積法或原子層沉積法(atomic layer deposition,ALD)。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,更可包括在阻障層上形成填滿開口的導體層。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,導體層的材料例如是鎢(W)。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,導體層的形成方法例如是物理氣相沉積法。
基於上述,在本發明所提出的內連線結構的製造方法中,由於在金屬層上形成應力調整層,且在進行熱製程之後,移除應力調整層,所以可藉由應力調整層的應力來調整層調整基底的應力,而使得所形成的金屬矽化物層的厚度增加。如此一來,金屬矽化物層可具有較低的接觸電阻與較高的導通電流。
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
圖1本發明一實施例的內連線結構的製造流程圖。圖2A至圖2F為本發明一實施例的內連線結構的製造流程剖面圖。
請參照圖1與圖2A,進行步驟S100,在矽層100上形成介電層102,其中在介電層102中具有暴露出矽層100的開口104。矽層100例如是矽基底或磊晶矽層。在此實施例中,矽層100是以矽基底為例來進行說明,但本發明並不以此為限。在其他實施例中,矽層100亦可為其他含矽膜層,如磊晶矽層。然而,只要是矽層100的材料可與後續形成於其上的金屬層106反應而形成金屬矽化物層110(圖1C)即屬於本發明的所主張的範圍。
介電層102的材料例如是氧化矽。介電層102的形成方法例如是化學氣相沉積法。開口104的形成方法例如是對介電層102進行圖案化。
接著,進行步驟S102,在開口104的表面上形成金屬層106。金屬層106的材料例如是鈦、鎳或鈷。在此實施例中,金屬層106的材料是以鈦為例來進行說明,但本發明並不以此為限。然而,只要是金屬層106的材料可與矽層100反應而形成金屬矽化物層110(圖1C)即屬於本發明的所主張的範圍。金屬層106的形成方法例如是物理氣相沉積法或化學氣相沉積法。
然後,請參照圖1與圖2B,進行步驟S104,在金屬層106上形成應力調整層108。此外,應力調整層108更可填滿開口104。應力調整層108的材料例如是氮化鈦、氮化矽或其組合。在此實施例中,應力調整層108的材料是以氮化鈦為例來進行說明,但本發明並不以此為限。應力調整層108的形成方法例如是射頻物理氣相沉積法。
另一方面,可藉由應力調整層108的應力來調整層調整基底100的應力,而使得後續所形成的金屬矽化物110(圖1C)的厚度增加,以降低接觸電阻。應力調整層108的應力可藉由設定沉積機台的可變電容值來進行調整。
此外,應力調整層108可防止因金屬層106被氧化而導致黏著性變差的情況產生,進而可防止後續形成的阻障層112(圖1E)或導體層114(圖1F)在如化學機械研磨製程等製程中產生剝落,且可延長製程等待時間(queue time,Q-time),以降低缺陷。
請參照圖1與圖2C,進行步驟S106,進行熱製程,使金屬層106與矽層100反應,而在矽層100上形成金屬矽化物層110。熱製程例如是回火製程。金屬矽化物層110可使用自對準金屬矽化物製程來形成。金屬矽化物層110的材料例如是矽化鈦、矽化鎳或矽化鈷。在此實施例中,金屬矽化物層110的材料是以矽化鈦為例來進行說明,但本發明並不以此為限。
舉例來說,當金屬層106的材料為鈦且與矽層100反應時,可形成材料為矽化鈦的金屬矽化物層110。此時,當應力調整層108的材料為氮化鈦時,可將應力調整層108的應力調整為適於形成具有較大厚度的金屬矽化物層110的應力,例如可將應力調整層108調整為具有較大的壓縮應力。
請參照圖1與圖2D,進行步驟S108,在進行熱製程之後,移除應力調整層108。應力調整層108的移除方法例如是濕式蝕刻法。濕式蝕刻法的蝕刻劑例如是稀釋氫氟酸(DHF)或是硫酸與過氧化氫的混合溶液(SPM)。
此外,在移除應力調整層108時,可同時移除未與矽層100反應的金屬層106。藉由移除未與矽層100反應的金屬層106,可防止因金屬層106被氧化而導致黏著性變差的情況產生。
另一方面,由於金屬層106可在此步驟中被移除,因此可將金屬層106形成為具有較大的厚度,而有助於形成具有較大厚度的金屬矽化物層110。在另一實施例中,在金屬層106具有較大的厚度的情況下,金屬層106可能會對開口104進行封口。
請參照圖1與圖2E,進行步驟S110,在開口104的表面上形成阻障層112。阻障層112的材料例如是氮化鈦。在此實施例中,當應力調整層108與阻障層112的材料同為氮化鈦的情況下,應力調整層108的壓縮應力例如是大於阻障層112的壓縮應力。應力調整層108與阻障層112例如是使用不同沉積方法所形成。舉例來說,應力調整層108的形成方法例如是射頻物理氣相沉積法,而阻障層112的形成方法例如是化學氣相沉積法或原子層沉積法(ALD)。
通常,在形成材料為氮化鈦的阻障層112之後,會對阻障層112進行氮氣處理(N2
treatment),以除去雜質。在本實施例中,由於在對阻障層112進行氮氣處理之前,就已經先形成金屬矽化物層110,因此金屬矽化物層110的形成並不會受到氮氣處理的影響,而可具有較大的厚度。
請參照圖1與圖2F,進行步驟S112,可在阻障層112上形成填滿開口104的導體層114。導體層114的材料例如是鎢。導體層114的形成方法例如是物理氣相沉積法。
在此實施例中,由於金屬層106可被移除,因此在開口104中形成導體層114時,在開口104中並不存在金屬層106,且更不會有金屬層106於開口104的頂部形成懸突(overhang)的情況,因此可有效地提高導體層114填入開口104時的溝填裕度(gap fill window)。
基於上述,在上述內連線結構的製造方法中,由於在金屬層106上形成應力調整層108,且在進行熱製程之後,移除應力調整層108,所以可藉由應力調整層108的應力來調整層調整基底100的應力,而使得所形成的金屬矽化物層110的厚度增加。如此一來,金屬矽化物層110可具有較低的接觸電阻與較高的導通電流。
綜上所述,在上述實施例所提出的內連線結構的製造方法中,可藉由應力調整層的製程,使得所形成的金屬矽化物層具有較低的接觸電阻與較高的導通電流。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100‧‧‧矽層
102‧‧‧介電層
104‧‧‧開口
106‧‧‧金屬層
108‧‧‧應力調整層
110‧‧‧金屬矽化物層
112‧‧‧阻障層
114‧‧‧導體層
S100、S102、S104、S106、S108、S110、S112‧‧‧步驟
圖1本發明一實施例的內連線結構的製造流程圖。 圖2A至圖2F為本發明一實施例的內連線結構的製造流程剖面圖。
Claims (20)
- 一種內連線結構的製造方法,包括: 在一矽層上形成一介電層,其中在該介電層中具有暴露出該矽層的一開口; 在該開口的表面上形成一金屬層; 在該金屬層上形成一應力調整層; 進行一熱製程,使該金屬層與該矽層反應,而在該矽層上形成一金屬矽化物層; 在進行該熱製程之後,移除該應力調整層;以及 在該開口的表面上形成一阻障層。
- 如申請專利範圍第1項所述的內連線結構的製造方法,其中該應力調整層與該阻障層是使用不同沉積方法所形成。
- 如申請專利範圍第1項所述的內連線結構的製造方法,其中該矽層包括矽基底或磊晶矽層。
- 如申請專利範圍第1項所述的內連線結構的製造方法,其中該介電層的形成方法包括化學氣相沉積法。
- 如申請專利範圍第1項所述的內連線結構的製造方法,其中該金屬層的材料包括鈦、鎳或鈷。
- 如申請專利範圍第1項所述的內連線結構的製造方法,其中該金屬層的形成方法包括物理氣相沉積法或化學氣相沉積法。
- 如申請專利範圍第1項所述的內連線結構的製造方法,其中該應力調整層的材料包括氮化鈦、氮化矽或其組合。
- 如申請專利範圍第1項所述的內連線結構的製造方法,其中該應力調整層的形成方法包括射頻物理氣相沉積法。
- 如申請專利範圍第1項所述的內連線結構的製造方法,其中該應力調整層的應力是藉由設定沉積機台的可變電容值來進行調整。
- 如申請專利範圍第1項所述的內連線結構的製造方法,其中該應力調整層更填滿該開口。
- 如申請專利範圍第1項所述的內連線結構的製造方法,其中該熱製程包括回火製程。
- 如申請專利範圍第1項所述的內連線結構的製造方法,其中該金屬矽化物層的材料包括矽化鈦、矽化鎳或矽化鈷。
- 如申請專利範圍第1項所述的內連線結構的製造方法,更包括在移除該應力調整層時,同時移除未與該矽層反應的該金屬層。
- 如申請專利範圍第1項所述的內連線結構的製造方法,其中該應力調整層的移除方法包括一濕式蝕刻法。
- 如申請專利範圍第14項所述的內連線結構的製造方法,其中該濕式蝕刻法的蝕刻劑包括稀釋氫氟酸或是硫酸與過氧化氫的混合溶液。
- 如申請專利範圍第1項所述的內連線結構的製造方法,其中該阻障層的材料包括氮化鈦。
- 如申請專利範圍第1項所述的內連線結構的製造方法,其中該阻障層的形成方法包括化學氣相沉積法或原子層沉積法。
- 如申請專利範圍第1項所述的內連線結構的製造方法,更包括在該阻障層上形成填滿該開口的一導體層。
- 如申請專利範圍第18項所述的內連線結構的製造方法,其中該導體層的材料包括鎢。
- 如申請專利範圍第18項所述的內連線結構的製造方法,其中該導體層的形成方法包括物理氣相沉積法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW106127797A TWI741007B (zh) | 2017-08-16 | 2017-08-16 | 內連線結構的製造方法 |
US15/711,854 US10497607B2 (en) | 2017-08-16 | 2017-09-21 | Manufacturing method of interconnect structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW106127797A TWI741007B (zh) | 2017-08-16 | 2017-08-16 | 內連線結構的製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201911513A true TW201911513A (zh) | 2019-03-16 |
TWI741007B TWI741007B (zh) | 2021-10-01 |
Family
ID=65360703
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW106127797A TWI741007B (zh) | 2017-08-16 | 2017-08-16 | 內連線結構的製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US10497607B2 (zh) |
TW (1) | TWI741007B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11127899B2 (en) * | 2019-04-11 | 2021-09-21 | Micron Technology, Inc. | Conductive interconnects suitable for utilization in integrated assemblies, and methods of forming conductive interconnects |
US20220277961A1 (en) | 2021-02-26 | 2022-09-01 | Applied Materials, Inc. | Low Resistivity Metal Contact Stack |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5654233A (en) | 1996-04-08 | 1997-08-05 | Taiwan Semiconductor Manufacturing Company Ltd | Step coverage enhancement process for sub half micron contact/via |
US6982226B1 (en) | 1998-06-05 | 2006-01-03 | Agere Systems Inc. | Method of fabricating a contact with a post contact plug anneal |
US7012022B2 (en) * | 2003-10-30 | 2006-03-14 | Chartered Semiconductor Manufacturing Ltd. | Self-patterning of photo-active dielectric materials for interconnect isolation |
JP4515305B2 (ja) | 2005-03-29 | 2010-07-28 | 富士通セミコンダクター株式会社 | pチャネルMOSトランジスタおよびその製造方法、半導体集積回路装置の製造方法 |
US20070161233A1 (en) * | 2005-12-28 | 2007-07-12 | Seok Ka M | Semiconductor Device and Method of Manufacturing the Same |
US8247850B2 (en) * | 2007-01-04 | 2012-08-21 | Freescale Semiconductor, Inc. | Dual interlayer dielectric stressor integration with a sacrificial underlayer film stack |
US20090026618A1 (en) * | 2007-07-25 | 2009-01-29 | Samsung Electronics Co., Ltd. | Semiconductor device including interlayer interconnecting structures and methods of forming the same |
US20090166866A1 (en) * | 2007-12-31 | 2009-07-02 | Michal Efrati Fastow | Contact metallization for semiconductor devices |
KR101669470B1 (ko) * | 2009-10-14 | 2016-10-26 | 삼성전자주식회사 | 금속 실리사이드층을 포함하는 반도체 소자 |
DE102010064288B4 (de) * | 2010-12-28 | 2012-12-06 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Halbleiterbauelement mit Kontaktelementen mit silizidierten Seitenwandgebieten |
US20140206190A1 (en) * | 2013-01-23 | 2014-07-24 | International Business Machines Corporation | Silicide Formation in High-Aspect Ratio Structures |
KR102019375B1 (ko) * | 2013-03-05 | 2019-09-09 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조방법, 그리고 반도체 장치를 포함하는 마이크로프로세서, 프로세서, 시스템, 데이터 저장 시스템 및 메모리 시스템 |
KR102033496B1 (ko) * | 2013-07-12 | 2019-10-17 | 에스케이하이닉스 주식회사 | 에어갭을 구비한 반도체장치 및 그 제조 방법 |
CN105826174B (zh) * | 2015-01-05 | 2021-06-15 | 联华电子股份有限公司 | 半导体装置及其制作方法 |
US10266940B2 (en) * | 2015-02-23 | 2019-04-23 | Applied Materials, Inc. | Auto capacitance tuner current compensation to control one or more film properties through target life |
US10079288B2 (en) * | 2016-06-07 | 2018-09-18 | International Business Machines Corporation | Contact formation on germanium-containing substrates using hydrogenated silicon |
US9899258B1 (en) * | 2016-09-30 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal liner overhang reduction and manufacturing method thereof |
-
2017
- 2017-08-16 TW TW106127797A patent/TWI741007B/zh active
- 2017-09-21 US US15/711,854 patent/US10497607B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20190057895A1 (en) | 2019-02-21 |
TWI741007B (zh) | 2021-10-01 |
US10497607B2 (en) | 2019-12-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI666704B (zh) | 半導體裝置與其形成方法 | |
TWI540678B (zh) | 接觸插塞及其製作方法與半導體元件 | |
US7719035B2 (en) | Low contact resistance CMOS circuits and methods for their fabrication | |
KR20190099990A (ko) | 접촉 저항 감소를 위한 이중 금속 비아 | |
JP2011018742A (ja) | 半導体装置の製造方法 | |
US9373542B2 (en) | Integrated circuits and methods for fabricating integrated circuits with improved contact structures | |
TW201913767A (zh) | 製造半導體裝置的方法 | |
US9379207B2 (en) | Stable nickel silicide formation with fluorine incorporation and related IC structure | |
KR100871920B1 (ko) | 반도체 장치의 제조 방법 및 반도체 장치 | |
KR100707656B1 (ko) | 금속배선의 형성 방법 및 그에 의해 형성된 금속배선을포함하는 반도체 소자 | |
US8969209B2 (en) | Method for removing oxide | |
JP3828511B2 (ja) | 半導体装置の製造方法 | |
TWI741007B (zh) | 內連線結構的製造方法 | |
CN106683996B (zh) | 金属硅化物及金属硅化物上接触孔的制造方法 | |
TWI528497B (zh) | 製造具有低電阻裝置接觸之積體電路的方法 | |
US8603915B2 (en) | Multi-stage silicidation process | |
US20070202695A1 (en) | Method for fabricating a semiconductor device | |
JP2006073846A (ja) | 絶縁ゲート型電界効果トランジスタの製法 | |
US20210017641A1 (en) | Carbon layer covered mask in 3d applications | |
JP2004111736A (ja) | 半導体装置及びその製造方法 | |
TWI792293B (zh) | 半導體裝置及其製造方法 | |
JP3998937B2 (ja) | 銅金属化プロセスにおけるTaCNバリア層の製造方法 | |
KR100750194B1 (ko) | 오믹콘택막의 형성 방법 및 이를 이용한 반도체 장치의금속배선 형성 방법 | |
JP2000133712A (ja) | 半導体装置の製造方法 | |
TWI552212B (zh) | 半導體元件及其製造方法 |