TWI792293B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI792293B
TWI792293B TW110115870A TW110115870A TWI792293B TW I792293 B TWI792293 B TW I792293B TW 110115870 A TW110115870 A TW 110115870A TW 110115870 A TW110115870 A TW 110115870A TW I792293 B TWI792293 B TW I792293B
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layer
semiconductor device
gas
epitaxial
cleaning process
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TW110115870A
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TW202209451A (zh
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張正偉
黃昱明
曾奕森
張根育
劉奕瑩
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台灣積體電路製造股份有限公司
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Abstract

半導體裝置的製造方法包括： 提供一結構，其包括半導體基板、半導體基板上的一磊晶源極/汲極部件、及磊晶源極/汲極部件上的一或多個介電層；在所述一或多個介電層中蝕刻出孔洞，以露出磊晶源極/汲極部件的一部分；形成矽化物層於磊晶源極/汲極部件的此部分上；形成導電阻障層於矽化物層上；以及對至少所述導電阻障層執行電漿清潔製程，其中電漿清潔製程使用包括N2 氣體及H2 氣體的氣體混合物且在至少300℃的溫度下執行。

Description

半導體裝置及其製造方法
本發明實施例是關於半導體裝置，特別是關於具有阻障層的半導體裝置及其製造方法。
半導體積體電路產業經歷了指數型的成長。積體電路材料及設計的技術進展產生了多個半導體世代，其中每個世代都比前一世代具有較小及較複雜的電路。積體電路演進期間，功能密度(亦即，單位晶片面積的互連裝置數量)通常會增加而幾何尺寸(亦即，可使用製程生產的最小元件(或線))卻減少。此微縮化的過程通常會提供增加生產效率與降低相關成本的助益。這樣的微縮化也增加了積體電路的製程及製造的複雜性。
舉例而言，隨著半導體裝置日益地微縮，源極/汲極(S/D)接觸電阻在電晶體的導電路徑中變得越來越重要(dominant)。有研究表明接觸電阻可能佔51%或更多的總導電路徑電阻。在降低源極/汲極接觸電阻的領域中的進步是被高度期望的。
本發明實施例提供一種半導體裝置的製造方法，包括：提供一結構，其包括半導體基板、半導體基板上的磊晶源極/汲極部件、及磊晶源極/汲極部件上的一或多個介電層；在所述一或多個介電層中蝕刻出孔洞，以露出磊晶源極/汲極部件的一部分；形成矽化物層於磊晶源極/汲極部件的此部分上；形成導電阻障層於矽化物層上；以及對至少所述的導電阻障層執行電漿清潔製程，其中電漿清潔製程使用包括N2氣體及H2氣體的氣體混合物且在至少300℃的溫度下執行。
本發明實施例提供一種半導體裝置的製造方法，包括：提供一結構，其包括基板、從基板突出的兩個半導體鰭片、包括矽鍺的源極/汲極部件，在所述兩個半導體鰭片上並連接至所述兩個半導體鰭片、及一或多個介電層，在所述半導體鰭片及源極/汲極部件上；在所述一或多個介電層中蝕刻出孔洞，以露出源極/汲極部件的一部分；形成一或多個導電層於源極/汲極部件的此部分上，其中所述一或多個導電層包括鈦；對所述一或多個導電層執行電漿清潔製程，其中電漿清潔製程使用由具有N2氣體及H2氣體的混合物產生的電漿且在約300℃至約400℃的溫度下執行；以及在執行電漿清潔製程之後，沉積金屬層至孔洞中。
本發明實施例提供一種半導體裝置，包括：基板；兩個半導體鰭片，從基板突出；磊晶部件，在所述兩個半導體鰭片上並連接所述兩個半導體鰭片；矽化物層，在磊晶部件上；阻障層，在矽化物層上，阻障層具有金屬氮化物；以及金屬層，在阻障層上，其中沿著阻障層與金屬層之間的邊界，氧與金屬氮化物的原子比為約0.15至約1.0。
10:方法
12,14,16,18,20,22,24,26:操作
100:半導體裝置
102:基板
104:隔離結構
106:鰭片
107:空隙
108:磊晶部件
108-S:側壁表面
108-T:頂表面
110:介電層
112:閘極結構
114:層間介電層
120:接觸孔
122:矽化物層
124,126:導電阻障層
128:金屬層
200:製程腔室
202:靜電吸盤
206:射頻1
208:射頻2
210:控制模組
302,304,306,308,309,310,312,314:曲線
T:厚度
由以下的詳細敘述配合所附圖式，可最好地理解本發明實施例。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製。事實上，可任意地放大或縮小各種元件的尺寸，以清楚地表現出本發明實施例之特徵。
第1圖是根據本揭露的各種方面，繪示出形成具有降低的源極/汲極接觸電阻的半導體裝置之方法的流程圖。
第2圖是根據第1圖的方法的一實施例，繪示出半導體裝置在製造的中間步驟的透視圖。
第3、4、5、6、及7圖是根據一些實施例，繪示出根據第1圖的方法形成半導體裝置的剖面圖。
第8圖是根據本發明的一些實施例，繪示出源極/汲極與其上的接觸件之間的界面的部分視圖。
第9圖是根據本發明實施例，繪示出在第1圖的方法的步驟中使用的清潔製程腔體的示意圖。
第10、11、及12圖是根據本發明的一些實施例，繪示出在源極/汲極與其上的接觸件之間的界面處的氧、金屬氮化物、及碳的強度。
第13圖是根據本發明的另一實施例，繪示出形成具有降低的源極/汲極接觸電阻的半導體裝置之方法的流程圖。
第14圖是根據一些實施例，繪示出根據第13圖的方法形成半導體裝置的剖面圖。
第15圖是根據本發明的一些實施例，繪示出源極/汲極與其上的接觸件之間的界面的部分視圖。
第16圖是根據本發明的一些實施例，繪示出形成具有降低的源極/汲極接觸電阻的半導體裝置之方法的流程圖。
第17圖是根據一些實施例，繪示出根據第16圖的方法形成半導體裝置的剖面圖。
第18圖是根據本發明的一些實施例，繪示出源極/汲極與其上的接觸件之間的界面的部分視圖。
以下揭露提供了許多的實施例或範例，用於實施本發明實施例之不同元件。各元件及其配置的具體範例描述如下，以簡化本發明實施例之說明。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例而言，敘述中若提及第一元件形成在第二元件之上，可能包含第一及第二元件直接接觸的實施例，也可能包含額外的元件形成在第一及第二元件之間，使得它們不直接接觸的實施例。此外，本發明實施例可能在各種範例中重複參考數值及/或字母。如此重複是為了簡明及清楚之目的，而非用以表示所討論的不同實施例及/或配置之間的關係。
此外，其中可能用到與空間相對用詞，例如「在......之下」、「下方」、「較低的」、「上方」、「較高的」等類似用詞，是為了便於描述圖式中一個(些)部件或特徵與另一個(些)部件或特徵之間的關係。空間相對用詞用以包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位)，其中所使用的空間相對形容詞也將依轉向後的方位來解釋。另外，當使用「約」、「近似」及類似的用語 描述數字或數字範圍時，除非特別說明，此類用語涵蓋在某個範圍內的數字(例如+/-10%內)，或本發明所屬技術領域中具有通常知識者考慮到本文揭露的特定技術所述的其他數字。舉例來說，用語「約5nm」涵蓋4.5nm至5.5nm、4.0nm至5nm等等的尺寸範圍。
本發明在各種實施例中大致上關於半導體裝置及其形成方法。本發明實施例特別關於在場效電晶體(FET)中形成源極/汲極(S/D)接觸件，所述場效電晶體包括：鰭式場效電晶體、奈米線場效電晶體、奈米片場效電晶體或其他先進的場效電晶體。源極/汲極接觸件可以形成在單個磊晶部件上、合併成一個連續件的多個磊晶部件上、或作為電晶體的源極/汲極電極的其他半導體結構上。源極/汲極接觸件通常包括多於一個的膜層，如：具有在下方源極/汲極半導體上的矽化物層、一或多個導電阻障層(例如：導電金屬氮化物)、以及高導電塊體金屬層(例如：鈷)。本揭露的發明人已發現在製造源極/汲極接觸件期間，可能不經意地在源極/汲極半導體材料及高導電塊體金屬層之間引入含氧的化合物(例如金屬氧化物)。舉例而言，當形成矽化物層及導電阻障層(一或多個)時，儘管是以非常低的密度，但是氧可能存在於環境中。氧與金屬反應形成金屬氧化物。這些化合物導致增加的源極/汲極接觸電阻。本揭露的各種實施例應用新穎的電漿清潔製程以有效地移除這些化學化合物，而對矽化物層及導電阻障層的損害是可忽略的。以下參照所附圖式敘述本發明的實施例。
第1圖繪示出根據本揭露的各種方面的形成半導體裝置的方法10的方框圖。方法10是示例，且不意圖將本揭露作出除了請求項中明確記載範圍之外的限制。可以在方法10之前、期間及之後提供附加的操作，且所述方法的其他實施例可以替換、刪除或調動所描述的一些操作。以下結合第2-12圖描述方 法10。第2圖特別地繪示出半導體裝置100的透視圖且第3-8是根據方法10繪示出半導體裝置100在製造的各種階段的剖面圖。第9圖是根據本發明實施例，繪示出執行電漿清潔製程之腔室的示意圖。第10、11及12圖是根據一些實施例，繪示出在半導體裝置100的某些層的某些化學元素的強度。
參照第1圖，在操作12，方法10提供一結構，所述的結構是在中間製造階段的半導體裝置100，如在第2圖中所示。
半導體裝置100可以是積體電路(IC)或其一部分在製程期間製造的中間裝置，其可以包括靜態隨機存取記憶體(SRAM)及/或邏輯電路、被動元件如電阻器、電容器、及電感器、以及主動元件如p型場效電晶體(PFET)、n型場效電晶體(NFET)、鰭式場效電晶體、奈米線場效電晶體、奈米片場效電晶體、金屬氧化物半導體場效電晶體(MOSFET)、互補式金屬氧化物半導體(CMOS)電晶體、雙極性電晶體、高壓電晶體、高頻電晶體、其他記憶體單元、及前述之組合。此外，所提供的各種部件，包括電晶體、鰭片、閘極堆疊、裝置區域、及本發明的各種實施例中的其他部件用於簡化及便於理解，而非必然將所述的實施例限制為任何類型的裝置、任何數量的裝置、任何數量的區域、或結構或區域的任何配置。儘管在各種實施例中繪示為鰭式場效電晶體裝置，在替代實施例中，裝置100也可以是平面的場效電晶體裝置及其他多閘極裝置如奈米線場效電晶體及奈米片場效電晶體。
參照第2圖，在本實施例中，裝置100包括基板102、基板102上的隔離結構104、以及在基板102上的兩個或更多個鰭片106(第2圖中繪示兩個)。鰭片106沿著「y」方向縱向延伸。儘管未繪示出，鰭片106的一些部分(例如，在閘極結構112下方)可突出於隔離結構104上。此外，在此實施例中，裝置100 包括一或多個磊晶生長的半導體部件108，在第2圖中繪示兩個。磊晶部件108的頂部可以合併成連續層。磊晶部件108作為半導體裝置100的源極/汲極(S/D)電極。因此，磊晶部件108在本揭露中也稱源極/汲極108。在一些實施例中，空隙107可以存在於隔離結構104的頂表面與磊晶部件108的合併部分之間。在替代實施例(未繪示)中，磊晶部件108可以是彼此分開的。半導體裝置100還包括在隔離結構104上方並接合鰭片106的通道區的閘極結構112、在隔離結構104及磊晶部件108上方的接觸蝕刻停止層110、以及在接觸蝕刻停止層110上的層間介電(ILD)層114。以下進一步描述半導體裝置100的各種元件。
在本實施例中，基板102是矽基板(例如，包括單晶矽)。替代地，基板102可以包括另一半導體，例如鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP；或前述的組合。在又一替代實施例中，基板102是絕緣體上覆半導體(SOI)，例如在介電層上具有半導體層。在實施例中，基板102包括用於形成主動裝置的主動區，例如p型井及n型井。
鰭片106可以包括與基板102實質上相同的半導體材料。舉例而言，它們主要都包括矽。替代地，鰭片106可包括與基板102不同的半導體材料。舉例而言，基板102可以主要包括矽，且鰭片106可以主要包括矽鍺。儘管在第2圖中未繪示，但是鰭片106的每一個包括通道區及將通道區夾在中間的兩個源極/汲極區。通道區在閘極結構112下方，而源極/汲極區(在磊晶部件108下方)在閘極結構112的兩側。鰭片106的通道區可以是用於鰭式場效電晶體的鰭片通道的形式、分別用於奈米線場效電晶體或奈米片場效電晶體的一或多個奈米線或奈米片的形式、其他形狀的形式。可以使用單一圖案化製程、雙重圖案化製程 或其他多重圖案化製程來形成鰭片106。
鰭片106被隔離結構104分隔。隔離結構104可以包括氧化矽、氮化矽、氮氧化矽、摻雜氟的矽酸鹽玻璃(FSG)、低介電常數(low-k)介電材料及/或其他合適的絕緣材料。在一些實施例中，隔離結構104可以是淺溝槽隔離(STI)部件。
在一實施例中，每個磊晶部件(S/D)108可以包括摻雜有一或多種n型摻雜劑(如磷或砷)的矽，用於形成n型場效電晶體裝置。在另一個實施例中，每個的磊晶部件108可以包括摻雜有一或多種p型摻雜劑(如硼或銦)的矽，用於形成p型場效電晶體裝置。每個磊晶部件108可以包括具有不同摻雜劑濃度的一或多層。舉例而言，磊晶部件108的上部可以包括摻雜有具有摻雜劑濃度為1e21cm-3至5e21cm-3的磷的矽，而磊晶部件108的下部可以包括摻雜有具有摻雜劑濃度為1e20cm-3至1e21cm-3的磷的矽。在磊晶部件108的上部處的較高濃度提高了半導體材料的導電性。
介電層110可以包括氮化物，如氮化矽、氮氧化矽或碳氮化矽的。層間介電層114包括與介電層110不同的材料。舉例而言，層間介電層114可以包括四乙基正矽酸鹽(tetraethylorthosilicate，TEOS)氧化物、摻雜或未摻雜的矽酸鹽玻璃，如摻雜氟的石英玻璃(FSG)，而介電層110包括氮化物。
閘極結構112包括閘極介電層及閘極電極層。閘極介電層可以包括氧化矽(SiO2)或高介電常數(high-k)介電材料，例如氧化鉿、氧化鋯、氧化鑭、氧化鈦、氧化釔及鈦酸鍶。可以由化學氧化、熱氧化、原子層沉積(ALD)、化學氣相沉積(CVD)及/或其他合適的方法來形成閘極介電層。在一實施例中，閘極電極層包括多晶矽，並且可以由合適的沉積製程來形成，例如低壓化學氣 相沉積(LPCVD)及電漿輔助化學氣相沉積(PECVD)。在一些實施例中，閘極電極層包括n型或p型功函數層及金屬填充層。舉例而言，n型功函數層可以包括具有足夠低的有效功函數的金屬，例如：鈦、鋁、碳化鉭、氮碳化鉭(tantalum carbide nitride)、氮化鉭矽或前述之組合。舉例而言，p型功函數層可以包括具有足夠大的有效功函數的金屬，例如：氮化鈦、氮化鉭、釕、鉬、鎢、鉑或前述之組合。舉例而言，金屬填充層可以包括鋁、鎢、鈷、銅及/或其他合適的材料。可以由化學氣相沉積、物理氣相沉積、電鍍及/或其他合適的製程來形成閘極電極層。在一些實施例中，閘極結構112在其閘極介電層與鰭片106之間包括界面層。界面層可以包括介電材料，如氧化矽或氮氧化矽，並且可以由化學氧化、熱氧化、原子層沉積、化學氣相沉積及/或其他合適的介電質形成。閘極結構112可以包括其他膜層，例如在閘極電極層上的硬遮罩層。
參照第1圖，在操作14，方法10蝕刻包括層間介電層114及蝕刻停止層110的各種介電層，以形成一或多個接觸孔120，露出磊晶部件108的頂部，如第3圖所示，其繪示出沿著第2圖中的1-1線(在xz平面中)切割的半導體裝置100的剖面圖。操作14可以包含多種製程，包括沉積、微影及蝕刻。舉例而言，操作14可以在半導體裝置100上形成蝕刻遮罩(未繪示)。蝕刻遮罩可以包括氮化矽、氧化矽、光阻層或前述之組合。透過微影對蝕刻遮罩進行圖案化，提供開口以露出裝置100的各個部分。然後，透過所述開口蝕刻裝置100以移除介電層114及110的露出部分，舉例而言，使用乾蝕刻製程、濕蝕刻製程、反應性離子蝕刻製程或前述之組合。在一些實施例中，透過調整蝕刻劑化學或蝕刻時間，操作14可以進一步蝕刻部分磊晶部件108。這有時稱為過蝕刻(over etching)，這可增加用於接觸件著陸(contact landing)的半導體材料的面積，從而降低源 極/汲極的接觸電阻。
如第3圖所示，在此實施例中，磊晶部件108包括合併的連續層。在操作14後，在接觸孔120中露出合併磊晶部件108的頂表面108-T及側壁表面(或側表面)108-S。在一些實施例中，接觸孔120僅露出所有側面上的部分側壁表面108-S。在一些實施例中，接觸孔120露出在合併磊晶部件108的至少一側上的整個側壁表面108-S。在各種實施例中，接觸孔120可露出對稱地或不對稱地圍繞頂表面108-T的合併磊晶部件108。在一實施例中，頂表面108-T是在立方晶{001}面(例如，矽鍺{001}晶面或矽{001}晶面)且側壁表面108-S是在立方晶{111}面(例如，矽鍺{111}晶面或矽{111}晶面)。本揭露的發明人已經發現難以從側壁表面108-S(特別是側壁表面108-S的底部附近)移除金屬氧化物(或其他氧化物殘留)，此為增加的源極/汲極接觸電阻的主要原因之一。
參照第1圖，在操作16，方法10在磊晶部件108的露出部分上形成矽化物層122。第4圖繪示出操作16產生的半導體裝置100的實施例。參照第4圖，在磊晶部件108的露出部分的頂部及側壁表面上形成矽化物層122。在一實施例中，操作16包括對半導體裝置100施加含金屬的化學品，其中所述含金屬的化學品與磊晶部件108中的半導體材料反應，以形成矽化物層122。舉例而言，操作16可以施加氯化鈦(例如TiCl4)以與矽鍺反應而形成鈦矽化物(titanium silicide)或鈦矽鍺化物(titanium germano-silicide)。在另一實施例中，操作16包括：在磊晶部件108的露出部分上沉積金屬層、對金屬層進行退火，使得金屬層與磊晶部件108中的半導體材料反應以形成矽化物層122、以及隨後移除未反應的金屬層。在各種實施例中，矽化物層122中的金屬元素(一或多種)可以包括：鈦、鈷、鉑、鎳、鉬、鉭、鎢或前述之組合。矽化物層122通常以兩種方式降低源極 /汲極接觸電阻。第一，矽化物層122的低薄片電阻(low sheet resistance)分流磊晶部件108的重摻雜擴散區域，以減小其面內電阻(in-plane resistance)、以及第二，矽化物反應導致緊密的及更可靠的金屬-半導體接觸並改善垂直方向上的導電性。
參照第1圖，在操作18，方法10在矽化物層122上形成導電阻障層124。第5圖繪示出操作18產生的半導體裝置100的實施例。參照第5圖，在本實施例中，導電阻障層124主要形成在接觸孔120的底表面上，且實質上不在接觸孔120的側壁表面。特別地，導電阻障層124形成於磊晶部件108的頂部及側壁表面上且完全覆蓋矽化物層122。在一實施例中，導電阻障層124是透過化學氣相沉積(CVD)製程形成，例如電漿輔助化學氣相沉積製程。舉例而言，可使用由氯化鈦(例如TiCl4)及氮(N2)、氨(NH3)、或氮(N2)及氨(NH3)的組合產生的電漿，沉積氮化鈦層作為導電阻障層124。在另一實施例中，導電阻障層124可以包括氮化鉭或其他導電氮化物。導電阻障層124用於防止隨後沉積的塊體接觸金屬中的金屬元素擴散至矽化物層122及磊晶部件108中。
本揭露的發明人已經發現，在形成矽化物層122及/或導電阻障層124期間，氧化物(如金屬氧化物)可能會非經意地沉積在接觸孔120中。舉例而言，含有Ti、Si、O及N的化合物可以形成於阻障層124之上或之中或遍及層122及124。這些氧化物不利地增加源極/汲極接觸電阻。
參照第1圖，在操作20，方法10對半導體裝置100(特別是對接觸孔120內的結構)施加電漿清潔製程，以從層122及124移除氧化物。在一實施例中，電漿清潔製程以某些比例的流量運用包括N2氣體及H2氣體的氣體混合物，以有效地移除氧化物，而不會不利地影響矽化物層122及導電阻障層124。此外， 在足夠高的溫度下執行電漿清潔製程，使得電漿可以與氧化物有效地反應且可以有效地從製程腔室排出反應的副產物，而不會對半導體裝置100的各種元件造成不利地影響。在目標氧化物包括TiSiON的一非限制性示例中，以下的反應可在電漿清潔製程期間發生：N2+H2+TiSiON→TiSixNy+H2O+NOz
在一實施例中，在整個或部分電漿清潔製程期間，N2氣體的流量與H2氣體的流量之比例控制在0.03至0.28，例如在0.22至0.26。已經發現此流量比例範圍達到了電漿清潔製程的主要目標-有效地移除氧化物化合物(oxide compound)並且降低源極/汲極接觸電阻。如果流量的比例低於0.03，則電漿中可能不具有足夠的氮來替代目標氧化物化合物中的氧。因此，電漿清潔製程在移除氧化物化合物的方面可能不是非常有效。另一方面，如果流量的比例高於0.28，則在矽化物層122及/或導電阻障層124中的金屬元素可能與氮反應，產生設置在磊晶部件108及稍後沉積的塊體金屬接觸件之間的厚的氮(或氮化物)化合物層。具有這樣的厚的氮化合物層將不利地增加源極/汲極接觸電阻。類似以上所述的原因，在本發明的各種實施例中，N2氣體的流量控制為每分鐘10標準立方公分(sccm)或更低，使得電漿清潔製程不會產生厚的氮化合物層。一實施例中，在電漿清潔製程期間，N2氣體的流量控制為約每分鐘1至9標準立方公分(sccm)且H2氣體的流量控制為約30sccm。
此外，在各種實施例中，在將半導體結構100保持在至少300℃的溫度(製程溫度)時執行電漿清潔製程。舉例而言，製程溫度可以為300℃至500℃、300℃至400℃、380℃至400℃、或大約400℃(例如，在400℃的+/-10%內)。如果製程溫度低於此範圍(例如，低於300℃)，則上述化學反應可能 會非常緩慢(或不發生)，以致於氧化物化合物的移除沒有效率。特別是，如果製程溫度低，則難以移除磊晶部件108的側壁表面108-S的下部附近的氧化物(參見第3圖)。具有在所揭露的範圍內的高溫的另一益處是化學反應的副產物(例如：H2O及NOz)可以有效地蒸發並從製程腔室排出。另一方面，如果製程溫度高於此範圍(例如，高於500℃)，則可能不利地影響半導體裝置100中的一些金屬元素(例如：閘極結構112中的金屬層)。在各種實施例中，操作20從層122及124移除氧化物化合物，使得層122及124中的氧的水平變得偵測不到(undetectable)。
在一實施例中，操作20在製程腔室200中執行，第9圖中繪示出參考圖。參照第9圖，製程腔室200包括圍住陶瓷鐘罩的石英圓頂。高溫靜電吸盤(靜電吸盤(e-chuck))202置於陶瓷鐘罩內。在本實施例中，靜電吸盤202是雙極性靜電吸盤，提供晶圓(例如，具有半導體裝置100的晶圓)的快速夾持(clamping)及解除夾持(de-clamping)。此外，靜電吸盤202提供具可調溫度的加熱功能。舉例而言，靜電吸盤202可以配置為加熱並維持其上的晶圓至所欲的溫度或溫度範圍。在本實施例中，在操作20期間，靜電吸盤202配置以加熱並維持其上的晶圓在300℃至500℃、在300℃至400℃、在380℃至400℃、或約400℃。在一實施例中，載氣(carrier gas)供應到靜電吸盤202的底側(晶圓保持在與底側相對的頂側)，以使整個晶圓的加熱均勻。舉例而言，可以以2sccm至20sccm的流量供應載氣。在一實施例中，對靜電吸盤202提供275V至350V的可調吸盤電壓(tunable chucking voltage)。
製程腔室200進一步包括兩個射頻(RF)電源，射頻1 206及射頻2 208。在一實施例中，射頻2 208配置為以1MHz至5MHz的頻率提供功率(例 如2MHz)，用於從具有N2氣體及H2氣體的氣體混合物產生電漿。射頻1 206配置為提供具有10MHz至20MHz的頻率(例如13.56MHz)的電源，用於引導電漿朝向靜電吸盤202所支撐的晶圓的表面上。此外，在操作20期間，射頻1 206可以供給50W至85W的功率，例如約75W。在操作20期間，射頻2 208可以供給850W至950W的功率。在操作20期間，將具有如上所討論的相應流量比例的N2氣體及H2氣體的氣體混合物供應至製程腔室200。此外，製程腔室200內的壓力可以保持在1mTorr至20mTorr。各種製程參數(例如：射頻範圍及射頻1 206及射頻2 208的功率、製程溫度、製程壓力、及氣體流量)設計為有效地移除半導體裝置100的層122及124中的氧化物化合物且降低其源極/汲極接觸電阻。製程腔室200耦合至控制模組210，用於配置及控制製程腔室200的各種組件(例如：靜電吸盤202、射頻1 206及射頻2 208)。
在一實施例中，以如上所討論的製程腔室200的配置(例如，具有所揭露的氣體流量、射頻功率、靜電吸盤溫度等等)，當執行時間為85秒至95秒(如90秒)時，操作20有效地從層122及124移除氧化物化合物。如果執行時間太短(例如，小於85秒)，則可能無法充分地清潔結構的某些區域(例如：側壁表面108-S的下邊緣)。執行時間超過95秒是可允許的，但可能不是必要的。為了晶圓量產的目的，通常期望操作20的持續時間較短。在各種實施例中，當執行所揭露的85秒至95秒的持續時間，操作20將層122及124的氧水平降低至到檢測不到的水平。
參照第1圖，在操作22，方法10在接觸孔120中沉積另一導電阻障層126。在本實施例中，操作22使用原子層沉積(ALD)技術(例如電漿輔助原子層沉積技術)來沉積導電阻障層126，使得層126形成為沿著接觸孔120的側壁 及底表面具有實質上均勻的厚度，如第6圖所示。因此，層126完全覆蓋在接觸孔120底部的導電阻障層124以及接觸孔120的介電側壁(亦即，在接觸孔120中露出的介電層114的側壁)。導電阻障層126用於防止隨後沉積的金屬元素擴散到介電層114中。在一實施例中，導電阻障層126包括導電氮化物，例如氮化鈦或氮化鉭。在一實施例中，導電阻障層126具有0.6nm至1.9nm的厚度，例如約1.2nm。如上所述，如果導電阻障層126太厚，則可能不利地增加源極/汲極接觸電阻。另一方面，如果導電阻障層126太薄，則可能無法有效地防止金屬擴散。
參照第1圖，在操作24，方法10沉積一或多個金屬層128至接觸孔120中，如第7圖所示。舉例而言，金屬層128可以包括金屬晶種層，金屬晶種層的沉積是使用物理氣相沉積(PVD)及/或化學氣相沉積(CVD)，接著使用電鍍沉積塊體金屬層。金屬層128可以包括Al、W、Cu、Co、前述之組合、或其他合適的材料。金屬層128也稱為塊體金屬接觸件。
第8圖繪示出半導體裝置100的局部示意圖，特別是繪示出塊體金屬接觸件128及磊晶部件108之間的界面。如圖所示，界面包括矽化物層122及導電阻障層124及126。不僅從磊晶部件108的頂面，還從磊晶部件108的側面，所揭露的電漿清潔製程能夠實質上消除界面中的氧化合物。作為一個附加的益處，相較於未使用所揭露的電漿清潔製程的製程，可將導電阻障層124及126製作得更薄。在一實施例中，導電阻障層124及126皆包括氮化鈦，且這兩層的平均厚度為約3.0nm或更薄。平均厚度是透過沿著磊晶部件108頂面及側面測量這兩層的厚度T來計算。在一實施例中，當以0.22至0.26的N2氣體流量與H2氣體流量的比例及射頻1 206提供約70至80W的功率來實施電漿清潔製程約85至95秒時，所述的平均厚度為約2.6nm。在另一實施例中，當以0.22至0.26的N2氣體流 量與H2氣體流量的比例及射頻1 206提供約45至55W的功率來實施電漿清潔製程約85至95秒時，所述的平均厚度為約2.3nm。
參照第1圖，在操作26，方法10對半導體裝置100執行進一步的製程。舉例而言，操作26可以執行化學機械平坦化(CMP)製程以移除接觸孔120外部的層128及126的任何多餘部分。舉例而言，操作26可以在層114、126及128上沉積介電層，且在那些介電層中形成金屬線及金屬通孔，以形成多層互連結構。
第10、11及12圖繪示出從二次離子質譜法(secondary ion mass spectrometry，SIMS)測量所得的實驗樣品的某些層中的某些化學元素的訊號強度(例如，原子的計數(count of atoms))曲線。每個的實驗樣品包括二氧化矽(SiO2)層、在二氧化矽層上的氮化鈦(TiN)層、在氮化鈦層上的鈷(Co)層。氮化鈦層的沉積類似於層124的沉積，並對其進行本揭露的電漿清潔製程。除了用二氧化矽(SiO2)層替換磊晶部件108及矽化物層122之外，這些樣品非常類似於半導體裝置100的源極/汲極接觸件結構。因此，這些樣本的測量結果密切地反映所揭露的製造半導體裝置100之製程的結果。參照第10圖，其中繪示出跨層的氧訊號強度曲線。特別地，曲線302反映了在氮化鈦(TiN)層的沉積期間完全不引入氧時的氧強度。然而，這在實際生產過程中難以實現。曲線304反映了當未對氮化鈦(TiN)層施加電漿清潔製程時的氧強度。曲線306反映了當應用所揭露的電漿清潔製程時的氧強度。特別地，曲線306反映了在約380℃至400℃以約0.22至0.26的N2氣體流量與H2氣體流量的比例來實施所揭露的電漿清潔製程時的氧強度。如第10圖中所示，相較於未使用所揭露的電漿清潔製程的製程相比，使用所揭露的電漿清潔製程顯著地降低氧訊號強度(例如，降低了 38%至55%)。參照第11圖，其中繪示出如第10圖的相同製程情況下的跨層的氮化鈦訊號強度曲線。曲線308對應在氮化鈦(TiN)層的沉積期間完全沒有氧的情況。曲線309對應當實施所揭露的電漿清潔製程時的情況。除了曲線308之外，在不同樣本之間的氮化鈦訊號強度大致相同。參照第12圖，其中繪示出如第10圖的相同製程情況下的跨層的碳訊號強度曲線。曲線310對應在氮化鈦(TiN)層的沉積期間完全不引入氧氣的情況。曲線312對應當未對氮化鈦(TiN)層施加電漿清潔製程時的情況。曲線314對應於與曲線306相同的製程條件。如第12圖所示，相較於未使用所揭露的電漿清潔製程的製程相比，使用所揭露的電漿清潔製程顯著地降低碳訊號強度(例如，降低了10至1000倍)。
在各種實施例中，由於所揭露的電漿清潔製程，半導體裝置100中的層128及126之間的界面處(對應於樣品中的Co層及TiN層之間的邊界)的氧與金屬氮化物(例如TiN)的原子比例之測量為約1.0或更低，例如約0.15至約1.0。這可以使用第10及11圖的曲線來計算。已發現在未使用所揭露的電漿清潔製程製造的樣品所測量的上述比例高於1.0。較低的比例表示源極/汲極接觸件結構中的氧含量較低以及較低的源極/汲極接觸電阻。
第13圖繪示出根據本發明的另一實施例的方法10的流程圖。此實施例與第1圖所示的相同，但省略了操作22。換言之，在此實施例中，方法10未沉積導電阻障層126。在第14圖中繪示出所得的裝置100的結構，且第15圖中繪示出金屬層128與源極/汲極108之間的界面。如所繪示的，金屬層128直接沉積在導電阻障層124上。為簡單起見，將此實施例中相同於上述參照第1圖所討論的其他方面省略了。
第16圖繪示出根據本發明的又一實施例的方法10的流程圖。此實 施例與第1圖所示的相同，但省略了操作18。換言之，在此實施例中，方法10不沉積導電阻障層124，並且實施操作20以從矽化物層122移除氧化物。此外，可以使用參照第1圖所討論的操作16來形成矽化物層122，或透過其他方法，例如物理氣相沉積(PVD)。所得的裝置100的結構在第17圖中繪示出，且第18圖繪示出金屬層128與源極/汲極108之間的界面。如所繪示的，導電阻障層126直接沉積在矽化物層122上。為簡單起見，將此實施例中相同於上述參照第1圖所討論的其他方面省略了。
非限制性的，本發明的一或多個實施例為半導體裝置及其形成提供許多益處。舉例而言，本發明的實施例運用電漿清潔製程來清潔用於源極/汲極接觸件的導電阻障層。所述的電漿清潔製程可以有效地從導電阻障層移除氧化物，從而降低源極/汲極接觸電阻。本發明的各種實施例可以輕易地整合至現有的製造製程中。
在一例示性方面，本揭露關於半導體裝置的製造方法。此方法包括：提供一結構，其包括半導體基板、半導體基板上的一磊晶源極/汲極部件、及磊晶源極/汲極部件上的一或多個介電層；在所述一或多個介電層中蝕刻出孔洞，以露出磊晶源極/汲極部件的一部分；形成矽化物層於磊晶源極/汲極部件的此部分上；形成導電阻障層於矽化物層上；以及對至少所述導電阻障層執行電漿清潔製程，其中電漿清潔製程使用包括N2氣體及H2氣體的氣體混合物且在至少300℃的溫度下執行。
在所述方法的一實施例中，在至少一部分的電漿清潔製程期間，所述N2氣體的流量與所述H2氣體的流量之比例控制在0.03至0.28。在所述方法的另一實施例中，在電漿清潔製程期間，所述N2氣體的流量與所述H2氣體的流量 之比例控制為約0.22至0.26。在所述方法的一實施例中，電漿清潔製程在300℃至500℃的溫度下執行。
一實施例中，所述方法更包括沉積金屬至孔洞中及導電阻障層上。在進一步的實施例中，所述方法包括：在所述沉積金屬之前，沉積第二導電阻障層於導電阻障層上。
在所述方法的一實施例中，電漿清潔製程在製程腔室中執行，在所述製程腔室中，加熱至約380℃至400℃的靜電吸盤支撐所述結構。在所述方法的一實施例中，執行電漿清潔製程85秒至95秒。
在所述方法的一實施例中，電漿清潔製程使用由1MHz至5MHz的射頻產生的電漿。在進一步的實施例中，在電漿清潔製程期間，所述電漿以10MHz至20MHz的另一射頻朝向結構。
在另一例示性方面，本揭露關於半導體裝置的製造方法。此方法包括，包括：提供一結構，其包括基板、從基板突出的兩個半導體鰭片、包括矽鍺的源極/汲極部件，在所述兩個半導體鰭片上並連接至所述兩個半導體鰭片、及一或多個介電層，在所述半導體鰭片及源極/汲極部件上；在所述一或多個介電層中蝕刻出孔洞，以露出源極/汲極部件的一部分；形成一或多個導電層於源極/汲極部件的此部分上，其中所述一或多個導電層包括鈦；對所述一或多個導電層執行電漿清潔製程，其中電漿清潔製程使用由具有N2氣體及H2氣體的混合物產生的電漿且在約300℃至約400℃的溫度下執行；以及在執行電漿清潔製程之後，沉積金屬層至孔洞中。
在所述方法的一實施例中，所述一或多個導電層包括氮化鈦層。在所述方法的一實施例中，在至少一部分的電漿清潔製程期間，所述N2氣體的 流量與所述H2氣體的流量之比例控制為0.03至0.28，而所述N2氣體的流量控制為每分鐘10標準立方公分(sccm)或更低。在進一步的實施例中，所述比例控制為約0.22至0.26。在另一進一步的實施例中，所述N2氣體的流量控制為約每分鐘1至9標準立方公分。
在所述方法的一實施例中，電漿清潔製程包括對所述電漿施加射頻功率，其中射頻功率為50W至85W。
在另一例示性方面，本揭露關於半導體裝置。所述半導體裝置包括：基板、兩個半導體鰭片，從基板突出、磊晶部件，在所述兩個半導體鰭片上並連接所述兩個半導體鰭片、矽化物層，在磊晶部件上、阻障層，在矽化物層上，阻障層具有金屬氮化物、以及金屬層，在阻障層上。沿著阻障層與金屬層之間的一邊界，氧與金屬氮化物的原子比為約0.15至約1.0。
在所述半導體裝置的一實施例中，磊晶部件的頂表面上及磊晶部件的側壁上的所述原子比大約相同。進一步的實施例中，磊晶部件包括矽鍺(SiGe)，磊晶部件的頂表面在矽鍺(001)晶面中，且磊晶部件的側壁在矽鍺(111)晶面中。在所述半導體裝置的另一實施例中，沿著邊界的阻障層的平均厚度為3.0nm或更薄。
以上概述數個實施例之特徵，以便在本發明所屬技術領域中具有通常知識者可更易理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應理解，他們能以本發明實施例為基礎，設計或修改其他製程及結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解到，此類等效的製程及結構並無悖離本發明的精神與範圍，且他們能在不違背本發明之精神及範圍之下，做各式各樣的改變、取代及 替換。
100:半導體裝置
102:基板
104:隔離結構
106:鰭片
107:空隙
108:磊晶部件
110:介電層
114:層間介電層
122:矽化物層
124,126:導電阻障層
128:金屬層

Claims (14)

  1. 一種半導體裝置的製造方法，包括：提供一結構，其包括一半導體基板、該半導體基板上的一磊晶源極/汲極部件、及該磊晶源極/汲極部件上的一或多個介電層；在所述一或多個介電層中蝕刻出一孔洞，以露出該磊晶源極/汲極部件的一部分，其中該孔洞的底部與該磊晶源極/汲極部件的一最寬部分對齊；形成一矽化物層於該磊晶源極/汲極部件的該部分上；形成一導電阻障層於該矽化物層上；以及對至少該導電阻障層執行一電漿清潔製程，其中該電漿清潔製程使用包括N2氣體及H2氣體的氣體混合物且在至少300℃的溫度下執行。
  2. 如請求項1之半導體裝置的製造方法，其中在至少一部分的該電漿清潔製程期間，所述N2氣體的流量與所述H2氣體的流量之比例控制在0.03至0.28。
  3. 如請求項1之半導體裝置的製造方法，其中在該電漿清潔製程期間，所述N2氣體的流量與所述H2氣體的流量之比例控制為約0.22至0.26。
  4. 如請求項1-3中任一項之半導體裝置的製造方法，其中該電漿清潔製程在300℃至500℃的溫度下執行。
  5. 如請求項1-3中任一項之半導體裝置的製造方法，更包括：沉積一金屬至該孔洞中及該導電阻障層上。
  6. 如請求項5之半導體裝置的製造方法，更包括：在所述沉積該金屬之前，沉積一第二導電阻障層於該導電阻障層上。
  7. 如請求項1-3中任一項之半導體裝置的製造方法，其中該電漿清 潔製程使用1MHz至5MHz的射頻產生的電漿，其中在該電漿清潔製程期間，所述電漿以10MHz至20MHz的另一射頻朝向該結構。
  8. 一種半導體裝置的製造方法，包括：提供一結構，其包括一基板、從該基板突出的兩個半導體鰭片、包括矽鍺的一源極/汲極部件，在所述兩個半導體鰭片上並連接至所述兩個半導體鰭片、及一或多個介電層，在所述兩個半導體鰭片及該源極/汲極部件上；在所述一或多個介電層中蝕刻出一孔洞，以露出該源極/汲極部件的一部分，其中該孔洞的底部與該源極/汲極部件的一最寬部分對齊；形成一或多個導電層於該源極/汲極部件的該部分上，其中所述一或多個導電層包括鈦；對所述一或多個導電層執行一電漿清潔製程，其中該電漿清潔製程使用由具有N2氣體及H2氣體的混合物產生的電漿且在約300℃至約400℃的溫度下執行；以及在執行該電漿清潔製程之後，沉積一金屬層至該孔洞中。
  9. 如請求項8之半導體裝置的製造方法，其中所述一或多個導電層包括一氮化鈦層。
  10. 如請求項8或9之半導體裝置的製造方法，其中在至少一部分的該電漿清潔製程期間，所述N2氣體的流量與所述H2氣體的流量之比例控制為0.03至0.28，而所述N2氣體的流量控制為每分鐘10標準立方公分(sccm)或更低。
  11. 一種半導體裝置，包括：一基板；兩個半導體鰭片，從該基板突出； 一磊晶部件，在所述兩個半導體鰭片上並連接所述兩個半導體鰭片；一矽化物層，在該磊晶部件上；一阻障層，在該矽化物層上，該阻障層具有一金屬氮化物，其中該阻障層延伸超過該磊晶部件的一最寬部分；以及一金屬層，在該阻障層上，其中沿著該阻障層與該金屬層之間的一邊界，氧與該金屬氮化物的原子比為約0.15至約1.0。
  12. 如請求項11之半導體裝置，其中該磊晶部件的一頂表面上及該磊晶部件的一側壁上的所述原子比大約相同。
  13. 如請求項12之半導體裝置，其中該磊晶部件包括矽鍺(SiGe)，該磊晶部件的該頂表面在矽鍺(001)晶面中，且該磊晶部件的該側壁在矽鍺(111)晶面中。
  14. 如請求項11或12之半導體裝置，其中沿著該邊界的該阻障層的平均厚度為3.0nm或更薄。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201937610A (zh) * 2018-03-01 2019-09-16 台灣積體電路製造股份有限公司 半導體結構
TW201946121A (zh) * 2018-04-30 2019-12-01 台灣積體電路製造股份有限公司 半導體裝置的形成方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI236092B (en) 2001-10-05 2005-07-11 Semiconductor Tech Acad Res Ct Electroless plating process, and embedded wire and forming process thereof
KR101776926B1 (ko) * 2010-09-07 2017-09-08 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR20120099863A (ko) 2011-03-02 2012-09-12 삼성전자주식회사 트랜지스터 및 그 제조 방법
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US10490459B2 (en) 2017-08-25 2019-11-26 Taiwan Semiconductor Manufacturing Co., Ltd. Method for source/drain contact formation in semiconductor devices
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8860148B2 (en) 2012-04-11 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET integrated with capacitor
US8823065B2 (en) 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8772109B2 (en) 2012-10-24 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for forming semiconductor contacts
US9236300B2 (en) 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
KR102432268B1 (ko) * 2015-04-14 2022-08-12 삼성전자주식회사 반도체 소자 및 그 제조 방법.
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US10490552B2 (en) * 2015-12-29 2019-11-26 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET device having flat-top epitaxial features and method of making the same
US10796924B2 (en) * 2016-02-18 2020-10-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof by forming thin uniform silicide on epitaxial source/drain structure
US9685439B1 (en) * 2016-05-02 2017-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10121675B2 (en) * 2016-12-29 2018-11-06 Taiwan Semiconductor Manufacturing Co., Ltd Semiconductor device and a method for fabricating the same
US10403550B2 (en) * 2017-08-30 2019-09-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and a semiconductor device
US10700177B2 (en) * 2017-09-27 2020-06-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with low resistivity contact structure and method for forming the same
US10332789B2 (en) * 2017-11-27 2019-06-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with TiN adhesion layer for forming a contact plug
US10714334B2 (en) * 2017-11-28 2020-07-14 Taiwan Semiconductor Manufacturing Co., Ltd. Conductive feature formation and structure
US11322397B2 (en) 2018-10-30 2022-05-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor devices including formation of adhesion enhancement layer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201937610A (zh) * 2018-03-01 2019-09-16 台灣積體電路製造股份有限公司 半導體結構
TW201946121A (zh) * 2018-04-30 2019-12-01 台灣積體電路製造股份有限公司 半導體裝置的形成方法

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