TW201841207A - 具有多個氮化層的裝置結構 - Google Patents

具有多個氮化層的裝置結構 Download PDF

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TW201841207A
TW201841207A TW106135070A TW106135070A TW201841207A TW 201841207 A TW201841207 A TW 201841207A TW 106135070 A TW106135070 A TW 106135070A TW 106135070 A TW106135070 A TW 106135070A TW 201841207 A TW201841207 A TW 201841207A
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layer
nitrogen
rich
dielectric layer
body region
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TW106135070A
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TWI668731B (zh
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史蒂芬 宣克
藍道爾 布勞特
傑 伯恩漢
約翰Ｊ 艾利斯蒙納翰
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美商格芯（美國）集成電路科技有限公司
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Abstract

本發明揭露場效應電晶體的裝置結構以及形成場效應電晶體的裝置結構的方法。在半導體層上形成第一介電層並氮化該第一介電層。在該第一介電層與該半導體層之間的第一界面處形成富氮層。在該半導體層與第二介電層之間的第二界面處形成另一富氮層。裝置結構可包括場效應電晶體，其包括該富氮層的其中一個、兩個以及/或者兩個都不包括。

Description

具有多個氮化層的裝置結構
本發明通常關於積體電路，尤其關於場效應電晶體的裝置結構以及形成場效應電晶體的裝置結構的方法。
互補金屬氧化物半導體(complementary-metal-oxide-semiconductor；CMOS)製程可用以構建p型場效應電晶體(PFET)與n型場效應電晶體(NFET)的組合，該些電晶體經耦接以實施邏輯門及其它類型的積體電路，例如開關。場效應電晶體通常包括主動半導體區、定義於該主動半導體區中的源極及汲極，以及與該主動半導體區中的溝道關聯的閘極電極。當在閘極電極上施加超過指定閾值電壓的控制電壓時，在源極與汲極之間的溝道中的反型或耗盡層中發生載流子流，從而產生裝置輸出電流。
絕緣體上矽(silicon-on-insulator；SOI)基板在CMOS製程中可能是有利的。與利用塊體矽晶圓構建的場效應電晶體相比，SOI基板允許電晶體以顯著較高的 速度操作，改進電性隔離並降低電性損失。依據該SOI基板的裝置層的厚度，場效應電晶體可以部分耗盡模式操作，其中，當向閘極電極施加典型的控制電壓時，該裝置層中的溝道中的耗盡層不完全延伸至埋置氧化物層。
需要改進的場效應電晶體的裝置結構以及形成場效應電晶體的裝置結構的方法。
在本發明的一個實施例中，一種方法包括在半導體層上形成第一介電層，氮化該第一介電層，在該第一介電層與該半導體層之間的第一界面處形成第一富氮層，以及在該半導體層與第二介電層之間的第二界面處形成第二富氮層。
在本發明的一個實施例中，一種方法包括在第一本體區以及通過溝槽隔離區與該第一裝置區隔開的第二本體區中的半導體層上形成介電層，以及在該第一裝置區中的該介電層與該半導體層之間以及在該第二裝置區中的該第一介電層與該半導體層之間的界面處形成富氮層。在形成該第一富氮層以後，自該第二本體區中的該半導體層移除該介電層及該富氮層。
在本發明的一個實施例中，一種結構包括：半導體層，具有第一本體區及第二本體區；溝槽隔離區，將該半導體層的該第一本體區與該半導體層的該第二本體區隔開；第一場效應電晶體，包括形成於該第一本體區中的該半導體層上的第一介電層；第二場效應電晶體，包括 形成於該第二本體區中的該半導體層上的第二介電層；以及富氮層，位於該第一本體區中的該第一介電層與該半導體層之間的第一界面處。在該第二本體區中的該第二介電層與該半導體層之間不具有該富氮層。
10‧‧‧基板
12‧‧‧裝置層
14‧‧‧埋置氧化物層、BOX層
15、25‧‧‧界面
16‧‧‧操作晶圓
18‧‧‧屏蔽氧化物層
19、21、23‧‧‧本體區
20‧‧‧溝槽隔離區
22‧‧‧基礎介電層
24、26‧‧‧富氮層
28‧‧‧介電層、基礎介電層
29、31‧‧‧介電材料的部分、部分
30‧‧‧介電層
36、38、40‧‧‧裝置結構
37‧‧‧複合閘極介電質、閘極介電質、氮化閘極介電質
39‧‧‧閘極介電質
41‧‧‧閘極介電質
42‧‧‧閘極電極
44‧‧‧重摻雜抬升式源/汲區、源/汲區
46‧‧‧阱區
48‧‧‧非導電間隙壁
50‧‧‧注入遮罩
52‧‧‧含氮離子、離子
54、58‧‧‧富氮層
56‧‧‧基礎介電層、介電層、氮化基礎介電層
60‧‧‧介電層
61‧‧‧介電材料的部分、部分
包含於並構成本說明書的一部分的圖式說明本發明的各種實施例，並與上面所作的本發明的概括說明以及下面所作的實施例的詳細說明一起用以解釋本發明的實施例。
第1至5圖顯示依據本發明的實施例處於製程的連續階段中的基板的部分的剖視圖。
第6至8圖顯示依據本發明的實施例處於製程的連續階段中的基板的部分的剖視圖。
請參照第1圖並依據本發明的一個實施例，以絕緣體上矽(SOI)基板為代表形式的基板10包括裝置層12，採用由矽的氧化物(例如，SiO2)組成的埋置氧化物(buried oxide；BOX)層14的形式的埋置介電層，以及操作晶圓16。裝置層12及BOX層14終止於操作晶圓16的邊緣。裝置層12通過中間的BOX層14與操作晶圓16隔開且遠比操作晶圓16薄。裝置層12通過BOX層14與操作晶圓16電性隔離。裝置層12與操作晶圓16可由單晶半導體材料組成，例如矽。BOX層14具有沿界面15與裝置層12直接接觸的表面以及沿另一個界面與操作晶圓 16直接接觸的另一個表面，且這些表面通過BOX層14的厚度隔開。操作晶圓16可經輕摻雜以具有例如p型導電性。
在裝置層12的頂部表面上形成屏蔽氧化物層18。在裝置層12中注入p阱及n阱期間，屏蔽氧化物層18保護裝置層12的頂部表面。溝槽隔離區20形成於裝置層12中，並將裝置層12劃分為本體區19、21、23。通過沉積介電材料以填充溝槽並利用例如化學機械拋光(chemical-mechanical polishing；CMP)相對屏蔽氧化物層18的頂部表面平坦化該介電材料，可形成溝槽隔離區20。包括溝槽隔離區20的該介電材料可為電性絕緣體，例如通過化學氣相沉積(chemical vapor deposition；CVD)沉積的矽的氧化物(例如，二氧化矽(SiO2))。
請參照第2圖，其中類似的元件符號表示第1圖中類似的特徵，且在下一製造階段，在裝置層12中注入所述p阱及n阱(未顯示)以後可剝離屏蔽氧化物層18。在所有本體區19、21、23中的裝置層12的頂部表面上形成基礎介電層22。基礎介電層22可由介電材料構成，例如二氧化矽(SiO2)，其通過氧化裝置層12的頂部表面生長或通過CVD沉積。基礎介電層22沿界面25接觸裝置層12的本體區19、21、23。
氮化基礎介電層22，以通過氮化製程沿其厚度向該構成介電材料添加氮成分。氮可不均勻地分佈於基礎介電層22的塊體上，且經氮化的基礎介電層22可包括富氮層24、26，其與基礎介電層22的塊體的其餘部分相 比包含較高峰值濃度的氮。由於擴散期間在界面25處的氮累積，在基礎介電層22與裝置層12之間的界面25處形成具有較高峰值氮濃度的富氮層24。由於擴散期間在界面15處的氮累積，在裝置層12與BOX層14之間的界面15處形成具有較高峰值氮濃度的富氮層26。富氮層24可全部或部分位於界面25處的基礎介電層22中以及/或者全部或部分位於界面25處的裝置層12中。富氮層26可全部或部分位於界面15處的裝置層12中以及/或者全部或部分位於界面15處的BOX層14中。
為形成富氮層24、26，可將基板10置於包括富氮源氣體(例如，氨氣(NH3))的氣氛中並加熱至足以將氮從該富氮源氣體引入基礎介電層22中並擴散的溫度(例如，855℃至1150℃)。富氮層26通過經由裝置層12至與BOX層14的界面的氮擴散形成。擴散氮往往聚集於介電與半導體材料之間的界面15、25處，從而導致以較高峰值濃度的氮為特徵的富氮層24、26的形成。在該氮化製程之後可接著執行在例如900℃的溫度下的氧化製程，以減少富氮層24、26中的陷阱並由此改進其介電屬性。
請參照第3圖，其中類似的元件符號表示第2圖中類似的特徵，且在下一製造階段，自本體區21及本體區23中的裝置層12移除基礎介電層22及富氮層24。可施加光阻層(未顯示)，對其光刻圖案化，並接著將其作為蝕刻遮罩用於使用例如包含氫氟酸(HF)的濕化學溶液的等向性蝕刻，以相對裝置層12的半導體材料選擇性移除 本體區21及23中的基礎介電層22及富氮層24的介電材料。本文中所使用的關於材料移除製程(例如，蝕刻)的術語“選擇性”表示目標材料的材料移除速率(也就是，蝕刻速率)高於暴露於該材料移除製程的至少另一種材料的材料移除速率(也就是，蝕刻速率)。保留與本體區21關聯的富氮層26以及與本體區23關聯的富氮層26。也保留與本體區19關聯的基礎介電層22及富氮層24，以及富氮層26。
在移除基礎介電層22的本體區21中及本體區23中的裝置層12的頂部表面上形成介電層28。介電層28可由介電材料構成，例如通過CVD沉積的二氧化矽(SiO2)。構成介電層28的該介電材料的部分29也可形成于本體區19中的基礎介電層22的頂部表面上。可接著執行在例如900℃的溫度下的氧化製程，以改進介電層28的介電屬性。
請參照第4圖，其中類似的元件符號表示第3圖中類似的特徵，且在下一製造階段，自本體區23中的裝置層12移除介電層28。在本體區21中的裝置層12上保留基礎介電層28且在本體區19中保留介電材料的部分29。可施加光阻層(未顯示)，對其光刻圖案化，並接著將其作為蝕刻遮罩用於使用例如包含氫氟酸(HF)的濕化學溶液的等向性蝕刻，以相對裝置層12的半導體材料選擇性移除本體區23中的介電層28的介電材料。
在移除介電層28的本體區23中的裝置層12 的頂部表面上形成介電層30。介電層30可由通過CVD沉積的電性絕緣體例如二氧化矽(SiO2)構成。在一個實施例中，介電層28、30可由相同的介電材料構成，且介電層30可具有小於介電層28的厚度的厚度。介電層30的部分31也可形成于本體區21中的介電層28的頂部表面上，以及本體區19中的基礎介電層22的頂部表面上。可接著執行在例如900℃的溫度下的氧化製程，以改進介電層30的介電屬性。
請參照第5圖，其中類似的元件符號表示第4圖中類似的特徵，且在下一製造階段，通過將裝置層12的相關部分用作半導體本體，在不同的本體區19、21、23中可分別形成裝置結構36、38、40。裝置結構36、38、40可為場效應電晶體，其包括閘極電極42以及鄰近閘極電極42形成於該半導體本體中的重摻雜抬升式源/汲區44。源/汲區44通過阱區46隔開，該阱區定義位於各半導體本體中並位於閘極電極42下方的溝道。構成阱區46的半導體材料可經摻雜以具有與包含於源/汲區44中的半導體材料的導電類型相反的導電類型。
閘極電極42由導體構成，例如金屬、摻雜多晶矽、金屬矽化物，或這些及其它導電材料的層式堆疊。可通過向裝置層12的半導體材料中注入或擴散合適的摻雜物(例如針對n型導電性的第V族摻雜物如砷(As)或磷(P)或針對p型導電性的第III族摻雜物如硼(B))以自對準方式形成源/汲區44。裝置結構40可包括其它組成 部分例如環狀區、輕摻雜汲極(lightly doped drain；LDD)延伸區等。在閘極電極42的垂直側壁上可形成非導電間隙壁48。
裝置結構36具有複合閘極介電質37，其包括基礎介電層22、富氮層24、介電材料的部分29，以及介電材料的部分31。裝置結構36的閘極介電質37是具有氮化區的較厚閘極介電質，可適合用於例如開關中的低導通電阻(Ron)場效應電晶體。通過形成由富氮層24、26表示的多個氮化物界面，可在保持高結擊穿及低漏電流的同時實現Ron的降低。該氮化物界面的其中之一位於閘極介電質37與由裝置層12及BOX層14的關聯部分提供的矽本體之間，且另一個氮化界面位於矽本體與BOX層14之間。
與裝置結構36的氮化閘極介電質37相比，裝置結構38及40具有非氮化閘極介電質。裝置結構38具有閘極介電質39，其包括介電層28以及介電材料的部分31。裝置結構38(其中，閘極介電質39也為厚閘極介電質，但不具有富氮層24)可適於構造例如位於本體區21中的p型場效應電晶體。裝置結構40具有閘極介電質41，其包括介電層30的圖案化部分。裝置結構40(包括不具有富氮層24的較薄閘極介電質)可適於例如製造用於低電壓邏輯的場效應電晶體。不同裝置結構36、38、40的閘極電極42及下方的閘極介電質37、39、41可通過在不同的閘極層上沉積用以形成閘極電極42的材料層並通過光刻 及蝕刻圖案化相應的閘極電極42及下方的閘極層來形成。在其中形成裝置結構38、40的本體區21、23中保留富氮層26。
具有氮化閘極介電質的裝置結構36可為用於開關例如RF應用的開關中的場效應電晶體。具有非氮化閘極介電質的裝置結構38及40可用於與場效應電晶體關聯的其它類型的應用(例如，具有厚閘極介電質或低電壓邏輯的p型場效應電晶體)。裝置結構38及40位於不同於裝置結構36的本體區19的裝置層12的本體區21、23中。
接著執行矽化、中間工藝(middle-of-line；MOL)及後端工藝(back-end-of-line；BEOL)製程，其包括形成局部互連結構的接觸及線路，以及形成介電層、過孔塞，以及線路，以供互連結構通過該互連線路與裝置結構36、38、40耦接。
一般來說，介電材料的氮化以及尤其氧化物的氮化具有多種益處及效果。在固定漏電流下的場效應電晶體的閾值電壓可因正的固定電荷及較高的介電常數而降低。場效應電晶體的寄生npn擊穿電壓可通過降低從阱至BOX層的摻雜物離析(例如，自p阱的硼離析)來降低。p型場效應電晶體的連接電阻(link resistance)可通過降低從該場效應電晶體的延伸區至BOX層的摻雜物(例如，硼)離析來降低。可降低矽化及中間工藝製程之前發生的預清洗期間的STI(淺溝槽隔離)下拉，從而因在本體及 閘極電極下方的矽化物的存在而可防止漏電流。介電材料的氮化(例如，氧化物氮化)也可降低來自後閘極注入的摻雜物(例如，硼)的滲透，在p型場效應電晶體的情況下，該後閘極注入往往反摻雜阱區。
請參照第6圖，其中類似的元件符號表示第1圖中類似的特徵，且依據替代實施例，在屏蔽氧化物層18的頂部表面上形成注入遮罩50。注入遮罩50可包括光阻層，其通過旋塗製程作為塗層施加、經預烘烤、曝光於通過光遮罩投射的光、在曝光後烘烤，以及通過化學顯影劑顯影以形成開口，從而在掩蔽本體區21及23的同時暴露本體區19。在注入遮罩50中的該開口的位置處，以選定的注入條件通過離子注入向本體區19中的裝置層12上的屏蔽氧化物層18中引入含氮離子52。富氮層54形成有深度分佈，其包括鄰近屏蔽氧化物層18與裝置層12之間的界面的峰值劑量(也就是，峰值濃度)。富氮層54至少部分(較佳地全部)位於屏蔽氧化物層18下方的裝置層12中。
用以形成富氮層54的離子52可自含氮的合適源氣體生成並利用離子注入工具注入。注入條件(例如，離子種類、劑量、動能、入射角)經選擇以在由注入遮罩50中的開口定義的位置處以給定的濃度分佈提供離子。該含氮離子被注入遮罩50阻止，從而不注入被掩蔽的本體區21及23。氮的峰值劑量可大於5x1014原子/平方釐米(原子/cm2)，鑒於這樣的離子劑量有效降低p型場效應電晶體 的負偏置溫度不穩定性(NBTI)退化，這被認為有效降低導通電阻(Ron)。
請參照第7圖，其中類似的元件符號表示第6圖中類似的特徵，且在下一製造階段，自所有本體區19、21、23中的裝置層12移除屏蔽氧化物層18。當移除屏蔽氧化物層18時，在裝置層12中保留富氮層54。在一個實施例中，當移除屏蔽氧化物層18時，可保留全部富氮層54。
在本體區19、21、23中的裝置層12的頂部表面上形成基礎介電層56。基礎介電層56可由介電材料組成，例如通過氧化裝置層12的頂部表面生長或通過CVD沉積的二氧化矽(SiO2)。富氮層54位於裝置層12與基礎介電層56之間的界面25處。
由於與基礎介電層56的生長關聯的溫度驅動擴散，氮自富氮層54垂直擴散進入基礎介電層56中並且還進入本體區19中的裝置層12中。本體區19中的基礎介電層56被擴散的氮成分氮化。本體區19中的裝置層12可包括濃度呈梯度的在富氮層54與富氮層58之間的氮成分。在一個實施例中，裝置層12中的梯度氮濃度可沿從界面25處的富氮層54朝向界面15的方向的距離增加而降低，從而梯度最大氮濃度位於靠近界面25的裝置層12中且梯度最小氮濃度位於靠近界面15的裝置層12中。由於擴散期間在界面15處的累積，具有峰值氮濃度的富氮層58形成于本體區19中的裝置層12與BOX層14之間的界 面15處。富氮層58可全部或部分位於界面15處的裝置層12中以及/或者全部或部分位於界面15處的BOX層14中。橫向氮擴散被中間的溝槽隔離區20阻擋，從而本體區21及23不包括富氮區54、58的其中任意一個。
請參照第8圖，其中類似的元件符號表示第7圖中類似的特徵，且在下一製造階段，自本體區23中的裝置層12的頂部表面移除基礎介電層56。可施加光阻層(未顯示)，對其光刻圖案化，並接著將其作為蝕刻遮罩用於使用例如包含氫氟酸(HF)的濕化學溶液的等向性蝕刻，以相對本體區23中的裝置層12的半導體材料選擇性移除基礎介電層56的介電材料。自本體區23移除基礎介電層56以後剝離該蝕刻遮罩。
在移除基礎介電層56的本體區23中的裝置層12的頂部表面上形成介電層60。介電層60可由電性絕緣體組成，例如通過CVD沉積的二氧化矽(SiO2)。在一個實施例中，介電層56、60可由相同的介電材料組成，且介電層60可具有小於基礎介電層56的厚度的厚度。
介電層60的介電材料的部分61也形成于本體區21中的基礎介電層56的頂部表面上，以及本體區19中的富氮層54上方的氮化基礎介電層56的頂部表面上。可接著執行在例如900℃的溫度下的氧化製程，以改進介電材料的這些部分61的介電屬性。
該製程繼續如第5圖的上下文中所述，以形成裝置結構36、38、40。
如上所述的方法用於積體電路芯片的製造中。製造者可以原始晶圓形式(例如作為具有多個未封裝芯片的單個晶圓)、作為裸芯片，或者以封裝形式分配所得的積體電路芯片。在後一種情況中，該芯片設于單芯片封裝件中(例如塑料承載件，其具有附著至母板或其它更高層次承載件的引腳)或者多芯片封裝件中(例如陶瓷承載件，其具有單面或雙面互連或嵌埋互連)。在任何情況下，可將該芯片與其它芯片、分立電路元件和/或其它信號處理裝置集成，作為中間產品或最終產品的部分。
本文中引用術語例如“垂直”、“水平”等作為示例來建立參考框架，並非限制。本文中所使用的術語“水平”被定義為與半導體基板的傳統平面平行的平面，而不論其實際的三維空間取向。術語“垂直”及“正交”是指垂直於如剛剛所定義的水平面的方向。術語“橫向”是指在該水平平面內的維度。術語例如“上方”及“下方”用以表示元件或結構相對彼此的定位，而不是相對標高。
與另一個元件“連接”或“耦接”的特徵可與該另一個元件直接連接或耦接，或者可存在一個或多個中間元件。如果不存在中間元件，則特徵可與另一個元件“直接連接”或“直接耦接”。如存在至少一個中間元件，則特徵可與另一個元件“非直接連接”或“非直接耦接”。
對本發明的各種實施例所作的說明是出於說明目的，而非意圖詳盡無遺或限於所揭露的實施例。許多修改及變更對於所屬技術領域中具有通常知識者將顯而易 見，而不背離所述實施例的範圍及精神。本文中所使用的術語經選擇以最佳解釋實施例的原理、實際應用或在市場已知技術上的技術改進，或者使所屬技術領域中具有通常知識者能夠理解本文中所揭露的實施例。

Claims (20)

  1. 一種方法，包括：在半導體層上形成第一介電層；氮化該第一介電層；在該第一介電層與該半導體層之間的第一界面處形成第一富氮層；以及在該半導體層與第二介電層之間的第二界面處形成第二富氮層。
  2. 如申請專利範圍第1項所述之方法，其中，該半導體層是絕緣體上矽基板的裝置層，且該第二介電層是該絕緣體上矽基板的埋置氧化物層。
  3. 如申請專利範圍第1項所述之方法，其中，該第二介電層通過該半導體層與該第一介電層隔開。
  4. 如申請專利範圍第1項所述之方法，其中，當氮化該第一介電層時形成該第一富氮層。
  5. 如申請專利範圍第4項所述之方法，其中，當氮化該第一介電層時形成該第二富氮層。
  6. 如申請專利範圍第4項所述之方法，其中，氮化該第一介電層包括：在該第一介電層暴露于包括富氮源氣體的氣氛的情況下加熱該第一介電層，其中，通過自該氣氛向該第一介電層及該半導體層中擴散氮並在該第一界面及該第二界面處累積該氮來形成該第一富氮層及該第二富氮層。
  7. 如申請專利範圍第6項所述之方法，其中，加熱期間的溫度在從855℃到1150℃的範圍內變化。
  8. 如申請專利範圍第1項所述之方法，其中，在形成該第一介電層之前形成該第一富氮層。
  9. 如申請專利範圍第8項所述之方法，其中，在該第一介電層與該半導體層之間的該第一界面處形成該第一富氮層包括：在該半導體層上形成屏蔽氧化物層；以及通過經由該屏蔽氧化物層的注入來形成該第一富氮層。
  10. 如申請專利範圍第9項所述之方法，更包括：在形成第一富氮層以後，移除該屏蔽氧化物層，其中，當形成該第一介電層時定義該第一界面。
  11. 如申請專利範圍第10項所述之方法，其中，當形成該第一介電層時，通過經由該半導體層至該第二界面的擴散來形成該第二富氮層。
  12. 如申請專利範圍第9項所述之方法，其中，當形成該第一介電層時，通過自該第一富氮層的擴散來氮化該第一介電層。
  13. 如申請專利範圍第12項所述之方法，其中，該半導體層包括自該第一富氮層起呈梯度濃度的氮，且呈該梯度濃度的該氮隨著從該第一界面沿朝向該第二界面的方向的距離增加而降低。
  14. 一種方法，包括： 在第一本體區以及通過溝槽隔離區與該第一本體區隔開的第二本體區中的半導體層上形成第一介電層；在該第一本體區中的該第一介電層與該半導體層之間以及在該第二本體區中的該第一介電層與該半導體層之間的第一界面處形成第一富氮層；以及在形成該第一富氮層以後，自該第二本體區中的該半導體層移除該第一介電層及該第一富氮層。
  15. 如申請專利範圍第14項所述之方法，更包括：在自該第二本體區中的該半導體層移除該第一介電層及該第一富氮層以後，在該第二本體區中的該半導體層上形成第二介電層。
  16. 如申請專利範圍第14項所述之方法，更包括：在該第一本體區及該第二本體區中的該半導體層與第二介電層之間的第二界面處形成第二富氮層。
  17. 如申請專利範圍第16項所述之方法，其中，當自該第二本體區中的該半導體層移除該第一介電層及該第一富氮層時，在該第二本體區中的該半導體層與該第二介電層之間的該第二界面處保留該第二富氮層。
  18. 如申請專利範圍第16項所述之方法，其中，通過在該第一介電層暴露于包括富氮源氣體的氣氛的情況下加熱該第一介電層來形成該第一富氮層及該第二富氮層，以及通過自該氣氛向該第一介電層及該半導體層中擴散氮並在該第一界面及該第二界面處累積來形成該第一富氮層及該第二富氮層。
  19. 一種裝置結構，包括：半導體層，包括第一本體區及第二本體區；溝槽隔離區，將該半導體層的該第一本體區與該半導體層的該第二本體區隔開；第一場效應電晶體，包括形成於該第一本體區中的該半導體層上的第一介電層；第二場效應電晶體，包括形成於該第二本體區中的該半導體層上的第二介電層；以及第一富氮層，位於該第一本體區中的該第一介電層與該半導體層之間的第一界面處，其中，在該第二本體區中的該第二介電層與該半導體層之間不具有該第一富氮層。
  20. 如申請專利範圍第19項所述之裝置結構，其中，該半導體層是絕緣體上矽基板的裝置層，且更包括：第二富氮層，位於該第一本體區中及該第二本體區中的該絕緣體上矽基板的該半導體層與埋置氧化物層之間的第二界面處。
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