TW201830662A - 用於多層級互連的半導體晶圓之同軸連接器饋通 - Google Patents

用於多層級互連的半導體晶圓之同軸連接器饋通 Download PDF

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TW201830662A
TW201830662A TW106120790A TW106120790A TW201830662A TW 201830662 A TW201830662 A TW 201830662A TW 106120790 A TW106120790 A TW 106120790A TW 106120790 A TW106120790 A TW 106120790A TW 201830662 A TW201830662 A TW 201830662A
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insulating layer
bottom oxide
layer
electrical
silicon
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約翰 德拉布
瑪莉 手柴
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雷森公司
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Abstract

一種半導體的氧化物上矽(SOI；silicon-on-oxide)結構，具有配置在底部氧化物(BOX；bottom oxide)絕緣層上的矽層。深凹槽隔離(DTI；deep trench isolation)材料垂直地通過矽層到底部氧化物隔離層。深凹槽隔離材料具有比矽的電容率(permittivity)更低的電容率。具有內部電導體及外部導電屏蔽結構的同軸傳輸線已配置在垂直通過深凹槽隔離材料的內部電導體周圍，用以將配置在底部氧化物絕緣層之上的電導體電性連接至配置在接觸底部氧化物絕緣層之下的電導體。

Description

用於多層級互連的半導體晶圓之同軸連接器饋通
此揭露一般關於多層級互連的半導體晶圓，且更特別的是關於使用以將在互連的晶圓之間的射頻(RF；radio frequency)能量互連的同軸連接器。
如在本領域已知的，往往想要將一對重疊的、接合的半導體晶圓之間的高頻能量(像是射頻(RF)或微波能量)耦合。此有時被稱為三維(3D)整合，例如請見：由Chen-Ta Ko、Kuan-Neng Chen在Microelectronics Reliability 53(2013)7-17上名為「Reliability of key technologies in 3D integration」的刊物；由Enquist等人在978-1-4244-4512 2009 IEEE上名為「Low Cost of Ownership Scalable Copper Direct Bond Interconnected 3D IC Technology for Three Dimensional Integrated Circuit Applications」的刊物；以及由P.Chang-Chien等人在2007 年5月於日本松江市的2007關於磷化銦及相關材料之國際會議18中名為「MMIC Compatible Wafer-Level Packaging Technology」的刊物。
如在本領域中所知，在許多應用中所欲的是，在3D整合中透過矽載體晶圓提供同軸屏蔽，如在由Ho等人於2006電子封裝技術會議825~830頁名為「Development of Coaxial Shield Via in Silicon Carrier for High Frequency Application」的刊物所述。
亦如在本領域所知，由David A.Wikner,Arttu R.Luukanen在Proc.of SPIE Vol.8715,871505．©2013 SPIE．CCC code中編輯的Arjun Kar-Roy等人之名為「Recent developments using TowerJazz SiGe BiCMOS platform for mmWave and THz applications」的刊物：0277-786X/13/$18 doi：10.1117/12.1518475報導在鍺化矽(SiGe)BiCMOS技術中形成射頻通孔。亦請見Hurwitz；Paul D.等人於2014年2月27日公開名為「Isolated Through Silicon Vias in RF Technologies」之美國專利申請公開案第2014/0054743號。
亦在本領域已知的，較大直徑銅填充通孔係透過相對厚的矽層來形成。由於矽基板之導電性，此造成在這些高頻能量上的高損耗。另一個使用的方法包括使用小的鎢填充通孔；然而，在當此方法對於高密度3D互連是適宜的時，其未將場局限而足以生成具有低高頻電量損耗的通孔。
依據本揭露，半導體、氧化物上矽(SOI；silicon-on-oxide)結構被提供具有配置在底部氧化物(BOX；bottom oxide)絕緣層上的矽層。深凹槽隔離(DTI；deep trench isolation)材料垂直地通過矽層到底部氧化物隔離層。深凹槽隔離材料具有比矽的電容率/介電常數(permittivity)更低的電容率。具有內部電導體及配置在內部電導體周圍的外部導電屏蔽結構的同軸傳輸線，其垂直地通過深凹槽隔離材料的，用以將配置在底部氧化物絕緣層之上的電導體電性連接至配置在接觸底部氧化物絕緣層之下的電導體。
發明人已認知的是，藉由讓同軸傳輸線通過較低電容率底部氧化物絕緣層而非通過矽，當通過底部氧化物絕緣層而非矽層時將會有較少信號傳輸損耗，因為底部氧化物絕緣層將在內部導體與外部導體屏蔽結構之間提供較低耗損介電質。進一步，發明人已認知的是，使用通過DTI材料的同軸傳輸線使能使用非常薄的矽層以為了最大化在矽層中形成的積體電路之功能密度，並且藉由將同軸傳輸線放置到具有相較於矽非常低導電性和損耗正切(loss tangent)的氧化物((DTI)材料)中來最小化通過通孔的損耗。使用SOI簡化了結構的構造，其將整合簡化成積體3D RF裝置。
在一實施例中，半導體、氧化物上矽(SOI；silicon-on-oxide)結構被提供具有配置在底部氧化物(BOX； bottom oxide)絕緣層上的矽層。矽層已在其中形成一對互補式金屬氧化物半導體(CMOS；complementary metal oxide semiconductor)電晶體，此電晶體藉由垂直通過矽層到底部氧化物隔離層的深凹槽隔離(DTI)材料將一者與該另一者電隔離。深凹槽隔離材料具有比矽的電容率(permittivity)更低的電容率。具有內部電導體及配置在內部電導體周圍的外部導電屏蔽結構的同軸傳輸線，其垂直地通過深凹槽隔離材料的，用以將配置在底部氧化物絕緣層之上的電導體電性連接至配置在接觸底部氧化物絕緣層之下的電導體。
在一實施例中，內部導體和外部導體屏蔽結構的外部為化學汽相沉積(CVD)的鎢。
在一實施例中，外部導體屏蔽結構包含複數個隔開的電導體，其將一者與另一者分開了小於同軸傳輸線之工作波長(operating wavelength)的四分之一波長，因而提供用於外部導體屏蔽結構的電連續導體。
以這樣的安排，使用氧化物上矽(SOI)開始結構來生成電晶體，其使用深凹槽隔離(DTI)來被隔離。形成夠大的DTI以用於要接著透過DTI材料形成的複數個通孔。藉由通過DTI材料及SIO埋入氧化物(BOX；buried oxide)層以的第一蝕刻及隨後使用化學汽相沉積(CVD)的鎢填充通孔來形成複數個通孔。這些複數個通孔以這類如以創建同軸或「假同軸(pseudo-coaxial)」結構的方式來排陣列(在外部導體屏蔽結構的含意上的「假同軸」並非實 體連續的導體而相反的是一者與另一者分開了小於導體之工作波長的四分之一的複數個隔開的導體，因而提供用於外部導體的電連續導體)。假同軸結構係設想為用以創建真同軸形狀之電特性的方法，以在不引起一些與CVD鎢填充有關的實際問題下傳播RF或微波能量。垂直鎢導體被連接至積體電路(IC)之第一金屬層。導電通孔之低部可藉由使用BOX層上的蝕刻停止移除半導體結構之基板晶圓來接入，且從而透過在用於直接接合混合(Direct Bond Hybridization)或其它三維(3D)堆疊技術(像是Cu熱壓縮或超音波接合)的DTI材料之底部上的導體揭示。
本揭露之一或多個實施例之細節在以下隨附的圖式及說明中提出。本揭露之其它特徵、目標及益處將自說明及圖式且自申請專利範圍來看是清楚明白的。
1‧‧‧控制信號輸入
2‧‧‧控制信號輸入
10‧‧‧二級對成CMOS放大器
10a‧‧‧CMOS電路
10b‧‧‧CMOS電路
11‧‧‧前端製程(FEOL)結構
12a‧‧‧上結構
12b‧‧‧下結構
14a‧‧‧nMOS場效電晶體
14b‧‧‧pMOS場效電晶體
14c‧‧‧nMOS場效電晶體
14d‧‧‧nMOS場效電晶體
16‧‧‧同軸傳輸線
16c‧‧‧內部電導體
16o‧‧‧外部電導屏蔽結構
18‧‧‧同軸傳輸線
18a‧‧‧同軸傳輸線
18a'‧‧‧同軸傳輸線之部分
18b‧‧‧同軸傳輸線之部分
18c‧‧‧內部電導體
18o‧‧‧外部電導屏蔽結構
18'o‧‧‧通孔
18'c‧‧‧通孔
20‧‧‧同軸傳輸線
20c‧‧‧內部電導體
20o‧‧‧外部電導屏蔽結構
22‧‧‧接地匯流排
28‧‧‧閘極氧化物層
30‧‧‧柄部
32‧‧‧底部氧化物(BOX)層
34‧‧‧矽層
36‧‧‧深凹槽隔離(DTI)區域
38‧‧‧閘極氧化物層
41‧‧‧通孔
41o‧‧‧通孔
41c‧‧‧通孔
41'o‧‧‧接觸墊
41'c‧‧‧接觸墊
42‧‧‧通孔
43‧‧‧通孔
44‧‧‧通孔
45‧‧‧通孔
45'‧‧‧接觸墊
46‧‧‧通孔
47‧‧‧電互連
48‧‧‧第一電互連介電質(ILD)結構
50‧‧‧第二電互連介電質(ILD)結構
51‧‧‧平面外導體
53‧‧‧中央孔
59‧‧‧電導體
60‧‧‧電連接器
62‧‧‧同軸接地墊
63‧‧‧垂直導電通孔
65‧‧‧中央導體
70‧‧‧通孔
72‧‧‧通孔
73‧‧‧柄部
74‧‧‧通孔
76‧‧‧接合氧化物
84a‧‧‧墊
84b‧‧‧墊
84o‧‧‧墊
84c‧‧‧墊
84d‧‧‧墊
84'a‧‧‧墊
84'b‧‧‧墊
84'o‧‧‧墊
84'c‧‧‧墊
84'd‧‧‧墊
85‧‧‧中央孔
圖1為依據本揭露之二級成對CMOS放大器電路之示意圖；圖2繪示依據本揭露圖2A及圖2B之安排，其綜合在一起為圖1之二級成對CMOS放大器電路之圖解的、剖面略圖；以及圖3A~3H為依據本揭露圖1及2之二級成對CMOS放大器電路之部分在其之製造中各種階段上、在其之製造過程中各種階段上之圖解的、剖面略圖；圖3D'為在圖3D中繪示的結構之部分的分解視圖；圖3G'為在圖3G 中繪示的結構之部分的分解視圖；圖3G"為圖3G'之頂部視圖且圖3G"為圖3G'之底部視圖。
在各種圖式中相似的參考符號指的是相似的元件。
現參照圖1，繪示二級對成CMOS放大器10之示意圖以包括第一級CMOS電路10a，如所繪示，其具有耦接至第第二級CMOS電路10b的輸出。CMOS電路10a、10b之各一者形成在如繪示成對堆疊的、直接接合的結構12a、12b之分別對應者上；上結構(層1)12a和下結構(層2)12b。第一級CMOS電路10a包括nMOS FET 14a，其具有透過同軸傳輸線16(有時稱為同軸(coax)，16)由RF輸入信號饋入(feed)的閘極(G)；如所繪示，汲極(D)連接至Vdd電壓供應且源極(S)連接至pMOS FET 14b之汲極(D)。如所指示的，pMOS FET 14b之閘極(G)係由控制信號輸入1饋入。nMOS FET 14a之源極對於第一級CMOS電路10a提供輸出且透過同軸傳輸線18來連接(有時稱為同軸，18)。同軸傳輸線18連接至第二級CMOS電路10b之輸入。更特別的是，如所繪示，於此電路10a之nMOS FET的源極透過同軸連接器18耦接至電路10b之nMOS FET 14c的閘極(G)。如所繪示，電路10b之nMOS FET 14c的汲極(D)連接至Vdd，且如所繪示，源極(S)連接至電路10b之nMOS FET 14d之汲極(D)。如所繪示，nMOSFET 14d之閘極(G) 連接至控制信號輸入2，並且如所繪示，電路10b之nMOS FET 14d的源極(S)提供二級放大器電路10之RF輸出，這類輸出透過同軸傳輸線20來耦接(有時稱為同軸，20)。要注意的是，如所繪示，第一及第二電路10a及10b之n通道電晶體的基體(body)連接至地，並且p通道電晶體之基體綁定至Vdd。或者，電晶體基體可以綁定至如常在SOI類比電路上完成的源極連接。亦應注意的是，同軸傳輸線16、18及20其各者分別的內部電導體16c、18c及20c，以及分別的接地外部電導屏蔽(electrically conductive shield)結構16o、18o及20o，其如所指示的分別配置在內部電導體16c、18c及20c周圍。在此範例中，如將於此說明的，外部電導屏蔽結構具有複數個隔開的電導體，其將一者與另一者分開了小於同軸傳輸線之工作波長(operating wavelength)的四分之一波長，因而提供用於外部導體屏蔽結構的電連續導體。然而，應了解的是，外部電導屏蔽結構可為連續電導體。
現請參照圖2、2A及2B，繪示了二級成對CMOS放大器電路10之圖解的、剖面略圖。首先請注意，同軸傳輸線18之一部分，部分18a係形成在層12a之低部部分中且另一部分18b係形成在層12b的上面部分中。亦要注意的是，對同軸傳輸線16、18及20之電導屏蔽結構的外部之連接係藉由要進行說明的垂直導電通孔以及藉由平面外接地匯流排(out-of-plane ground bus)22來互連，並且如所指示的連接至地。
現參照圖3A~3H，已形成於其中的積體電路之部分(成對的CMOS電路10之一者)，於此為電路10a，繪示於圖3A中。電路10a係使用傳統SOI前端製程(FEOL；front end of line)柄部30來形成，於此例如為矽晶圓。FEOL結構11包括BOX層32(於此為二氧化矽)，其在柄部30之上表面上形成。矽之層34係形成在BOX層32上；矽層34合適地摻雜以使用傳統處理在其中形成nMOS電晶體14a和pMOS電晶體14b。如所繪示，使用任何傳統的技術在矽層34之部分上形成閘極氧化物層38。如所繪示，使用傳統的光刻蝕刻處理分別在nMOS及pMOS電晶體12a、12b之閘極氧化物層28之上形成閘極(G)電極40。
接著，參照圖3B，如所繪示，CMOS電晶體14a、14b藉由深凹槽隔離(DTI；deep trench isolation)區域36(於此為使用傳統處理的電漿輔助化學氣相沉積(PECVD；Plasma Enhanced Chemical Vapor Deposition)四乙基正矽酸鹽(TEOS；Tetraethylorthosilicate))來與彼此絕緣且與其它部分及電元件絕緣；深凹槽隔離區域36自矽層34之頂部延伸下至BOX層32。要注意的是，深凹槽隔離材料36具有比矽34的電容率(permittivity)更低的電容率。於此，TEOS之相對電容率(relative permittivity)為3.9且矽層34之相對電容率為11.9。因此，具有通過較低電容率DTI 36而非通過矽層34的同軸傳輸線18a(圖2)，當通過DTI層36時將有比矽層34更低的信號傳輸損耗，因為DTI 36將提供在內部導體與外部導體屏蔽結構之間的介電質。 進一步，使用通過DTI材料36的同軸傳輸線使能使用非常薄的矽層34以為了最大化在矽層中形成的積體電路之功能密度，並且藉由將同軸傳輸18、20線放置到具有相較於矽非常低導電性和損耗正切(loss tangent)的氧化物((DTT)材料36)中來最小化通過通孔的損耗。使用SOI簡化了結構的構造，其將整合簡化成積體3D RF裝置。如在圖3B中所繪示，鈍化層(passivation layer)、介電層44(於此例如為氮化矽)係形成在DTI區域36之上。
接著，參照圖3C，形成同軸傳輸線18之部分18a'。首先，複數個電導通孔18'o於此在具有使用光刻蝕刻(photolithographic-etching)技術的中央導電通孔18'c的導電通孔之圓形陣列中以預定的圖型來形成。接著，通孔開口係使用CVD以鎢來填充以形成內部、或中央電導體18'c和外部電導屏蔽結構18'o；外部電導屏蔽結構18'o於此形成為桿狀(rod-like)電導體18"之圓形陣列，其如在圖3C'中所繪示，其繪示圖3C中繪示的區段之頂部視圖。
接著，參照圖3D，形成第一電互連介電質(ILD；electric interconnect dielectric)結構48(於此為二氧化矽)以提供具有接觸墊(contact pad)41'o、41'c的電通孔41o、41c，如繪示其分別連接至同軸傳輸線18之部分18a'的電導體18'o、18c'；提供電通孔43給CMOS電晶體14a、14b之源極和汲極區域；提供用於連接到地的接地通孔42以及要說明的在層2、12b中對應的通孔；提供上面在圖1中說明用於FET14a及14c的Vdd導電通孔46；提供具有接 觸墊45'的導電通孔45到FET14a、14b之閘極(G)；提供要說明的用於連接至FET 14c之閘極G的電通孔46；並且提供電互連47，其將FET 14b之源極連接到導電通孔41，該導電通孔41連接至同軸傳輸線18之中央導體18'c；以及提供用於將Vdd連接至FET 14a之汲極的電導體59。亦形成用於對接地匯流排22(圖2)連接的平面外導體51。
接著，形成第二電互連介電質(ILD)結構50(於此為二氧化矽)以提供用於同軸傳輸線16的同軸接地墊62，其連接至用於同軸傳輸線16的垂直導電通孔63之圓形陣列；提供用於同軸傳輸線16的中央導體65；如所繪示，提供電連接器60，以用於將同軸傳輸線18之中央導體18c透過通孔74連接至FET 14b之源極；提供連接至通孔42的通孔70；如所繪示，提供連接至通孔46及通孔43的通孔72和將FET14a及14b之源極及汲極連接的互連43。要注意的是，接觸墊64o通常為方形或矩形形狀的墊，其具有用於接觸墊65的中央孔(central aperture)(圖3D')。
接著，在圖3E中，接合氧化物76係形成在結構70之上表面之上(其包括FEOL結構11、第一ILD結構48以及第二ILD結構50，如在圖3D中所繪示)，接合至新的柄部73，於此例如使用接合氧化物層76，如繪示(圖3F)在其之後移除第一柄部30，如繪示暴露結構70之底部。
接著，隨著第一柄部30移除，圖3F繪示金屬墊84a、84b、84o、84c以及84d如繪示形成在暴露BOX層32之部分上、在導電通孔42、72、18'o、18'c以及44之 下，用以生成對於通孔42、72、18'o、18'c以及44的接點，如所指示，其中接點84o及84c接著分別提供對同軸傳輸線18之外部導體及中央導體的接觸。於此，用於同軸連接器18之上部的金屬墊被指示為用於外部導體的84o和用於中央導體的84c。圖3G'繪示從層50之頂部到BOX 32之底部的結構之部分的圖解剖面視圖，頂視圖繪示於圖3G"中且低視圖繪示於圖3G'''中。要注意的是，接觸墊41o'為具有用於接觸墊41c的中央孔53的墊，且同樣，接觸墊84o為具有用於接觸墊84c的中央孔85的墊。
接著，在圖3H中繪示低結構12b(圖2、2A及2B)，以類似的方式形成。二結構12a、12b對齊(例如具有結構12a之接觸墊84a、84b、84c、84o以及84d分別與接觸墊84'a、84'b、84'o以及84'd對齊，如圖2、2A及2B所繪示)且接著結構12a及12b而接合在一起以生成在圖2、2A及2B中繪示的結構。此接合能使用各種方法形成，包括在金屬墊84a到84'a與84b到84'b之間的附著(adhesive)、陽極(anodic)、熱壓(thermo-compressive)或以電連接的氧化物接合。要注意的是，接觸墊84'o為具有用於接觸墊84'c之中央孔的墊84o。
已說明本揭露之若干實施例。然而，將了解的是，可在不悖離本揭露之精神及範圍下作成各種修飾。例如，可使用其它金屬取代鎢，例如像是銅及鉭。進一步，通過DTI材料36的導電通孔可為中空管而非實心桿。據此，其它實施例係在下列申請專利範圍之範圍內。

Claims (5)

  1. 一種半導體結構，包含：底部氧化物絕緣層；矽層，配置在該底部氧化物絕緣層上；深凹槽隔離(DTI)材料，垂直地通過該矽層到該底部氧化物絕緣層，該深凹槽隔離材料具有比該矽層之電容率更低的電容率；以及同軸傳輸線，具有內部電導體及配置在該內部電導體周圍的外部導電屏蔽結構，其垂直地通過該深凹槽隔離材料，用以將配置在該底部氧化物絕緣層之上的電導體電性連接至配置在接觸底部氧化物絕緣層之下的電導體。
  2. 一種半導體結構，包含：底部氧化物絕緣層；矽層，配置在該底部氧化物絕緣層之上表面上；其中該矽層的深凹槽隔離材料垂直地通過該矽層到該底部氧化物隔離層；介電結構，配置在該矽層之上；複數個電接點，配置在該介電結構上，該電接點之第一部分被電子地連接，導電通孔垂直地通過該介電結構，並且該電接點之第二部分藉由垂直地通過該介電結構、該深凹槽隔離材料以及該底部氧化物層的複數個隔開的導電通孔被電連接到配置於該底部氧化物絕緣層之底部表面上 的電接點；以及其中連接至該電接點之該第二部分的該複數個隔開的導電通孔被安排以提供該電接點之該第二部分與配置在該底部氧化物絕緣層之底部表面上的該電接點之間的同軸連接器。
  3. 一種半導體的氧化物上矽(SOI)結構，包含：底部氧化物(BOX)絕緣層；矽層，配置在該底部氧化物(BOX)絕緣層上；深凹槽隔離(DTI)材料，垂直地通過該矽層到該底部氧化物絕緣層，該深凹槽隔離材料具有比該矽之電容率更低的電容率；其中該矽層已在其中形成一對互補式金屬氧化物半導體(CMOS)電晶體，該電晶體藉由該深凹槽隔離(DTI)材料將一者與該另一者電隔離；以及同軸傳輸線，具有內部電導體及配置在該內部電導體周圍的外部導電屏蔽結構，其垂直地通過該深凹槽隔離材料，用以將配置在該底部氧化物絕緣層之上的電導體電性連接至配置在接觸底部氧化物絕緣層之下的電導體。
  4. 如申請專利範圍第3項的結構，其中該內部導體和該外部導體屏蔽結構的外部為化學汽相沉積(CVD)的鎢。
  5. 如申請專利範圍第3項的結構，其中該外部導體屏蔽 結構包含複數個隔開的電導體，其將一者與另一者分開了小於同軸傳輸線之工作波長的四分之一波長，因而提供用於該外部導體屏蔽結構的電連續導體。
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