CN109643687A - 用于多层互连半导体晶片的同轴连接器穿通件 - Google Patents

用于多层互连半导体晶片的同轴连接器穿通件 Download PDF

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CN109643687A
CN109643687A CN201780051951.3A CN201780051951A CN109643687A CN 109643687 A CN109643687 A CN 109643687A CN 201780051951 A CN201780051951 A CN 201780051951A CN 109643687 A CN109643687 A CN 109643687A
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insulating layer
bottom oxide
oxide insulating
transmission line
trench isolation
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J·J·德拉布
M·A·手柴
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Raytheon Co
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Abstract

一种半导体绝缘体上硅(SOI)结构，具有设置在底部氧化物(BOX)绝缘层上的硅层。深槽隔离(DTI)材料垂直穿过硅层至底部氧化物绝缘层。深槽隔离材料具有比硅的介电常数小的介电常数。同轴传输线具有内部电导体和绕内部电导体设置的外部导电屏蔽结构，同轴传输线垂直通过深槽隔离材料，以使在底部氧化物绝缘层之上设置的电导体电连接到触头底部氧化物绝缘层之下设置的电导体。

Description

用于多层互连半导体晶片的同轴连接器穿通件
技术领域
本公开总的涉及多层互连半导体晶片，且更具体地，涉及用于使互连晶片之间射频(RF)能量互连的同轴连接器。
背景技术
如现有技术已知的，常期望联接一对叠覆结合半导体晶片之间的诸如射频(RF)或微波能量的高频能量。这有时被称为三维(3D)集成，例如见：由Chen-Ta Ko、Kuan-NengChen所作的题为“Reliability of key technologies in 3D integration”(Microelectronics Reliability 53(2013)7-17)的文章；由Enquist等人所作的题为“LowCost of Ownership Scalable Copper Direct Bond Interconnected 3D IC Technologyfor Three Dimensional Integrated Circuit Applications”(978-1-4244-45122009IEEE)的文章；和由P.Chang-Chien等人所作的题为“MMIC Compatible Wafer-LevelPackaging Technology”(2007International Conference on Indium Phosphide andRelated Materials,18,May 2007 Matsue,Japan)的文章。
另外如现有技术已知的，在许多应用中，期望以3D集成的方式提供穿过硅载体晶片的同轴屏蔽，如Ho等人所作的题为“Development of Coaxial Shield Via in SiliconCarrier for High Frequency Application”(2006Electronics Packaging TechnologyConference pages 825-830)的文章中所描述的。
另外如现有技术已知的，Arjun Kar-Roy等人的题为“Recent developmentsusing TowerJazz SiGe BiCMOS platform for mmWave and THz applications”(Passiveand Active Milllimeter-Wave Imaging XVI,edited by David A.Wikner,ArttuR.Luukanen,Proc.of SPIE Vol.8715,871505·2013SPIE·CCC code:0277-786X/13/$18doi:10.1117/12.1518475)的文章中报道了射频过孔形成在硅锗(SiGe)BiCMOS中的技术。也见2014年2月27日公开的、申请人为Hurwitz；Paul D.等的、题为“Isolated ThroughSilicon Vias in RF Technologies”的美国专利申请公开号2014/0054743。
另外如现有技术已知的，大直径铜充填过孔穿过相对厚的硅层被形成。由于硅衬底的传导率，这导致在这些高频能量的高损耗。采用的另一方法包括小的钨充填过孔的使用；然而，尽管该方法对于高密度3D互连是良好的，但它对场的限制不足以产生具有低的高频能量损耗的过孔。
发明内容
根据本公开，提供一种半导体氧化物上硅(SOI)结构，其具有设置在底部氧化物(BOX)绝缘层上的硅层。深槽隔离(DTI)材料垂直穿过硅层至底部氧化物绝缘层。深槽隔离材料具有比硅的介电常数低的介电常数。同轴传输线具有内部电导体和绕内部电导体设置的外部导电屏蔽结构，同轴传输线垂直穿过深槽隔离材料，以使附在底部氧化物绝缘层上设置的电导体电连接到触头底部氧化物绝缘层之下设置的电导体。
发明人认识到，通过令同轴传输线穿过较低介电常数的底部氧化物绝缘层而非穿过硅，由于底部氧化物绝缘层将在内部导体与外部导体屏蔽结构之间提供较低损耗的电介质，因此当穿过底部氧化物绝缘层而非硅层时，将存在较少的信号传输损耗。另外，发明人认识到，通过将同轴传输线放置在与硅相比具有非常低的传导率和损耗因数的氧化物((DTI)材料)中，穿过DTI材料的同轴传输线的使用允许非常薄的硅层的使用从而最大化硅层中形成的集成电路的功能密度，并且最小化通过过孔的损耗。SOI的使用简化了结构的构造，这简化了向集成3D RF装置中的集成。
在一个实施例中，提供了一种半导体氧化物上硅(SOI)结构，其具有设置在底部氧化物(BOX)绝缘层上的硅层。在硅层中形成有一对互补的金属氧化物半导体(CMOS)晶体管，晶体管通过垂直穿过硅层至底部氧化物绝缘层的深槽隔离(DTI)材料彼此电隔离。深槽隔离材料具有比硅的介电常数低的介电常数。同轴传输线具有内部电导体和绕内部电导体设置的外部导电屏蔽结构，同轴传输线垂直穿过深槽隔离材料，以使在底部氧化物绝缘层之上设置的电导体电连接到触头底部氧化物绝缘层之下设置的电导体。
在一个实施例中，内部导体和外部的外部导体屏蔽结构是化学气相沉积(CVD)的钨。
在一个实施例中，外部导体屏蔽结构包括彼此间距小于同轴传输线工作波长的四分之一波长的多个间隔的电导体，且如此提供用于外部导体屏蔽结构的电连续导体。
利用该布置结构，氧化物上硅(SOI)初始结构被用于制作晶体管，所述晶体管利用深槽隔离(DTI)隔离。DTI形成得足够大，使得多个过孔得以穿过该DTI材料被形成。多个过孔通过以下方式被形成：首先蚀刻穿过DTI材料和SOI隐埋氧化物(BOX)层被形成并随后利用化学气相沉积(CVD)钨充填过孔。这些多个过孔以形成同轴或“伪同轴”结构这样的方式排列(“伪同轴”就如下意义而言：外部导体屏蔽结构不是物理上连续的导体，而是彼此间距小于连接器工作波长的四分之一波长的多个间隔的导体，且如此提供用于外部导体的电连续导体)。伪同轴结构被设想为如下方法：其产生真实同轴形状的电特性以传播RF或微波能量，而不导致与CVD钨充填相关联的一些实践问题。对于直接结合混合法(Direct BondHybridization)或其它三维(3D)堆叠技术，比如Cu热压或超声结合，导电过孔的底部可通过以下方式来触及，利用刻蚀移除半导体结构的衬底晶片、在BOX层上停止并由此通过DTI材料底部上的导体显露。
本公开的一个或更多实施例的细节在附图及以下描述中陈述。从说明书和附图，以及从权利要求书，本公开的其它特征、目标和优点将是显而易见的。
附图说明
图1是根据本公开的两级双CMOS放大器电路的示意图；
图2示出图2A和图2B的布置结构，图2A和图2B合起来是根据本公开的图1的两级双CMOS放大器电路的概略截面草图；以及
图3A-3H是根据本公开的在制造过程中不同阶段的，制作中不同阶段的图1和图2的两级双CMOS放大器电路的一部分的概略截面草图；图3D’是图3D中所示结构的一部分的放大视图；图3D’是图3D的该部分的俯视图；图3G’是图3G中所示结构的一部分的放大视图；图3G”是图3G’的俯视图，图3G”是图3G’的仰视图。
不同附图中相似的附图标记指示相似的元件。
具体实施方式
现在参考图1，如所示的，两级双CMOS放大器电路10的示意图被示出为包括第一级CMOS电路10a，第一级CMOS电路10a具有联接到第二级CMOS电路10b的输出。如所示的，CMOS电路10a、10b中的每一个分别形成在一对堆叠、直接结合的结构12a、12b(上部结构(层1)12a和下部结构(层2)12b)中的对应一个结构上。如所示的，第一级CMOS电路10a包括：nMOSFET 14a，nMOS FET 14a具有由RF输入信号通过同轴传输线16馈给的栅极(G)，同轴传输线16有时也被称为同轴缆线16；连接到Vdd电压供给的漏极(D)和连接到pMOS FET 14b的漏极(D)的源极(S)。如标示的，pMOS FET 14b的栅极(G)由控制信号输入1馈给。nMOS FET 14a的源极给第一级CMOS电路10a提供输出，并通过同轴传输线18被连接，同轴传输线18有时也被称为同轴缆线18。同轴传输线18连接到第二级CMOS电路10b的输入。更具体地，如所示的，这里电路10a的nMOS FET的源极通过同轴连接器18联接到电路10b的nMOS FET 14c的栅极(G)。如所示的，电路10b的nMOS FET 14c的漏极(D)连接到Vdd，并且如所示的，源极(S)连接到电路10b的nMOS FET 14d的漏极(D)。如所示的，nMOSFET 14d的栅极(G)连接到控制信号输入2，并且如所示的，电路10b的nMOS FET 14d的源极(S)提供两级放大器电路10的RF输出，该输出通过同轴传输线20被联接，同轴传输线20有时也被称为同轴缆线20。注意到，第一和第二电路10a和10b的n沟道晶体管的本体接地，并且p沟道晶体管的本体连接到Vdd，如所示的。替代地，晶体管本体可连接到源连接，如SOI模拟电路上通常做的那样。还应注意到，同轴传输线16、18和20各自分别内部电导体16c、18c和20c和接地的外部导电屏蔽结构16o、18o和20o，接地的外部导电屏蔽结构16o、18o和20o分别绕内部电导体16c、18c和20c设置，如标示的。这里，在该例子中，如将描述的，外部导电屏蔽结构具有彼此间距小于同轴传输线工作波长的四分之一波长的多个间隔的电导体，且如此提供用于外部导体屏蔽结构的电连续导体。然而，应理解的是，外部导电屏蔽结构可以是连续的电导体。
现在参考图2、图2A和图2B，示出了两级双CMOS放大器电路10的概略截面草图。首先注意到，同轴传输线18的一部分，部分18a形成在层12a的底部中，另一部分18b形成在层12b的上部中。还注意到，到同轴传输线16、18和20的外部导电屏蔽结构的连接部通过垂直导电过孔(待述)以及通过面外接地总线22互连并接地，如标示的。
现在参考图3A-3H，该对CMOS电路10中的一个(这里是电路10a)形成于其中的集成电路的一部分被示出在图3A中。电路10a利用常规的SOI前段制程(FEOL)操作片30(这里例如是硅晶片)形成。FEOL结构11包括BOX层32(这里是二氧化硅)，被形成在操作片30的上表面上。硅层34形成在BOX层32上；硅层34利用常规加工适当掺杂，以在其中形成nMOS晶体管14a和pMOS晶体管14b。利用任何常规的技术，如所示的，栅氧化层38形成在硅层34的部分上。利用常规的光刻-蚀刻加工，如所示的，栅极(G)电极40分别附在nMOS和pMOS晶体管12a、12b的栅氧化层28上形成。
接下来参考图3B，如所示的，利用常规加工，CMOS晶体管14a、14b通过深槽隔离(DTI)区域36(这里是等离子体增强化学气相沉积(PECVD)四乙基原硅酸盐(TEOS))彼此电绝缘且与其它部分和电元件电绝缘；深槽隔离区域36从硅层34的顶部向下延伸到BOX层32。注意到，深槽隔离材料36具有比硅34的介电常数低的介电常数。这里，TEOS的相对介电常数是3.9，硅层34的相对介电常数是11.9。因此，令同轴传输线18a(图2)穿过较低介电常数的DTI 36而非穿过硅层34，由于DTI 36将在内部导体与外部导体屏蔽结构之间提供电介质，因此当穿过DTI层36而非硅层34时，将存在较少的信号传输损耗。另外，通过将同轴传输线18、20放置在与硅相比具有非常低的传导率和损耗因数的氧化物((DTI材料36)中，穿过DTI材料36的同轴传输线的使用允许非常薄的硅层34的使用从而最大化硅层中形成的集成电路的功能密度，并且最小化通过过孔的损耗。SOI的使用简化了结构的构造，这简化了向集成3D RF装置中的集成。如图3B中所示，钝化层、介电层44(这里例如是氮化硅)在DTI区域36之上形成。
接下来参考图3C，同轴传输线18的部分18a’被形成。首先，利用光刻-蚀刻技术(这里是反应离子蚀刻)，多个导电过孔18’o以预定的模式(这里以带有中心导电过孔18’c的圆形阵列的导电过孔的形式)被形成。然后，利用CVD以钨充填过孔开口，以形成内部或中心电导体18’c及外部导电屏蔽结构18’o；如图3C’中所示，这里，外部导电屏蔽结构18’o被形成为圆形阵列的杆状电导体18”，图3C’示出了图3C中所示截面的俯视图。
接下来参考图3D，第一电互连介电(ILD)结构48(这里是二氧化硅)被形成，以提供：具有接触焊盘41’o、41’c的电过孔41o、41c，如所示的，电过孔41o、41c分别连接到同轴传输线18的部分18a’的电导体18’o、18c’；到CMOS晶体管14a、14b的源极区域和漏极区域的电过孔43；用于连接到大地和层2 12b中对应过孔的接地过孔42(待述)；用于图1中以上描述的FETs 14a和14c的Vdd导电过孔46；到FETS14a、14b的栅极(G)的导电过孔45，导电过孔45具有接触焊盘45’；用于连接到FET 14c的电过孔46(待述)；和电互连部47，电互连部47使FET 14b的源极连接到导电过孔41，导电过孔41连接到同轴传输线18的中心导体18’c；以及用于使Vdd连接到FET 14a的漏极的电连接器59。用于连接到地线22(图2)的面外导体51也被形成。
接下来，第二电互连介电(ILD)结构50(这里是二氧化硅)被形成，以提供：用于同轴传输线16的同轴缆线接地焊盘62，同轴缆线接地焊盘62连接到用于同轴传输线16的圆形阵列的垂直导电过孔63；用于同轴传输线16的中心导体65；用于使同轴传输线18的中心导体18c通过过孔74连接到FET 14b的源极的电连接器60，如所示的；连接到过孔42的过孔70；连接到过孔46和过孔43的过孔72以及用于连接FETs 14a和14b的源极和漏极的互连件，如所示的。注意到，接触焊盘64o是大体方形或矩形形状的焊盘，具有用于接触焊盘65(图3D’)的中心孔口。
接下来，在图3E中，结合氧化物76附在结构70(如图3D中所示，结构70包括FEOL结构11、第一ILD结构48和第二ILD结构50)的上表面上形成，这里例如利用结合氧化物层76结合到新操作片73，在此之后，如所示的(图3F)，第一操作片30被移除，暴露结构70的底部，如所示的。
接下来，在第一操作片30移除的情况下，如所示的，图3G示出，金属焊盘84a、84b、84o、84c和84d形成在暴露的BOX层32的在导电过孔42、72、18’o、18’c和44的暴露端下的部分上，以产生用于过孔42、72、18’o、18’c和44的触头，于是其中触头84o和84c分别提供到同轴传输线18的外部导体和中心导体的触头，如标示的。这里，用于同轴连接器18的上部的金属焊盘被标示成：84o用于外部导体，以及84c用于中心导体。图3G’示出从层50顶部到BOX32底部的结构的一部分的概略截面图；俯视图示出在图3G”中，仰视图示出在图3G”’中。注意到，接触焊盘41o’是具有用于接触焊盘41c的中心孔口53的焊盘。且类似的，接触焊盘84o是具有用于接触焊盘84c的中心孔口85的焊盘。
接下来，下部结构12b(图2、图2A和图2B)示出在图3H中，以相似的方式被形成。两个结构12a、12b对准(伴随着，例如结构12a的接触焊盘84a、84b、84c、84o和84d分别与接触焊盘84’a、84’b、84’o和84’d对准；如图2、图2A和图2B所示，然后，结构12a和12b被结合在一起，以产生图2、图2A和图2B中所示的结构。该结合可利用多种方法形成，包括粘合、阳极、热压或利用金属焊盘84a到84’a和84b到84’b之间电连接的氧化物结合。注意到，接触焊盘84’o是具有用于接触焊盘84’c的中心孔口的焊盘84o。
现在应理解的是，根据本公开的半导体结构包括：底部氧化物绝缘层；设置在底部氧化物绝缘层上的硅层；垂直穿过硅层至底部氧化物绝缘层的深槽隔离(DTI)材料，深槽隔离材料具有比硅层的介电常数低的介电常数；以及同轴传输线，同轴传输线具有内部电导体和绕内部电导体设置的外部导电屏蔽结构，同轴传输线垂直穿过深槽隔离材料，以使在底部氧化物绝缘层之上设置的电导体电连接到触头底部氧化物绝缘层之下设置的电导体。
现在还应理解的是，根据本公开的半导体结构包括：底部氧化物绝缘层；设置在底部氧化物绝缘层的上表面上的硅层；其中，硅层，深槽隔离材料垂直穿过硅层至底部氧化物绝缘层；在硅层之上设置的介电结构；设置在介电结构上的多个电触头，电触头的第一部分是垂直穿过介电结构的、电子连接的导电过孔，并且电触头的第二部分通过垂直穿过介电结构、深槽隔离材料和底部氧化物层的多个间隔的导电过孔电连接到底部氧化物绝缘层的底表面上设置的电触头；并且其中，连接到电触头的第二部分的多个间隔的导电过孔布置成在电触头的第二部分与底部氧化物绝缘层的底表面上设置的电触头之间提供同轴连接器。
现在还应理解的是，根据本公开的半导体氧化物上硅(SOI)结构包括：底部氧化物(BOX)绝缘层；设置在底部氧化物(BOX)绝缘层上的硅层；垂直穿过硅层至底部氧化物绝缘层的深槽隔离(DTI)材料，深槽隔离材料具有比硅的介电常数低的介电常数；其中，在硅层中形成有一对互补的金属氧化物半导体(CMOS)晶体管，晶体管通过深槽隔离(DTI)材料彼此电隔离；以及同轴传输线，同轴传输线具有内部电导体和绕内部电导体设置的外部导电屏蔽结构，同轴传输线垂直穿过深槽隔离材料，以使在底部氧化物绝缘层之上设置的电导体电连接到触头底部氧化物绝缘层之下设置的电导体。半导体SOI结构可独立地或与另一特征相组合地包括以下特征中的一个或多个，以包括：其中，内部导体和外部的外部导体屏蔽结构是化学气相沉积(CVD)的钨，或者其中，外部导体屏蔽结构包括彼此间距小于同轴传输线工作波长的四分之一波长的多个间隔的电导体，且如此提供用于外部导体屏蔽结构的电连续导体。
已经描述了本公开的多个实施例。将理解的是，在不偏离本公开的精神及范围的情况下，可作出各种修改。例如，可使用其它的金属代替钨，比如，例如铜和钽。另外，穿过DTI材料36的导电过孔可以是中空管而非实心杆。相应地，其它实施例在所附权利要求的范围内。

Claims (5)

1.一种半导体结构，包括：
底部氧化物绝缘层；
设置在底部氧化物绝缘层上的硅层；
垂直穿过所述硅层至所述底部氧化物绝缘层的深槽隔离(DTI)材料，所述深槽隔离材料具有比所述硅层的介电常数低的介电常数；以及
同轴传输线，所述同轴传输线具有内部电导体和绕所述内部电导体设置的外部导电屏蔽结构，所述同轴传输线垂直穿过深槽隔离材料，以使在底部氧化物绝缘层之上设置的电导体电连接到触头底部氧化物绝缘层之下设置的电导体。
2.一种半导体结构，包括：
底部氧化物绝缘层；
设置在底部氧化物绝缘层的上表面上的硅层；
其中，所述硅层，深槽隔离材料垂直穿过所述硅层至所述底部氧化物绝缘层；
在所述硅层之上设置的介电结构；
设置在所述介电结构上的多个电触头，所述电触头的第一部分是垂直穿过介电结构的、电子连接的导电过孔，并且所述电触头的第二部分通过垂直穿过介电结构、深槽隔离材料和底部氧化物层的多个间隔的导电过孔电连接到底部氧化物绝缘层的底表面上设置的电触头；以及
其中，连接到所述电触头的第二部分的多个间隔的导电过孔布置成在电触头的第二部分与底部氧化物绝缘层的底表面上设置的电触头之间提供同轴连接器。
3.一种半导体氧化物上硅(SOI)结构，包括：
底部氧化物(BOX)绝缘层；
设置在底部氧化物(BOX)绝缘层上的硅层；
垂直穿过所述硅层至所述底部氧化物绝缘层的深槽隔离(DTI)材料，所述深槽隔离材料具有比硅的介电常数低的介电常数；
其中，在所述硅层中形成有一对互补的金属氧化物半导体(CMOS)晶体管，所述晶体管通过深槽隔离(DTI)材料彼此电隔离；以及
同轴传输线，所述同轴传输线具有内部电导体和绕所述内部电导体设置的外部导电屏蔽结构，所述同轴传输线垂直穿过深槽隔离材料，以使在底部氧化物绝缘层之上设置的电导体电连接到触头底部氧化物绝缘层之下设置的电导体。
4.如权利要求3所述的结构，其中，内部导体和外部的外部导体屏蔽结构是化学气相沉积(CVD)的钨。
5.如权利要求3所述的结构，其中，外部导体屏蔽结构包括彼此间距小于同轴传输线工作波长的四分之一波长的多个间隔的电导体，且如此提供用于外部导体屏蔽结构的电连续导体。
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