TW201810389A - 運用選擇性移除鰭部之半導體結構的形成 - Google Patents

運用選擇性移除鰭部之半導體結構的形成 Download PDF

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TW201810389A
TW201810389A TW106106412A TW106106412A TW201810389A TW 201810389 A TW201810389 A TW 201810389A TW 106106412 A TW106106412 A TW 106106412A TW 106106412 A TW106106412 A TW 106106412A TW 201810389 A TW201810389 A TW 201810389A
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瑞龍 謝
卡瑞妮Ｂ 拉貝爾
敏圭 成
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格羅方德半導體公司
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Abstract

運用選擇性移除鰭部之半導體結構的形成，舉例而言，包括提供基材，其具備上有第一硬遮罩之第一複數個鰭部、上有第二硬遮罩之第二複數個鰭部，該第一硬遮罩有別於該第二硬遮罩，在該等第一與第二鰭部之諸下部分之間沉積第一填充材料，在介於該等第一與第二鰭部之間的該第一填充材料上沉積第三硬遮罩層，在延展於該等第一與第二鰭部之諸上部分之間的該第三硬遮罩上沉積第二填充材料，選擇性地移除該等第二硬遮罩及該等第二鰭部以在該等第一與第二填充材料中形成開穴，在該等開穴中沉積第三填充材料，以及移除該第三硬遮罩上面之該第二填充材料與該第三填充材料以形成鰭部切口區。

Description

運用選擇性移除鰭部之半導體結構的形成
本揭露大體上係關於半導體裝置的製作方法，並且更尤指運用選擇性移除鰭部來形成半導體結構。
目前正在開發鰭式場效電晶體(FinFET)裝置，用以取代先進互補式金屬氧化物半導體(CMOS)技術中習知的平面型金屬氧化物半導體場效電晶體(MOSFET)，因為其改善了短通道效應抗擾度，而且導通電流與斷開電流比(Ion/Ioff)也更高。正如已知，「鰭部」一詞係指一種垂直結構，其內或其上舉例來說，形成一或多個FinFET或其它鰭部裝置，諸如包括電容器、二極體等在內的被動裝置。
在一項態樣中，透過提供一種方法，不僅克服先前技術的缺點，還提供另外的優點，該方法舉例來說，包括提供基材，其具備上有第一硬遮罩之第一複數個鰭部、上有第二硬遮罩之第二複數個鰭部，該第一硬罩有別於該第二硬罩，在該等第一與第二複數個鰭部的下部分之間沉積第一填充材料，在介於該第一與該第二複數個鰭 部之間的該第一填充材料上沉積第三硬遮罩層，在延展於該等第一與第二複數個鰭部之諸上部分之間的該第三硬遮罩上沉積第二填充材料，選擇性地移除該等第二硬遮罩及該第二複數個鰭部以在該等第一與第二填充材料中形成開穴，在該等開穴中沉積第三填充材料，以及移除該第三硬遮罩上面的該第二填充材料及該第三填充材料以形成鰭部切口區。
在另一態樣中，一種半導體結構，舉例而言，包括中間半導體基材，其舉例而言，包括：基材；複數個鰭部，以距離D1相隔；填充材料，沿著該複數個鰭部之下部分而布置；鰭部切口區，以距離D2布置於該複數個鰭部之間；以及其中，該鰭部切口區在該填充材料中包括以距離D1相隔之溝槽。
附加特徵及優點係透過本揭露之技巧來實現。本揭露之其它具體實施例及態樣係於本文中詳述，並且視為申請專利範圍之一部分。
100‧‧‧起始中間半導體結構
102‧‧‧主體半導體基材、基材
104‧‧‧圖型化硬遮罩、硬遮罩
210‧‧‧填充材料
300‧‧‧圖型化阻隔層
404‧‧‧硬遮罩
504‧‧‧硬遮罩、第二硬遮罩、第二遮罩
710‧‧‧鰭部、第一鰭部
712、722‧‧‧下部分
714、724‧‧‧上部分
720‧‧‧鰭部、第二鰭部
725‧‧‧剩餘部分
810‧‧‧填充材料
910‧‧‧填充材料、第一填充材料
1000‧‧‧第三硬遮罩層、第三硬遮罩
1110‧‧‧填充材料、第二填充材料
1310、1410‧‧‧開穴、凹穴
1510‧‧‧填充材料、第三填充材料
1710‧‧‧鰭部切口區
1750‧‧‧溝槽
1800‧‧‧方法
1810至1870‧‧‧步驟
本說明書之結論部分中特別指出並且明確主張本揭露之專利標的。然後，若要對本揭露有最深刻的理解，可參照以下各項具體實施例之詳細說明及附圖，其中：第1至17圖是截面圖，其根據本揭露之一具體實施例，以繪圖方式說明一種運用選擇性移除鰭部來形成半導體結構之方法；以及 第18圖是流程圖，其根據本揭露之一具體實施例，繪示一種運用選擇性移除鰭部來形成半導體結構之方法。
本揭露及某些特徵、優點、及其細節乃引用附圖所示非限制性具體實施例於下文更完整闡釋。省略眾所周知之材料、製作工具、處理技術等之說明以避免非必要地混淆本揭露之詳細說明。然而，應該了解的是，詳細說明及特定實施例雖然指出本揭露之具體實施例，仍係僅舉例來提供，並且非是作為限制。本概念之精神及/或範疇內之各種取代、修改、添加及/或配置經由本揭露對所屬技術領域中具有通常知識者將顯而易見。下文引用為易於了解未依比例繪示的圖式，其中各個不同圖中所用相同的參考元件符號表示相同或類似組件。
本揭露係針對形成諸如FinFET裝置之半導體裝置，其運用選擇性移除一些鰭部以例如在諸其餘鰭部之間形成溝槽。下面有更詳細的描述，舉例而言，使用具有不同性質的硬遮罩來形成半導體裝置容許初始形成複數個鰭部，然後採用硬遮罩中的差異來選擇性地移除一些鰭部。另外，可運用第三硬遮罩來錨定鰭部顯露位置。如將會領會的是，本揭露可提供的效益與優點優於習知的選擇性鰭部移除，諸如「鰭部先割(fin cut first)」程序或「鰭部後割(fin cut last)」程序。
第1至17圖根據本揭露之一具體實施例以 繪圖方式說明一種方法，其係用於形成具有複數個鰭部之中間半導體裝置，並且選擇性移除一些鰭部。
第1圖繪示起始中間半導體結構100之截面圖，其具有主體半導體基材102、及布置於半導體基材102上之圖型化硬遮罩104。圖型化硬遮罩之間可具有等間隔D1。基材102可由矽或任何半導體材料所形成，包括但不侷限於矽(Si)、鍺(Ge)、化合物半導體材料、分層半導體材料、矽絕緣體(SOI)材料、SiGe絕緣體(SGOI)材料、及/或鍺絕緣體(GOI)材料、或其它合適的半導體材料或多種材料。圖型化硬遮罩104可以是SiBCN、或SiCO、或SiN。圖型化硬遮罩104可使用習知的微影及蝕刻技巧由第一硬遮罩層所形成。如所屬技術領域中具有通常知識者將會理解的是，正如本實施例，使用半導體材料可形成許多鰭部，這可跨佈諸如晶圓之基材重複很多次數。
如第2圖所示，諸如氧化物層之填充材料舉例而言，可藉由化學機械程序(CMP)在圖型化硬遮罩104、及填充材料遭受移除的部分上沉積，導致填充材料210布置於各圖型化硬遮罩104之間。
之後，諸如有機平坦化層(OPL)之阻隔材料層係沉積於第2圖之結構上方，並予以圖型化而產生圖型化阻隔層300，用以曝露一些圖型化硬遮罩104，如第3圖所示。對第3圖之結構進行蝕刻程序，其選擇性地移除某些已曝露之硬遮罩104而產生剩餘的第一硬遮罩404，如第4圖所示。
請參閱第5圖，移除或剥除圖型化阻隔層300(第4圖)，沉積與硬遮罩404具有不同材料之第二硬遮罩層，以及舉例而言，藉由化學機械程序(CMP)來移除第二硬遮罩層之諸部分而產生第二硬遮罩504。舉例而言，第二硬遮罩504可由氮化矽(SiN)、SiBCN或SiCO所形成。氧化物填充材料210係諸如藉由已緩衝處理HF或已稀釋HF濕式程序來移除而產生第6圖之結構。在其它具體實施例中，第一硬遮罩材料可以是SiN，而第二硬遮罩材料可以是SiCO。在又其它具體實施例中，第一硬遮罩材料可以是SiCO，而第二硬遮罩材料可以是SiN。在進一步具體實施例中，第一硬遮罩及第二硬遮罩可以是SiBCN/SiN；SiN/SiBCN；SiN/SiCO；SiCO/SiN。將會領會的是，可將其它合適的材料組合運用於第一硬遮罩及第二硬遮罩。
移除或蝕刻程序係運用於第6圖之結構上，諸如第6圖之結構上的反應性離子蝕刻或乾蝕刻程序導致形成布置於第一遮罩404下面之第一鰭部710、及布置於第二遮罩504下面之第二鰭部720，如第7圖所示。第一鰭部與第二鰭部可具有對應的相同關鍵尺寸CD或寬度，而第一與第二鰭部之間可具有相同間距D1。就不希望的鰭部維持第二硬遮罩504而不是將其完全移除有助於形成鰭海(sea-of-fins)，例如：沒有鰭部蝕刻負載效應(loading effect)，並且還維持具有均勻關鍵尺寸的鰭部。將會領會的是，第二硬遮罩504若是在鰭部蝕刻之前遭受移除，則在鰭部蝕刻之後，密集鰭部陣列內部的鰭部外形/關鍵尺 寸、及陣列邊緣處的鰭部外形/關鍵尺寸可以不同。
諸如氧化物層之填充材料可沉積於第7圖之結構上，諸如局部STI填充及化學機械程序(CMP)，而產生布置於鰭部710與720之間的填充材料810。在其它具體實施例中，沉積填充材料前，可先沉積諸如Ox/SiN襯墊之鰭部襯墊。
第9圖繪示鰭部顯露，例如：具有鰭海的晶圓。舉例而言，運用諸如蝕刻之部分填充材料移除程序，產生沿著第一鰭部710之下部分712、及第二鰭部720之下部分722而布置的第一填充材料910。舉例而言，圍繞鰭部710及720回蝕填充材料810(第8圖)之頂端部分，以顯露鰭部710與720之頂端部分，舉例來說，沒有鰭部顯露負載效應，並且還維持具有均勻關鍵尺寸之鰭部。
如第10圖所示，第三硬遮罩層1000係沉積於第一與第二鰭部710與720之間第一填充材料910的頂端表面上。舉例而言，可運用氣體團簇離子束(GCIB)定向SiN沉積。在其它具體實施例中，將第三硬遮罩層取而代之的是，可運用諸如SiN襯墊、HfO2襯墊等之襯墊，其延展於第一填充材料、及第一與第二鰭部之上部分的側壁上方。
如第11圖所示，諸如氧化物層之填充材料可沉積在第10圖之結構、及填充材料中舉例而言可藉由化學機械程序(CMP)移除之部分上，而產生布置於第三硬遮罩層1000上、並且在第一鰭部710之上部分714與第二鰭 部720之上部分724之間、及硬遮罩404與504之間延展的填充材料1110。填充材料1110可與填充材料910相同。
第二硬遮罩504可諸如藉由蝕刻來移除以曝露鰭部720之上表面，如第12圖所示。舉例而言，使用HFEG溶液可選擇性地移除SiN第一硬遮罩，同時仍保留SiBCN第一硬遮罩。在其它具體實施例中，可移除第一硬遮罩，同時仍保留第二硬遮罩。舉例而言，SiN硬遮罩可藉由乾蝕刻至SiCO來選擇性地移除。
可在第12圖之結構上運用諸如非等向性Si蝕刻之第一鰭部移除程序以將鰭部720之一部分移除，產生第13圖所示在第一填充材料910、第二填充材料1110與鰭部720(第12圖)之剩餘部分725之間具有開穴1310之結構。
可進行諸如等向性Si蝕刻之下一個或第二移除程序或蝕刻以放大開穴1310，例如：將鰭部720(第12圖)之剩餘部分725移除，用以在第一填充材料910與第二填充材料1110之間形成放大之開穴1410，如第14圖所示。舉例而言，此移除程序可相對較小，例如：約6奈米，而產生小且可預測的斜度。
請再次地參照第13及14圖，選擇性鰭部移除或蝕刻程序產生過蝕刻之凹穴1310及1410，例如：布置於剩餘鰭部710之底端下面之凹穴的下部分。在其它具體實施例中，移除或蝕刻程序可導致凹穴未遭到過蝕刻，例如：凹穴的下部分被設置成與剩餘鰭部的底部均平。
第三填充材料是第14圖之結構上諸如氧化物層之沉積物，而且第三填充材料有部分舉例而言，遭受化學機械程序(CMP)移除而產生布置於凹穴1410(第14圖)中之填充材料1510，如第15圖所示。
如第16圖所示，在第15圖之結構上進行鰭部顯露或填充材料移除，用以將布置於第三硬遮罩層1000上面之填充材料移除。舉例而言，可進行氧化物凹陷或濕蝕刻程序以移除第二填充材料1110(第15圖)、及第三硬遮罩1000上面的第三填充材料1510(第15圖)之上部分。
移除第三硬遮罩1000及第一硬遮罩404以形成第17圖中所示之中間結構，其相較於其它諸鰭部之間的間隔D1，具有在一些鰭部之間有更大間隔D2的鰭部切口區1710、以及形成於該鰭部切口區中之溝槽1750。舉例而言，可進行氮化物移除程序以移除第三硬遮罩1000及硬遮罩404。
請參閱第10圖，第三硬遮罩層1000、及布置於第三硬遮罩層1000上之填充材料1110有助於例如在蝕刻第15圖之中間結構以形成第16圖之中間結構時，錨定鰭部顯露位置、界定鰭部顯露高度、及維持具有均勻關鍵尺寸之鰭部。相比之下，不用第三硬遮罩層，鰭部顯露負載效應也可導致諸如鰭部具有不同關鍵尺寸的鰭部顯露負載效應。
第18圖根據本揭露之一具體實施例，是方法1800之另一具體實施例的流程圖。方法1800包括：於 步驟1810，提供基材，其具備上有第一硬遮罩之第一複數個鰭部、上有第二硬遮罩之第二複數個鰭部，該第一硬遮罩有別於該第二硬遮罩，於步驟1820，在該等第一與第二複數個鰭部的下部分之間沉積第一填充材料，於步驟1830，在介於該第一與該第二複數個鰭部之間的該第一填充材料上沉積第三硬遮罩層，於步驟1840，在延展於該等第一與第二複數個鰭部的上部分之間的該第三硬遮罩上沉積第二填充材料，於步驟1850，選擇性地移除該等第二硬遮罩及該第二複數個鰭部以在該等第一與第二填充材料中形成開穴，於步驟1860，在該等開穴中沉積第三填充材料，以及於步驟1870，移除該第三硬遮罩上面的該第二填充材料及該第三填充材料。
將會領會的是，相較於習知的「鰭部先割」程序，本揭露提供更好的切割裕度、更好的斜削裝置相容性。本揭露相較於習知的「鰭部後割」程序可提供更均勻的鰭高，而且沒有負載效應。本揭露可避免典型由於「鰭部先割」程序所導致的最後鰭部斜削及鰭部顯露負載效應等問題，還可避免僅與鰭部後割相容之「鰭部後割」程序中的問題。
本文所用術語的目的僅在於說明特殊具體實施例並且意圖不在於限制本揭露。單數形之「一」(及其變形)及「該」於本文中使用時，用意在於同樣包括複數形，除非內容另有清楚指示。將再理解術語「包含」(以及包含的任何形式，如單數的「包含」和動名詞的「包含」)、 「具有」(以及具有的任何形式，如單數的「具有」和動名詞的「具有」)、「包括」(以及包括的任何形式，如單數的「包括」和動名詞的「包括」)、「含有」(以及含有的任何形式，如單數的「含有」和動名詞的「含有」)為開放式連接動詞。因此，「包含」、「具有」、「包括」或「含有」一或多個步驟或元件的方法或裝置處理那些一或多個步驟或元件，但不受限於僅處理那些一或多個步驟或元件。同樣地，「包含」、「具有」、「包括」或「含有」一或多個特徵之方法的步驟或裝置的元件處理那些一或多個特徵，但不受限於僅處理那些一或多個特徵。此外，以特定方式予以配置的裝置或結構係以至少那方式予以配置，但也可用未列示的方式予以配置。
下文申請專利範圍中所有的手段功能元件或步驟功能元件的相應結構、材料、動作、及均等意，若存在，係有意於包括以明確主張專利權之其它所主張專利權元件共同用於進行功能的任何結構、材料、或動作。已為了描述及說明而呈現本揭露的說明，但無意於具有徹底性或侷限於所揭示形式的揭露。許多修改及變化對於所屬技術領域中具有通常知識者將顯而易知而不脫離本揭露的範疇及精神。具體實施例經選用及說明是為了解釋本揭露一或多項態樣的原理及實際應用，並且令具有所屬技術領域中具有通常知識者憑藉適於所思的特定使用，能夠就具有各種修改之各項具體實施例理解本揭露的一或多項態樣。

Claims (20)

  1. 一種方法，包含：提供基材，其具備上有第一硬遮罩之第一複數個鰭部、上有第二硬遮罩之第二複數個鰭部，該第一硬遮罩有別於該第二硬遮罩；在該等第一與第二複數個鰭部的下部分之間沉積第一填充材料；在介於該第一與該第二複數個鰭部之間的該第一填充材料上沉積第三硬遮罩層；在延展於該等第一與第二複數個鰭部之諸上部分之間的該第三硬遮罩上沉積第二填充材料；選擇性地移除該等第二硬遮罩及該第二複數個鰭部以在該第一與第二填充材料中形成開穴；在該等開穴中沉積第三填充材料；以及移除該第三硬遮罩上面的該第二填充材料及該第三填充材料以形成鰭部切口區。
  2. 如申請專利範圍第1項所述之方法，其中，該第一複數個鰭部與該第二複數個鰭部具有對應的相同關鍵尺寸。
  3. 如申請專利範圍第1項所述之方法，其中，該第一複數個鰭部與該第二複數個鰭部之間具有相同間距。
  4. 如申請專利範圍第1項所述之方法，其中，該選擇性地移除該第二複數個鰭部包含蝕刻。
  5. 如申請專利範圍第1項所述之方法，其中，該選擇性 地移除該第二複數個鰭部包含第一蝕刻及第二蝕刻，以及其中，該第一蝕刻有別於該第二蝕刻。
  6. 如申請專利範圍第1項所述之方法，其中，該選擇性地移除該第二複數個鰭部包含非等向性蝕刻。
  7. 如申請專利範圍第1項所述之方法，其中，該選擇性地移除該第二複數個鰭部包含進行等向性蝕刻。
  8. 如申請專利範圍第1項所述之方法，其中，該選擇性地移除該第二複數個鰭部包含在非等向性蝕刻之後接著等向性蝕刻。
  9. 如申請專利範圍第1項所述之方法，其中，該沉積該第三硬遮罩層包含定向沉積。
  10. 如申請專利範圍第1項所述之方法，其中，該沉積該第三硬遮罩層包含在該第一與該第二複數個鰭部之間的該第一填充材料上、及該第一與該第二複數個鰭部上沉積襯墊。
  11. 如申請專利範圍第1項所述之方法，其中，該第一填充材料、該第二填充材料、及該第三填充材料包含相同材料。
  12. 如申請專利範圍第1項所述之方法，其中，該第一填充材料、該第二填充材料、及該第三填充材料包含氧化物。
  13. 如申請專利範圍第1項所述之方法，其中，該等第一硬遮罩包含SiBCN且該等第二硬遮罩包含SiN。
  14. 如申請專利範圍第1項所述之方法，其中，該等第一 硬遮罩包含SiN且該等第二硬遮罩包含SiCO，或該等第一硬遮罩包含SiCO且該等第二硬遮罩包含SiN。
  15. 如申請專利範圍第1項所述之方法，其中，該第一複數個鰭部與該第二複數個鰭部具有對應的相同關鍵尺寸，並且該第一複數個鰭部與該第二複數個鰭部之間具有相同間距。
  16. 如申請專利範圍第1項所述之方法，其中，該提供包含在該基材上形成包含該第一材料之複數個硬遮罩，以包含該第二材料之該等第二硬遮罩選擇性地取代某些該等硬遮罩。
  17. 一種中間半導體結構，包含：基材；複數個鰭部，以距離D1相隔；填充材料，沿著該複數個鰭部之下部分而布置；鰭部切口區，布置於該複數個鰭部之間具有距離D2；以及其中，該鰭部切口區在該填充材料中包含以距離D1相隔之溝槽。
  18. 如申請專利範圍第17項之中間半導體結構，其中，該基材及該複數個鰭部包含矽。
  19. 如申請專利範圍第17項所述之半導體結構，其中，該填充材料包含氧化物。
  20. 如申請專利範圍第17項之中間半導體結構，其中，該等鰭部及該等溝槽具有相同關鍵尺寸。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102330087B1 (ko) * 2017-04-03 2021-11-22 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US10431660B2 (en) 2018-02-07 2019-10-01 International Business Machines Corporation Self-limiting fin spike removal
US10439047B2 (en) * 2018-02-14 2019-10-08 Applied Materials, Inc. Methods for etch mask and fin structure formation
US10832971B2 (en) 2018-08-30 2020-11-10 International Business Machines Corporation Fabricating tapered semiconductor devices
US10658190B2 (en) * 2018-09-24 2020-05-19 International Business Machines Corporation Extreme ultraviolet lithography patterning with directional deposition
US10818556B2 (en) * 2018-12-17 2020-10-27 United Microelectronics Corp. Method for forming a semiconductor structure
CN113394092B (zh) * 2020-03-13 2022-08-09 中芯国际集成电路制造（天津）有限公司 半导体结构及其形成方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7994020B2 (en) * 2008-07-21 2011-08-09 Advanced Micro Devices, Inc. Method of forming finned semiconductor devices with trench isolation
US8569152B1 (en) * 2012-06-04 2013-10-29 International Business Machines Corporation Cut-very-last dual-epi flow
KR102013842B1 (ko) * 2013-02-08 2019-08-26 삼성전자주식회사 반도체 소자의 제조 방법
TWI587375B (zh) * 2013-03-27 2017-06-11 聯華電子股份有限公司 形成鰭狀結構的方法
US9530775B2 (en) * 2013-06-12 2016-12-27 Globalfoundries Inc. Methods of forming different FinFET devices having different fin heights and an integrated circuit product containing such devices
DE112013007021T5 (de) * 2013-06-26 2016-01-21 Intel Corporation Tri-Gate-Transistorstruktur mit unversenktem Feldisolator und dünneren Elektroden über dem Feldisolator
US9472672B2 (en) * 2013-09-04 2016-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminating fin mismatch using isolation last
US9209178B2 (en) * 2013-11-25 2015-12-08 International Business Machines Corporation finFET isolation by selective cyclic etch
US9305930B2 (en) * 2013-12-11 2016-04-05 Globalfoundries Inc. Finfet crosspoint flash memory
US9660080B2 (en) * 2014-02-28 2017-05-23 Stmicroelectronics, Inc. Multi-layer strained channel FinFET
US9147730B2 (en) 2014-03-03 2015-09-29 Globalfoundries Inc. Methods of forming fins for FinFET semiconductor devices and selectively removing some of the fins by performing a cyclical fin cutting process
US9704973B2 (en) * 2014-04-01 2017-07-11 Globalfoundries Inc. Methods of forming fins for FinFET semiconductor devices and the selective removal of such fins
US20150287743A1 (en) * 2014-04-02 2015-10-08 International Business Machines Corporation Multi-height fin field effect transistors
US9281382B2 (en) * 2014-06-04 2016-03-08 Stmicroelectronics, Inc. Method for making semiconductor device with isolation pillars between adjacent semiconductor fins
US9524986B2 (en) * 2014-06-26 2016-12-20 Globalfoundries Inc. Trapping dislocations in high-mobility fins below isolation layer
TWI615976B (zh) * 2014-07-07 2018-02-21 聯華電子股份有限公司 鰭式場效電晶體及其製造方法
US9324799B2 (en) * 2014-09-09 2016-04-26 Globalfoundries Inc. FinFET structures having uniform channel size and methods of fabrication

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