TW201807788A - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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Publication number
TW201807788A
TW201807788A TW105127804A TW105127804A TW201807788A TW 201807788 A TW201807788 A TW 201807788A TW 105127804 A TW105127804 A TW 105127804A TW 105127804 A TW105127804 A TW 105127804A TW 201807788 A TW201807788 A TW 201807788A
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Taiwan
Prior art keywords
wafer
active surface
primer
semiconductor package
conductive bumps
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TW105127804A
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English (en)
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TWI610409B (zh
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沈更新
凃清鎮
吳自勝
林俊辰
葉惠雯
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南茂科技股份有限公司
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Priority to TW105127804A priority Critical patent/TWI610409B/zh
Priority to CN201611022516.1A priority patent/CN107785325A/zh
Priority to US15/373,494 priority patent/US20180061811A1/en
Application granted granted Critical
Publication of TWI610409B publication Critical patent/TWI610409B/zh
Publication of TW201807788A publication Critical patent/TW201807788A/zh

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Abstract

一種半導體封裝，包括第一、第二晶片、多個第一、第二導電凸塊及底膠。第一晶片包括一第一主動面，其中第一主動面包括一晶片接合區、多個位於晶片接合區內的第一內接點以及多個位於晶片接合區外之第一外接點。第二晶片覆置於第一晶片的晶片接合區處。第一導電凸塊配置於第一外接點上。第二導電凸塊位於第一晶片的第一內接點與第二晶片的第二接點之間。底膠位在第一主動面上且包覆第二導電凸塊、至少局部的各第二晶片側面及至少局部的各第一導電凸塊。本發明更提供多種半導體封裝的製造方法。

Description

半導體封裝及其製造方法
本發明是有關於一種封裝及其製造方法，且特別是有關於一種半導體封裝及其製造方法。
隨著科技日新月異，積體電路(integrated circuits，IC)元件已廣泛地應用於我們日常生活當中。一般而言，積體電路的生產主要分為三個階段：矽晶圓的製造、積體電路的製作及積體電路的封裝。
在目前的封裝結構中，將小尺寸的晶片以覆晶的方式配置於大尺寸的晶片上並透過兩者之間的導電凸柱電性連接是一種相當常見的封裝型態。然而，在目前的多晶片封裝中，小尺寸的晶片的側面裸露，晶背也常是裸露的，而使得多晶片封裝中小尺寸晶片的破裂率(chipping rate)較高。
本發明提供一種半導體封裝，其具有較低的破裂率。
本發明提供多種半導體封裝的製造方法，其可製造出上述的半導體封裝。
本發明的一種半導體封裝，包括一第一晶片、一第二晶片、多個第一導電凸塊、多個第二導電凸塊及一底膠。第一晶片包括一第一主動面，其中第一主動面包括一晶片接合區、多個位於晶片接合區內的第一內接點以及多個位於晶片接合區外之第一外接點。第二晶片覆置於(flip on)第一晶片的晶片接合區處，且包括一第二主動面及連接於第二主動面的多個第二晶片側面，其中第二主動面包括多個第二接點。這些第一導電凸塊配置於這些第一外接點上。這些第二導電凸塊位於這些第一內接點與這些第二接點之間，各第一內接點分別透過對應的第二導電凸塊與對應的第二接點電性連接。底膠位在第一主動面上且包覆這些第二導電凸塊、至少局部的各第二晶片側面及至少局部的各第一導電凸塊。
在本發明的一實施例中，上述的底膠包括一封模底膠(molded underfill，MUF)，封模底膠包覆全部的這些第二晶片側面。
在本發明的一實施例中，上述的第二晶片更包括相對於第二主動面的一晶背，晶背被封模底膠覆蓋，或者晶背外露於封模底膠。
在本發明的一實施例中，上述的半導體封裝更包括多個銲件，這些第一導電凸塊外露於封模底膠，這些銲件配置於封模底膠上且連接於這些第一導電凸塊，其中各銲件包括一銲球、一銲帽或一銲層。
在本發明的一實施例中，上述的這些第一導電凸塊的高度大於或等於第二晶片的晶背至第一內接點之間的距離。
在本發明的一實施例中，上述的半導體封裝更包括多個銲球及一保護層，這些銲球配置於這些第一導電凸塊上，各第一導電凸塊為一球底金屬層(UBM)，封模底膠包覆局部的各銲球。保護層配置於第一晶片的第一主動面上，保護層包括至少對應於晶片接合區的一開口，且這些第一內接點與這些第一外接點外露於保護層。
在本發明的一實施例中，上述的第二晶片更包括相對於第二主動面的一晶背，第二晶片的晶背至第一內接點之間的距離大於各第一導電凸塊的高度，且各第一導電凸塊的高度大於各第二導電凸塊的高度。
在本發明的一實施例中，上述的各銲球凸出於封模底膠的高度為銲球的高度的0.5倍至0.8倍之間。
在本發明的一實施例中，上述的半導體封裝更包括一保護層，配置於第一晶片的第一主動面上，這些第一內接點與這些第一外接點外露於保護層，保護層包括對應於晶片接合區的一開口，底膠包括一內底膠，內底膠位在第一晶片的晶片接合區與第二晶片之間，封模底膠包覆內底膠。
在本發明的一實施例中，上述的半導體封裝更包括一保護層，配置於第一晶片的第一主動面上的這些第一外接點所環繞的一虛擬範圍以外的區域，底膠包覆第二晶片的局部的各第二晶片側面及局部的這些第一導電凸塊，各第一導電凸塊為一銲球。
本發明的一種半導體封裝的製造方法，包括：提供一晶圓，包括陣列排列的多個第一晶片，其中各第一晶片包括一第一主動面，第一主動面包括一晶片接合區、多個位於晶片接合區內的第一內接點以及多個位於晶片接合區外之第一外接點；配置多個第一導電凸塊於這些第一外接點上；覆置多個第二晶片於這些第一晶片的這些晶片接合區，其中各第二晶片包括一第二主動面及連接於第二主動面的多個第二晶片側面，各第二主動面包括多個第二接點，各第二主動面面對第一主動面且這些第二接點電性連接於這些第一內接點；進行一模製(molding)底膠製程，以在第一主動面上形成一封模底膠，其中封模底膠包覆這些第一導電凸塊及這些第二晶片；對封模底膠進行一研磨製程，而使這些第一導電凸塊外露；配置多個銲件於這些第一導電凸塊上以形成多個半導體封裝；以及進行一切割製程，以使這些半導體封裝彼此分離。
在本發明的一實施例中，上述的各銲件包括一銲球、一銲帽或一銲層。
在本發明的一實施例中，上述的第二晶片更包括相對於第二主動面的一晶背，在對封模底膠進行研磨製程的步驟之後，晶背外露於封模底膠。
在本發明的一實施例中，在覆置這些第二晶片之後且進行模製底膠製程之前，更包括：配置一保護層於第一晶片的第一主動面上，這些第一內接點與這些第一外接點外露於保護層，保護層包括對應於晶片接合區的一開口；以及配置一內底膠於第一晶片的晶片接合區與第二晶片之間，其中在進行模製底膠製程之後，封模底膠包覆內底膠。
本發明的一種半導體封裝的製造方法，包括：提供一晶圓，包括陣列排列的多個第一晶片，其中各第一晶片包括一第一主動面，第一主動面包括一晶片接合區、多個位於晶片接合區內的第一內接點以及多個位於晶片接合區外之第一外接點，第一主動面上配置有一保護層，保護層包括至少對應於晶片接合區的一開口，且這些第一內接點與這些第一外接點外露於保護層；配置多個銲球於這些第一外接點上以與這些第一外接點電性連接；覆置多個第二晶片於這些第一晶片的這些晶片接合區，其中各第二晶片包括一第二主動面及連接於第二主動面的多個第二晶片側面，各第二主動面包括多個第二接點，各第二主動面面對第一主動面且這些第二接點電性連接於這些第一內接點；進行一模製(molding)底膠製程，在第一主動面上形成一封模底膠，其中封模底膠包覆這些第二晶片及局部的各銲球，以完成多個半導體封裝；以及進行一切割製程，以使這些半導體封裝彼此分離。
在本發明的一實施例中，上述的這些銲球與這些第一外接點之間配置有多個球底金屬層(UBM)，封模底膠包覆這些球底金屬層。
在本發明的一實施例中，上述的第二晶片更包括相對於第二主動面的一晶背，第二晶片的晶背至第一內接點之間的距離大於各球底金屬層的高度，且各球底金屬層的高度大於第一主動面與第二主動面之間的距離。
在本發明的一實施例中，上述的各銲球凸出於封模底膠的高度為銲球的高度的0.5倍至0.8倍之間。
在本發明的一實施例中，在覆置這些第二晶片之後且進行模製底膠製程之前，更包括：配置一內底膠於第一晶片的晶片接合區與第二晶片之間，其中在進行模製底膠製程之後，封模底膠包覆內底膠。
在本發明的一實施例中，上述的保護層位於第一晶片的第一主動面上的這些第一外接點所環繞的一虛擬範圍以外的區域，封模底膠包覆第二晶片的局部的各第二晶片側面及局部的這些第一導電凸塊，各第一導電凸塊為一銲球。
基於上述，本發明的半導體封裝的底膠包覆這些第二導電凸塊、至少局部的各第二晶片側面及至少局部的各第一導電凸塊，以增加整體的結構強度。因此，本發明的半導體封裝能具有較低的破裂率。此外，本發明更提供多種半導體封裝的製造方法，以製造出上述的半導體封裝。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖1F是依照本發明的一實施例的一種半導體封裝100的製造流程示意圖。本實施例的半導體封裝100的製造方法包括下列步驟。首先，請先參閱圖1A，提供一晶圓105，晶圓105包括陣列排列的多個第一晶片110。在圖1A中僅示意性地繪示出晶圓105的其中一個剖面，此剖面以三個並排的第一晶片110為示意，實際上晶圓105的第一晶片110的數量並不以此為限制。在本實施例中，各第一晶片110包括一第一主動面112，第一主動面112包括一晶片接合區114、多個位於晶片接合區114內的第一內接點116以及多個位於晶片接合區114外之第一外接點118。
在製程的一開始可選擇性地對晶圓105進行清洗(Incoming Clean)的步驟，透過例如是高壓水柱清洗的方式來移除第一晶片110表面的髒污。當然，在其他實施例中，也可以選擇不對晶圓105進行清洗。
接著，配置一保護層170於第一晶片110的第一主動面112上，這些第一內接點116與這些第一外接點118外露於保護層170，保護層170包括對應於晶片接合區114的一開口。詳細地說，可先在第一晶片110上塗佈保護層170，保護層170之材料可為一般之感光性光阻材料，如聚醯亞胺(Polyimide, PI)、聚苯噁唑 (Polybenzoxazole, PBO)、 苯並環丁烯(Benzocyclobuten, BCB)、丙烯酸酯(Acrylates) 或環氧樹脂(Epoxy)等。再罩設一光罩(未繪示)在保護層170，並且進行曝光(Exposure)的程序，其中光罩的圖案對應於所欲露出的第一晶片110的圖案。之後進行顯影(Develop)的程序，以顯影液將未曝光的保護層170溶解並移除。接著，透過加熱的方式固化(Curing)未被移除的保護層170，再透過例如是氧氣電漿或氮氣電漿或氮氧混合氣電漿等的方式對固化的保護層170進行表面處理，即可完成保護層170。再來，配置多個第一導電凸塊130於這些第一外接點118上。配置第一導電凸塊130的方式可包括植球、電鍍、印刷等方式經後迴焊(reflow)成型或不經後迴焊(reflow)製程。在本實施例中，第一導電凸塊130的材質包括單一金屬元素或合金，其材質可包括金、銀、銅、錫、鎳或其合金。且在本發明圖式中，第一導電凸塊130以柱狀為例，然而，第一導電凸塊130的外觀形狀也可以是球狀，並不以上述為限制，且其所選用之材料亦可採用單一種金屬材料或採用兩種或兩種以上之金屬材料電鍍成型，例如，銅柱(Copper Pillar)上形成一層錫銀合金(Solder layer)，或銅柱(Copper Pillar)上形成一錫銀合金帽(Solder cap)或銅柱上覆蓋一層鎳及金或於銅柱外壁覆蓋一層金，均為本發明可行之導電凸塊。
再來，請參閱圖1B，覆置多個尺寸較小的第二晶片120於這些第一晶片110的這些晶片接合區114。在本實施例中，各第二晶片120包括一第二主動面122、連接於第二主動面122的多個第二晶片120側面、相對於第二主動面122的一晶背128及配置在第二主動面122上的保護層175。各第二主動面122包括多個第二接點124，第二接點124外露於保護層175，各第二主動面122面對第一主動面112且這些第二接點124透過多個第二導電凸塊140電性連接於這些第一內接點116使第一晶片110與第二晶片120接合並產生電性連接。接合的方式可為迴焊(reflow)、熱壓合(thermal compression bond, TCB)、熱壓共晶(thermal eutectic)、超音波熱壓(thermal ultrasonic)等方式。在本實施例中，第一導電凸塊130的高度會大於第二導電凸塊140的高度。更進一步地說，第一導電凸塊130的高度會大於第二導電凸塊140與第二晶片120的總高度。
同樣地，在本實施例中，第二導電凸塊140的材質包括單一金屬元素或合金，其材質可包括金、銀、銅、錫、鎳或其合金。且在本發明圖式中，第二導電凸塊140以柱狀為例，然而，第二導電凸塊140的外觀形狀也可以是球狀，並不以上述為限制，且其所選用之材料亦可採用單一種金屬材料或採用兩種或兩種以上之金屬材料電鍍成型，例如，銅柱(Copper Pillar)上形成一層錫銀合金(Solder Layer)，或銅柱(Copper Pillar)上形成一錫銀合金帽(Solder Cap)，或銅柱上覆蓋一層鎳及金或於銅柱外壁覆蓋一層金，均為本發明之可行之導電凸塊。
接著，請參閱圖1C，進行一模製(molding)底膠製程，以在第一晶片110的第一主動面112上形成一底膠150。在本實施例中，底膠150以封模底膠152為例，其中封模底膠152包覆這些第一導電凸塊130及這些第二晶片120。在本實施例中，封模底膠152之材質例如是由環氧樹脂型材料、熱固性材料、熱塑性材料、UV固化材料、或其相似物所形成。熱固性材料可包括酚型、酸酐型、或胺型硬化劑及丙烯酸聚合物添加劑。但封模底膠152之材質並不以此為限制。封模底膠152可用來提供第一晶片110與第二晶片120之間的固定效果，並能夠提供緩衝及防潮防塵等效果來提昇封裝的可靠度。
再來，請參閱圖1D，對底膠150(封模底膠152)進行一研磨製程，而使這些第一導電凸塊130外露。在本實施例中，透過對底膠150(封模底膠152)進行機械研磨來降低底膠150(封模底膠152)的高度。由於第一導電凸塊130的高度大於第二晶片120的晶背128與第一主動面112之間的距離，因此，當第一導電凸塊130外露時，第二晶片120的晶背128尚會被底膠150(封模底膠152)覆蓋。
接著，請參閱圖1E，配置多個銲件160於這些第一導電凸塊130上以形成多個半導體封裝100。在本實施例中，銲件160以銲球162為例，但銲件160的種類並不以此為限制。最後，進行一切割製程，以使這些半導體封裝100彼此分離，而形成如圖1F所示的半導體封裝100。
請參閱圖1F，本實施例的半導體封裝100包括一第一晶片110、一第二晶片120、多個第一導電凸塊130、多個第二導電凸塊140、一底膠150、多個銲件160及一保護層170。第一晶片110包括一第一主動面112，其中第一主動面112包括一晶片接合區114、多個位於晶片接合區114內的第一內接點116以及多個位於晶片接合區114外之第一外接點118。保護層170配置於第一晶片110的第一主動面112上，這些第一內接點116與這些第一外接點118外露於保護層170，保護層170包括對應於晶片接合區114的一開口。
第二晶片120覆置於(flip on)第一晶片110的晶片接合區114處，且包括一第二主動面122及連接於第二主動面122的多個第二晶片120側面，其中第二主動面122包括多個第二接點124。這些第一導電凸塊130配置於這些第一外接點118上。這些第二導電凸塊140位於這些第一內接點116與這些第二接點124之間，各第一內接點116分別透過對應的第二導電凸塊140與對應的第二接點124電性連接。
底膠150位在第一主動面112上且包覆這些第二導電凸塊140、至少局部的各第二晶片120側面及至少局部的各第一導電凸塊130。更明確地說，底膠150包括一封模底膠152(molded underfill，MUF)，封模底膠152包覆全部的這些第二晶片120側面。
在本實施例中，這些第一導電凸塊130的高度大於或等於第二晶片120的晶背128至第一內接點116之間的距離，這些第一導電凸塊130外露於封模底膠152，第二晶片120更包括相對於第二主動面122的一晶背128，晶背128被封模底膠152覆蓋。這些銲件160配置於封模底膠152上且連接於這些第一導電凸塊130，銲件160的種類以銲球162為例。
本實施例的半導體封裝100透過底膠150(封模底膠152)包覆這些第二導電凸塊140、至少局部的各第二晶片120側面及至少局部的各第一導電凸塊130，因此，半導體封裝100的整體結構強度可有效地提升，而使得本實施例的半導體封裝100能具有較低的破裂率。
需說明的是，雖然在本實施例中是先在這些第一外接點118上形成多個第一導電凸塊130之後，再將第二晶片120覆設於晶片接合區114上。但在其他實施例中，也可以是先將第二晶片120覆設於晶片接合區114上，以使第二導電凸塊140連接至第一內接點116，再在這些第一外接點118上形成多個第一導電凸塊130，製程順序上可視需求而調整。
值得一提的是，在一未繪示的製程中，可再使這些單離化之半導體封裝100以這些第一導電凸塊130電性連接至一線路板(未繪示)，以使第一晶片110、第二晶片120與線路板三者之間電性連接。在上述結構中，第二晶片120與第二導電凸塊140會位於線路板與第一晶片110之間。
上面僅顯示其中一種半導體封裝100的形式。下面將舉出其他種半導體封裝100a、100b、100c、100d，為了方便了解，在下面的這些實施例中，與前一實施例相同或相似的元件以與前一實施例相同或相似的元件編號來表示，不再多加贅述。圖1G至圖1J是依照本發明的其他實施例的多種半導體封裝的示意圖。
請先參閱圖1G與圖1H，圖1G的半導體封裝100a、圖1H的半導體封裝100b與前一實施例的半導體封裝100的主要差異在於銲件160的形式。在圖1F中，銲件160以銲球162為例。在圖1G中，銲件160以銲帽164為例。在圖1H中，銲件160以銲層166為例。當然，上面僅是舉出其中幾種銲件160的形式，實際上銲件160的形式並不以上述為限制。
請參閱圖1I，圖1I的半導體封裝100c與圖1F的半導體封裝100的主要差異在於，在本實施例中，第二晶片120的晶背128外露於封模底膠152。也就是說，在製造本實施例的半導體封裝100的過程中，對封模底膠152進行研磨製程時，會將封模底膠152研磨到晶背128外露的狀態。因此，在研磨製程之後，第一導電凸塊130會與第二晶片120的晶背128齊平。
請參閱圖1J，圖1J的半導體封裝100d與圖1F的半導體封裝100的主要差異在於，在本實施例中，底膠150還包括一內底膠154，內底膠154位在第一晶片110的晶片接合區114與第二晶片120之間，內底膠154填入保護層170的開口，且封模底膠152包覆內底填膠154。內底膠154的材質可與封模底膠152不同或相同。本實施例的半導體封裝100藉由先利用內底膠154填充於第一晶片110的晶片接合區114與第二晶片120之間，以保護第二導電凸塊140，再透過封模底膠152包覆第二晶片120與第一導電凸塊130的兩階段式封裝，以提供半導體封裝100d良好的結構強度。
下面再提供另一種半導體封裝的製造流程，圖2A至圖2E是依照本發明的另一實施例的一種半導體封裝100的製造流程示意圖。本實施例的半導體封裝的製造方法包括下列步驟。
首先，請參閱圖2A，提供一晶圓105，包括陣列排列的多個第一晶片110，其中各第一晶片110包括一第一主動面112，第一主動面112包括一晶片接合區114、多個位於晶片接合區114內的第一內接點116以及多個位於晶片接合區114外之第一外接點118，第一主動面112上配置有一保護層170，保護層170包括至少對應於晶片接合區114的一開口，且這些第一內接點116與這些第一外接點118外露於保護層170。
接著，進行一球底金屬層132(UBM)的沉積製程。在本實施例中，先透過氬氣去移除第一外接點118上的氧化物。接著，在第一外接點118上依序濺鍍鈦鎢層與金層或鈦層與銅層，然後再電鍍上金或銅或銅、鎳、金等，以在這些第一外接點118形成多個球底金屬層132。接著，配置多個銲球162於這些第一外接點118上的球底金屬層132以與這些第一外接點118電性連接。
再來，請參閱圖2B，覆置尺寸較小的多個第二晶片120於這些第一晶片110的這些晶片接合區114，其中各第二晶片120包括一第二主動面122、連接於第二主動面122的多個第二晶片120側面及相對於第二主動面122的一晶背128。各第二主動面122包括多個第二接點124，各第二主動面122面對第一主動面112且這些第二接點124電性連接於這些第一內接點116。
接著，請參閱圖2C，進行一模製(molding)底膠製程，在第一主動面112上形成一底填膠150，在本實施例中，底膠150為封模底膠152，其中封模底膠152包覆這些第二晶片120、這些球底金屬層132及局部的各銲球162，以完成多個半導體封裝200。最後，請參閱圖2D，進行一切割製程，以使這些半導體封裝200彼此分離。
請參閱圖2E，本實施例的半導體封裝200包括一第一晶片110、一第二晶片120、多個第一導電凸塊130(各第一導電凸塊130為一球底金屬層132)、多個第二導電凸塊140、一底膠150(封模底膠152)、多個銲件160及一保護層170。第一晶片110包括一第一主動面112，其中第一主動面112包括一晶片接合區114、多個位於晶片接合區114內的第一內接點116以及多個位於晶片接合區114外之第一外接點118。保護層170配置於第一晶片110的第一主動面112上，這些第一內接點116與這些第一外接點118外露於保護層170，保護層170包括對應於晶片接合區114的一開口。
第二晶片120覆置於(flip on)第一晶片110的晶片接合區114處，且包括一第二主動面122及連接於第二主動面122的多個第二晶片120側面，其中第二主動面122包括多個第二接點124。這些球底金屬層132配置於這些第一外接點118上。這些第二導電凸塊140位於這些第一內接點116與這些第二接點124之間，各第一內接點116分別透過對應的第二導電凸塊140與對應的第二接點124電性連接。
封模底膠152位在第一主動面112上且包覆這些第二導電凸塊140、各第二晶片120側面、各球底金屬層132及局部的各銲球162。在本實施例中，第二晶片120的晶背128至第一內接點116之間的距離大於各球底金屬層132的高度，且各球底金屬層132的高度大於第一主動面112與第二主動面122之間的距離。此外，在本實施例中，各銲球162凸出於封模底膠152的高度為銲球162的高度的0.5倍至0.8倍之間，上述數值範圍可使得封模底膠152對銲球162有一定的固定效果且不影響銲球162後續與線路板(未繪示)的連接。本實施例的半導體封裝100除了第二晶片120被封模底膠152包封之外，銲球162的一部分也被封模底膠152包封，可有效增加整體的結構強度。
下面繼續介紹其他半導體封裝200a、200b。圖2F至圖2G是依照本發明的其他實施例的多種半導體封裝100的示意圖。請先參閱圖2F，圖2F的半導體封裝200a與圖2E的半導體封裝200的主要差異在於，保護層170在第一晶片110上的位置。在圖2E中，一部分的保護層170位在兩第一外接點118之間，保護層170的開口大致上對應於晶片接合區114(標示於圖2D)。在圖2F中，保護層170只位在兩第一外接點118之外，也就是說，保護層170的開口範圍接近於第一外接點118所圍繞的範圍。
請參閱圖2G，圖2G的半導體封裝200b與圖2E的半導體封裝200的主要差異在於，在本實施例中，底填膠150還包括一內底膠154，內底膠154位在第一晶片110的晶片接合區114與第二晶片120之間，封模底膠152包覆內底膠154。內底膠154的材質可與封模底膠152不同或相同。本實施例的半導體封裝100藉由先利用內底膠154填充於第一晶片110的晶片接合區114與第二晶片120之間，以保護第二導電凸塊140，再透過封模底膠152包覆第二晶片120、球底金屬層132及局部的各銲球162的兩階段式封裝，以提供半導體封裝200b良好的結構強度。
圖3是依照本發明的一實施例的一種半導體封裝100的示意圖。請參閱圖3，圖3的半導體封裝300與圖2E的半導體封裝200的主要差異在於，在本實施例中，保護層170配置於第一晶片110的第一主動面112上的這些第一外接點118所環繞的一虛擬範圍119以外的區域。底填膠150以充填塗膠的方式包覆各第二晶片120側面及局部的這些第一導電凸塊130(銲球162)，而完全的包覆住第一外接點118與導電凸塊130接合處，並終止於保護層170之邊緣。本實施例的半導體封裝100透過底膠150包覆第二晶片120的局部的各第二晶片120側面及局部的銲球162而使半導體封裝300的整體結構強度能夠提升。
綜上所述，本發明的半導體封裝的底膠包覆這些第二導電凸塊、至少局部的各第二晶片側面及至少局部的各第一導電凸塊，以增加整體的結構強度。因此，本發明的半導體封裝能具有較低的破裂率。此外，本發明更提供多種半導體封裝的製造方法，以製造出上述的半導體封裝。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100、100a、100b、100c、100d、200、200a、200b、300‧‧‧半導體封裝
105‧‧‧晶圓
110‧‧‧第一晶片
112‧‧‧第一主動面
114‧‧‧晶片接合區
116‧‧‧第一內接點
118‧‧‧第一外接點
119‧‧‧虛擬範圍
120‧‧‧第二晶片
122‧‧‧第二主動面
124‧‧‧第二接點
126‧‧‧第二晶片側面
128‧‧‧晶背
130‧‧‧第一導電凸塊
132‧‧‧球底金屬層
140‧‧‧第二導電凸塊
150‧‧‧底膠
152‧‧‧封模底膠
154‧‧‧內底膠
160‧‧‧銲件
162‧‧‧銲球
164‧‧‧銲帽
166‧‧‧銲層
170、175‧‧‧保護層
圖1A至圖1F是依照本發明的一實施例的一種半導體封裝的製造流程示意圖。 圖1G至圖1J是依照本發明的其他實施例的多種半導體封裝的示意圖。 圖2A至圖2E是依照本發明的另一實施例的一種半導體封裝的製造流程示意圖。 圖2F至圖2G是依照本發明的其他實施例的多種半導體封裝的示意圖。 圖3是依照本發明的一實施例的一種半導體封裝的示意圖。
100‧‧‧半導體封裝
110‧‧‧第一晶片
116‧‧‧第一內接點
118‧‧‧第一外接點
120‧‧‧第二晶片
124‧‧‧第二接點
130‧‧‧第一導電凸塊
140‧‧‧第二導電凸塊
150‧‧‧底膠
152‧‧‧封模底膠
160‧‧‧銲件
162‧‧‧銲球
170、175‧‧‧保護層

Claims (20)

  1. 一種半導體封裝，包括： 一第一晶片，包括一第一主動面，其中該第一主動面包括一晶片接合區、多個位於該晶片接合區內的第一內接點以及多個位於該晶片接合區外之第一外接點； 一第二晶片，覆置於(flip on)該第一晶片的該晶片接合區處，且包括一第二主動面及連接於該第二主動面的多個第二晶片側面，其中該第二主動面包括多個第二接點； 多個第一導電凸塊，配置於該些第一外接點上； 多個第二導電凸塊，位於該些第一內接點與該些第二接點之間，各該第一內接點分別透過對應的該第二導電凸塊與對應的該第二接點電性連接；以及 一底填膠，位在該第一主動面上且包覆該些第二導電凸塊、至少局部的各該第二晶片側面及至少局部的各該第一導電凸塊。
  2. 如申請專利範圍第1項所述的半導體封裝，其中該底填膠包括一封模底膠(molded underfill，MUF)，該封模底膠包覆全部的該些第二晶片側面。
  3. 如申請專利範圍第2項所述的半導體封裝，其中該第二晶片更包括相對於該第二主動面的一晶背，該晶背被該封模底膠覆蓋，或者該晶背外露於該封模底膠。
  4. 如申請專利範圍第2項所述的半導體封裝，更包括： 多個銲件，該些第一導電凸塊外露於該封模底膠，該些銲件配置於該封模底膠上且連接於該些第一導電凸塊，其中各該銲件包括一銲球、一銲帽或一銲層。
  5. 如申請專利範圍第4項所述的半導體封裝，其中該些第一導電凸塊的高度大於或等於該第二晶片的該晶背至該第一內接點之間的距離。
  6. 如申請專利範圍第2項所述的半導體封裝，更包括： 多個銲球，配置於該些第一導電凸塊上，各該第一導電凸塊為一球底金屬層(UBM)，該封模底膠包覆局部的各該銲球：以及 一保護層，配置於該第一晶片的該第一主動面上，該保護層包括至少對應於該晶片接合區的一開口，且該些第一內接點與該些第一外接點外露於該保護層。
  7. 如申請專利範圍第6項所述的半導體封裝，其中該第二晶片更包括相對於該第二主動面的一晶背，該第二晶片的該晶背至該第一內接點之間的距離大於各該第一導電凸塊的高度，且各該第一導電凸塊的高度大於各該第二導電凸塊的高度。
  8. 如申請專利範圍第6項所述的半導體封裝，其中各該銲球凸出於該封模底膠的高度為該銲球的高度的0.5倍至0.8倍之間。
  9. 如申請專利範圍第2項所述的半導體封裝，更包括： 一保護層，配置於該第一晶片的該第一主動面上，該些第一內接點與該些第一外接點外露於該保護層，該保護層包括對應於該晶片接合區的一開口，該底填膠包括一內底膠，該內底膠位在該第一晶片的該晶片接合區與該第二晶片之間，該封模底膠包覆該內底膠。
  10. 如申請專利範圍第1項所述的半導體封裝，更包括： 一保護層，配置於該第一晶片的該第一主動面上的該些第一外接點所環繞的一虛擬範圍以外的區域，該底膠包覆該第二晶片的局部的各該第二晶片側面及局部的該些第一導電凸塊，各該第一導電凸塊為一銲球。
  11. 一種半導體封裝的製造方法，包括： 提供一晶圓，包括陣列排列的多個第一晶片，其中各該第一晶片包括一第一主動面，該第一主動面包括一晶片接合區、多個位於該晶片接合區內的第一內接點以及多個位於該晶片接合區外之第一外接點； 配置多個第一導電凸塊於該些第一外接點上； 覆置多個第二晶片於該些第一晶片的該些晶片接合區，其中各該第二晶片包括一第二主動面及連接於該第二主動面的多個第二晶片側面，各該第二主動面包括多個第二接點，各該第二主動面面對該第一主動面且該些第二接點電性連接於該些第一內接點； 進行一模製(molding)底膠製程，以在該第一主動面上形成一封模底膠，其中該封模底膠包覆該些第一導電凸塊及該些第二晶片； 對該封模底膠進行一研磨製程，而使該些第一導電凸塊外露； 配置多個銲件於該些第一導電凸塊上以形成多個半導體封裝；以及 進行一切割製程，以使該些半導體封裝彼此分離。
  12. 如申請專利範圍第11項所述的半導體封裝的製造方法，其中各該銲件包括一銲球、一銲帽或一銲層。
  13. 如申請專利範圍第11項所述的半導體封裝的製造方法，其中該第二晶片更包括相對於該第二主動面的一晶背，在對該封模底膠進行該研磨製程的步驟之後，該晶背外露於該封模底膠。
  14. 如申請專利範圍第11項所述的半導體封裝的製造方法，在覆置該些第二晶片之後且進行該模製底膠製程之前，更包括： 配置一保護層於該第一晶片的該第一主動面上，該些第一內接點與該些第一外接點外露於該保護層，該保護層包括對應於該晶片接合區的一開口；以及 配置一內底膠於該第一晶片的該晶片接合區與該第二晶片之間， 其中在進行該模製底膠製程之後，該封模底膠包覆該內底膠。
  15. 一種半導體封裝的製造方法，包括： 提供一晶圓，包括陣列排列的多個第一晶片，其中各該第一晶片包括一第一主動面，該第一主動面包括一晶片接合區、多個位於該晶片接合區內的第一內接點以及多個位於該晶片接合區外之第一外接點，該第一主動面上配置有一保護層，該保護層包括至少對應於該晶片接合區的一開口，且該些第一內接點與該些第一外接點外露於該保護層； 配置多個銲球於該些第一外接點上以與該些第一外接點電性連接； 覆置多個第二晶片於該些第一晶片的該些晶片接合區，其中各該第二晶片包括一第二主動面及連接於該第二主動面的多個第二晶片側面，各該第二主動面包括多個第二接點，各該第二主動面面對該第一主動面且該些第二接點電性連接於該些第一內接點； 進行一模製(molding)底膠製程，在該第一主動面上形成一封模底膠，其中該封模底膠包覆該些第二晶片及局部的各該銲球，以完成多個半導體封裝；以及 進行一切割製程，以使該些半導體封裝彼此分離。
  16. 如申請專利範圍第15項所述的半導體封裝的製造方法，其中該些銲球與該些第一外接點之間配置有多個球底金屬層(UBM)，該封模底膠包覆該些球底金屬層。
  17. 如申請專利範圍第16項所述的半導體封裝的製造方法，其中該第二晶片更包括相對於該第二主動面的一晶背，該第二晶片的該晶背至該第一內接點之間的距離大於各該球底金屬層的高度，且各該球底金屬層的高度大於該第一主動面與該第二主動面之間的距離。
  18. 如申請專利範圍第15項所述的半導體封裝的製造方法，其中各該銲球凸出於該封模底膠的高度為該銲球的高度的0.5倍至0.8倍之間。
  19. 如申請專利範圍第15項所述的半導體封裝的製造方法，在覆置該些第二晶片之後且進行該模製底膠製程之前，更包括：配置一內底膠於該第一晶片的該晶片接合區與該第二晶片之間，其中在進行該模製底膠製程之後，該封模底膠包覆該內底膠。
  20. 如申請專利範圍第15項所述的半導體封裝的製造方法，其中該保護層位於該第一晶片的該第一主動面上的該些第一外接點所環繞的一虛擬範圍以外的區域，該封模底膠包覆該第二晶片的局部的各該第二晶片側面及局部的該些第一導電凸塊，各該第一導電凸塊為一銲球。
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