TW201801245A - 堆疊半導體晶粒用於系統級靜電放電保護的半導體裝置及方法 - Google Patents

堆疊半導體晶粒用於系統級靜電放電保護的半導體裝置及方法 Download PDF

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TW201801245A
TW201801245A TW106105448A TW106105448A TW201801245A TW 201801245 A TW201801245 A TW 201801245A TW 106105448 A TW106105448 A TW 106105448A TW 106105448 A TW106105448 A TW 106105448A TW 201801245 A TW201801245 A TW 201801245A
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semiconductor die
semiconductor
die
protection circuit
conductive
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TW106105448A
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TWI713146B (zh
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黃昌俊
喬納森 克拉克
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先科公司
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Abstract

一種半導體裝置,其具有包含一第一保護電路的一第一半導體晶粒。包含一第二保護電路的一第二半導體晶粒被設置在該第一半導體晶粒之上。該第一半導體晶粒以及第二半導體晶粒的一部分被移除,以降低晶粒的厚度。一互連結構被形成以共同地連接該第一保護電路以及第二保護電路。入射至該互連結構的一暫態狀況係整體透過該第一保護電路以及第二保護電路來加以放電。任意數目的具有保護電路的半導體晶粒都可加以堆疊並且經由該互連結構來加以互連,以增進ESD電流放電能力。該晶粒堆疊可以藉由將一第一半導體晶圓設置在一第二半導體晶圓之上,並且接著單粒化該些晶圓來加以達成。或者是,利用晶粒至晶圓或晶粒至晶粒的組件。

Description

堆疊半導體晶粒用於系統級靜電放電保護的半導體裝置及方法
本發明係大致有關於半導體裝置,並且更具體而言係有關於一種堆疊半導體晶粒以在小型的半導體封裝中提供系統級靜電放電(ESD)、過度電性應力(EOS)、以及電性快速暫態脈衝(EFT)保護之半導體裝置及方法。
半導體裝置係常見於現代的電子產品中。半導體裝置係在電性構件的數目及密度上變化。離散的半導體裝置一般包含一類型的電性構件,例如是發光二極體(LED)、小信號電晶體、電阻器、電容器、電感器、或是功率金屬氧化物半導體場效電晶體(MOSFET)。集積的半導體裝置通常包含數百個到數百萬個電性構件。集積的半導體裝置的例子係包含微控制器、微處理器、電荷耦合裝置(CCD)、太陽能電池、以及數位微鏡裝置(DMD)。
半導體裝置係執行廣範圍的功能,例如是信號處理、高速的計算、傳送及接收電磁信號、控制電子裝置、轉換太陽光成為電力、以及產生用於電視顯示器的視覺影像。半導體裝置係見於娛樂、通訊、電力轉換、網路、電腦以及消費者產品的領域中。半導體裝置亦見於軍事的應用、航空、汽車、工業用的控制器、以及辦公室設備中。
半導體製造的一目標是產出較小的半導體裝置。較小的裝置通常消耗較低的功率,可以更有效率地加以生產,並且具有較高的效能。此外,較小的半導體裝置係具有一較小的覆蓋區,其係增加在印刷電路板上的裝置密度以及縮減終端產品的尺寸所期望的。較小的晶粒尺寸可藉由在產生具有較小且較高密度的主動及被動構件之半導體晶粒的前端製程中的改良來加以達成。後端製程可以藉由在電互連及封裝材料上的改良來產生具有較小覆蓋區的半導體裝置封裝。
半導體裝置已知是容易受到來自整體被稱為ESD事件的靜電放電(ESD)、過度電性應力(EOS)、以及電性快速暫態脈衝(EFT)的損壞影響的。當譬如靜電電荷累積在人體上時,一高的靜態電位係相對於接地被形成。若該人體電性接觸一半導體裝置時,則該人體的靜態電位係透過該半導體裝置來放電一電流,在給定一足夠大的電流下,其可能會損壞該半導體裝置的主動及被動電路。若一個別的電路元件的一崩潰電壓被超過時,則該半導體裝置可能會遠在其有用的預期壽命之前就會變成是有缺陷的。
半導體裝置可包含一針對於ESD事件的保護電路。該保護電路係具有有限的放電來自該ESD事件的電流之能力。為了增進該保護能力,該半導體封裝通常是被做成較大的,以包含更多晶粒面積並且處理一更高的電流。然而,增加半導體封裝尺寸是和較小的封裝以及終端產品的目標不一致的。許多的應用就是不容許有較大的半導體封裝,甚至是在需要較大的ESD保護的情況中也是如此。
在第一實施例中,一種製造一半導體裝置之方法,其包括下列步驟:提供包含一第一保護電路的一第一半導體晶粒;在該第一半導體晶粒之上設置包含一第二保護電路的一第二半導體晶粒,其中該第一半導體晶粒的一第一導電貫孔係對準該第二半導體晶粒的一第二導電貫孔;在該第一導電貫孔以及第二導電貫孔之間提供一互連結構;以及將該第一半導體晶粒以及第二半導體晶粒設置在一引線架之上,其中該第一保護電路以及第二保護電路係並聯電性耦接在該引線架的一第一端子以及一第二端子之間。
在第二實施例中,一種製造一半導體裝置之方法,其包括下列步驟:提供包含一第一保護電路的一第一半導體晶粒;以及在該第一半導體晶粒之上設置包含一第二保護電路的一第二半導體晶粒,其中該第一保護電路以及第二保護電路係並聯電性耦接的。
在第三實施例中,一種半導體裝置,其包括一第一半導體晶粒,其包含一第一保護電路。一第二半導體晶粒,其包含被設置在該第一半導體晶粒之上的一第二保護電路。該第一保護電路以及第二保護電路係並聯電性耦接在一引線架的一第一端子以及該引線架的一第二端子之間。
50‧‧‧電子裝置
52‧‧‧PCB
54‧‧‧信號線路
56-72‧‧‧半導體封裝
120‧‧‧半導體晶圓
122‧‧‧主體基板材料
124、124a、124b、124c‧‧‧半導體晶粒
126‧‧‧切割道
128‧‧‧背表面(非主動表面)
130‧‧‧主動表面
132、132a、132b‧‧‧直通矽晶穿孔(TSV)
134、134a、134b‧‧‧導電層(接觸墊)
138‧‧‧研磨機
140‧‧‧凸塊(球體)
140a‧‧‧端子(凸塊)
140b‧‧‧端子(凸塊)
142‧‧‧鋸刀(雷射切割工具)
150‧‧‧保護電路(TVS二極體)
160‧‧‧引線架(基板)
160a、160b‧‧‧端子(引線架接點)
162‧‧‧密封劑(模製化合物)
164‧‧‧半導體封裝
166、167‧‧‧輸入端子
168‧‧‧負載電路
170‧‧‧半導體晶粒
172‧‧‧半導體晶圓
174‧‧‧導電層
176‧‧‧導電的TSV
178‧‧‧凸塊
180‧‧‧鋸刀(雷射切割工具)
182‧‧‧半導體封裝
184‧‧‧引線架(基板)
186‧‧‧密封劑
190‧‧‧半導體晶圓
192‧‧‧半導體晶圓
194‧‧‧導電層
196‧‧‧導電的TSV
197‧‧‧凸塊
198‧‧‧半導體晶粒
200‧‧‧導電層
202‧‧‧導電的TSV
204‧‧‧凸塊
206‧‧‧半導體晶粒
210‧‧‧鋸刀(雷射切割工具)
212‧‧‧半導體封裝
214‧‧‧引線架(基板)
216‧‧‧密封劑
230‧‧‧導電層(接觸墊)
232‧‧‧絕緣(鈍化)層
233‧‧‧鋸刀(雷射切割工具)
234‧‧‧TVS封裝
240‧‧‧底板
244‧‧‧頂板
250‧‧‧TVS封裝
260‧‧‧引線架
262‧‧‧晶粒墊
264‧‧‧引線
266‧‧‧黏著層
268‧‧‧接合線
270‧‧‧密封劑
272‧‧‧TVS裝置
圖1是描繪一印刷電路板(PCB),其中不同類型的封裝被安裝到該PCB的一表面;圖2a-2e描繪形成一具有半導體晶粒的半導體晶圓的製程;圖3是描繪被形成在該半導體晶粒上的一保護電路; 圖4a-4b描繪具有分別包含該保護電路的堆疊的半導體晶粒的一半導體封裝,並且該半導體封裝係耦接以保護一負載免於ESD事件;圖5a-5c描繪在一半導體晶圓之上堆疊一半導體晶粒;圖6a-6c描繪在一第二半導體晶圓之上堆疊一第一半導體晶圓;圖7a-7d描繪被形成在該些半導體晶圓或半導體晶粒的背表面上的接觸墊;圖8a-8c描繪利用熱壓來將半導體晶圓或半導體晶粒接合在一起;以及圖9是描繪利用接合線來將一半導體晶粒的堆疊耦接至一引線架。
本發明在以下參考該些圖式的說明中,以一或多個實施例來加以描述,其中相同的元件符號係代表相同或類似的元件。儘管本發明以用於達成本發明之目的之最佳模式來加以描述,但熟習此項技術者將會體認到的是,該說明欲涵蓋可內含在藉由以下的揭露內容及圖式所支持之所附的申請專利範圍及該些申請專利範圍的等同項所界定的本發明的精神與範疇內的替換物、修改以及等同物。
圖1描繪具有一晶片載體基板或是PCB 52之電子裝置50,其中複數個半導體封裝係被安裝於PCB 52的一表面之上。電子裝置50可具有一種類型之半導體封裝、或是多種類型之半導體封裝,此係根據應用而定。不同類型之半導體封裝係為了說明之目的而展示於圖1中。
電子裝置50可以是使用該些半導體封裝以執行一或多種電性功能之一獨立的系統。或者是,電子裝置50可以是一較大系統之子構件。舉例而言,電子裝置50可以是平板電腦、行動電話、數位相機、或是其它 電子裝置的一部份。或者是,電子裝置50可以是一可插入電腦中之顯示卡、網路介面卡、或是其它信號處理卡。該半導體封裝可包括微處理器、記憶體、特殊應用積體電路(ASIC)、微機電系統(MEMS)、邏輯電路、類比電路、射頻(RF)電路、離散裝置、或是其它半導體晶粒或電性構件。小型化及重量減輕是這些產品能夠被市場接受所不可少的。在半導體裝置間的距離可加以縮短,以達到更高的密度。
在圖1中,PCB 52係提供一般的基板以供安裝在該PCB上之半導體封裝的結構支撐及電互連。導電的信號線路54係利用蒸鍍、電解的電鍍、無電的電鍍、網版印刷、或其它適合的金屬沉積製程而被形成在PCB 52的一表面之上或是在層內。信號線路54係提供在半導體封裝、安裝的構件、以及其它外部的系統構件的每一個之間的電性通訊。線路54亦提供電源及接地連接給每一個半導體封裝。
圖2a展示具有一種主體基板材料122的一半導體晶圓120,該主體基板材料122例如是矽、鍺、磷化鋁、砷化鋁、砷化鎵、氮化鎵、磷化銦、碳化矽、或是其它基體半導體材料,以用於結構的支撐。複數個半導體晶粒或構件124係被形成在晶圓120上,其藉由如上所述的一非主動的晶粒間的晶圓區域或切割道126來加以分開。切割道126提供切割區域以將半導體晶圓120單粒化成為個別的半導體晶粒124。在一實施例中,半導體晶圓120係具有一200-300毫米(mm)的寬度或直徑以及700微米(μm)的厚度。在另一實施例中,半導體晶圓120係具有一100-450mm的寬度或直徑。
圖2b係展示半導體晶圓120的一部分的橫截面圖。每一個半導體晶粒124係具有一背面或非主動表面128以及一主動表面130,該主 動表面130係包含被實施為主動裝置、被動裝置、導電層、以及介電層的類比或數位電路,其係被形成在該晶粒之內並且根據該晶粒的電性設計以及功能來電性互連的。半導體晶圓120係具有一1k歐姆/cm的數量級或更大的高電阻率。主動表面130可被植入氧化物,以抑制表面導通。
複數個盲貫孔係利用雷射鑽孔、機械式鑽孔、深反應性離子蝕刻(DRIE)、或是其它適當的製程,部分地穿過主體基板材料122來加以形成。該些穿透貫孔係利用電解的電鍍、無電的電鍍製程、或是其它適合的金屬沉積製程而被填入鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鈦(Ti)、鎢(W)、多晶矽、或是其它適當的導電材料,以形成z方向垂直的互連結構或是導電的直通矽晶穿孔(TSV)132。
一導電層134係利用PVD、CVD、電解的電鍍、無電的電鍍、或是其它適合的金屬沉積製程而被形成在主動表面130之上。導電層134係包含與主動表面130共平面的一表面。在另一實施例中,導電層134係部分或是完全地在主動表面130之上而被形成。
導電層134係包含一或多層的Al、Cu、Sn、Ni、Au、Ag、或是其它適當的導電材料、或是其之組合。導電層134係運作為接觸墊,其係電連接至在主動表面130上的電路、以及導電的TSV 132。如同在圖2b中所示,導電層134係被形成為接觸墊,該些接觸墊係與半導體晶粒124的邊緣相隔一第一距離而被並排設置。或者是,導電層134係被形成為偏置的接觸墊於多個列中,使得一第一列的接觸墊係相隔該晶粒的邊緣一第一距離而被設置,並且和該第一列交錯的一第二列的接觸墊係相隔該晶粒的邊緣一第二距離而被設置。在一實施例中,半導體晶粒124是一離散的 暫態電壓抑制(TVS)二極體,並且只有兩個接觸墊134係被設置以用於該兩個二極體端子。
導電層134的部分是根據半導體晶粒124的路由設計(routing design)及功能而為電性共通或是電性隔離的。在某些實施例中,導電層134係運作為一重分佈層(RDL),以從導電的TSV 132延伸電連接,並且橫向地重分佈電性信號至半導體晶粒124的其它區域。在另一實施例中,導電層134係運作為一可以引線接合的墊或層,以用於往返於導電的TSV 132的電互連。
在圖2c中,半導體晶圓120的背表面128係利用研磨機138或是其它適當的機械、化學、或是蝕刻製程來進行一背面研磨操作,以移除主體材料122的一部分。該背面研磨操作降低包含半導體晶粒124的半導體晶圓120的厚度,並且露出導電的TSV 132。在一實施例中,半導體晶粒具有一50-200μm的研磨後的厚度。在該背面研磨操作之後,TSV 132係包含與半導體晶粒124的新的背表面128共平面的表面。
在圖2d中,一種導電凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落、或是網版印刷製程而被沉積在導電層134之上。該凸塊材料係包含具有一選配的助焊溶劑的Al、Sn、Ni、Au、Ag、鉛(Pb)、鉍(Bi)、Cu、焊料、或是其之組合。例如,該凸塊材料可以是共晶Sn/Pb、高鉛的焊料、或是無鉛的焊料。該凸塊材料係利用一適當的附接或接合製程而被接合到導電層134。在一實施例中,該凸塊材料係藉由加熱該材料超過其熔點來加以回焊,以形成球狀的球體或凸塊140。在某些應用中,凸塊140係被回焊第二次以改善至導電層134的電性接觸。該些凸塊亦可被壓縮 接合到導電層134。凸塊140係代表一種被形成在導電層134之上的互連結構的類型。該互連結構亦可以使用接合線、柱形凸塊、微凸塊、或是其它電互連。凸塊140或是其它互連結構是選配的,並且可以在半導體晶圓120的單粒化之後加以形成。
在圖2e中,半導體晶圓120係利用一鋸刀或雷射切割工具142,穿過切割道126而被單粒化成為個別的半導體晶粒124。在另一實施例中,半導體晶圓120係利用DRIE而被單粒化成為個別的半導體晶粒124。
半導體晶粒124係利用在PCB 52上的半導體封裝56-72來操作,以提供保護免於ESD事件。當靜電電荷累積在人體上時,一高的靜態電壓電位係相對於接地而被形成。若該人體電性接觸該半導體裝置,則該靜態電位係注入大的電流並且透過該裝置來放電,此可能會損壞在該裝置上的主動及被動電路。
在一實施例中,半導體晶粒124係專用於ESD保護。例如,半導體晶粒124係包含一或多個被形成在主動表面130之內的電晶體、二極體、以及其它電路元件以實施一ESD保護電路,其係提供五十安培或更高的波峰電流放電或耗散。在另一實施例中,每一個半導體晶粒124是一離散的TVS二極體,其係在一橫跨端子的電壓超出一臨界值時,從端子140a至端子140b導通電力。當橫跨端子140a及140b的電壓電位低於該臨界值時,半導體晶粒124的TVS二極體係近似在該些端子之間的開路。
圖3是展示半導體晶粒124的TVS二極體或保護電路150。保護電路150的一輸入通常是耦接至導電層134a、導電的TSV 132a、以及凸塊140a。保護電路150的一輸出通常是耦接至導電層134b、導電的TSV 132b、以及凸塊140b。半導體晶粒124的凸塊140a係連接至一在PCB 52上的電路節點,該電路節點係與該ESD事件可能會發生在其上的一或多個半導體封裝56-72共用的。凸塊140b係耦接至一接地電位節點。
在例如是2.5伏特下的正常的操作中,保護電路150係非作用中的,並且電性信號係流向在PCB 52上的半導體封裝56-72。在一ESD事件期間,在PCB 52的電路節點上的一電壓尖脈衝或是暫態狀況亦入射到凸塊140a,並且啟動保護電路150(或是導通TVS 150)。當被啟動時,保護電路150係透過導電層134b以及凸塊140b來放電和該ESD事件相關的電流尖脈衝至接地。例如,該ESD事件可能是由帶有靜電電荷的人體接觸到在PCB 52上的一或多個半導體封裝56-72所引起的。保護電路150係偵測在凸塊140a之處所產生的電壓暫態,並且透過半導體晶粒124來放電該高電流至接地。
保護電路150可以利用一電壓箝位電路來加以實施,該電壓箝位電路係連接至凸塊140a並且包含一或多個具有充分額定值的電晶體,以放電或耗散一50安培或更高的大ESD電流。半導體封裝56-72係藉由電流透過半導體晶粒124而被分流來加以保護免於該ESD事件,而不是透過在PCB 52上的封裝。其它半導體晶粒124的其它凸塊140係連接至在PCB 52上的其它易受ESD事件影響的電路節點。
在PCB 52上可利用於ESD保護的空間是有限的。圖4a係描繪一種具有增進的ESD電流放電能力以及小的半導體封裝尺寸之裝置。如同在圖2c中所敘述的,半導體晶粒124係進行背面研磨以降低晶粒厚度。複數個半導體晶粒124係被堆疊在基板或引線架160上,以形成半導體封裝 164。如同在圖2e中從半導體晶圓120被單粒化的半導體晶粒124c係被設置在引線架160之上,其中凸塊140係被接合到端子160a及160b。半導體晶粒124c的凸塊140是在一個別的引線架接點160a及160b的一覆蓋區之內,並且是在一個別的引線架接點與半導體晶粒124c之間。半導體晶粒124c的凸塊140係被回焊,以透過該些凸塊來機械式及電性耦接半導體晶粒124c至引線架160。
同樣如同從半導體晶圓120被單粒化的半導體晶粒124b係被設置在半導體晶粒124c之上,其中半導體晶粒124b的凸塊140係被接合到半導體晶粒124c的導電的TSV 132。如同從半導體晶圓120被單粒化的半導體晶粒124a係被設置在半導體晶粒124b之上,其中半導體晶粒124a的凸塊140係被接合到半導體晶粒124b的導電的TSV 132。於是,半導體晶粒124a-124c係被堆疊,並且透過包括導電層134、導電的TSV 132、以及凸塊140的互連結構來電性並聯連接在引線架接點160a及160b之間。儘管每一個半導體晶粒124的每一個主動表面130都被定向在一共同的方向上,但是許多TVS二極體的實施例是對稱的,並且可以在晶粒或晶圓層級下,面對面或是背對背地加以堆疊。
在半導體晶粒124a-124c之間的互連結構亦可以利用引線接合、柱形凸塊、導電膏、直接的晶粒附接、或是其它電互連結構來加以實施。例如,在每一個半導體晶粒124a-124c中的保護電路150是利用引線接合來共同地連接。或者是,半導體封裝164的厚度可以藉由將半導體晶粒124c的導電層134a直接接合至端子160a-160b,亦即在無凸塊140下直接接合來進一步降低。半導體晶粒124b的導電層134a係直接接合至半導體晶粒 124c的導電的TSV 132a,並且半導體晶粒124a的導電層134a係直接接合至半導體晶粒124b的導電的TSV 132a。接觸墊134a至端子160a-160b或是至導電貫孔132的直接的金屬到金屬的接合在一實施例中係利用熱壓接合來加以完成。
一密封劑或模製化合物162係利用一膏印刷、壓縮模製、轉移模製、液體密封劑模製、真空疊層、旋轉塗覆、或是其它適當的施用器,而被沉積在半導體晶粒124a-124c以及引線架160之上來作為一種絕緣材料。密封劑162係包含聚合物複合材料,例如是環氧樹脂、環氧丙烯酸酯、或是具有適當的填充物的聚合物。密封劑162是非導電的,並且在環境上保護半導體裝置免於外部的元素及污染物。
圖4b係描繪具有保護電路150的半導體封裝164,該保護電路150係耦接在輸入端子166-167以及一負載電路168之間,以保護該負載電路免於在輸入端子166上的ESD事件。負載電路168係代表ESD保護是所要的電子裝置50的半導體封裝或是其它電路。輸入端子166-167係代表至電子裝置50的電源及接地輸入。在其它實施例中,輸入端子166-167係代表電子裝置50的類比或數位輸入或輸出,例如是一頭戴式耳機插頭、或是一行動電話或平板電腦的萬用串列匯流排埠。半導體封裝164係被耦接在輸入端子166與運作為一用於信號傳送的接地節點的輸入端子167之間。
在利用一例如是2.5伏特的電壓之正常的操作中,在半導體晶粒124a-124c上的保護電路150係非作用中的,並且電性信號係流向在PCB 52上的半導體封裝56-72。通往半導體封裝56-72的電性信號係耦接至封裝164,使得在一ESD事件期間,在PCB 52的一電路節點上的一電壓尖脈衝 或暫態狀況亦入射在凸塊140a上。利用在半導體晶粒124a-124c上的晶粒堆疊以及用於保護電路150的共同的互連結構,該電壓尖脈衝係同時入射在每一個半導體晶粒124a-124c的導電層134a以及導電的TSV 132a上。
在每一個半導體晶粒124a-124c上的保護電路150係被並聯耦接在一電性信號與一接地電壓節點之間。每一個半導體晶粒124係同時感測到該電壓暫態狀況,並且啟動以一相當高的電流,透過導電層134b、導電的TSV 132b、以及凸塊140b來全體放電來自該ESD事件的電荷至接地。例如,該ESD事件可能是由帶有靜電電荷的人體接觸在PCB 52上的一或多個半導體封裝56-72所引起的。在半導體晶粒124a-124c上的保護電路150偵測所產生的電壓尖脈衝、或是被其啟動,並且透過導電層134b、導電的TSV 132b、以及凸塊140b來放電電流至接地。
在其中半導體晶粒124包含一離散的TVS二極體的實施例中,該ESD事件超過每一個並聯耦接的半導體晶粒的TVS二極體的導通電壓。來自該ESD事件的電流係被指定路由為透過並聯的每一個半導體晶粒124至一接地電壓節點。因此,半導體封裝56-72與該ESD事件隔離開。當一ESD事件發生在特定的ESD敏感的電路節點上時,多個半導體封裝164可被利用以將PCB 52上的多個ESD敏感的電路節點耦接至接地。
在半導體晶粒124a-124c上的保護電路150的堆疊性質以及共同的電連接係增進半導體封裝164的ESD保護能力,而在封裝覆蓋區上並無顯著的增加。在封裝164之內並聯電連接多個半導體晶粒124係使得來自一ESD事件的電流被指定路由來通過任意數目的並聯的保護電路150。儘管單一保護電路150可能只有額定來指定路由例如是一百毫安培的電 流,但是在封裝164之內並聯連接三個半導體晶粒124係產生一可以處理三倍的該電流、或是高達三百毫安培的封裝。
該增大的ESD保護能力係歸功於並聯的半導體晶粒124,其將高的ESD電流分散在堆疊的半導體晶粒的多個保護電路150之間。在該些堆疊的半導體晶粒124a-124c上的保護電路150係全體運作以增加被配置用於該ESD電流尖脈衝透過導電層134b、導電的TSV 132b、以及凸塊140b的放電或耗散至接地的總矽表面積。因為額外的處理電流的能力係由堆疊在和其它半導體晶粒相同的覆蓋區之內的額外的半導體晶粒124所提供,因此在處理電流的能力上的增加係在封裝覆蓋區上無顯著的增加下發生。
在圖4a中的半導體封裝164係包含三個堆疊的半導體晶粒124a-124c,每一個半導體晶粒係具有一保護電路150,該些保護電路150係透過包括導電層134、導電的TSV 132、以及凸塊140的互連結構來共同地連接。半導體封裝164的高ESD保護能力係藉由如同在圖2c中所敘述的最小化半導體晶粒124a-124c的厚度的本質,並且接著如同在圖4中所示地堆疊經薄化的半導體晶粒,而以小的封裝尺寸來加以達成。在一實施例中,每一個半導體晶粒124的長度及寬度尺寸是1mm×1mm、以及一50-200μm的厚度。在半導體封裝164中的半導體晶粒124的堆疊數目可以根據保護的需求而變化。半導體封裝164可包含盡可能實際且必要多的堆疊且電性並聯耦接的半導體晶粒124以實現目標的ESD保護能力,例如在某些實施例中使用5-7個堆疊的半導體晶粒。
除了保護電路150之外,主動表面130可包含類比電路或數位電路,例如是數位信號處理器(DSP)、ASIC、MEMS、記憶體、或是其它 信號處理電路。在一實施例中,主動表面130係包含一MEMS,例如是一加速度計、陀螺儀、應變計、麥克風、或是其它響應於各種外部刺激的感測器。半導體晶粒124亦可包含整合的被動裝置(IPD),例如是電感器、電容器、以及電阻器,以用於信號處理或調節。
圖5a-5c描繪另一實施例,其中來自圖26的經單粒化的半導體晶粒124被安裝在半導體晶圓172的半導體晶粒170之上。半導體晶圓172依照一種和半導體晶圓120類似的結構。類似於圖2b,導電層174、導電的TSV 176、以及凸塊178係被形成於半導體晶粒170。半導體晶粒124及170分別包含例如是一TVS二極體的保護電路150。在圖5a中,在類似於圖2c的背面研磨半導體晶圓172之後,半導體晶粒124係被拾起,並且與對應的半導體晶粒170對準地加以放置。半導體晶粒124的凸塊140係被接合到半導體晶粒170中的導電的TSV 176。
在圖5b中,半導體晶圓172係利用一鋸刀或雷射切割工具180而被單粒化成為個別的半導體晶粒124及170的堆疊。類似於圖4,圖5c係展示半導體封裝182,其中堆疊的半導體晶粒124及170係被安裝到基板或引線架184,並且被覆蓋密封劑186。半導體封裝182係提供增大的ESD保護能力,因為複數個保護電路150係如同針對於半導體封裝164所敘述地並聯耦接在一小型的半導體封裝中。
圖6a-6c係描繪另一實施例,其中半導體晶圓192被安裝在半導體晶圓190之上。半導體晶圓190及192依照一種和半導體晶圓120類似的結構。類似於圖2b,導電層194、導電的TSV 196、以及凸塊197被形成於半導體晶粒198。同樣地,導電層200、導電的TSV 202、以及凸塊204 被形成於半導體晶粒206。半導體晶粒198及206分別包含保護電路150。在圖6a中,在類似於圖2c的背面研磨半導體晶圓190及192之後,半導體晶圓192被安裝到半導體晶圓190,其中半導體晶粒206係對準到半導體晶粒198。半導體晶粒206的凸塊204被接合到半導體晶粒198中的導電的TSV 196。
在圖6b中,半導體晶圓190及192利用一鋸刀或雷射切割工具210而被單粒化成為個別的堆疊的半導體晶粒198及206。類似於圖4,圖6c展示半導體封裝212,其中堆疊的半導體晶粒198及206被安裝到基板或引線架214,並且被覆蓋密封劑216。如同針對於半導體封裝164所敘述的,半導體封裝212在一小型的半導體封裝中提供高的ESD保護能力。
圖6a-6c描繪保護裝置的晶圓至晶圓的接合,而圖5a-5c描繪晶粒至晶圓的接合。在某些實施例中,晶圓至晶圓的接合可以與晶粒至晶圓的接合結合。譬如,來自圖5a的半導體晶粒124可以在半導體晶圓192被接合到半導體晶圓190之前或是之後,被接合在圖6a中的半導體晶圓192之上。
圖7a-7d描繪在圖2c中的背面研磨半導體晶圓120之後,在半導體晶粒124的背表面128之上形成一導電層230。在圖7a中,導電層230在每一個導電貫孔132之上形成接觸墊,以用於凸塊140至該半導體晶粒的背表面128的改善的接合。在其它實施例中,導電層230包含用於電性信號至背表面128上的替代位置的重分佈之導電線路。導電層230以一種類似於導電層134的方式來加以形成。
在圖7b中,一選配的絕緣或鈍化層232被形成在導電層230 周圍的背表面128之上。絕緣層232利用PVD、CVD、印刷、疊層、旋轉塗覆、或是噴霧塗覆來加以形成。絕緣層232包含一或多層的二氧化矽(SiO2)、矽氮化物(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、鋁氧化物(Al2O3)、阻焊劑、或是其它具有類似絕緣及結構的性質之材料。絕緣層232的一部分藉由蝕刻或雷射直接剝蝕(LDA)來加以移除,以在該絕緣層中形成開口並且露出導電層230以用於後續的電互連。在某些實施例中,絕緣層232的一部分係藉由背面研磨來加以移除,以從該絕緣層露出導電層230並且產生該絕緣層的一與該導電層的一表面共平面的表面。
在圖7c中,複數個具有導電層230的導電的晶圓120係被堆疊,並且透過導電凸塊140來加以連接。導電凸塊140係被回焊在一半導體晶圓120的接觸墊134以及一第二半導體晶圓的接觸墊230之間,以將該些晶圓彼此機械式地接合及電耦接。任何所要的數目的半導體晶圓120都可加以堆疊以及並聯連接。該半導體晶圓120接著藉由鋸刀或雷射切割工具233而被單粒化為個別的裝置。具有導電層230的半導體晶粒124亦可以在單粒化或是晶粒至晶圓之後,晶粒至晶粒地加以堆疊。
在圖7c中被單粒化的堆疊的半導體晶粒124的經單粒化的單元係在圖7d中被設置在引線架160之上,並且透過半導體晶粒124b的凸塊140來連接至接點160a-160b。密封劑162被沉積在引線架160以及半導體晶粒124之上,以用於電性隔離以及環境的保護。半導體晶粒124a及124b被並聯耦接在端子160a及160b之間。一般而言,引線架160被提供為一相當大的片,並且許多堆疊的半導體晶粒124的單元被設置在單一引線架之上,而且一起被封入。密封劑162延伸在每一個半導體晶粒124之間以及在 引線架160與半導體晶粒124b之間。當密封劑162被沉積時,引線架160通常是在一載體上,此係導致密封劑162的一下表面是與引線架160的底部共平面的。
在封入之後,該複數個TVS封裝234係穿過引線架160以及密封劑162而被單粒化,以分開該些個別的封裝。單粒化係切穿過引線架160,並且產生從密封劑162露出的端子160a-160b的新的側表面或是側面。TVS封裝234係被設置在圖1中的PCB 52上,並且端子160a及160b係被焊接到該PCB上的導電的墊或線路,以保護一電路元件免於ESD事件。端子160a-160b的露出的側表面係可藉由焊料潤濕的,因而增加用於在TVS封裝234與PCB 52之間的焊料的表面積。
圖8a-8c描繪堆疊複數個半導體晶圓120,其中該些晶圓藉由熱壓或是擴散接合來機械式且電性連接至彼此。圖8a描繪具有接觸墊230、但不具有導電凸塊140或絕緣層232的晶圓120。在圖8b中,來自圖8a的複數個晶圓120被堆疊在一熱壓夾具的一底板240以及一頂板244之間。板240及244被用來施加力及熱至半導體晶圓120。在接觸墊230與接觸墊134之間的熱及壓力使得在對齊的接觸墊之內的金屬原子擴散到彼此之內。
在晶圓120藉由熱壓而被接合在一起之後,該些堆疊的晶圓係被單粒化,並且利用導電凸塊140而被安裝到引線架160之上。在其它實施例中,該些堆疊的半導體晶粒124在無導電凸塊140下,藉由熱壓來耦接至引線架160。晶圓120至引線架160的熱壓可以是在一和晶圓120彼此的接合共同的熱壓步驟中、或是以另一熱壓步驟來加以執行。熱壓可以是晶 圓至晶圓、晶粒至晶圓、或是晶粒至晶粒的。密封劑162沉積在半導體晶粒124以及引線架160之上以形成一面板,並且接著該面板被單粒化以彼此分開TVS封裝250。利用熱壓接合係藉由消除在某些或是全部的裝置層之間的導電凸塊140的厚度,而降低TVS封裝250的整體厚度。
圖9是描繪另一實施例,其中除了引線264之外,引線架260具有一晶粒墊262。先前揭露的半導體晶粒堆疊的任一個利用一選配的黏著層266而被設置在晶粒墊262上。半導體晶粒124的堆疊可被設置在晶粒墊262之上,其中主動表面130係朝向或是遠離該晶粒墊來加以定向。在某些實施例中,半導體晶粒124的主動表面130被定向在相反的方向上。在所要的實施例中,黏著層266在半導體晶粒124與晶粒墊262之間提供電性隔離。接觸墊230或134(根據頂端的半導體晶粒124的朝向而定)藉由接合線268來耦接至引線264。接合線268藉由熱壓接合、超音波接合、楔形接合、線尾接合、球形接合、或是其它適當的接合技術,來機械式且電性耦接至接觸墊230以及端子264。接合線268包含一種例如是Cu、Al、Au、Ag、其之一組合的導電材料、或是其它適當的導電材料。
密封劑270沉積在半導體晶粒124、引線架260、以及接合線268之上,以形成一片封入的裝置。該片係藉由一鋸刀或雷射切割工具而被單粒化,以產生個別的TVS裝置272。TVS裝置272藉由並聯耦接複數個經薄化的保護裝置,而無顯著地增加裝置尺寸來增進保護能力。
具有互連的保護電路之堆疊的半導體晶粒係提供一種具有一小的封裝形式因數的系統級ESD保護。該半導體封裝的每單位尺寸的功率處理能力(功率額定值)的增大係藉由該堆疊的拓撲以增加被配置用於 ESD電流尖脈衝的放電或耗散的總矽表面積,同時藉由在一共同的覆蓋區中堆疊保護電路以維持一小的封裝形狀因數。來自ESD事件的能量透過每一個堆疊的半導體晶粒的共同連接的保護電路而被分散及耗散。分別具有一保護電路的多個半導體晶粒的堆疊的性質提供增進該ESD保護功能的能力,而不顯著地增加封裝尺寸。該堆疊的拓撲可以藉由晶粒至晶粒、晶粒至晶圓、或是晶圓至晶圓的堆疊製程來加以達成。
儘管本發明的一或多個實施例已經詳細地描述,但是本領域的技術人員將會體認到可以對於那些實施例做成修改及調適,而不脫離如同在以下的申請專利範圍中所闡述的本發明的範疇。
124a、124b、124c‧‧‧半導體晶粒
132a、132b‧‧‧直通矽晶穿孔(TSV)
134a、134b‧‧‧導電層(接觸墊)
140a‧‧‧端子(凸塊)
140b‧‧‧端子(凸塊)
160a、160b‧‧‧端子(引線架接點)
162‧‧‧密封劑(模製化合物)
164‧‧‧半導體封裝

Claims (15)

  1. 一種製造一半導體裝置之方法,其係包括:提供包含一第一保護電路的一第一半導體晶粒;在該第一半導體晶粒之上設置包含一第二保護電路的一第二半導體晶粒,其中該第一半導體晶粒的一第一導電貫孔係對準該第二半導體晶粒的一第二導電貫孔;在該第一導電貫孔以及第二導電貫孔之間提供一互連結構;以及將該第一半導體晶粒以及第二半導體晶粒設置在一引線架之上,其中該第一保護電路以及第二保護電路係並聯電性耦接在該引線架的一第一端子以及一第二端子之間。
  2. 如申請專利範圍第1項之方法,其中提供該互連結構包含:在該第一導電貫孔之上的該第一半導體晶粒的一表面上形成一第一接觸墊;在該第二導電貫孔之上的該第二半導體晶粒的一表面上形成一第二接觸墊;以及藉由熱壓以將該第一接觸墊接合至該第二接觸墊。
  3. 如申請專利範圍第1項之方法,其中提供該互連結構包含:在該第二半導體晶粒的一表面上形成一接觸墊,並且該接觸墊與該第一導電貫孔對準;以及在該接觸墊以及該第一導電貫孔之間設置一導電凸塊。
  4. 如申請專利範圍第1項之方法,其進一步包含當該第一半導體晶粒還是一第一半導體晶圓的部分時,在該第一半導體晶粒之上設置該第二半導 體晶粒。
  5. 如申請專利範圍第4項之方法,其進一步包含當該第二半導體晶粒還是一第二半導體晶圓的部分時,在該第一半導體晶粒之上設置該第二半導體晶粒。
  6. 如申請專利範圍第1項之方法,其進一步包含在該第一半導體晶粒、第二半導體晶粒、以及引線架之上沉積一密封劑。
  7. 一種製造一半導體裝置之方法,其包括:提供包含一第一保護電路的一第一半導體晶粒;以及在該第一半導體晶粒之上設置包含一第二保護電路的一第二半導體晶粒,其中該第一保護電路以及第二保護電路係並聯電性耦接的。
  8. 如申請專利範圍第7項之方法,其進一步包含將該第一半導體晶粒以及第二半導體晶粒設置在一引線架之上,其中該第一保護電路以及第二保護電路係並聯電性耦接在該引線架的一第一端子以及該引線架的一第二端子之間。
  9. 如申請專利範圍第7項之方法,其進一步包含利用熱壓來將該第一半導體晶粒接合至該第二半導體晶粒。
  10. 如申請專利範圍第7項之方法,其進一步包含:在該第一半導體晶粒中形成一導電貫孔;背面研磨該第一半導體晶粒以露出該導電貫孔;以及在該第一半導體晶粒之上設置該第二半導體晶粒,其中該第二半導體晶粒的一接觸墊係與該導電貫孔對準。
  11. 一種半導體裝置,其包括: 一第一半導體晶粒,其包含一第一保護電路;一第二半導體晶粒,其包含一第二保護電路且被設置在該第一半導體晶粒之上;以及一引線架,其中該第一保護電路以及第二保護電路係並聯電性耦接在該引線架的一第一端子以及該引線架的一第二端子之間。
  12. 如申請專利範圍第11項之半導體裝置,其進一步包含該第一半導體晶粒的一接觸墊,其直接接合到該第二半導體晶粒的一第二接觸墊。
  13. 如申請專利範圍第11項之半導體裝置,其進一步包含從該第一半導體晶粒延伸至該第二半導體晶粒的一第一導電凸塊。
  14. 如申請專利範圍第13項之半導體裝置,其進一步包含從該第一半導體晶粒延伸至該引線架的一第二導電凸塊。
  15. 如申請專利範圍第14項之半導體裝置,其進一步包含一導電貫孔,其穿過該第一半導體晶粒而被形成在該第一導電凸塊以及第二導電凸塊之間。
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