TW201740461A - 具有改良的拓撲之扇出型晶圓層級封裝 - Google Patents

具有改良的拓撲之扇出型晶圓層級封裝 Download PDF

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Publication number
TW201740461A
TW201740461A TW106102356A TW106102356A TW201740461A TW 201740461 A TW201740461 A TW 201740461A TW 106102356 A TW106102356 A TW 106102356A TW 106102356 A TW106102356 A TW 106102356A TW 201740461 A TW201740461 A TW 201740461A
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interconnects
die
fowlp
dielectric layer
molding compound
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TW106102356A
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English (en)
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李傑錫
韋鴻博
金東武
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高通公司
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Publication of TW201740461A publication Critical patent/TW201740461A/zh

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Abstract

本發明提供一種扇出型晶圓層級處理積體電路，其中複數個互連件耦接至一經囊封晶粒上之墊。該等互連件具有一面向墊的表面，其經由一晶種層耦接至一對應墊。該晶種層未覆蓋該等互連件之側壁。

Description

具有改良的拓撲之扇出型晶圓層級封裝
本申請案係關於扇出型晶圓層級封裝，且更特定而言係關於一種具有改良的拓撲之扇出型晶圓層級封裝。
智慧型電話市場之爆發性增長已增加封裝技術中對功能趨同及晶粒整合之需求。為滿足此需求，已研發扇出型晶圓層級封裝(FOWLP)封裝。在平面(2D) FOWLP中，一或多個晶粒嵌入在模製晶圓中，從而使得每一晶粒之活性表面與模製化合物表面共面。重佈層(RDL)可因此從晶粒之活性表面「扇出」至模製化合物表面上。在3D FOWLP中，額外晶粒堆疊至共面晶粒之活性表面上且線接合至在模製化合物表面上方之RDL。與習用層疊封裝(PoP)技術相比，FOWLP消除有機基板以便具有減小的高度及增加的外觀尺寸以及減少的成本。 因此，儘管FOWLP為具吸引性之封裝技術，但其製造具有多個缺陷。舉例而言，通常在沈積RDL及其相關聯通孔之前將聚合物介電層沈積在共面晶粒之活性表面及模製化合物表面上方。接著對聚合物介電層圖案化，從而使得可隨後沈積RDL通孔。為增加密度，通孔直徑及間距必須相對小，此需要聚合物介電層相對薄。儘管模製化合物表面與嵌入晶粒之活性表面共面，但其未必具有相同高度，使得覆蓋模製化合物之相對薄聚合物介電層具有比覆蓋晶粒之相同聚合物介電層上部表面低的上部表面。此高度階差在於沈積RDL通孔之前圖案化聚合物介電層時導致微影問題。 因此，此項技術中存在對具有改良的拓撲之扇出型晶圓層級封裝之需求。
提供一種扇出型晶圓層級處理(FOWLP)積體電路封裝，其包括其中至少一個晶粒囊封在模製化合物中之模製封裝。該模製封裝具有其中至少一個晶粒之活性表面經曝露之模製化合物表面。複數個互連件延伸穿過聚合物介電層以將對應墊耦接在至少一個晶粒之活性表面上。互連件中之每一者具有經由晶種層耦接至對應墊之面向墊的表面。另外，互連件各自具有在面向墊的表面處結束之縱向延伸金屬體。圓周表面環繞每一互連件之縱向延伸金屬體。介電層覆蓋模製化合物表面且環繞每一互連件，使得介電層直接接觸互連件之縱向延伸金屬體的圓周表面。 每一互連件之圓周表面與介電層之間的直接接觸是由於在沈積介電層之前形成互連件造成的。相比而言，常見的係：首先圖案化介電層，從而使得通孔可電鍍至或穿過介電層沈積至模製封裝中之囊封晶粒(或多個晶粒)之活性表面上之墊。為獲得減少的間距，此些習用通孔之形成需要介電層為相對薄的。但鑒於模製化合物表面與囊封晶粒之經曝露活性表面之間的明顯高度階差，此相對厚度為有問題的。相對薄習用介電層因此保持此高度階差，此使重佈層(RDL)在習用介電層上方之隨後形成複雜化。強烈相比而言，本文中所揭示之互連件可形成在相對厚的可光成像層(諸如光阻劑層，其接著在形成互連件之後經移除)中。因此，如與習用通孔相比，所得互連件可相對高。因此，介電層之隨後沈積可造成相對厚的介電層，其不具有由模製化合物表面上之高度階差所造成的階梯式表面。以此方式，所得介電層具有相對平面拓撲，從而使得可準確地沈積RDL。除了改良RDL之微影外，本文中之經改良介電層對翹曲更穩健。貫穿以下實例實施例之揭示可更佳地瞭解此等有利特徵。
為提供改良的拓撲，提供扇出型晶圓層級封裝(FOWLP)，其中在沈積介電層(諸如，聚合物介電層)之前將複數個互連件沈積在模製封裝上。模製封裝具有其中一或多個晶粒之活性表面經曝露之模製化合物表面。活性表面包括對應於複數個互連件之複數個墊。在沈積複數個互連件之後，每一墊耦接至對應互連件。接著將聚合物介電層沈積在模製化合物表面上方以便環繞每一互連件。由於聚合物介電層不再需要經圖案化及蝕刻以形成任何通孔以耦接至墊，因此聚合物介電層可相對厚。以此方式，不管模製封裝中之囊封晶粒之活性表面與模製化合物表面之間的高度階差如何，背對模製化合物嵌入式晶粒之活性表面的聚合物介電層之相對表面可為相對平面的。可接著在聚合物介電層之平面表面上方沈積重佈層(RDL)之金屬層而不存在由非平面性造成之微影問題。另外，在一些實施例中，聚合物介電層之相對厚度使得其能夠沈積於抑制所得FOWLP之翹曲之層狀或旋塗層中。貫穿以下實例實施例可更佳地瞭解此等有利特徵。 現在轉向圖式，在圖 1A 中展示實例FOWLP 100。晶粒105及晶粒110嵌入於模製化合物135中，使得每一晶粒之具有墊111的活性表面在模製化合物135之模製化合物表面136內曝露。每一晶粒105及110之活性表面因此與模製化合物表面136對準或共面，使得模製化合物表面136圓周地環繞每一活性表面。儘管模製化合物表面136與活性表面共面，但由模製化合物135對晶粒105及110之囊封可在模製化合物表面136與晶粒105及110中之每一者之活性表面之間造成高度階差(未說明)。然而，此高度階差有利地未在介電層(諸如，聚合物介電層155)之平面表面156中造成高度階差，如本文中進一步所論述。類似於晶粒105及110，電容器115及電容器120可由模製化合物135囊封。每一電容器115及120具有接觸表面，該接觸表面具有在模製化合物表面136中曝露之複數個觸點或墊，使得模製化合物表面136圓周地環繞每一電容器接觸表面。正如同晶粒105及110之活性表面，每一電容器115及120之接觸表面與模製化合物表面共面且對準，惟除任何相對小的高度階差(例如，數微米)之外。 將瞭解，在替代實施例中，可將額外晶粒囊封在模製化合物135中。此外，在替代實施例中，可僅將單個晶粒囊封(或嵌入)在模製化合物135中。另外，在替代實施例中，嵌入式被動組件(諸如，電容器115及120)之數目及類型可改變。舉例而言，亦可如關於電容器115及120所論述類似地將電感器囊封在模製化合物135中。 在沈積聚合物介電層155之前，將第一複數個互連件125 (諸如銅柱(或其他適合互連件))沈積在晶粒105及晶粒110之活性表面之墊111上。每一墊111因此耦接至至少一個對應互連件125。第二複數個互連件125耦接至電容器115及120之複數個觸點。每一觸點因此耦接至至少一個對應互連件125。如本文中將進一步闡釋，互連件125可相對高，諸如10至35微米。聚合物介電層155之隨後沈積環繞此等相對高互連件125，使得聚合物介電層155亦相對厚。以此方式，聚合物介電層155之相對厚度使得其相對表面156為平面，而不管底層模製化合物表面136與晶粒105及110之活性表面之間的高度階差如何且不管底層模製化合物表面136與電容器115及120之接觸表面之間的高度階差如何。聚合物介電層155之相對厚度有效地「消除」此等高度階差，從而使得其相對表面156相對平面。相比而言，習用聚合物介電層需要為相對薄的，從而使得其通孔可具有減少的間距。習用聚合物介電層因此具有反映此等高度階差之相對表面。由於聚合物介電層155之相對表面156之所得極性，因此可接著將重佈層(RDL) 130之金屬層準確地沈積至相對表面156上。焊球140耦接至RDL 130，從而使得可將FOWLP 100安裝至電路板或其他結構上。 在圖 1B 中之近視圖中展示互連件125。由於互連件125係在沈積聚合物介電層155之前沈積，因此晶種層145將不會塗覆互連件之側壁，而是將僅覆蓋互連件125之面向墊的(或面向觸點的)表面146。晶種層145繼而接觸墊111中之一者或電容器115及120之觸點。縱向延伸金屬體150 (諸如銅填料或其他適合金屬)完成互連件125。金屬體150之圓周表面147因此直接接觸聚合物介電層155 (圖1A)而不存在任何介入晶種層。 現在將論述FOWLP 100之製造的實例方法。如圖 2A 中所展示，可經由雙面黏合層(雙面膠帶) 205將晶粒105及110之活性表面耦接至載體200。將電容器115及120中之每一者之墊或接觸表面以類似方式附接至黏合層205。將瞭解，為清楚說明起見，在圖2A中不展示自其單體化晶粒105及110之晶圓之剩餘部分(如在晶圓層級處理中常見)。 可接著用模製化合物135囊封晶粒105及110與電容器115及120以形成模製封裝210，如圖 2B 中所展示。應注意，模製化合物135僅囊封晶粒105及110之側及背表面，此係因為此等晶粒之活性表面面向黏合層205。類似地，模製化合物135僅囊封電容器115及120之背表面及側，此係因為此等電容器中之每一者之墊表面經黏合至黏合層205。可接著將載體200及雙面黏合層205自圖 2C 中所展示之模製封裝210移除。 可接著如圖 2D 中所展示翻轉所得模製封裝210以曝露晶粒105及110以及電容器115及120之墊。由於先前關於圖2A至2B所論述的黏合至黏合層205，模製化合物表面136與晶粒105及110中之每一者之活性表面共面，惟除任何較小高度階差(例如，數微米)之外。類似地，模製化合物表面136與電容器115及120中之每一者之接觸表面共面，除任何較小高度階差外。可接著將圖1B之晶種層145沈積至模製化合物表面136、每一晶粒105及110之活性表面，及電容器115及120中之每一者之接觸表面上。晶種層145可接著由可使用光微影圖案化之光可成像聚合物層(未說明) (諸如，光阻劑層)覆蓋。可接著電化學電鍍(ECP)經圖案化光阻劑層以將互連件125 (諸如，微凸塊或銅柱)形成至晶粒105及110之墊111上且亦形成至電容器115及120之觸點上。接著移除光阻劑層，後續接著蝕刻晶種層145。互連件125因此具有關於圖1B所論述之輪廓，此係因為晶種層145不存在於側壁147中。由於光阻劑層145將被移除，因此其可沈積為相對厚，諸如10微米至35微米之厚度。互連件125將接著具有匹配此相對厚度之高度。 如圖 2E 中所展示，可接著將聚合物介電層155沈積於晶粒105及110，電容器115及120及模製化合物表面136上方。聚合物介電層135可相對厚，從而使得其可沿著每一互連件125之金屬體150 (圖1B)之整個縱向範圍環繞圓周表面147。舉例而言，可將聚合物介電層155層壓或旋塗於晶粒105及110、電容器115及120及模製化合物135之經曝露表面上方。大體而言，聚合物介電層155將經沈積，使得其實際上覆蓋互連件125。為曝露互連件125，可接著平坦化聚合物介電層155之相對表面156，諸如經由研磨、化學機械拋光或飛切。替代地，可將微影及RDL用於互連件125。再次參考圖1A，可接著使用半加成製程來完成RDL 130，後續接著沈積球140以完成FOWLP 100。 可關於圖 3 之流程圖來概括製造FOWLP 100之方法。該方法包括：用模製化合物囊封至少一個晶粒以形成模製封裝的動作300，該模製封裝具有其中具有複數個墊之至少一個晶粒之活性表面經曝露的平面表面。關於圖2B及圖2C所論述之模製封裝210之形成為動作300之實例。該方法進一步包括將複數個互連件沈積至模製封裝之平面表面上，從而使得每一墊耦接至互連件中之對應者的動作305。如關於圖2D所論述之微凸塊或互連件125之沈積為動作305之實例。最終，該方法包括在沈積複數個互連件之後執行之動作310且其包含將聚合物介電層沈積至模製封裝之平面表面上。關於圖1A及圖2E所論述之聚合物介電層155之沈積為動作310之實例。 現在將論述實例電子系統。實例電子系統 如本文中所描述之FOWLP積體電路封裝可併入至廣泛各種電子系統中。舉例而言，如圖 4 中所展示，行動電話400、膝上型電腦405及平板PC 410可皆包括根據本發明構造之FOWLP積體電路封裝。其他例示性電子系統(諸如，音樂播放器、視訊播放器、通信裝置及個人電腦)亦可經組態有根據本發明構造之積體電路封裝。 如熟習此項技術者現在將瞭解且取決於眼前之特定應用，可在不脫離本發明之範疇的情況下在使用本發明之裝置時對材料、設備、組態及方法進行諸多修改、替換及變換。鑒於此，本發明之範疇不應限於本文中所說明及所描述之特定實施例之範疇，此係因為該等特定實施例僅係作為其之一些實例，而是應與下文隨附之申請專利範圍及其功能等效物完全相稱。
100‧‧‧扇出型晶圓層級封裝(FOWLP)
105‧‧‧晶粒
110‧‧‧晶粒
111‧‧‧墊
115‧‧‧電容器
120‧‧‧電容器
125‧‧‧互連件
130‧‧‧重佈層(RDL)
135‧‧‧模製化合物
136‧‧‧底層模製化合物表面
140‧‧‧焊球
145‧‧‧晶種層
146‧‧‧面向墊的(或面向觸點的)表面
147‧‧‧圓周表面
150‧‧‧金屬體
155‧‧‧聚合物介電層
156‧‧‧表面
200‧‧‧載體
205‧‧‧雙面黏合層(雙面膠帶)
210‧‧‧模製封裝
300‧‧‧動作
305‧‧‧動作
310‧‧‧動作
400‧‧‧行動電話
405‧‧‧膝上型電腦
410‧‧‧平板PC
圖1A為根據本發明之態樣之實例扇出型晶圓層級處理(FOWLP)積體電路封裝的剖面圖。 圖1B為用於圖1A之FOWLP積體電路封裝之互連件的剖面圖。 圖2A為在圖1A之FOWLP積體電路封裝之製造期間之載體及電路組件的剖面圖。 圖2B為在圖1A之FOWLP積體電路封裝之製造期間在用模製化合物囊封之後的模製封裝的剖面圖。 圖2C為在將載體及黏合層移除之後的圖2B之模製封裝的剖面圖。 圖2D為在沈積微凸塊之後的圖2C之模製封裝的剖面圖。 圖2E為在沈積聚合物介電層之後的圖2D之模製封裝的剖面圖。 圖3為製造圖1A之FOWLP積體電路封裝之實例方法的流程圖。 圖4說明根據本發明之實施例的併有FOWLP積體電路封裝之一些實例電子系統。 藉由參考隨後之詳細描述來最佳地理解本發明之實施例及其優勢。應瞭解，使用相同參考編號來識別圖中之一或多者中所說明之相同元件。
100‧‧‧扇出型晶圓層級封裝(FOWLP)
105‧‧‧晶粒
110‧‧‧晶粒
111‧‧‧墊
115‧‧‧電容器
120‧‧‧電容器
125‧‧‧互連件
130‧‧‧重佈層(RDL)
135‧‧‧模製化合物
136‧‧‧底層模製化合物表面
140‧‧‧焊球
155‧‧‧聚合物介電層
156‧‧‧表面

Claims (22)

  1. 一種製造一扇出型晶圓層級處理(FOWLP)電路封裝之方法，其包含： 用模製化合物囊封一至少一個晶粒以形成一模製封裝，該模製封裝具有其中具有複數個墊之該至少一個晶粒之一活性表面經曝露之一平面表面； 將複數個互連件沈積至該模製封裝之該平面表面上，從而使得每一墊耦接至該等互連件中之一對應者；及 在沈積該複數個互連件之後，將一介電層沈積至該模製封裝之該平面表面上。
  2. 如請求項1之方法，其中囊封該至少一個晶粒包含：用該模製化合物囊封一對晶粒。
  3. 如請求項1之方法，其中囊封該至少一個晶粒進一步包含：用該模製化合物囊封一被動組件，從而使得使該模製封裝之該平面表面與該被動組件之一接觸表面對準，且其中沈積該複數個互連件進一步包含：沈積該複數個互連件，從而使得該被動組件之該接觸表面上之每一觸點耦接至該等互連件中之一對應者。
  4. 如請求項1之方法，其中沈積該複數個互連件包含：電鍍複數個微凸塊。
  5. 如請求項4之方法，其中電鍍該複數個微凸塊包含：電鍍複數個銅柱。
  6. 如請求項1之方法，其中該介電層為一聚合物介電層，該方法進一步包含： 平坦化該聚合物介電層；及 將一重佈層(RDL)沈積在該經平坦化聚合物介電層上方。
  7. 如請求項6之方法，其中沈積該RDL包含：沈積複數個經圖案化金屬層。
  8. 如請求項6之方法，其進一步包含：沈積耦接至該RDL之複數個焊球。
  9. 如請求項1之方法，其中囊封該至少一個晶粒包含：將該至少一個晶粒之該活性表面附接至一載體，及用該模製化合物囊封該所附接之至少一個晶粒，從而使得該模製封裝形成為附接至該載體。
  10. 如請求項9之方法，其中囊封該至少一個晶粒進一步包含：將該模製封裝自該載體移除。
  11. 如請求項10之方法，其中囊封該至少一個晶粒進一步包含：自額外模製封裝之一晶圓單體化該模製封裝。
  12. 一種扇出型晶圓層級處理(FOWLP)積體電路封裝，其包含： 一至少一個晶粒，其包括具有複數個墊之一活性表面； 一模製化合物，其經組態以囊封該至少一個晶粒，使得該至少一個晶粒之一活性表面經曝露且與該模製化合物之一表面共面；及 複數個第一互連件，其對應於該複數個墊，其中每一第一互連件包括耦接至該對應墊之一面向墊的表面，且其中每一第一互連件進一步包括僅在其面向墊的表面上之一晶種層。
  13. 如請求項12之FOWLP積體電路封裝，其進一步包含一聚合物介電層，其環繞該複數個第一互連件且覆蓋該至少一個晶粒之該活性表面及該模製化合物之該表面。
  14. 如請求項12之FOWLP積體電路封裝，其中該至少一個晶粒包含複數個晶粒。
  15. 如請求項13之FOWLP積體電路封裝，其進一步包含一重佈層，其覆蓋該聚合物介電層且耦接至該複數個第一互連件。
  16. 如請求項15之FOWLP積體電路封裝，其進一步包含耦接至該重佈層之複數個焊球。
  17. 如請求項12之FOWLP積體電路封裝，其進一步包含： 至少一個被動電路，其包括具有複數個觸點之一接觸表面，其中該至少一個被動電路經囊封在該模製化合物中，使得該接觸表面經曝露且與該模製化合物表面共面； 複數個第二互連件，其對應於該複數個觸點，其中每一第二互連件包括耦接至該對應觸點之一面向觸點的表面，且其中每一第二互連件包括僅在其面向觸點的表面上之一晶種層。
  18. 如請求項17之FOWLP積體電路封裝，其中該聚合物介電層經組態以環繞該複數個第二互連件。
  19. 如請求項17之FOWLP積體電路封裝，其中該至少一個被動電路包含至少一個電容器。
  20. 一種扇出型晶圓層級處理(FOWLP)積體電路，其包含： 一模製封裝，其具有其中至少一個晶粒之一活性表面經曝露之一模製化合物表面，該活性表面包括複數個墊； 複數個互連件，其耦接至該複數個墊，每一互連件具有一縱向延伸金屬體，該縱向延伸金屬體具有一圓周表面； 一介電層，其在該模製化合物表面上，該介電層經組態以直接接觸且環繞每一互連件之該金屬體之該圓周表面。
  21. 如請求項20之FOWLP積體電路，其進一步包含在該介電層上之一重佈層(RDL)。
  22. 如請求項20之FOWLP積體電路，其中該FOWLP積體電路整合至一行動電子系統中，該行動電子系統選自由一蜂巢式電話、一膝上型電腦及一平板電腦組成之群組。
TW106102356A 2016-02-19 2017-01-23 具有改良的拓撲之扇出型晶圓層級封裝 TW201740461A (zh)

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