TW201715697A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

Info

Publication number
TW201715697A
TW201715697A TW105106578A TW105106578A TW201715697A TW 201715697 A TW201715697 A TW 201715697A TW 105106578 A TW105106578 A TW 105106578A TW 105106578 A TW105106578 A TW 105106578A TW 201715697 A TW201715697 A TW 201715697A
Authority
TW
Taiwan
Prior art keywords
support
semiconductor wafer
elongation
nominal
daf
Prior art date
Application number
TW105106578A
Other languages
Chinese (zh)
Other versions
TWI624029B (en
Inventor
Tsutomu Fujita
Hideko Mukaida
Yoshifumi Sugisawa
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of TW201715697A publication Critical patent/TW201715697A/en
Application granted granted Critical
Publication of TWI624029B publication Critical patent/TWI624029B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Laser Beam Processing (AREA)

Abstract

An embodiment of the present invention provides a method of manufacturing a semiconductor device that can easily produce a semiconductor device. A method of manufacturing a semiconductor device according to an embodiment includes a step of attaching a first support tape to a first surface of a semiconductor wafer; a step of singulating the semiconductor wafer into a plurality of semiconductor chips; a step of attaching the second support tape on the second surface of the plurality of semiconductor chips along the first direction; a step of peeling off the first support tape from the plurality of semiconductor chips; and a step of enlarging a distance between the semiconductor chips by extending the second support band; a ratio of a nominal stress generated by elongation of the second semiconductor support band relative to the first direction to a nominal stress generated by elongation relative to the second direction is 0.7 to 1.4.

Description

半導體裝置之製造方法 Semiconductor device manufacturing method [相關申請案][Related application]

本申請案享有以日本專利申請案2015-78578號(申請日:2015年4月7日)及日本專利申請案2016-27371號(申請日:2016年2月16日)為基礎申請案之優先權。本申請係藉由參照該等基礎申請案而包含基礎申請之全部內容。 This application is based on the priority of the application based on Japanese Patent Application No. 2015-78578 (application date: April 7, 2015) and Japanese Patent Application No. 2016-27371 (application date: February 16, 2016). right. This application contains the entire contents of the basic application by reference to the same basic application.

本發明之實施形態係關於一種半導體裝置之製造方法。 Embodiments of the present invention relate to a method of fabricating a semiconductor device.

晶圓存在單片化為半導體晶片之前接著於支持帶而被處理之情形。 The wafer is singulated into a semiconductor wafer and then processed in the support strip.

本發明之實施形態提供一種可使晶片之單片化穩定地進行之半導體裝置之製造方法。 Embodiments of the present invention provide a method of manufacturing a semiconductor device in which wafer singulation can be stably performed.

實施形態之半導體裝置之製造方法具備:將第一支持帶貼附於半導體晶圓之第一面之步驟;將上述半導體晶圓單片化為複數個半導體晶片之步驟;將第二支持帶沿第一方向貼附於上述複數個半導體晶片之第二面之步驟;將上述第一支持帶自上述複數個半導體晶片剝離之步驟;及藉由使上述第二支持帶延伸而擴大上述半導體晶片之間之距離之步驟;上述第二半導體支持帶相對於第一方向之伸長而產生之標稱應力與相對於第二方向之伸長而產生之標稱應力之比為0.7~1.4。 A method of manufacturing a semiconductor device according to an embodiment includes: a step of attaching a first support tape to a first surface of a semiconductor wafer; a step of singulating the semiconductor wafer into a plurality of semiconductor wafers; and a second support strip a step of attaching the first direction to the second surface of the plurality of semiconductor wafers; a step of stripping the first support strip from the plurality of semiconductor wafers; and expanding the semiconductor wafer by extending the second support strip The step of the distance; the ratio of the nominal stress generated by the elongation of the second semiconductor support strip relative to the first direction to the nominal stress generated by the elongation with respect to the second direction is 0.7 to 1.4.

10‧‧‧半導體晶圓 10‧‧‧Semiconductor wafer

10a‧‧‧第一面 10a‧‧‧ first side

10b‧‧‧第二面 10b‧‧‧ second side

20‧‧‧切割刀片 20‧‧‧Cutting Blade

30‧‧‧刀片槽 30‧‧‧ blade slot

40‧‧‧輥 40‧‧‧roll

50‧‧‧第一支持帶 50‧‧‧First support belt

60‧‧‧研磨磨石 60‧‧‧grinding grindstone

80‧‧‧半導體晶片 80‧‧‧Semiconductor wafer

80a‧‧‧第一面 80a‧‧‧ first side

80b‧‧‧第二面 80b‧‧‧ second side

85‧‧‧晶片 85‧‧‧ wafer

90‧‧‧率 90‧‧‧ rate

100‧‧‧第二支持帶 100‧‧‧second support belt

110‧‧‧支持環 110‧‧‧Support ring

115‧‧‧輥 115‧‧‧roll

117‧‧‧馬達 117‧‧‧ motor

120‧‧‧治具 120‧‧‧ fixture

140‧‧‧吸附夾頭 140‧‧‧Adsorption chuck

150‧‧‧拾取機構 150‧‧‧ picking institutions

200‧‧‧DAF 200‧‧‧DAF

210‧‧‧黏著劑層 210‧‧‧Adhesive layer

220‧‧‧基材層 220‧‧‧Substrate layer

310‧‧‧雷射 310‧‧‧Laser

320‧‧‧改質區域 320‧‧‧Modified area

330‧‧‧龜裂 330‧‧‧ crack

500‧‧‧支架 500‧‧‧ bracket

510‧‧‧帶 510‧‧‧With

A‧‧‧區域 A‧‧‧ area

B‧‧‧區域 B‧‧‧Area

D‧‧‧距離 D‧‧‧Distance

D1‧‧‧距離 D1‧‧‧ distance

D2‧‧‧距離 D2‧‧‧ distance

D3‧‧‧距離 D3‧‧‧ distance

D4‧‧‧距離 D4‧‧‧ distance

H‧‧‧擴展量 H‧‧‧Extension

S1‧‧‧區域 S1‧‧‧ area

S2‧‧‧區域 S2‧‧‧ area

S3‧‧‧區域 S3‧‧‧ area

W1‧‧‧寬度 W1‧‧‧Width

W2‧‧‧寬度 W2‧‧‧Width

X‧‧‧方向 X‧‧‧ direction

Y‧‧‧方向 Y‧‧‧ direction

圖1係說明第一實施形態之半導體裝置之製造方法之模式性立體圖。 Fig. 1 is a schematic perspective view showing a method of manufacturing the semiconductor device of the first embodiment.

圖2係說明第一實施形態之半導體裝置之製造方法之模式性剖視圖。 Fig. 2 is a schematic cross-sectional view showing a method of manufacturing the semiconductor device of the first embodiment.

圖3係說明第一實施形態之半導體裝置之製造方法之模式性立體圖。 Fig. 3 is a schematic perspective view showing a method of manufacturing the semiconductor device of the first embodiment.

圖4係說明第一實施形態之半導體裝置之製造方法之模式性剖視圖。 Fig. 4 is a schematic cross-sectional view showing a method of manufacturing the semiconductor device of the first embodiment.

圖5係說明第一實施形態之半導體裝置之製造方法之模式性立體圖。 Fig. 5 is a schematic perspective view showing a method of manufacturing the semiconductor device of the first embodiment.

圖6係說明第一實施形態之半導體裝置之製造方法之模式性剖視圖。 Fig. 6 is a schematic cross-sectional view showing a method of manufacturing the semiconductor device of the first embodiment.

圖7係說明第一實施形態之半導體裝置之製造方法之模式性立體圖。 Fig. 7 is a schematic perspective view showing a method of manufacturing the semiconductor device of the first embodiment.

圖8係說明第一實施形態之半導體裝置之製造方法之模式性剖視圖。 Fig. 8 is a schematic cross-sectional view showing a method of manufacturing the semiconductor device of the first embodiment.

圖9係說明第一實施形態之半導體裝置之製造方法之模式性立體圖。 Fig. 9 is a schematic perspective view showing a method of manufacturing the semiconductor device of the first embodiment.

圖10係說明第一實施形態之半導體裝置之製造方法之模式性剖視圖。 Fig. 10 is a schematic cross-sectional view showing a method of manufacturing the semiconductor device of the first embodiment.

圖11係說明第一實施形態之半導體裝置之製造方法之模式性立體圖。 Fig. 11 is a schematic perspective view showing a method of manufacturing the semiconductor device of the first embodiment.

圖12係說明第一實施形態之半導體裝置之製造方法之模式性剖視圖。 Fig. 12 is a schematic cross-sectional view showing a method of manufacturing the semiconductor device of the first embodiment.

圖13係說明第一實施形態之半導體裝置之製造方法之模式性剖 視圖。 Figure 13 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device of the first embodiment; view.

圖14係說明第一實施形態之半導體裝置之製造方法之模式性剖視圖。 Fig. 14 is a schematic cross-sectional view showing a method of manufacturing the semiconductor device of the first embodiment.

圖15(A)係圖12之S1區域之放大圖,並且係表示擴展前之第二支持帶100及半導體晶片80之模式性剖視圖,圖15(B)係圖13之S2區域之放大圖,並且係表示擴展後之第二支持帶100及半導體晶片80之模式性剖視圖。 15(A) is an enlarged view of the S1 region of FIG. 12, and is a schematic cross-sectional view showing the second support strip 100 and the semiconductor wafer 80 before expansion, and FIG. 15(B) is an enlarged view of the S2 region of FIG. Also, a schematic cross-sectional view of the expanded second support tape 100 and the semiconductor wafer 80 is shown.

圖16(A)係說明DAF(Die Attach Film,晶粒黏著膜)剝離不良之模式性剖視圖,圖16(B)係說明DAF割斷不良之模式性剖視圖。 Fig. 16(A) is a schematic cross-sectional view showing a DAF (Die Attach Film) peeling failure, and Fig. 16(B) is a schematic cross-sectional view showing a DAF cutting failure.

圖17(A)係表示標稱應變中之降伏時伸長率較小之情形時之第二支持帶之標稱應變與標稱應力之關係之模式性圖表,圖17(B)係表示標稱應變中之降伏時伸長率較大之情形時之第二支持帶之標稱應變與標稱應力之關係之模式性圖表。 Fig. 17(A) is a schematic diagram showing the relationship between the nominal strain of the second support zone and the nominal stress in the case where the elongation at the time of the nominal strain is small, and Fig. 17(B) shows the nominal A pattern of the relationship between the nominal strain of the second support zone and the nominal stress in the case of a large elongation at the time of strain in the strain.

圖18係表示對標稱應變中之第二支持帶之降伏時伸長率不同之實施例與比較例測定擴展後之距離D所得之結果之圖表。 Fig. 18 is a graph showing the results obtained by measuring the extended distance D between the examples in which the elongation at the time of the fall of the second support zone in the nominal strain is different.

圖19(A)係表示異向性較大之情形時之第二支持帶之標稱應變與標稱應力之關係之模式性圖表,圖19(B)係表示異向性較小之情形時之第二支持帶之標稱應變與標稱應力之關係之模式性圖表。 Fig. 19(A) is a schematic diagram showing the relationship between the nominal strain and the nominal stress of the second support zone when the anisotropy is large, and Fig. 19(B) shows the case where the anisotropy is small. A schematic chart of the relationship between the nominal strain and the nominal stress of the second support zone.

圖20(A)係擴展後之自半導體晶片80之上表面觀察之俯視圖,圖20(B)係異向性較大之情形時之圖20(A)中之S3區域之放大圖,圖20(C)係異向性較小之情形時之圖20(A)中之S3區域之放大圖。 20(A) is a plan view of the upper surface of the semiconductor wafer 80 after expansion, and FIG. 20(B) is an enlarged view of the S3 area of FIG. 20(A) when the anisotropy is large, FIG. 20 (C) An enlarged view of the S3 region in Fig. 20(A) in the case where the anisotropy is small.

圖21係表示對第二支持帶之X方向與Y方向之標稱應力之比不同之實施例與比較例測定擴展後之距離D所得之結果之圖表。 Fig. 21 is a graph showing the results obtained by measuring the extended distance D between the examples and the comparative examples in which the ratio of the nominal stress in the X direction to the Y direction of the second support band is different.

圖22係表示第二支持帶之X方向之帶之標稱應變與DAF割斷不良率之關係之圖表。 Fig. 22 is a graph showing the relationship between the nominal strain of the X-direction belt of the second support belt and the DAF cut-off rate.

圖23係表示對比較例1、比較例2、實施例之第二支持帶測定擴 展後之貼附時之帶標稱應變、距離D、DAF割斷不良所得之結果之表。 Figure 23 is a view showing the measurement of the second support band of Comparative Example 1, Comparative Example 2, and Example The results of the results of the nominal strain, distance D, and DAF cut defects at the time of attachment.

圖24~圖28係說明第一實施形態之半導體裝置之製造方法之模式性立體圖。 24 to 28 are schematic perspective views for explaining a method of manufacturing the semiconductor device of the first embodiment.

圖29(a)~(c)係說明標稱應變/標稱應力、真實應變/真實應力之模式性圖。 Figures 29(a)-(c) are schematic diagrams illustrating nominal strain/nominal stress, true strain/true stress.

圖30(a)係表示某一樣本中之標稱應變與標稱應力之關係之圖表,圖30(b)係表示相同樣本中之真實應變與真實應力之關係之圖表。 Fig. 30(a) is a graph showing the relationship between the nominal strain and the nominal stress in a sample, and Fig. 30(b) is a graph showing the relationship between the true strain and the true stress in the same sample.

圖31係對複數個樣本之DAF割斷不良之評價結果、使用標稱應變、標稱應力時之降伏時伸長率、使用真實應力時之斷裂時或降伏時之標稱應變與真實應變進行彙總之表。 Figure 31 is a summary of the evaluation results of DAF cut defects for a plurality of samples, the nominal strain, the elongation at the time of the nominal stress, the nominal strain at the time of the fracture using the true stress, or the true strain. table.

以下,參照圖式對實施形態進行說明。於以下之說明中,對於大致相同之功能及構成要素標註相同之符號。 Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same functions and constituent elements are denoted by the same reference numerals.

再者,於本說明書及圖式中,即便半導體晶圓10被單片化為半導體晶片80與缺損晶片85,於利用帶等將其等固定化且大體上維持晶圓之形狀之情形時,有時記載為半導體晶圓10。 In the present specification and the drawings, even when the semiconductor wafer 10 is singulated into the semiconductor wafer 80 and the defective wafer 85, and the shape of the wafer is substantially maintained by a tape or the like, and the shape of the wafer is substantially maintained. It is sometimes described as the semiconductor wafer 10.

(第1實施形態之半導體裝置之製造方法) (Method of Manufacturing Semiconductor Device According to First Embodiment)

圖1~圖14係說明第一實施形態之半導體裝置之製造方法之圖。 1 to 14 are views for explaining a method of manufacturing the semiconductor device of the first embodiment.

如圖1及圖2所示,半導體晶圓10被切割。 As shown in FIGS. 1 and 2, the semiconductor wafer 10 is diced.

半導體晶圓10具有第一面10a與第二面10b。第一面10a係形成有NAND(Not AND,反及)元件、電晶體、配線等(未圖示)之元件面。第二面10b係與第一面10a為相反側之面。 The semiconductor wafer 10 has a first surface 10a and a second surface 10b. The first surface 10a is formed with an element surface of a NAND (Not AND) element, a transistor, a wiring, or the like (not shown). The second surface 10b is a surface opposite to the first surface 10a.

如圖1及圖2所示,使用切割刀片20於半導體晶圓10之第一面10a形成刀片槽30。刀片槽30例如係以格子狀而設置。刀片槽30形成為較 半導體晶圓10之厚度淺。 As shown in FIGS. 1 and 2, the blade groove 30 is formed on the first surface 10a of the semiconductor wafer 10 using the dicing blade 20. The blade grooves 30 are provided, for example, in a lattice shape. The blade slot 30 is formed to be The thickness of the semiconductor wafer 10 is shallow.

如圖3及圖4所示,將第一支持帶50貼附於第一面10a。第一支持帶50例如為背面研磨帶。第一支持帶50係使用輥40而貼附於第一面10a。 As shown in FIGS. 3 and 4, the first support tape 50 is attached to the first surface 10a. The first support belt 50 is, for example, a back grinding belt. The first support belt 50 is attached to the first surface 10a using the roller 40.

如圖5及圖6所示,第二面10b係使用研磨磨石60而被研磨。 As shown in FIGS. 5 and 6, the second surface 10b is polished using the grindstone 60.

第二面10b藉由研磨接近第一面10a。而且,第二面10b與刀片槽30接觸。如此一來,刀片槽30貫通至第一面10a與第二面10b。而且,半導體晶圓10係利用刀片槽30而被單片化為複數個半導體晶片80與缺損晶片85。半導體晶片80及缺損晶片85維持貼附於第一支持帶之狀態,因此不會離散。 The second face 10b is approached to the first face 10a by grinding. Moreover, the second face 10b is in contact with the insert pocket 30. In this way, the insert pocket 30 penetrates the first surface 10a and the second surface 10b. Further, the semiconductor wafer 10 is singulated into a plurality of semiconductor wafers 80 and defective wafers 85 by the blade grooves 30. The semiconductor wafer 80 and the defective wafer 85 are maintained in a state of being attached to the first support tape, and thus are not discrete.

再者,半導體晶片80係指作為半導體裝置之製品而出廠之晶片,缺損晶片85係指未作為半導體裝置之製品而出廠之晶片。半導體晶圓10分割為半導體晶片80或缺損晶片85之個數為任意。 Furthermore, the semiconductor wafer 80 refers to a wafer that is shipped as a product of a semiconductor device, and the defective wafer 85 refers to a wafer that is not shipped as a product of a semiconductor device. The number of semiconductor wafers 10 divided into semiconductor wafers 80 or defective wafers 85 is arbitrary.

半導體晶片80亦與半導體晶圓10同樣地,具有第一面80a與第二面80b。第一面80a係形成有NAND元件、電晶體、配線等(未圖示)之元件面。第一面80a係貼附於第一支持帶50之面。第二面80b係與第一面80a為相反側之面。 Similarly to the semiconductor wafer 10, the semiconductor wafer 80 has a first surface 80a and a second surface 80b. The first surface 80a is formed with an element surface of a NAND element, a transistor, a wiring, or the like (not shown). The first side 80a is attached to the face of the first support belt 50. The second surface 80b is a surface opposite to the first surface 80a.

於以下之說明中,只要將缺損晶片85以與半導體晶片80相同之方式處理即可。因此,除必要情況以外省略缺損晶片85之說明。 In the following description, the defective wafer 85 may be processed in the same manner as the semiconductor wafer 80. Therefore, the description of the defective wafer 85 is omitted except where necessary.

如圖7及圖8所示,第二支持帶100貼附於半導體晶片80之第二面80b與支持環110。 As shown in FIGS. 7 and 8, the second support tape 100 is attached to the second surface 80b of the semiconductor wafer 80 and the support ring 110.

貼附於第一支持帶50之半導體晶片80與第一支持帶50一起上下翻轉。支持環110配置於複數個半導體晶片80之外側。而且,第二支持帶100係使用輥115而貼附於第二面80b及支持環110。 The semiconductor wafer 80 attached to the first support tape 50 is flipped upside down with the first support tape 50. The support ring 110 is disposed on the outer side of the plurality of semiconductor wafers 80. Further, the second support tape 100 is attached to the second surface 80b and the support ring 110 by using the roller 115.

第二支持帶100例如係於使用馬達117等而被拉伸之狀態下貼附於第二面80b及支持環110。由於係將第二支持帶100一面拉伸一面貼 附,故而可於第二支持帶100與第二面80b、第二支持帶100與支持環110之間縮小間隙而將第二支持帶100貼附。 The second support tape 100 is attached to the second surface 80b and the support ring 110, for example, in a state of being stretched using a motor 117 or the like. Because the second support belt 100 is stretched on one side Therefore, the second support tape 100 can be attached by narrowing the gap between the second support tape 100 and the second surface 80b, and between the second support tape 100 and the support ring 110.

再者,可於輥115與馬達117之間配置任意數量之輥等。馬達可為任意種類之馬達。又,即便並非為馬達,只要可使第二支持帶100拉伸,則亦可為任意之機構。 Further, an arbitrary number of rolls or the like may be disposed between the roller 115 and the motor 117. The motor can be any type of motor. Further, even if it is not a motor, any mechanism can be used as long as the second support tape 100 can be stretched.

將使用輥115對第二支持帶進行接著之方向稱為X方向,將與X方向正交之方向稱為Y方向。換言之,輥115相對於半導體晶片80之相對前進方向為X方向,輥115之延伸方向為Y方向。 The direction in which the second support belt is carried out using the roller 115 is referred to as the X direction, and the direction orthogonal to the X direction is referred to as the Y direction. In other words, the relative advancement direction of the roller 115 with respect to the semiconductor wafer 80 is the X direction, and the extending direction of the roller 115 is the Y direction.

再者,存在X方向與第二支持帶之MD(Machine Direction,縱向)一致之情況。又,存在Y方向與第二支持帶之TD(Transverse Direction,橫向)一致之情況。 Furthermore, there is a case where the X direction coincides with the MD (Machine Direction) of the second support band. Further, there is a case where the Y direction coincides with the TD (Transverse Direction) of the second support band.

關於第二支持帶100,於下文中詳細地進行說明。 Regarding the second support belt 100, it will be described in detail below.

圖9及圖10係表示將第二支持帶100貼附於第二面80b及支持環110後再次上下翻轉後之狀態之模式性立體圖及剖視圖。 9 and 10 are schematic perspective views and cross-sectional views showing a state in which the second support tape 100 is attached to the second surface 80b and the support ring 110, and then turned upside down again.

再者,圖9及圖10表示第二支持帶100被支持環110之下表面切斷之狀態,但並不限定於此。例如,第二支持帶100可被支持環110之外側切斷,亦可不被切斷。 9 and 10 show a state in which the second support tape 100 is cut by the lower surface of the support ring 110, but the invention is not limited thereto. For example, the second support strip 100 may be cut off by the outer side of the support ring 110 or may not be cut.

如圖11及圖12所示,將第一支持帶50自半導體晶片80剝離。半導體晶片80貼附於第二支持帶100。即,半導體晶片80係經由第二支持帶100而與支持環110相連,故而可將第一支持帶50自半導體晶片80剝離。 As shown in FIGS. 11 and 12, the first support tape 50 is peeled off from the semiconductor wafer 80. The semiconductor wafer 80 is attached to the second support tape 100. That is, the semiconductor wafer 80 is connected to the support ring 110 via the second support tape 100, so that the first support tape 50 can be peeled off from the semiconductor wafer 80.

如圖13所示,第二支持帶100被伸長(擴展)。 As shown in FIG. 13, the second support belt 100 is elongated (expanded).

半導體晶片80係使用治具120而相對於支持環110向上方推出。將該第二支持帶100被推出之長度稱為擴展量H。藉由將第二支持帶100擴展,經單片化之半導體晶片80間之距離D擴大。 The semiconductor wafer 80 is pushed upward with respect to the support ring 110 using the jig 120. The length at which the second support tape 100 is pushed out is referred to as the amount of expansion H. By expanding the second support strip 100, the distance D between the singulated semiconductor wafers 80 is enlarged.

對擴展時之第二支持帶100之伸長方法更詳細地進行說明。於擴 展時,第二支持帶100係貼附於支持環110。且,利用治具120將第二支持帶100拉長。接下來,由於在治具120與第二支持帶100之間會產生摩擦力,故而首先被拉長者係支持環110與治具120之間之區域A。 The method of elongating the second support strip 100 at the time of expansion will be described in more detail. Expansion At the time of exhibition, the second support tape 100 is attached to the support ring 110. And, the second support tape 100 is elongated by the jig 120. Next, since a frictional force is generated between the jig 120 and the second support belt 100, the stretcher is first supported by the region A between the support ring 110 and the jig 120.

若區域A被充分地拉長且第二支持帶100所產生之應力大於治具120與第二支持帶之摩擦力,則半導體晶片80之下方之區域B被拉長。 If the area A is sufficiently elongated and the stress generated by the second support strip 100 is greater than the friction of the jig 120 and the second support strip, the area B below the semiconductor wafer 80 is elongated.

因此,例如,若第二支持帶100容易伸長、即對於第二支持帶所伸長之長度(標稱應變(Normal Strain))而產生之標稱應力(Normal Stress)較小,則區域B不易被拉長。相反的,若第二支持帶100不易伸長、即相對於標稱應變所產生之標稱應力較大,則區域B容易被拉長。 Therefore, for example, if the second support belt 100 is easily elongated, that is, the normal stress generated by the length of the second support belt (Normal Strain) is small, the area B is not easily Elongated. Conversely, if the second support strip 100 is not easily stretched, i.e., the nominal stress generated relative to the nominal strain is large, the region B is easily elongated.

如圖14所示,半導體晶片80例如係使用具備吸附夾頭140之拾取機構150拾取,並被運送至對基板或者其它半導體晶片之安裝步驟等半導體裝置之特定製造步驟。再者,半導體晶片80於拾取時,亦可為附著有第二支持帶之一部分之狀態。再者,具體而言,下述DAF(未圖示)亦可與半導體晶片80一起被拾取。 As shown in FIG. 14, the semiconductor wafer 80 is, for example, a specific manufacturing step of a semiconductor device such as a step of mounting a substrate or other semiconductor wafer by picking up the pick-up mechanism 150 having the chuck 13 and transporting it to a substrate or other semiconductor wafer. Furthermore, when the semiconductor wafer 80 is picked up, it may be in a state in which a portion of the second support tape is attached. Further, specifically, the following DAF (not shown) may be picked up together with the semiconductor wafer 80.

(關於第二支持帶) (about the second support belt)

使用圖15(A)及圖15(B)對第二支持帶100更詳細地進行說明。圖15(A)及圖15(B)分別係表示擴展前及擴展後之第二支持帶100及半導體晶片80之模式性剖視圖。 The second support belt 100 will be described in more detail with reference to FIGS. 15(A) and 15(B). 15(A) and 15(B) are schematic cross-sectional views showing the second support tape 100 and the semiconductor wafer 80 before and after expansion, respectively.

第二支持帶100例如具有基材層220、黏著劑層210、及DAF(Die Attach Film)200。 The second support tape 100 has, for example, a base material layer 220, an adhesive layer 210, and a DAF (Die Attach Film) 200.

基材層220例如包含聚對苯二甲酸乙二酯、聚烯烴等合成樹脂。 The base material layer 220 contains, for example, a synthetic resin such as polyethylene terephthalate or polyolefin.

黏著劑層210係貼合基材層220及DAF200之任意材料。黏著劑層210例如包含環氧樹脂、聚醯亞胺、丙烯酸系樹脂、聚烯烴、矽酮等合成樹脂。 The adhesive layer 210 is bonded to any of the substrate layer 220 and the DAF 200. The adhesive layer 210 contains, for example, a synthetic resin such as an epoxy resin, a polyimide, an acrylic resin, a polyolefin, or an anthrone.

DAF200例如包含丙烯酸系樹脂、聚醯亞胺、環氧樹脂。 The DAF 200 includes, for example, an acrylic resin, a polyimide, or an epoxy resin.

如圖15(B)所示,第二支持帶100之一部分藉由擴展而針對各半導體晶片之每個切斷。具體而言,第二支持帶所含之DAF200係藉由擴展而被切斷。 As shown in FIG. 15(B), a portion of the second support tape 100 is cut for each of the semiconductor wafers by expansion. Specifically, the DAF 200 included in the second support zone is cut by expansion.

於藉由該擴展將DAF切斷時,可能會產生例如DAF割斷不良、及DAF剝離不良。使用圖16(A)及圖16(B)對該不良進行說明。再者,圖16(A)及圖16(B)係相當於圖13之S2區域之放大圖之圖。 When the DAF is cut by the expansion, for example, DAF cut failure and DAF peeling failure may occur. This defect will be described using FIG. 16(A) and FIG. 16(B). 16(A) and 16(B) are views corresponding to an enlarged view of the S2 region of Fig. 13.

圖16(A)係表示DAF剝離不良之模式性剖視圖。DAF剝離不良係將DAF200自黏著劑層210剝離之不良。半導體晶片80及DAF200之位置偏移,且視情況會飛散。因此,半導體晶片80及DAF200之拾取變得困難。 Fig. 16(A) is a schematic cross-sectional view showing a defect in DAF peeling. The DAF peeling failure is a defect in which the DAF 200 is peeled off from the adhesive layer 210. The position of the semiconductor wafer 80 and the DAF 200 is shifted and may be scattered as the case may be. Therefore, pickup of the semiconductor wafer 80 and the DAF 200 becomes difficult.

擴展時,半導體晶片80及其下部之DAF200因黏著劑層210之張力而向四方拉伸。此處,例如於擴展量H較大之情形時,存在黏著劑層210之張力大於黏著劑層210與DAF200之密接力之清晰。於該張力大於密接力之情形時,DAF200無法附著於黏著劑層210。即,會產生圖16(A)所示般之DAF剝離不良。 At the time of expansion, the semiconductor wafer 80 and the lower portion of the DAF 200 are stretched in a square shape due to the tension of the adhesive layer 210. Here, for example, when the amount of expansion H is large, the tension of the adhesive layer 210 is greater than the adhesion of the adhesive layer 210 to the DAF 200. When the tension is greater than the adhesion, the DAF 200 cannot adhere to the adhesive layer 210. That is, a DAF peeling failure as shown in Fig. 16(A) is generated.

本次,藉由申請人之實驗確認了DAF剝離不良與擴展量H之關係。而且,於擴展量H大於8mm之情形時,會尤其顯著地發生DAF剝離不良。又,DAF200與黏著劑層210之間之黏著力為0.1N/25mm以上之情況對防止DAF剝離不良較佳。 This time, the relationship between the DAF peeling failure and the expansion amount H was confirmed by the applicant's experiment. Moreover, when the amount of expansion H is larger than 8 mm, DAF peeling failure particularly occurs remarkably. Further, when the adhesion between the DAF 200 and the adhesive layer 210 is 0.1 N/25 mm or more, it is preferable to prevent DAF peeling failure.

圖16(B)係表示DAF割斷不良之模式性剖視圖。DAF割斷不良係DAF200未被充分地割斷之不良。由於DAF200接著於複數個半導體晶片80,故而難以將分離之半導體晶片80與DAF200一起拾取。 Fig. 16 (B) is a schematic cross-sectional view showing a defective DAF cut. The DAF cut-off defect is not sufficiently broken by the DAF200. Since the DAF 200 is followed by a plurality of semiconductor wafers 80, it is difficult to pick up the separated semiconductor wafer 80 together with the DAF 200.

於發生DAF割斷不良之情形時,由於DAF200未被切斷,故而距離D並未充分地擴大。因此,藉由測定距離D,可對DAF割斷不良進行評價。 In the case where the DAF cut is bad, since the DAF 200 is not cut, the distance D is not sufficiently enlarged. Therefore, by measuring the distance D, the DAF cut failure can be evaluated.

DAF割斷不良取決於第二支持帶100之特性。 The DAF cut defect depends on the characteristics of the second support strip 100.

以下,對DAF割斷不良與第二支持帶100之特性之關係進一步進行說明。 Hereinafter, the relationship between the DAF cut failure and the characteristics of the second support tape 100 will be further described.

首先,對第二支持帶100之降伏時伸長率與DAF割斷不良之關係進行說明。 First, the relationship between the elongation at break of the second support tape 100 and the DAF cut failure will be described.

圖17(A)及圖17(B)係表示第二支持帶100之標稱應變與標稱應力之關係之模式性圖表。如圖17(A)所示,若第二支持帶使標稱應變自0%增加,則於超過某一標稱應變之時點標稱應力降低(降伏)。將該標稱應力最先下降之點稱為降伏點,將與該降伏點對應之標稱應變稱為降伏時伸長率。例如,與圖17(A)之比較例相比,圖17(B)之實施例之降伏時伸長率較大。 17(A) and 17(B) are schematic diagrams showing the relationship between the nominal strain of the second support band 100 and the nominal stress. As shown in Fig. 17(A), if the second support band increases the nominal strain from 0%, the nominal stress decreases (falls and falls) at a point above a certain nominal strain. The point at which the nominal stress first drops is referred to as the point of undulation, and the nominal strain corresponding to the point of undulation is referred to as the elongation at the time of the fall. For example, in the embodiment of Fig. 17(B), the elongation at the time of the fall is larger than that of the comparative example of Fig. 17(A).

圖18係針對第二支持帶之降伏時伸長率不同之實施例及比較例,對擴展量H與半導體晶片80之間之距離D之關係進行繪製而成之實驗資料。於本實驗中,若距離D為40μm以上,則意味著DAF割斷不良較少。圖18之資料係於25處測定點對不同晶片間之距離之X方向之距離、及Y方向之距離進行測定所得之大約50處之測定資料。 Fig. 18 is an experimental data obtained by plotting the relationship between the amount of expansion H and the distance D between the semiconductor wafers 80 in the examples and comparative examples in which the second support tape has different elongation at the time of the fall. In the present experiment, if the distance D is 40 μm or more, it means that the DAF is less defective. The data of Fig. 18 is measured data of about 50 points measured at 25 points in the X direction of the distance between different wafers and the distance in the Y direction.

如圖18所示,即便於降伏時伸長率為40%之比較例中將擴展量H設為8mm,亦無法抑制DAF割斷不良。於降伏時伸長率為55%之比較例中,雖然較降伏時伸長率為40%之比較例得以改善,但仍然會發生DAF割斷不良。相對於此,於降伏時伸長率為90%之樣本中,藉由將擴展量H設為8mm,DAF割斷不良大幅被抑制。認為其原因在於:例如降伏時伸長率較高之樣本可不受第二支持帶100之差異等影響而均等地伸長。 As shown in Fig. 18, even in the comparative example in which the elongation was 40% at the time of the fall, the expansion amount H was set to 8 mm, and the DAF cutting failure could not be suppressed. In the comparative example in which the elongation at the time of lodging was 55%, the comparative example in which the elongation was 40% at the time of the fall was improved, but the DAF cut defect still occurred. On the other hand, in the sample in which the elongation at the time of the fall was 90%, the DAF cutting failure was largely suppressed by setting the expansion amount H to 8 mm. The reason is considered to be that, for example, the sample having a higher elongation at the time of the fall can be equally elongated without being affected by the difference of the second support tape 100 or the like.

繼而,為了進一步抑制DAF割斷不良,對擴展時之第二支持帶100之X方向及Y方向上所產生之標稱應力之異向性與DAF割斷不良之關係進行說明。第二支持帶100例如存在因第二支持帶100之製造上之 原因而導致X方向與Y方向上所產生之標稱應力不同之情形。 Then, in order to further suppress the DAF cut failure, the relationship between the anisotropy of the nominal stress generated in the X direction and the Y direction of the second support tape 100 during expansion and the DAF cut failure will be described. The second support strip 100 is, for example, present in the manufacture of the second support strip 100. The reason is that the nominal stress generated in the X direction and the Y direction is different.

圖19(A)及圖19(B)係表示第二支持帶100之標稱應變與標稱應力之關係之模式性圖表。於各個圖表中,(a)表示X方向之關係,(b)表示Y方向之關係。標稱應變係將自然狀態設為1時自自然狀態伸長之長度之比例。 19(A) and 19(B) are schematic diagrams showing the relationship between the nominal strain of the second support band 100 and the nominal stress. In each graph, (a) shows the relationship of the X direction, and (b) shows the relationship of the Y direction. The ratio of the length of the nominal strain system to the length of the natural state when the natural state is set to 1.

圖19(A)之比較例於標稱應變為e時,X方向之標稱應力為Y方向之標稱應力之大致2倍。另一方面,圖19(B)之實施例於標稱應變為e時,X方向之標稱應力為Y方向之標稱應力之大致1倍。即,比較例係Y方向與X方向相比容易伸長,相對於此,實施例係Y方向與X方向之伸長容易度之差較小。 In the comparative example of Fig. 19(A), when the nominal strain is e, the nominal stress in the X direction is approximately twice the nominal stress in the Y direction. On the other hand, in the embodiment of Fig. 19(B), when the nominal strain is e, the nominal stress in the X direction is approximately one times the nominal stress in the Y direction. That is, in the comparative example, the Y direction is more likely to be elongated than the X direction, whereas the difference between the ease of elongation in the Y direction and the X direction in the embodiment is small.

使用圖20(A)~(C)對使該比較例及實施例之第二支持帶100擴展後之狀態進行說明。 The state in which the second support band 100 of the comparative example and the embodiment is expanded will be described with reference to Figs. 20(A) to (C).

圖20(A)係相當於圖13之擴展後之模式性俯視圖。圖20(B)或圖20(C)係圖20(A)之區域S3之模式性放大圖。圖20(B)表示相當於圖19(A)之比較例之清晰。圖20(C)表示相當於圖19(B)之實施例之情形。 Fig. 20(A) is a schematic plan view corresponding to the expansion of Fig. 13. Fig. 20(B) or Fig. 20(C) is a schematic enlarged view of a region S3 of Fig. 20(A). Fig. 20(B) shows the clarity of the comparative example corresponding to Fig. 19(A). Fig. 20(C) shows a case corresponding to the embodiment of Fig. 19(B).

首先,對比較例之情形進行說明。如上所述,若第二支持帶100容易伸長,則圖13中之第二支持帶100之區域B難以被拉長。相反,若第二支持帶100難以伸長,則第二支持帶100之區域B容易被拉長。而且,於比較例中,第二支持帶100係Y方向與X方向相比容易伸長。 First, the case of the comparative example will be described. As described above, if the second support tape 100 is easily elongated, the region B of the second support tape 100 in Fig. 13 is difficult to be elongated. On the contrary, if the second support tape 100 is difficult to elongate, the region B of the second support tape 100 is easily elongated. Further, in the comparative example, the second support belt 100 is more likely to be elongated in the Y direction than in the X direction.

因此,如圖20(B)所示,於區域B中,第二支持帶100係容易沿X方向伸長,而難以沿Y方向伸長。即,X方向之半導體晶片80間之距離D1較Y方向之半導體晶片80間之距離D2大。因此,第二支持帶100所包含之DAF200容易於X方向上被割斷,相對於此,難以於Y方向上被割斷。 Therefore, as shown in FIG. 20(B), in the region B, the second support tape 100 is easily elongated in the X direction and is difficult to elongate in the Y direction. That is, the distance D1 between the semiconductor wafers 80 in the X direction is larger than the distance D2 between the semiconductor wafers 80 in the Y direction. Therefore, the DAF 200 included in the second support belt 100 is easily cut in the X direction, whereas it is difficult to be cut in the Y direction.

另一方面,如圖20(C)所示,於X方向之標稱應力與Y方向之伸長容易度之差較小之情形時,X方向與Y方向大致均等地擴大。即,X方 向之半導體晶片80之距離D3與Y方向之距離D4大致相等。因此,第二支持帶100所包含之DAF200於X方向及Y方向上被均等地割斷。 On the other hand, as shown in FIG. 20(C), when the difference between the nominal stress in the X direction and the easiness of elongation in the Y direction is small, the X direction and the Y direction are substantially uniformly expanded. That is, the X side The distance D3 to the semiconductor wafer 80 is substantially equal to the distance D4 in the Y direction. Therefore, the DAF 200 included in the second support belt 100 is equally cut in the X direction and the Y direction.

若對以上進行彙總,則為了防止DAF割斷不良,第二支持帶較佳為X方向之標稱應力與Y方向之標稱應力之比接近1、即異向性較小。 When the above is summarized, in order to prevent the DAF from being cut, the second support band preferably has a ratio of the nominal stress in the X direction to the nominal stress in the Y direction, that is, the anisotropy is small.

圖21係針對第二支持帶100之異向性不同之樣本,對擴展量H與半導體晶片80之間之距離D之關係進行繪製而成之實驗資料。再者,本實驗所使用之第二支持帶100之降伏時伸長率均為90%以上。又,於本實驗中,若距離D為40μm以上,則亦意味著DAF割斷不良較少,係測定點與上述實驗相同之約50處之測定資料。 FIG. 21 is an experimental data obtained by plotting the relationship between the amount of expansion H and the distance D between the semiconductor wafers 80 for samples having different anisotropy of the second support strip 100. Furthermore, the elongation of the second support tape 100 used in this experiment was 90% or more. Further, in the present experiment, when the distance D is 40 μm or more, it means that the DAF is less defective in cutting, and the measurement data of about 50 points which are the same as the above-mentioned experiment are measured.

如圖21所示,於標稱應力之比為1.7之情形時,即便將擴展量H設為8mm,亦會發生距離D為40μm以下之DAF割斷不良。另一方面,於標稱應力之比為1.4及1.0之情形時,若將擴展量H設為8mm,則於所有測定資料中確認到DAF被割斷。因此,第二支持帶100之X方向之標稱應力與Y方向之標稱應力之比較理想為1.4以下。再者,理所當然,於Y方向之標稱應力較X方向之標稱應力強之情形時,該比成為1.4之倒數即約0.7以上。 As shown in Fig. 21, when the ratio of the nominal stress is 1.7, even if the expansion amount H is set to 8 mm, DAF cut failure having a distance D of 40 μm or less occurs. On the other hand, when the ratio of the nominal stress is 1.4 and 1.0, if the expansion amount H is set to 8 mm, it is confirmed that the DAF is cut in all the measurement data. Therefore, the comparison between the nominal stress in the X direction of the second support tape 100 and the nominal stress in the Y direction is preferably 1.4 or less. Furthermore, it is a matter of course that when the nominal stress in the Y direction is stronger than the nominal stress in the X direction, the ratio becomes a reciprocal of 1.4, that is, about 0.7 or more.

再者,如上所述,使X方向與Y方向上所產生之標稱應力接近1未必意指使第二支持帶100之MD與TD上所產生之標稱應力接近1。即便MD與TD上所產生之標稱應力存在異向性,藉由將第二支持帶100傾斜地貼附於半導體晶片80,亦可使X方向與Y方向上所產生之標稱應力接近1。 Furthermore, as described above, making the nominal stress generated in the X direction and the Y direction close to 1 does not necessarily mean that the MD generated by the second support strip 100 and the nominal stress generated on the TD are close to 1. Even if the nominal stress generated on the MD and the TD is anisotropic, by attaching the second support strip 100 obliquely to the semiconductor wafer 80, the nominal stress generated in the X direction and the Y direction can be made close to 1.

進而,對貼附狀態之第二支持帶100之標稱應變、及第二支持帶100之拉伸強度與DAF割斷不良之關係進行說明。 Further, the relationship between the nominal strain of the second support tape 100 in the attached state and the tensile strength of the second support tape 100 and the DAF cut failure will be described.

如參照圖8所說明般,第二支持帶100係一面被拉伸,一面沿X方向貼附。因此,第二支持帶100係於沿X方向伸長之狀態下貼附於第二面80b。而且,第二支持帶100係沿X方向伸長而貼附,故而若第二 支持帶100被擴展,則X方向與Y方向之伸長容易度不同。假設X方向與Y方向之伸長容易度不同,則如於標稱應力之異向性中所說明般,可能會使DAF割斷不良惡化。 As described with reference to Fig. 8, the second support tape 100 is attached while being stretched in the X direction. Therefore, the second support tape 100 is attached to the second surface 80b in a state of being elongated in the X direction. Moreover, the second support tape 100 is elongated and attached in the X direction, so if the second When the support belt 100 is expanded, the ease of elongation in the X direction and the Y direction is different. Assuming that the easiness of elongation in the X direction and the Y direction is different, as described in the anisotropy of the nominal stress, the DAF cut defect may be deteriorated.

換言之,不僅藉由上述第二支持帶100之降伏時伸長率及標稱應力之異向性,亦藉由於貼附時不使第二支持帶沿X方向伸長,可進一步抑制DAF割斷不良。 In other words, not only the elongation of the second support tape 100 at the time of the fall and the anisotropy of the nominal stress but also the elongation of the second support tape in the X direction at the time of attachment can be further suppressed.

圖22係表示貼附狀態下之第二支持帶100之X方向之標稱應變與DAF割斷不良之關係之圖表。再者,第二支持帶100之X方向之標稱應變係貼附後常溫下之測定值。 Fig. 22 is a graph showing the relationship between the nominal strain in the X direction of the second support tape 100 in the attached state and the DAF cut failure. Furthermore, the nominal strain in the X direction of the second support strip 100 is attached to the measured value at normal temperature.

如圖22所示,得知若第二支持帶100之X方向之標稱應變超過1.9%,則會發生DAF割斷不良。即,得知若第二支持帶100之X方向之標稱應變至少未達1.9%,則有利於減少DAF割斷不良。 As shown in FIG. 22, it is found that if the nominal strain in the X direction of the second support tape 100 exceeds 1.9%, DAF cut failure occurs. That is, it is known that if the nominal strain in the X direction of the second support strip 100 is at least less than 1.9%, it is advantageous to reduce the DAF cut failure.

為了減少該第二支持帶100之X方向之伸長,只要第二支持帶100並未因貼附時之拉伸力而過分伸長即可。具體而言,若第二支持帶100之拉伸強度(用於使單位長度伸長所需之力)較大,則可減少貼附時之拉伸力下之X方向之伸長。 In order to reduce the elongation in the X direction of the second support tape 100, it is sufficient that the second support tape 100 is not excessively stretched by the tensile force at the time of attachment. Specifically, if the tensile strength (the force required to elongate the unit length) of the second support tape 100 is large, the elongation in the X direction under the tensile force at the time of attachment can be reduced.

圖23係對第二支持帶之拉伸強度不同之樣本之帶之X方向之標稱應變、距離D、距離D之差異、DAF割斷不良進行彙總所得之表。於圖23中,拉伸強度示出常溫時(24℃)與高溫時(70℃)之各自之資料。此處,所謂常溫,例如係指10℃~30℃,高溫時例如為40~90℃。常溫例如為擴展時之溫度,高溫例如為貼附第二支持帶時之溫度。 Fig. 23 is a table summarizing the nominal strain in the X direction, the difference in the distance D, the distance D, and the DAF cut defect in the tape of the sample having different tensile strengths of the second support tape. In Fig. 23, the tensile strength shows the respective data at normal temperature (24 ° C) and high temperature (70 ° C). Here, the normal temperature means, for example, 10 to 30 ° C, and for example, 40 to 90 ° C at a high temperature. The normal temperature is, for example, the temperature at the time of expansion, and the high temperature is, for example, the temperature at which the second support tape is attached.

再者,於圖23中,拉伸強度表示用以使寬度20mm之第二支持帶100於標稱應變中伸長2%所必需之力。第二支持帶100之實際寬度例如係相對於300mm半導體晶圓而為最大350~390mm之寬度。即,相對於圖23所示之值,於施加了17.5倍~19.5倍左右之力之情形時,第二支持帶100之長度伸長2%。 Further, in Fig. 23, the tensile strength indicates the force necessary to elongate the second support tape 100 having a width of 20 mm by 2% in the nominal strain. The actual width of the second support strip 100 is, for example, a width of up to 350-390 mm with respect to a 300 mm semiconductor wafer. That is, with respect to the value shown in Fig. 23, when the force of about 17.5 times to 19.5 times is applied, the length of the second support tape 100 is extended by 2%.

又,本實驗為降伏時伸長率為90%以上並且X方向與Y方向上所產生之標稱應力之異向性為1.2以下之第二支持帶100。即便距離D之最短距離超過40μm亦會存在不良之原因在於:圖18或圖21之樣本數約為50處,相對於此,圖23之樣本數較多,約為350處,從而進行更精密之評價。 Further, this experiment is a second support tape 100 in which the elongation at the time of lodging is 90% or more and the anisotropy of the nominal stress generated in the X direction and the Y direction is 1.2 or less. Even if the shortest distance from the distance D exceeds 40 μm, there is a disadvantage that the number of samples in Fig. 18 or Fig. 21 is about 50. In contrast, the number of samples in Fig. 23 is more than 350, which makes it more precise. Evaluation.

以下,對圖23之實驗結果進行說明。 The experimental results of Fig. 23 will be described below.

關於帶之標稱應變,比較例1、比較例2、實施例分別為2.1%、0.8%、1.1%。得知比較例2與實施例常溫時之拉伸強度與比較例1相比較大,故而帶之標稱應變減小。尤其是比較例2常溫時之拉伸強度最大,因此認為帶之標稱應變變得最小。 Regarding the nominal strain of the belt, Comparative Example 1, Comparative Example 2, and Example were 2.1%, 0.8%, and 1.1%, respectively. It was found that the tensile strength at the normal temperature of Comparative Example 2 and the Example was larger than that of Comparative Example 1, and the nominal strain of the belt was decreased. In particular, in Comparative Example 2, the tensile strength at the normal temperature was the largest, and therefore the nominal strain of the belt was considered to be the smallest.

關於距離D之最小值,於比較例1、比較例2、實施例中分別為123mm、103mm、156mm。實施例相對於比較例1及比較例2,距離D之最小值變大。認為其原因在於第二支持帶100之貼附時之高溫下之拉伸強度較大。再者,比較例2之距離D之最小值較比較例1小。認為其原因在於高溫時之拉伸強度較比較例1小。 The minimum value of the distance D was 123 mm, 103 mm, and 156 mm in Comparative Example 1, Comparative Example 2, and Example, respectively. In the examples, with respect to Comparative Example 1 and Comparative Example 2, the minimum value of the distance D became large. The reason is considered to be that the tensile strength at a high temperature at the time of attachment of the second support tape 100 is large. Further, the minimum value of the distance D of Comparative Example 2 was smaller than that of Comparative Example 1. The reason was considered to be that the tensile strength at a high temperature was smaller than that of Comparative Example 1.

關於距離D之標準偏差,於比較例1、比較例2、實施例中分別為12.4mm、17.1mm、8.6mm。實施例相對於比較例1及比較例2,距離D之標準偏差較小。即,實施例之距離D之差異較小。認為距離D之差異較小係與距離D之最小值同樣地受到高溫下之拉伸強度之影響所致。 The standard deviation of the distance D was 12.4 mm, 17.1 mm, and 8.6 mm in Comparative Example 1, Comparative Example 2, and Example, respectively. In the examples, the standard deviation of the distance D was small with respect to Comparative Example 1 and Comparative Example 2. That is, the difference in the distance D of the embodiment is small. It is considered that the difference in the distance D is small as a result of the tensile strength at a high temperature as well as the minimum value of the distance D.

最後,關於DAF割斷不良率,於比較例1、比較例2、實施例中分別為5.1%、0.7%、0.0%。實施例之貼附時之帶之標稱應變雖然較比較例2差,為1.1%,但不良率為0.0%,較比較例2之不良率好。認為實施例相對於比較例1、比較例2,距離D之最小值更大、距離D之標準偏差更小之原因在於不良率較小。 Finally, the DAF cut-off rate was 5.1%, 0.7%, and 0.0% in Comparative Example 1, Comparative Example 2, and Example, respectively. Although the nominal strain of the tape at the time of attachment was 1.1% worse than that of Comparative Example 2, the defective ratio was 0.0%, which was better than that of Comparative Example 2. It is considered that the reason why the minimum value of the distance D is larger and the standard deviation of the distance D is smaller than that of the comparative example 1 and the comparative example 2 is that the defect rate is small.

對本實驗進行總結,若標稱應變為2%之常溫時之拉伸強度大於 2.8[N/20mm],則容易使貼附後之第二支持帶100之標稱應變小於上述1.9%。即,可減少DAF割斷不良。而且,若高溫時之拉伸強度大於1.6[N/20mm],則可使距離D進一步增大,且使距離D之標準偏差進一步減小。即,可進一步減少DAF割斷不良。 Summarize the experiment, if the nominal strain is 2% of the normal temperature, the tensile strength is greater than 2.8 [N/20 mm], it is easy to make the nominal strain of the attached second support tape 100 less than the above 1.9%. That is, the DAF cut failure can be reduced. Further, if the tensile strength at a high temperature is more than 1.6 [N/20 mm], the distance D can be further increased, and the standard deviation of the distance D can be further reduced. That is, DAF cut failure can be further reduced.

(第二實施形態) (Second embodiment)

使用圖24~圖28對第二實施形態進行說明。再者,對於與第一實施形態大致相同之要素標註相同之符號,並適當省略說明。 The second embodiment will be described with reference to Figs. 24 to 28 . The same components as those in the first embodiment are denoted by the same reference numerals, and their description will be appropriately omitted.

如圖24所示,將第一支持帶50貼附於半導體晶圓10之第一面10a。於本實施形態中,未形成刀片槽30地貼附第一支持帶50。 As shown in FIG. 24, the first support tape 50 is attached to the first face 10a of the semiconductor wafer 10. In the present embodiment, the first support tape 50 is attached without forming the blade groove 30.

如圖25及圖26所示,將半導體晶圓10上下翻轉,使用雷射310自第二面10b側切割。具體而言,使用雷射310於半導體晶圓10內部形成改質區域320。自該改質區域320朝向例如晶圓之下側產生龜裂(解理面)330。再者,龜裂330亦可沿上下產生。 As shown in FIGS. 25 and 26, the semiconductor wafer 10 is turned upside down, and the laser 310 is used to cut from the second surface 10b side. Specifically, the modified region 320 is formed inside the semiconductor wafer 10 using the laser 310. A crack (cleavage plane) 330 is generated from the modified region 320 toward, for example, the lower side of the wafer. Furthermore, the cracks 330 can also be generated up and down.

如圖27及圖28所示,將半導體晶圓10再次翻轉,使用研磨磨石60對第二面10b進行研磨。與第一實施形態之圖5同樣地對背面進行研磨。藉此,接下來半導體晶圓10藉由龜裂330而被單片化為複數個半導體晶片80與缺損晶片85。再者,由於存在龜裂330微細之情形,故而存在於外觀上無法視認出龜裂330之情形。 As shown in FIGS. 27 and 28, the semiconductor wafer 10 is again inverted, and the second surface 10b is polished using the grinding stone 60. The back surface is polished in the same manner as in Fig. 5 of the first embodiment. Thereby, the semiconductor wafer 10 is then singulated into a plurality of semiconductor wafers 80 and defective wafers 85 by cracks 330. Further, since the cracks 330 are fine, there is a case where the cracks 330 cannot be visually recognized.

以下,利用與第一實施形態相同之製造方法製造半導體裝置。 Hereinafter, a semiconductor device is manufactured by the same manufacturing method as that of the first embodiment.

於第二實施形態中使用基於雷射之切割,該點與第一實施形態不同。與使用刀片之切割相比,第二實施形態可防止因切割時產生灰塵所導致之良率降低,此外,可減少用於清洗之純水之使用量。 The laser-based cutting is used in the second embodiment, which is different from the first embodiment. The second embodiment can prevent the yield from being lowered due to the generation of dust during cutting as compared with the cutting using the blade, and can also reduce the amount of pure water used for cleaning.

(變化例) (variation)

於上述說明中,半導體晶圓10係於利用雷射切割後使用研磨磨石進行研磨。該研磨亦可於雷射切割前進行。例如,半導體晶圓10預先藉由研磨而薄膜化。其後,半導體晶圓10使用基於雷射之切割而形 成到達至半導體晶圓10之第一面10a及第二面10b之龜裂330。 In the above description, the semiconductor wafer 10 is polished by using a grinding grindstone after laser cutting. This grinding can also be carried out before laser cutting. For example, the semiconductor wafer 10 is previously thinned by grinding. Thereafter, the semiconductor wafer 10 is shaped using a laser-based cut. The cracks 330 reach the first surface 10a and the second surface 10b of the semiconductor wafer 10.

(第三實施形態) (Third embodiment)

於第一實施形態及第二實施形態中,貼附第二支持帶100之方向與半導體晶圓10之切割方向大致平行或大致正交,但並不限定於此。 In the first embodiment and the second embodiment, the direction in which the second support tape 100 is attached is substantially parallel or substantially orthogonal to the cutting direction of the semiconductor wafer 10, but the invention is not limited thereto.

例如,亦可與半導體晶圓10之切割方向傾斜45度。於此情形時,例如可更均勻地擴展。 For example, it is also possible to incline 45 degrees from the cutting direction of the semiconductor wafer 10. In this case, for example, it can be expanded more uniformly.

(第四實施形態) (Fourth embodiment)

使用圖29對第四實施形態進行說明。圖29(a)及(b)表示帶510之拉伸試驗之方法。圖29(a)表示拉伸前之狀態,圖29(b)表示拉伸後之狀態。 The fourth embodiment will be described with reference to Fig. 29 . 29(a) and (b) show the method of the tensile test of the belt 510. Fig. 29 (a) shows the state before stretching, and Fig. 29 (b) shows the state after stretching.

支架500使帶510之兩端拉伸,藉此可測定帶510之拉伸強度、標稱應力、標稱應變、伸長率等。帶510例如為第二支持帶100。 The stent 500 stretches both ends of the belt 510, whereby the tensile strength, nominal stress, nominal strain, elongation, and the like of the belt 510 can be determined. The strap 510 is, for example, a second support strap 100.

如圖29(a)及(b)所示,於拉伸後,帶510成為帶510',其寬度自W1變細成W2。 As shown in Figs. 29(a) and (b), after stretching, the belt 510 is a belt 510' whose width is reduced from W1 to W2.

另一方面,圖29(c)表示於將帶510貼附於半導體晶圓10之狀態下拉伸之狀態。如圖29(c)所示,帶510沿所有方向被拉伸,故而其粗細度不會如圖29(b)所示般變細。 On the other hand, FIG. 29(c) shows a state in which the tape 510 is stretched in a state of being attached to the semiconductor wafer 10. As shown in Fig. 29 (c), the belt 510 is stretched in all directions, so that the thickness thereof does not become thin as shown in Fig. 29 (b).

即,於圖29(a)及圖29(b)所示之帶510之拉伸試驗之方法中,存在無法恰當地算出貼附於晶圓10之狀態之應力、應變等之情形。因此,使用以下關係所表示之真實應力(True Stress)、真實應變(True Strain)。 That is, in the method of the tensile test of the tape 510 shown in FIGS. 29(a) and 29(b), there is a case where stress, strain, and the like in a state of being attached to the wafer 10 cannot be appropriately calculated. Therefore, the true stress (True Stress) and the true strain (True Strain) expressed by the following relationship are used.

σtnn+1) σ tnn +1)

εt=ln(εn+1) ε t =ln(ε n +1)

此處,σt為真實應力,σn為標稱應力,εt為真實應變,εn為標稱應變。利用真實應力、真實應變,可於降低拉伸試驗中帶510變細之效果且更接近實際使用帶10之環境之狀態下進行評價。 Here, σ t is the true stress, σ n is the nominal stress, ε t is the true strain, and ε n is the nominal strain. The true stress and the true strain can be evaluated in a state where the effect of the tape 510 is reduced in the tensile test and the environment in which the tape 10 is actually used is lowered.

圖30係表示利用標稱應力、標稱應變對相同樣本進行評價之情形(圖30(a))與利用真實應力、真實應變進行評價之情形(圖30(b))之比較之圖。 Fig. 30 is a view showing a comparison between the case where the same sample is evaluated by the nominal stress and the nominal strain (Fig. 30 (a)) and the case where the evaluation is performed using the true stress and the true strain (Fig. 30 (b)).

如圖30(a)所示,若使用標稱應力、標稱應變,則本樣本之降伏時伸長率為20%左右。另一方面,如圖30(b)所示,若使用真實應力、真實應變,則本樣本並未降伏,而是於真實應變約250%左右處斷裂。 As shown in Fig. 30 (a), if the nominal stress and the nominal strain are used, the elongation at the time of the fall of the sample is about 20%. On the other hand, as shown in Fig. 30(b), if true stress and true strain are used, the sample does not fall, but breaks at about 250% of the true strain.

即,圖30之樣本於利用標稱應力、標稱應變進行評價之情形時,降伏時伸長率為90%以下,故而存在會產生DAF割斷不良之顧慮。但是,若利用真實應力、真實應變進行評價,則不會降伏。而且,於發明者等人之實驗中確認到,於實際之樣本中,利用真實應力、真實應變進行評價更恰當。 That is, in the case where the sample of Fig. 30 is evaluated by the nominal stress or the nominal strain, the elongation at the time of the fall is 90% or less, and there is a concern that DAF cut failure occurs. However, if the evaluation is performed using real stress and true strain, it will not fall. Moreover, it was confirmed in experiments by the inventors and the like that it is more appropriate to evaluate with actual stress and true strain in the actual sample.

圖31係對針對第二支持帶100之樣本A~F中之DAF割斷不良試驗之評價實驗之結果進行彙總而成之表。圖31之表表示各樣本之評價結果、使用標稱應變、標稱應力時之降伏時伸長率、使用真實應力時之斷裂時或降伏時之標稱應變與真實應變。再者,各值係針對MD及TD而分別表示。 Fig. 31 is a table summarizing the results of evaluation experiments for the DAF cut failure test in the samples A to F of the second support tape 100. The table of Fig. 31 shows the evaluation results of each sample, the elongation at the time of using the nominal strain, the nominal stress, the nominal strain and the true strain at the time of the fracture or the fall when the true stress is used. Furthermore, each value is represented separately for MD and TD.

關於圖31之實驗,DAF割斷不良試驗之評價與圖23等同樣地係針對半導體晶圓10之評價試驗結果。降伏時伸長率、標稱應變、真實應變等之測定係使用島津製作所製造之Autograph(型式AGS-D)而進行測定。試驗時之拉伸速度為500mm/min。 With respect to the experiment of FIG. 31, the evaluation of the DAF cut failure test is the evaluation test result for the semiconductor wafer 10 in the same manner as in FIG. 23 and the like. The measurement of the elongation at break, the nominal strain, the true strain, and the like was measured using an Autograph (type AGS-D) manufactured by Shimadzu Corporation. The tensile speed at the time of the test was 500 mm/min.

實施DAF割斷不良之評價,結果樣本A~C、E良好,於樣本D、F中更多地產生不良。 The evaluation of the DAF cut failure was performed, and the samples A to C and E were good, and the samples D and F were more likely to be defective.

例如,如觀察圖31之樣本A可知那樣,使用標稱應力時之降伏時伸長率為28%、20%,小於90%。另一方面,使用真實應力時之斷裂時或降伏時之伸長率較大,為105%、124%。而且,實際上於樣本A 中DAF割斷不良之評價良好。 For example, as can be seen by observing the sample A of Fig. 31, the elongation at the time of the use of the nominal stress is 28%, 20%, and less than 90%. On the other hand, when the true stress is used, the elongation at break or at the time of the fall is large, which is 105% and 124%. And, actually, sample A The evaluation of poor DAF cuts was good.

相對於此,樣本D使用標稱應力時之降伏時伸長率為30%、30%,與樣本A大致同等。另一方面,使用真實應力時之斷裂時或降伏時之伸長率為199%、25%,於TD方面大幅差於樣本A。而且,實際上於樣本D中DAF割斷不良之評價並不良好。 On the other hand, when the sample D used the nominal stress, the elongation at the time of the fall was 30% and 30%, which was substantially the same as the sample A. On the other hand, when the true stress is used, the elongation at break or at the time of the fall is 199%, 25%, which is significantly worse than the sample A in terms of TD. Moreover, the evaluation of the DAF cut defect in the sample D was actually not good.

即,存在使用真實應力時之斷裂時或降伏時之伸長率與DAF割斷不良進一步相關之情形。 That is, there is a case where the elongation at the time of fracture or the fall at the time of using the true stress is further related to the poor DAF cut.

根據圖31之結果得知,於DAF割斷不良良好之樣本A~C、E中,使用真實應力時之斷裂時或降伏時之伸長率最小的是樣本C之TD中之72%。即,若為72%以上,則關於DAF割斷不良,可期待良好之結果。 According to the results of Fig. 31, in the samples A to C and E in which the DAF was poorly cut, the elongation at the time of the fracture using the true stress or the minimum at the time of the fall was 72% of the TD of the sample C. In other words, when it is 72% or more, a good result can be expected with respect to DAF cut failure.

再者,於不良樣本D、F中,認為MD與TD中較小之值與DAF割斷不良相關,故而需要對MD與TD之值中較小之值進行評價。於樣本D與F中,使用真實應力時之斷裂時或降伏時之伸長率最大的成為樣本F之39%。 Furthermore, in the bad samples D and F, it is considered that the smaller value of MD and TD is related to the poor DAF cut, so it is necessary to evaluate the smaller of the values of MD and TD. In the samples D and F, the maximum elongation at break or at the time of the fall when using the true stress was 39% of the sample F.

已對本發明之實施形態進行了說明,但本實施形態係作為例子而提出,並非意圖限定發明之範圍。該新穎之實施形態可以其它各種形態加以實施,且可於不脫離發明主旨之範圍內進行各種省略、替換、變更。本實施形態或其變化包含於發明之範圍或主旨中,並且包含於申請專利範圍所記載之發明與其均等之範圍內。 The embodiments of the present invention have been described, but the embodiments are presented as examples and are not intended to limit the scope of the invention. The present invention may be embodied in various other forms, and various omissions, substitutions and changes may be made without departing from the scope of the invention. The present invention and its modifications are intended to be included within the scope and spirit of the invention, and are included in the scope of the invention described in the claims.

Claims (7)

一種半導體裝置之製造方法,其包括:將第一支持帶貼附於半導體晶圓之第一面之步驟;將上述半導體晶圓單片化為複數個半導體晶片之步驟;將第二支持帶沿第一方向貼附於上述複數個半導體晶片之第二面之步驟;將上述第一支持帶自上述複數個半導體晶片剝離之步驟;及藉由使上述第二支持帶延伸而擴大上述半導體晶片之間之距離之步驟;且上述第二支持帶相對於上述第一方向之伸長而產生之標稱應力與相對於與上述第一方向交叉之第二方向之伸長而產生之標稱應力之比為0.7~1.4。 A method of fabricating a semiconductor device, comprising: a step of attaching a first support strip to a first side of a semiconductor wafer; a step of singulating the semiconductor wafer into a plurality of semiconductor wafers; and a second support strip a step of attaching the first direction to the second surface of the plurality of semiconductor wafers; a step of stripping the first support strip from the plurality of semiconductor wafers; and expanding the semiconductor wafer by extending the second support strip a step of a distance therebetween; and a ratio of a nominal stress generated by the elongation of the second support strip relative to the first direction to a nominal stress generated by elongation with respect to a second direction crossing the first direction is 0.7~1.4. 如請求項1之半導體裝置之製造方法,其中上述第二支持帶降伏時伸長率為90%以上。 The method of manufacturing a semiconductor device according to claim 1, wherein the second support tape has an elongation at which the elongation is 90% or more. 如請求項1之半導體裝置之製造方法,其中上述第二支持帶使用真實應力時之斷裂時或降伏時之伸長率為72%以上。 The method of manufacturing a semiconductor device according to claim 1, wherein the second support tape has an elongation at break or a fall of 72% or more when the true stress is used. 如請求項1之半導體裝置之製造方法,其中上述第二支持帶用於將寬度20mm之上述第二支持帶伸長2%所需之力,於24度下大於2.8[N],於70度下大於1.6[N]。 The method of manufacturing the semiconductor device of claim 1, wherein the force required for the second support strip to elongate the second support strip having a width of 20 mm by 2% is greater than 2.8 [N] at 24 degrees, at 70 degrees Greater than 1.6 [N]. 如請求項1之半導體裝置之製造方法,其中上述第二支持帶於貼附後於常溫下向上述第一方向之標稱應變為1.9%以下。 The method of manufacturing a semiconductor device according to claim 1, wherein the second support strip has a nominal strain of 1.9% or less in the first direction at a normal temperature after the attachment. 如請求項1至5中任一項之半導體裝置之製造方法,其進而包括如下步驟:於貼附上述第一支持帶之步驟之前,使用刀片於上述半導體晶圓形成刀片槽,上述單片化步驟係藉由如下方式進行:對上述半導體晶圓之 與上述第一面相反之第二面進行研磨,使上述刀片槽到達至上述第二面。 The method of manufacturing a semiconductor device according to any one of claims 1 to 5, further comprising the step of forming a blade groove on the semiconductor wafer using the blade before the step of attaching the first support tape, the singulation The steps are performed by: for the above semiconductor wafer The second surface opposite to the first surface is ground to cause the insert pocket to reach the second surface. 如請求項1至5中任一項之半導體裝置之製造方法,其中上述單片化步驟係藉由如下方式進行:對上述半導體晶圓照射雷射而形成解理面。 The method of manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the singulation step is performed by irradiating the semiconductor wafer with a laser to form a cleavage surface.
TW105106578A 2015-04-07 2016-03-03 Manufacturing method of semiconductor device TWI624029B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015078578 2015-04-07
JP2016027371A JP6502874B2 (en) 2015-04-07 2016-02-16 Semiconductor device manufacturing method

Publications (2)

Publication Number Publication Date
TW201715697A true TW201715697A (en) 2017-05-01
TWI624029B TWI624029B (en) 2018-05-11

Family

ID=57424464

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105106578A TWI624029B (en) 2015-04-07 2016-03-03 Manufacturing method of semiconductor device

Country Status (3)

Country Link
JP (1) JP6502874B2 (en)
CN (1) CN106057792B (en)
TW (1) TWI624029B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111697049A (en) * 2019-03-15 2020-09-22 东芝存储器株式会社 Semiconductor device with a plurality of semiconductor chips

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6938212B2 (en) * 2017-05-11 2021-09-22 株式会社ディスコ Processing method
JP2019149472A (en) * 2018-02-27 2019-09-05 株式会社東芝 Semiconductor device and dicing method
JP6915675B2 (en) * 2019-01-22 2021-08-04 住友ベークライト株式会社 Adhesive tape and base material for adhesive tape

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11297646A (en) * 1998-04-10 1999-10-29 Techno Onishi:Kk Film for supporting semiconductor chip
JP2002009018A (en) * 2000-06-19 2002-01-11 Mitsubishi Plastics Ind Ltd Dicing film for semiconductor wafer
JP4536407B2 (en) * 2004-03-30 2010-09-01 浜松ホトニクス株式会社 Laser processing method and object to be processed
JP2011216671A (en) * 2010-03-31 2011-10-27 Furukawa Electric Co Ltd:The Tape for processing semiconductor wafer, method of manufacturing the same, and method of processing the semiconductor wafer
JP4976522B2 (en) * 2010-04-16 2012-07-18 日東電工株式会社 Thermosetting die bond film, dicing die bond film, and semiconductor device manufacturing method
JP2012079936A (en) * 2010-10-01 2012-04-19 Nitto Denko Corp Dicing, die-bonding film and method for manufacturing semiconductor device
JP5932290B2 (en) * 2011-10-20 2016-06-08 株式会社テラバイト Mechanical property creation method considering parameters related to plastic volume change
JP5975763B2 (en) * 2012-07-05 2016-08-23 株式会社ディスコ Wafer processing method
US8664089B1 (en) * 2012-08-20 2014-03-04 Semiconductor Components Industries, Llc Semiconductor die singulation method
CN103715117B (en) * 2012-09-28 2016-11-16 株式会社东芝 The manufacture device of semiconductor device and the manufacture method of semiconductor device
JP2014204089A (en) * 2013-04-09 2014-10-27 株式会社ディスコ Wafer transfer mechanism and wafer processing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111697049A (en) * 2019-03-15 2020-09-22 东芝存储器株式会社 Semiconductor device with a plurality of semiconductor chips
TWI707454B (en) * 2019-03-15 2020-10-11 日商東芝記憶體股份有限公司 Semiconductor device
CN111697049B (en) * 2019-03-15 2023-10-24 铠侠股份有限公司 Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Also Published As

Publication number Publication date
JP6502874B2 (en) 2019-04-17
CN106057792A (en) 2016-10-26
JP2016201533A (en) 2016-12-01
TWI624029B (en) 2018-05-11
CN106057792B (en) 2020-02-07

Similar Documents

Publication Publication Date Title
TW201715697A (en) Method for manufacturing semiconductor device
JP5391158B2 (en) Wafer sticking adhesive sheet and wafer processing method using the same
US20060223234A1 (en) Semiconductor-device manufacturing method
JP2007165371A (en) Method of manufacturing semiconductor device
JP4767122B2 (en) Method for replacing tape and method for dividing substrate using the method for replacing tape
US20190189497A1 (en) Workpiece processing method
TWI419217B (en) Device manufacturing method
TWI724109B (en) Adhesive sheet and method of use
JP2011159679A (en) Method of manufacturing chip
JP2004342896A (en) Semiconductor device and method of manufacturing the same
US9018080B2 (en) Wafer processing method
TW201843720A (en) Method of manufacturing semiconductor device
JP6594930B2 (en) Wafer processing method and wafer processing system
TW200524185A (en) Method for production of semiconductor chip and semiconductor chip
JP6010945B2 (en) Dicing film
TWI729174B (en) Semiconductor device and manufacturing method thereof
TWI779024B (en) processing methods
JP6298699B2 (en) Wafer processing method
JP6209097B2 (en) Wafer processing method
JP2016201412A (en) Division method of wafer
TWI644774B (en) a method for separating a brittle material substrate, a substrate holding member for breaking a brittle material substrate, and a frame for adhering the adhesive film used for breaking the brittle material substrate
JP2012182342A (en) Expand device and expand processing method of semiconductor substrate
TW202307947A (en) Method of processing a substrate and system for processing a substrate
TW201921453A (en) Method of manufacturing a semiconductor device
JP6362484B2 (en) Semiconductor wafer dicing method