TW201633460A - 半導體裝置與其形成方法 - Google Patents

半導體裝置與其形成方法 Download PDF

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TW201633460A
TW201633460A TW104122488A TW104122488A TW201633460A TW 201633460 A TW201633460 A TW 201633460A TW 104122488 A TW104122488 A TW 104122488A TW 104122488 A TW104122488 A TW 104122488A TW 201633460 A TW201633460 A TW 201633460A
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doped
drain
source
substrate
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TWI616982B (zh
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霍克孝
蔣昕志
陳奕寰
蔡俊琳
陳益民
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台灣積體電路製造股份有限公司
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Abstract

高電壓半導體裝置包括：具有第一導電型態的源極與汲極位於基板中；第一介電構件位於源極與汲極之間的基板表面上；漂移區位於基板中，其中漂移區具有第一導電型態；第一掺雜區具有第二導電型態且位於介電構件下的漂移區中，且第二導電型態與第一導電型態相反；具有第二導電型態的第二掺雜區位於漂移區中，其中第二掺雜區至少圍繞源極與汲極中的一者；電阻直接位於介電構件上；以及閘極直接位於介電構件上，其中閘極直接電性耦接至電阻。

Description

半導體裝置與其形成方法
本發明係關於高電壓半導體裝置，更特別關於其電阻裝置的電性狀態。
半導體積體電路(IC)產業快速成長。IC材料與設計的技術進步，使IC更小且其電路更複雜。製程尺寸縮小增加製程複雜度。然而製程尺寸縮小的優點顯而易見，因此需要更小的IC製程。新一代的IC具有較大的功能密度(比如固定晶片面積中的內連線裝置數目)，與較小的尺寸(比如製程形成的最小構件或連線)。
這些IC包括高電壓半導體裝置。當裝置尺寸持續縮小時，現有的高電壓半導體裝置將難以達到所需的效能標準。舉例來說，習知的高電壓半導體裝置之效能將受限於崩潰電壓。在習知的高電壓半導體裝置中，為改良崩潰電壓而降低漂移區的掺雜，將會導致裝置之開啟狀態的電阻增加。
如此一來，現有的高電壓半導體裝置一般只能符合特定需求，而無法滿足所有應用。
本發明一實施例提供之半導體裝置，包括：源極與汲極位於基板中，源極具有第一導電型態，且汲極具有第一 導電型態；第一介電構件位於源極與汲極之間的基板之表面上；漂移區位於基板中，且漂移區具有第一導電型態；第一掺雜區位於介電構件下的漂移區中，第一掺雜區具有第二導電型態，且第二導電型態與第一導電型態相反；第二掺雜區位於漂移區中，其中第二掺雜區至少圍繞源極區與汲極區之一者，且第二掺雜區具有第二導電型態；電阻直接位於介電構件上；以及閘極直接位於介電構件上，其中閘極電性耦接至該電阻。
本發明一實施例提供之半導體裝置，包括：電晶 體，具有閘極、源極、與汲極，其中：源極與汲極係形成於掺雜基板中，且源極與汲極之間隔有掺雜基板之漂移區，其中漂移區包含p型掺雜部份與n型掺雜部份；閘極係位於漂移區上，並位於源極與汲極之間；以及電晶體係設置以處理至少幾百伏特的高電壓；介電結構形成於電晶體之源極與汲極之間，介電結構穿入並凸出掺雜基板，其中介電結構的不同部份具有不一致的厚度；以及電阻形成於介電結構上，電阻具有多個纏繞部件，且纏繞部件之間具有實質上相同的間距；其中電阻電性耦接至電晶體的閘極。
本發明一實施例提供之半導體裝置的形成方法， 包括：形成漂移區於基板中，其中漂移區包含不同導電型態的多個掺雜區；形成介電隔離結構於漂移區上；形成電晶體的閘極於介電隔離結構上；形成電阻裝置於介電隔離結構上，其中電阻裝置包含多個纏繞部件；以及形成源極與汲極於基板中，其中源極與汲極之間隔有漂移區與介電隔離結構，其中電阻裝置與閘極位於源極與汲極之間，以及電阻裝置與閘極係電性耦 接。
10‧‧‧方法
12、14、16、18、20‧‧‧步驟
20A、20B、20C、20D‧‧‧高電壓半導體裝置
30‧‧‧基板
35‧‧‧埋井
50‧‧‧高電壓掺雜井
60‧‧‧反轉層
80、81‧‧‧隔離結構
90‧‧‧厚度
100‧‧‧掺雜延伸區
105‧‧‧凸出部份
110‧‧‧掺雜隔離區
120‧‧‧閘極
130‧‧‧電阻裝置
150‧‧‧重掺雜汲極區
160‧‧‧重掺雜源極區
161‧‧‧重掺雜區
170‧‧‧導電墊
200‧‧‧內連線結構
210、211、212、213、214、215‧‧‧接點
220、221、222‧‧‧金屬線路
230‧‧‧金屬導體
250‧‧‧掺雜井
260‧‧‧掺雜埋層
第1圖係本發明多個實施例中，形成高電壓半導體裝置之方法的流程圖。
第2至5圖係本發明多個實施例中，高電壓半導體裝置的部份剖視圖。
可以理解的是，下述揭露內容提供的不同實施例可實施本發明的不同結構。下述特定構件與排列的實施例係用以簡化本發明而非侷限本發明。此外，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。為簡化及清楚說明本發明，可採用任意比例繪示多種結構。
第1圖係本發明多種實施例中，製作高電壓半導體裝置的方法10流程圖。方法10之步驟12形成漂移區於基板中。漂移區包含不同導電型態的掺雜區。方法10之步驟14接著形成介電隔離結構於漂移區上。在某些實施例中，介電隔離結構包括凸出基板表面外的局部氧化矽(LOCOS)。方法10之步驟16接著形成電晶體閘極於部份的介電隔離結構上。在形成閘極後，方法10之步驟18接著形成電阻裝置於介電隔離結構上。電阻裝置包括多個纏繞部件。在某些實施例中，纏繞部件具有實質上一致的尺寸與間距。方法10之步驟20接著形成源極與汲極於基板中。在特定實施例中，源極與汲極之間隔有漂移區與介電隔 離結構，且電阻裝置與閘極位於源極與汲極之間。在某些實施例中，電阻裝置與閘極電性耦接。
藉由電性耦接閘極與電阻裝置，可施加相同電壓 至電晶體之閘極與形成於漂移區上的電阻裝置。如此一來，當電壓施加至閘極時，可形成反轉層於漂移區與介電隔離結構之間的界面。在一實例中，「反轉」在這指的是在具有第一導電型態之半導體結構中，有部份的半導體結構被誘導以具有相反的導電型態。在一實例中，高電壓半導體裝置之漂移區可具有p型掺雜部份，且在電壓施加至閘極時具有n型掺雜反轉層形成於漂移區與介電隔離結構之間的界面。在另一實例中，漂移區可具有n型掺雜部份，且在電壓施加至閘極時具有p型掺雜反轉層形成於漂移區與介電隔離結構之間的界面。
一般而言，低掺雜濃度可用於高電壓裝置之漂移 區中，使高電壓裝置具有較高的崩潰電壓。然而降低掺雜濃度將導致電晶體之導電性較低(比如增加電晶體之電阻)或單純增加開啟電阻。增加開啟電阻將負面影響電晶體效能，比如較低的速度、較高的阻抗、或類似性質。在不妥協效能的情況下，具有上述誘發的反轉層可正面影響高電壓裝置，使其同時具有所需的高崩潰電壓與低電阻。
可以理解的是，其他額外步驟可用以製作高電壓 半導體裝置。舉例來說，上述方法可形成內連線結構於基板上。內連線結構可使電晶體與電阻裝置電性並聯，或讓電阻電性浮置。
第2圖為本發明一實施例中，高電壓半導體裝置 20A之剖視圖。可以理解的是，第2圖已簡化以利了解本發明概念。
如第2圖所示，高電壓半導體裝置20A包括部份的 基板30。基板30掺雜p型掺質如硼。在另一實施例中，基板30可掺雜n型掺質如磷或砷。基板30亦包含其他合適的半導體元素材料如鑽石或鍺；合適的半導體化合物如碳化矽、砷化銦、或磷化銦；或合適的半導體合金如碳化矽鍺、磷化鎵砷、或磷化鎵銦。
藉由離子佈植製程，形成埋井35於部份的基板30 中。埋井35之導電型態與基板30相反。在此實施例中，埋井35為n型掺雜，而基板30為p型基板。在另一實施例中，基板30為n型基板，而埋井35為p型掺雜。埋井35之形成方法可為佈植製程，其掺雜劑量介於約1×1012原子/cm2至約2×1012原子/cm2之間。埋井35之掺雜濃度介於於約1×1015原子/cm3至約1×1016原子/cm3之間。
高電壓掺雜井50形成於基板30中。高電壓掺雜井 50之形成方法可為離子佈植製程。舉例來說，用以形成高電壓掺雜井50之離子佈植製程其掺雜劑量介於約3×1012原子/cm2至約4×1012原子/cm2之間。在一實施例中，高電壓掺雜井50之掺雜濃度介於於約1×1015原子/cm3至約1×1016原子/cm3之間。在進行離子佈植製程時，圖案化光阻層(未圖示)可形成於基板30上以作為遮罩。
高電壓掺雜井50之掺雜導電型態與埋井35相同， 並與基板30相反。如此一來，此實施例之高電壓掺雜井50為高 電壓n型井(HVNW)。高電壓掺雜井50亦可稱作漂移區。
在第2圖中，多個隔離結構80與81係形成於高電壓 掺雜井50上。隔離結構80與81可包含介電材料。在第2圖所示之實施例中，隔離結構80與81為局部氧化矽(LOCOS)裝置，又稱作場氧化物。LOCOS裝置之形成方法可採用氮化物遮罩，再經由遮罩開口熱成長氧化物材料。部份的LOCOS裝置將朝下穿入並朝上凸出高電壓掺雜井50。此外，LOCOS裝置具有不一致的厚度(或深度)。舉例來說，LOCOS裝置的邊緣部份可為較小厚度的錐形。在某些實施例中，LOCOS裝置的非邊緣部份的厚度90，係介於約0.2微米至約1微米之間。
在另一實施例中，隔離結構80與81可為淺溝槽隔 離(STI)裝置或深溝槽隔離(DTI)裝置。隔離結構80與81可定義稍後形成的掺雜區之間的邊界，比如場效電晶體(FET)裝置之源極與汲極區的邊界。
掺雜延伸區100係形成於高電壓掺雜井50中。在圖 示的實施例中，掺雜延伸區100係形成於高電壓掺雜井50與埋井35之間。掺雜延伸區100之導電型態與基板30相同，但與高電壓掺雜井50相反。如此一來，圖示之實施例中的掺雜延伸區100具有p型導電型態。
在此實施例中，掺雜延伸區100之形成方法可為兩 道分開的離子佈植製程。第一道離子佈植製程，可形成掺雜區於高電壓掺雜井50其至少部份的上半部(靠近其上表面)中。第二道離子佈植製程，可形成較深與較廣的掺雜區，且此掺雜區橫向地向外延伸或凸出。接著進行熱製程使兩道離子佈植製程 形成的掺雜區擴散合併為單一掺雜區，即掺雜延伸區100。上述步驟形成的掺雜延伸區100，其凸出部份105橫向延伸或凸出至部份的高電壓掺雜井50中。如此一來，掺雜延伸區100亦可稱為p型體延伸區。
如第2圖所示，凸出部份105埋入高電壓掺雜井50 中，而非靠近高電壓掺雜井50的上表面。換言之，凸出部份105遠離高電壓掺雜井50的表面。上述結構的好處之一為凸出部份105可提供額外的導電路徑，以降低電晶體於開啟狀態的電阻。
在一實施例中，形成掺雜隔離區110之佈植製程亦 可形成掺雜延伸區100。在一實施例中，掺雜隔離區110之形成方法，為形成掺雜延伸區100的第二道佈植製程(即形成較寬與較深之掺雜區的佈植製程)。為定義掺雜隔離區110之橫向尺寸，可形成具有開口之光阻遮罩層於基板上，再進行前述的第二道佈植製程穿過開口，以定義掺雜隔離區110。換言之，在形成掺雜延伸區100之凸出部份105時，亦可形成掺雜隔離區110。如此一來，掺雜隔離區110與凸出部份105將具有類似的掺雜濃度。
閘極120係形成於高電壓掺雜井50上。在特定實施 例中，閘極120可形成於部份的隔離結構80上。閘極120之形成方法可為多重沉積與圖案化製程。在某些實施例中，閘極120為具有金屬矽化物表面的多晶矽材料。舉例來說，金屬矽化物表面可為鎢矽化物。
電阻裝置130係形成於隔離結構80上。在某些實施 例中，電阻裝置130包含多晶矽材料，並因此稱作為多晶矽電 阻。舉例來說，電阻裝置130可包含未掺雜之多晶矽材料、p型掺雜之多晶矽材料、或多晶矽材料上的金屬矽化物。電阻裝置130設計以處理高電壓，比如大於約100伏特或幾百伏特的電壓。如此一來，電阻裝置130亦可稱為高電壓電阻裝置。在某些實施例中，電阻裝置130與閘極120同時形成。在其他實施例中，電阻裝置130與閘極120以不同製程分開形成。
在本發明多種實施例中，電阻裝置130具有細長的 纏繞形狀。如第2圖所示之剖視圖，電阻裝置130的外觀為多個纏繞部件。雖然剖視圖中電阻裝置130之纏繞部件為分開的部件，但應理解這些纏繞部件實際上為單一細長電阻裝置130之部份。在某些實施例中，電阻裝置130的纏繞部件具有實質上一致的垂直與橫向尺寸(比如高度/厚度與寬度)。舉例來說，不同纏繞部件的垂直與橫向尺寸之間的差異，只有幾個百分比或更小。在某些實施例中，電阻裝置130其相鄰的纏繞部件之間距也實質上一致。在某些其他實施例中，電阻裝置130其相鄰的纏繞部件之間距可依合適應用而有所不同。
重掺雜汲極區150係形成於隔離結構80一側上的 高電壓掺雜井50之上表面中，而重掺雜源極區160係形成於隔離結構80另一側上的掺雜延伸區100之上表面中。換言之，重掺雜汲極區150與重掺雜源極區160係位於隔離結構80的相反兩側上。重掺雜區161係形成於與重掺雜源極區160相鄰處。在某些實施例中，重掺雜區161可作為保護環。
重掺雜汲極區150與重掺雜源極區160的導電型態 與高電壓掺雜井50相同，且重掺雜區161的導電型態與掺雜延 伸區100相同。如此一來第2圖所示之實施例中，重掺雜汲極區150與重掺雜源極區160為n型掺雜，而重掺雜區161為p型掺雜。重掺雜汲極區150與重掺雜源極區160之掺質濃度，明顯高於高電壓掺雜井50之掺質濃度。重掺雜區161之掺質濃度，明顯高於掺雜延伸區100之掺質濃度。在圖示的實施例中，重掺雜汲極區150與重掺雜源極區160可稱作N+區，而重掺雜區161可稱作P+區。導電墊170亦可形成於源極或汲極區(或掺雜隔離區110)上，以幫助建立電性連接至源極或汲極區。
閘極120(位於重掺雜汲極區150與重掺雜源極區 160之間)、重掺雜汲極區150、與重掺雜源極區160為FET電晶體裝置的構件。本發明之FET電晶體裝置為可處理高電壓的高電壓電晶體。舉例來說，FET電晶體裝置設置於幾百伏特的電壓下操作。
內連線結構200係形成於基板30的表面上。換言 之，除了基板30外，內連線結構200亦係形成於隔離結構80與81、閘極120、電阻裝置130、重掺雜源極區160、與重掺雜汲極區150上。內連線結構200包含多個圖案化介電層與導電層，以提供電路、輸入/輸出、及多種掺雜結構(如高電壓掺雜井50)之間的內連線(如線路)。進一步來說，內連線結構200可包含多個內連線層(亦稱作金屬層)。每一內連線層包括多個內連線結構(亦稱作金屬線路)。金屬線路可為鋁內連線線路或銅內連線線路，且可包括導電材料如鋁、銅、鋁合金、銅合金、鋁/矽/銅合金、鈦、氮化鈦、鉭、氮化鉭、鎢、多晶矽、金屬矽化物、或上述之組合。金屬線路之形成方法可為物理氣相沉積法 (PVD)、化學氣相沉積法(CVD)、濺鍍法、電鍍法、或上述之組合。
內連線結構200包含層間介電層(ILD)以隔離內連 線層。ILD可包含介電材料如低介電常數材料或氧化物材料。 內連線結構200亦包含多個接點，以提供基板上不同內連線層及/或結構(比如重掺雜源極區160、重掺雜汲極區150、及電阻裝置130)之間的電性連接。
舉例來說，部份的內連線結構200與多個接點 210、211、212、213、214、及215可提供電性連接至掺雜隔離區110、閘極120、電阻裝置130、重掺雜汲極區150、及重掺雜源極區160。在第2圖中的實施例，接點211及212係形成於電阻裝置130之相反兩端上，且電性耦接至電阻裝置130之相反兩端。
內連線結構200包含的金屬線路(或內連線線路)電 性耦接至接點210、211、212、213、214、及215。舉例來說，金屬線路220電性耦接至接點212與213，金屬線路221電性耦接至接點210與214，而金屬線路222電性耦接至接點211與215。 換言之，電阻裝置130的一端電性耦接至重掺雜汲極區150，而電阻裝置130的另一端電性耦接至閘極120。這種情況下的電阻裝置130將與FET電晶體裝置並聯耦接，特別是與FET裝置的汲極與閘極並聯耦接。如此一來，施加至電阻裝置130與閘極的電壓相同，當施加高閘極電壓時將形成反轉層60於高電壓掺雜井50及隔離結構80之間的界面。在高電壓下同時維持電晶體的崩潰電壓時，反轉層60可使電晶體更導電。
此外，本發明之多個實施例之並聯耦接的電阻裝 置130可改善高電壓掺雜井50中電場的一致性。如前所述，電阻裝置130具有多個實質上一致的纏繞部件，且這些纏繞部件之間的距離實質上一致。如此一來，每一纏繞部件可承受實質上固定且定量的電壓。換言之，由於FET電晶體與電阻裝置並聯耦合，當高電壓(如幾百伏特)施加至FET電晶體的源極與汲極之間時，高電壓即施加至電阻裝置130。電阻裝置130之構件尺寸與間距的一致性，可讓高電壓平均分佈於電阻裝置130，進而改善電阻裝置130下之高電壓掺雜井50中的電場一致性。 更加一致的電場分佈可增加FET電晶體的崩潰電壓。藉由測試可知本發明中並聯的電阻裝置，可讓崩潰電壓增加幾百伏特。
第3至5圖係本發明其他實施例中，高電壓裝置的 部份剖視圖。為了說明清楚及一致性，將以相同標號標示第2至5圖中的類似構件。
如第3圖所示，高電壓半導體裝置20B與前述之高 電壓半導體裝置20A多有類似，兩者之間的差異在於高電壓半導體裝置20B具有電性浮置的金屬導體230作為內連線結構200的一部份。電性浮置的金屬導體230位於電阻裝置130上，但未直接電性連接至FET電晶體的構件。
如第4圖所示，高電壓半導體裝置20C與前述之高 電壓半導體裝置20A多有類似，兩者之間的差異在於高電壓半導體裝置20C具有一導電型態之高電壓掺雜井50延伸至基板30中。在此實施例中，高電壓半導體裝置20C具有n型的漂浮區(高電壓掺雜井50)。與此相較，高電壓半導體裝置20A之高電壓掺 雜井50包含n型掺雜區(比如n型的埋井35與高電壓掺雜井50)及p型掺雜部份(比如p型的掺雜延伸區100)。FET電晶體裝置之重掺雜源極區160係形成於掺雜井250中(並被掺雜井250圍繞)，且此實施例之掺雜井250為p型井。在一實施例中，掺雜井250係形成於高電壓掺雜井50中。掺雜井250的導電型態與基板30的導電型態相同，但與高電壓掺雜井50的導電型態相反。如此一來，此實施例中掺雜井250具有p型的導電型態。
如第5圖所示，高電壓半導體裝置20D與前述之高 電壓半導體裝置20C多有類似，兩者之間的差異在於高電壓半導體裝置20D更包含掺雜埋層260於高電壓掺雜井50中。掺雜埋層260之導電型態與高電壓掺雜井50導電型態相反。如此一來，第5圖中此實施例之掺雜埋層260為p型埋層。以功能來說，掺雜埋層260與前述之p型的掺雜延伸區100類似。然而如圖所示，掺雜埋層260與掺雜井250並非連續結構。
可以理解的是高電壓半導體裝置20A至20D的任一 實施例均可與另一實施例組合，端視設計與製程需要而定。舉例來說，高電壓半導體裝置的實施例可具有電性浮置電阻裝置(如第3圖所示之結構)，以及單一導電型態的高電壓掺雜井(如第4圖所示之結構)。為簡化說明起見，不特別討論上述實施例之間的可能組合。
除了上述製程步驟外，可進行其他額外步驟以完 成高電壓半導體裝置。舉例來說，在形成內連線結構後，可對高電壓半導體裝置進行鈍化製程。在另一實施例中，高電壓半導體裝置亦包括一或多道測試製程如晶圓允收測試製程。為簡 化說明，將不在此詳述這些額外製程。
本發明之一上位概念與裝置相關，其包括：源極 與汲極位於基板中，源極具有第一導電型態，且汲極具有第一導電型態；第一介電構件位於源極與汲極之間的基板之表面上；漂移區位於基板中，且漂移區具有第一導電型態；第一掺雜區位於介電構件下的漂移區中，第一掺雜區具有第二導電型態，且第二導電型態與第一導電型態相反；第二掺雜區位於漂移區中，其中第二掺雜區至少圍繞源極區與汲極區之一者，且第二掺雜區具有第二導電型態；電阻直接位於介電構件上；以及閘極直接位於介電構件上，其中閘極電性耦接至電阻。
本發明另一廣義概念關於半導體裝置，其包括： 電晶體，具有閘極、源極、與汲極，其中：源極與汲極係形成於掺雜基板中，且源極與汲極之間隔有掺雜基板之漂移區；閘極係位於漂移區上，並位於源極與汲極之間；以及電晶體係設置以處理至少幾百伏特的高電壓；介電結構形成於電晶體之源極與汲極之間，介電結構穿入並凸出掺雜基板，其中介電結構的不同部份具有不一致的厚度；以及電阻形成於介電結構上，電阻具有多個纏繞部件，且纏繞部件之間具有實質上相同的間距。在多種實施例中，電阻電性耦接至電晶體的閘極。
本發明又一上位概念關於高電壓半導體裝置的形 成方法，包括：形成漂移區於基板中，其中漂移區包含不同導電型態的多個掺雜區；形成介電隔離結構於漂移區上；形成電晶體的閘極於介電隔離結構上；形成電阻裝置於介電隔離結構上，其中電阻裝置包含多個纏繞部件；以及形成源極與汲極於 基板中，其中源極與汲極之間隔有漂移區與介電隔離結構，其中電阻裝置與閘極位於源極與汲極之間，以及電阻裝置與閘極係電性耦接。
本發明之特徵已以數個實施例揭露如上，以利本技術領域中具有通常知識者得以更理解本發明。本技術領域中具有通常知識者應理解，可採用本發明為基礎設計或改良其他製程與結構，以達上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解這些等效構建並未偏離本發明之精神與範疇，且可在未偏離本發明之精神與範疇下進行多種改變、置換、與替換。
20A‧‧‧高電壓半導體裝置
30‧‧‧基板
35‧‧‧埋井
50‧‧‧高電壓掺雜井
60‧‧‧反轉層
80、81‧‧‧隔離結構
90‧‧‧厚度
100‧‧‧掺雜延伸區
105‧‧‧凸出部份
110‧‧‧掺雜隔離區
120‧‧‧閘極
130‧‧‧電阻裝置
150‧‧‧重掺雜汲極區
160‧‧‧重掺雜源極區
161‧‧‧重掺雜區
170‧‧‧導電墊
200‧‧‧內連線結構
210、211、212、213、214、215‧‧‧接點
220、221、222‧‧‧金屬線路

Claims (11)

  1. 一種半導體裝置，包括：一源極與一汲極位於一基板中，該源極具有一第一導電型態，且該汲極具有該第一導電型態；一第一介電構件位於該源極與該汲極之間的該基板之表面上；一漂移區位於該基板中，且該漂移區具有該第一導電型態；一第一掺雜區位於該介電構件下的該漂移區中，該第一掺雜區具有一第二導電型態，且該第二導電型態與該第一導電型態相反；一第二掺雜區位於該漂移區中，其中該第二掺雜區至少圍繞該源極區與該汲極區之一者，且該第二掺雜區具有該第二導電型態；一電阻直接位於該介電構件上；以及一閘極直接位於該介電構件上，其中該閘極電性耦接至該電阻。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該第一掺雜區與該第二掺雜區互相交錯，以形成一連續的掺雜延伸區。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該第一掺雜區與該第二掺雜區為不連續的結構，且部份該漂移區延伸於該第一掺雜區與該第二掺雜區之間。
  4. 如申請專利範圍第1項所述之半導體裝置，更包括一第二介電構件位於該基板中並與該第二掺雜區具有界面；以及一掺雜隔離區位於該基板中並與該第二介電構件具有界 面，且該掺雜隔離區具有該第二導電型態。
  5. 如申請專利範圍第1項所述之半導體裝置，其中當一電壓施加至該閘極時，該漂移區包括一反轉層，且該反轉層具有該第二導電型態，其中該反轉層係位於該第一介電構件與該漂移區之間的界面。
  6. 一種半導體裝置，包括：一電晶體，具有一閘極、一源極、與一汲極，其中：該源極與該汲極係形成於一掺雜基板中，且該源極與該汲極之間隔有該掺雜基板之一漂移區，其中該漂移區包含p型掺雜部份與n型掺雜部份；該閘極係位於該漂移區上，並位於該源極與該汲極之間；該電晶體係設置以處理至少幾百伏特的高電壓；一介電結構形成於該電晶體之該源極與該汲極之間，該介電結構穿入並凸出該掺雜基板，其中該介電結構的不同部份具有不一致的厚度；以及一電阻形成於該介電結構上，該電阻具有多個纏繞部件，且該些纏繞部件之間具有實質上相同的間距；其中該電阻電性耦接至該電晶體的該閘極。
  7. 如申請專利範圍第6項所述之半導體裝置，其中當電壓施加至該閘極時，該電阻設置以操作於反轉模式中。
  8. 如申請專利範圍第6項所述之半導體裝置，其中：該p型掺雜部份包含p型主體延伸部，其電性耦接至該源極並橫向凸出於該介電結構下；以及該n型掺雜部份包含n型井區，其位於該介電結構與該p型主 體延伸部之間。
  9. 如申請專利範圍第6項所述之半導體裝置，其中該電阻並聯地電性耦接至該電晶體之該汲極與該閘極。
  10. 一種半導體裝置的形成方法，包括：形成一漂移區於一基板中，其中該漂移區包含不同導電型態的多個掺雜區；形成一介電隔離結構於該漂移區上；形成一電晶體的一閘極於該介電隔離結構上；形成一電阻裝置於該介電隔離結構上，其中該電阻裝置包含多個纏繞部件；以及形成一源極與一汲極於該基板中，其中該源極與該汲極之間隔有該漂移區與該介電隔離結構，其中該電阻裝置與該閘極位於該源極與該汲極之間，以及該電阻裝置與該閘極係電性耦接。
  11. 如申請專利範圍第10項所述之半導體裝置的形成方法，更包括形成一內連線結構於該基板上，使該電阻裝置並聯地電性耦接至該電晶體，或電性浮置。
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US10297661B2 (en) * 2017-06-30 2019-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. High voltage resistor device
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US10262938B2 (en) * 2017-08-31 2019-04-16 Vanguard International Semiconductor Corporation Semiconductor structure having conductive layer overlapping field oxide
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US11296075B2 (en) * 2018-08-31 2022-04-05 Texas Instruments Incorporated High reliability polysilicon components
US11349025B2 (en) * 2018-10-31 2022-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-channel device to improve transistor speed
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