TW201613021A - Board processing apparatus and board processing method - Google Patents

Board processing apparatus and board processing method

Info

Publication number
TW201613021A
TW201613021A TW104131751A TW104131751A TW201613021A TW 201613021 A TW201613021 A TW 201613021A TW 104131751 A TW104131751 A TW 104131751A TW 104131751 A TW104131751 A TW 104131751A TW 201613021 A TW201613021 A TW 201613021A
Authority
TW
Taiwan
Prior art keywords
board processing
board
holder
processing apparatus
processing method
Prior art date
Application number
TW104131751A
Other languages
English (en)
Inventor
Kenichi Kobayashi
Toshio Yokoyama
Original Assignee
Ebara Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ebara Corp filed Critical Ebara Corp
Publication of TW201613021A publication Critical patent/TW201613021A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Weting (AREA)
  • Cleaning By Liquid Or Steam (AREA)
TW104131751A 2014-09-26 2015-09-25 Board processing apparatus and board processing method TW201613021A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014196353A JP2016072256A (ja) 2014-09-26 2014-09-26 基板処理装置及び基板処理方法

Publications (1)

Publication Number Publication Date
TW201613021A true TW201613021A (en) 2016-04-01

Family

ID=55581202

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104131751A TW201613021A (en) 2014-09-26 2015-09-25 Board processing apparatus and board processing method

Country Status (3)

Country Link
JP (1) JP2016072256A (zh)
TW (1) TW201613021A (zh)
WO (1) WO2016047679A1 (zh)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01261296A (ja) * 1988-04-08 1989-10-18 Rohm Co Ltd 分子線エピタキシー装置
JPH0791645B2 (ja) * 1989-04-28 1995-10-04 株式会社日立製作所 薄膜形成装置
JPH0729880A (ja) * 1993-06-25 1995-01-31 Nec Corp 半導体製造装置
JP2002222806A (ja) * 2001-01-26 2002-08-09 Ebara Corp 基板処理装置
JP5582895B2 (ja) * 2010-07-09 2014-09-03 キヤノンアネルバ株式会社 基板ホルダーストッカ装置及び基板処理装置並びに該基板ホルダーストッカ装置を用いた基板ホルダー移動方法

Also Published As

Publication number Publication date
JP2016072256A (ja) 2016-05-09
WO2016047679A1 (ja) 2016-03-31

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