TW201535731A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW201535731A
TW201535731A TW103121984A TW103121984A TW201535731A TW 201535731 A TW201535731 A TW 201535731A TW 103121984 A TW103121984 A TW 103121984A TW 103121984 A TW103121984 A TW 103121984A TW 201535731 A TW201535731 A TW 201535731A
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Yasuhiro Isobe
Naoharu Sugiyama
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Toshiba Kk
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Abstract

本發明提供一種具有累積有壓縮應力之GaN之半導體裝置。 實施形態之半導體裝置包含GaN層、及AlXGa1-XN(0≦X<1)層。上述AlXGa1-XN(0≦X<1)層係與上述GaN層接觸地設於上述GaN層之上，且含有C。

Description

半導體裝置 [相關申請案]
本申請案享受以日本專利申請2014-50877號(申請日：2014年3月13日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
本發明之實施形態係關於一種半導體裝置。
於Si基板上成長GaN之情形時，存在如下問題，因Si和GaN之晶格常數差(約17%)與熱膨脹係數差(約56%)而於GaN層產生拉伸應力，難以獲得優質之無龜裂之GaN系氮化物半導體磊晶膜。
本發明提供一種包含累積有壓縮應力之GaN之半導體裝置。
實施形態之半導體裝置包含GaN層、及AlXGa1-XN(0≦X<1)層。上述AlXGa1-XN(0≦X<1)層係與上述GaN層相接而設於上述GaN層之上，且含有C。
10‧‧‧緩衝層
11‧‧‧u型GaN層
12‧‧‧AlN層
13‧‧‧C-AlxGa1-XN層
14‧‧‧i型GaN層
15‧‧‧AlxGaN層
30e‧‧‧二維電子系
31‧‧‧源極(汲極)電極
32‧‧‧汲極(源極)電極
33‧‧‧閘極電極
101‧‧‧AlN層
102AlyGa1-yN層
S‧‧‧基板
圖1係表示實施形態1之半導體裝置之概略剖面圖之一例。
圖2係模式性表示參考例中之壓縮應力之累積之圖之一例。
圖3係模式性表示圖1所示之半導體裝置中之壓縮應力之累積的圖之一例。
圖4係表示圖1所示之半導體裝置之一變化例之概略剖面圖之一 例。
圖5係表示實施形態2之半導體裝置之概略構造之概略剖面圖之一例。
以下，一面參照圖式一面說明若干實施形態。於圖式中，對相同部分標註相同參照編號，並適當地省略其重複說明。
隨附圖式分別係用於幫助發明說明及其理解者，請留意各圖中之形狀、尺寸、比等有與實際裝置不同之部分。若為本領域技術人員便可參照以下說明及公知技術適當地對該等不同點進行設計變更。
本案說明書中，「積層」除了包含彼此接觸地重疊之情形以外，還包含中間介插有其他層而重疊之情形。又，所謂「設於…上」，除了包含直接接觸地設置之情形以外，還包含中間介插有其他層而設置之情形。進而，「主面」係指基板或層之表面中形成有元件之表面。
(1)實施形態1
圖1係表示實施形態1之半導體裝置之概略剖面圖之一例。本實施形態之半導體裝置包含基板S、緩衝層10、u型GaN層11、C-AlxGa1-XN層13、i型GaN層14、及AlxGa1-xN層15。
基板S於本實施形態中係包含(111)面之Si基板。Si基板之膜厚為例如500μm以上且2mm以內，更理想為700μm以上且1.5mm以內。又，基板S亦可為於主面積層有薄層Si之基體。於使用積層有薄層Si之基體之情形時，薄層Si之膜厚為例如5nm以上且500nm以內。
緩衝層10包含於基板S之上接觸基板S而設置之AlN層101、及於AlN層101之上接觸AlN層101而設置之AlyGaN1-y層(0<y<1)102。AlN層101為例如50nm以上且500nm以下，較理想為100nm以上且300nm以下。AlyGa1-yN層(0<y<1)102為例如100nm以上且1000nm以下，亦可積層複數之含有Al組成之層。於積層複數之含有Al組成之層之情 形時，例如為AlyGa1-yN層(0.3<y<0.7)與AlzGa1-zN層(0.05<z<0.3)依序積層而成之積層構造亦可。然而，根據半導體裝置之總膜厚或半導體裝置之設計，亦可不存在AlyGa1-yN層(0<y<1)102。
C-AlxGa1-xN層13係設於緩衝層10之上且含有C之AlxGa1-xN層(0≦X<1)。C-AlxGa1-xN層13為例如500nm以上且10μm以下之層厚，例如C之濃度為5×1017cm-3以上且5×1019cm-3以下。作為更理想之實施例，例如於AlxGa1-xN層(X=0)中，添加之碳[C]濃度為1×1018cm-3以上且1×1019cm-3以下，膜厚為0.5μm以上且5μm以下，例如於AlxGa1-xN層(X=0.03)中，添加之碳[C]濃度為8×1017cm-3以上且5×1018cm-3以下，膜厚為0.5μm以上且3μm以下。於本實施形態中，C-AlxGa1-xN層13係對應於例如第1 AlxGa1-xN層。
未特意添加雜質而形成之Undoped-GaN(以下僅稱為「u-GaN」)層11係以介插於緩衝層10與C-AlxGa1-xN層13之間之方式設置。u型GaN層11係未特意添加雜質而形成之GaN層，其膜厚為例如100nm以上且2μm以下，更理想為200nm以上且1μm以下。u型GaN層11之雜質濃度為碳[C]、氧[O]及矽[Si]均未達5×1017cm-3。緩衝層10中所含之錯位密度為1×1010cm-2以上，但藉由介插u型GaN層11，可獲得積層於上層之氮化物半導體層之穿透錯位密度未達2×109cm-2之氮化物半導體晶體。又，於本半導體裝置中未介插u型GaN層11之情形時，積層於上層之氮化物半導體層之穿透錯位密度為2×109cm-2以上。
i型GaN層14係設於C-AlxGa1-xN層13之上。i型GaN層14較理想為相比u型GaN層11而雜質濃度更低。i型GaN層14之膜厚為例如0.5μm以上且3μm以下，i型GaN層14之雜質濃度為碳[C]、氧[O]及矽[Si]均未達3×1017cm-3。
AlxGa1-xN層15係形成於i型GaN層14之上，且包含非摻雜或n型之AlxGa1-xN(0<X≦1)。於i型GaN層14內之i型GaN層14與AlxGaN層15之 界面附近產生二維電子系30e。藉此，i型GaN層14作為通道而發揮功能。於本實施形態中，AlxGa1-xN層15係對應於例如第2 AlxGa1-xN層。
於本實施形態中，實現藉由於基板S上以較厚膜厚積層氮化物半導體層而使用GaN-on-Si磊晶基板之具有1000V以上之耐壓的半導體裝置。
如上述般對於提高耐壓而言重要的是於GaN中添加C或Al，但由於原子半徑較小之雜質之C添加量之增加或Al混晶比之增加，GaN之晶格常數變小，影響到積層於緩衝層10上之氮化物半導體層之壓縮應力之累積。即，如圖2之參考例所示，未進行充分之壓縮應力之累積，難以獲得無龜裂、優質、且積層膜厚較厚之GaN系氮化物半導體磊晶膜。相反，若不於GaN中添加C或Al，則存在雖容易進行壓縮應力之累積，但難以獲得充分之耐壓之問題。
因此，於本實施形態中，係於緩衝層10與C-AlxGa1-xN層13之間設置非摻雜之GaN層11作為應力控制層。
圖3模式性地表示本實施形態之半導體裝置中之壓縮應力之累積。如圖3所示，與雜質濃度高之C-AlxGa1-xN層13相比，雜質濃度低且高品質之u型GaN層11於成長中能夠累積之壓縮應力較大，因此，即便積層之後之C-AlxGa1-xN層13及i型GaN層14亦可維持氮化物半導體層中累積有充分之壓縮應力之狀態直至結晶成長結束。若C-AlxGa1-xN層13於成長中累積之壓縮應力之大小設為SC1，將u型GaN層11於成長中累積之壓縮應力之大小設為SC2，則相同積層膜厚下SC2>SC1之關係成立。即，可藉由u型GaN層11控制晶圓之應力，即便於使氮化物半導體層以厚膜成長之情形時，亦可於完成階段具有良好之表面平坦性，從而可獲得上方為凸形狀且無龜裂之晶圓，進而可實現使用GaN-on-Si磊晶基板之具有1000V以上之耐壓的半導體裝置。
又，除了因C-AlxGa1-xN層13自身之原子半徑較小所致之壓縮應 力累積低下之影響以外，於緩衝層10上未介插u型GaN層11之情形時之C-AlxGa1-xN層13由於含有高濃度之雜質而難以成為表面平坦之膜。即，根據氮化物半導體之成長模式容易變成三維之情況，對於壓縮應力之累積效果少，故而有效的是介插u型GaN層11。
藉由介插u型GaN層11，氮化物半導體層容易成為表面平坦之膜，即可加快壓縮應力之累積，故而C-AlxGa1-xN層13中並不限於包含原子半徑較小之雜質，亦可以例如1×1018cm-2左右包含Fe、Mg、Zn等過渡金屬。
圖4係表示圖1所示之半導體裝置之一變化例之概略剖面圖之一例。藉由與圖1之對比而可明瞭，本變化例之半導體裝置進而包含以介插於u型GaN層11與C-AlxGa1-xN層13之間之方式設置之AlN層12。由於介插有AlN層12，藉由有意地製造晶格常數差而使得C-AlxGa1-xN層13容易累積壓縮應力。藉此，可使u型GaN層11更薄。於本例中，u型GaN層11之膜厚為例如50nm以上且300nm以下，AlN層12之膜厚為例如5nm以上且50nm以下。
(2)實施形態2
圖5係表示實施形態2之半導體裝置之概略構造之概略剖面圖之一例。
藉由與圖1之對比而可明瞭，本實施形態之半導體裝置藉由於圖1所示之半導體裝置中進而設置電極31至33，而實現橫型HEMT(High Electron Mobility Transistor，高電子移動性電晶體)。
具體而言，圖5所示之半導體裝置除了包含將基板S、緩衝層10、u型GaN層11、C-AlxGa1-xN層13、i型GaN層14、及AlxGaN層15依序積層而成之半導體裝置之外，並進而包含源極(或汲極)電極31、汲極(或源極)電極32及閘極電極33。緩衝層10包含AlN層101、及於AlN層101之上接觸AlN層101而設之AlGaN層102。
源極(或汲極)電極31、及汲極(或源極)電極32係形成為於障壁層15之上相互隔開而設，且分別與障壁層15歐姆接合。於本實施形態中，源極(或汲極)電極31、及汲極(或源極)電極32分別對應於例如第1及第2電極。
閘極電極33係以夾於源極(或汲極)電極31、及汲極(或源極)電極32之間之方式形成於障壁層15之上。於本實施形態中，閘極電極33係對應於例如控制電極。
於圖5中，雖未圖示，但亦可於該等電極31~33間之障壁層15上之區域成膜絕緣膜。又，亦可於閘極電極33與障壁層15之間介插閘極絕緣膜(未圖示)。
根據上述至少一個實施形態之半導體裝置，由於包含具有累積有壓縮應力之GaN之半導體裝置，故而可提供高耐壓且牢固之半導體裝置。
雖對本發明之若干實施形態進行了說明，但該等實施形態係作為例子而提示者，並不試圖限定發明之範圍。
例如，於上述實施形態中，使用AlN層101及AlGaN層10之積層體作為緩衝層10，但亦可使用超晶格構造之多層膜來代替緩衝層10。此處，所謂「超晶格構造」係指例如將膜厚5nm之AlN層與膜厚20nm之GaN層設為1對，並交替積層20對而成之構造。
該等實施形態可以其他各種形態實施，於不脫離發明之主旨之範圍內，可進行各種省略、置換、變更。該等實施形態及其變化包含於發明之範圍及主旨內，同樣地，包含於申請專利範圍所記載之發明及其均等範圍內。
10‧‧‧緩衝層
11‧‧‧u型GaN層
13‧‧‧C-AlxGa1-XN層
14‧‧‧i型GaN層
15‧‧‧AlxGaN層
30e‧‧‧二維電子系
101‧‧‧AlN層
102‧‧‧AlyGa1-yN層
S‧‧‧基板

Claims (7)

  1. 一種半導體裝置，其包含：GaN層；及AlxGa1-XN(0≦X<1)層，其與上述GaN層接觸而設於上述GaN層之上，且含有C。
  2. 一種半導體裝置，其包含：GaN層；AlN層，其與上述GaN層接觸地設於上述GaN層之上；及AlxGa1-XN(0≦X<1)層，其與上述AlN層接觸而設於上述AlN層之上。
  3. 如請求項1或2之半導體裝置，其中上述GaN層含有濃度未達5×1017cm-3之C、O及Si之至少任一者。
  4. 如請求項1或2之半導體裝置，其中上述GaN層之錯位密度未達2×109cm-2。
  5. 如請求項1或2之半導體裝置，其中上述GaN層之膜厚為100nm以上且2μm以下。
  6. 如請求項1或2之半導體裝置，其中上述AlxGa1-XN層之膜厚為500nm以上且10μm以下。
  7. 一種半導體裝置，其包含：含有AlN之緩衝層；GaN層，其與上述緩衝層接觸地設於上述緩衝層之上；第1 AlxGa1-xN(0≦X<1)層，其設於上述GaN層之上，且含有C；i型GaN層，其設於上述第1 AlxGa1-XN層(0≦X<1)之上；第2 AlxGa1-xN層，其設於上述i型GaN層之上； 第1及第2電極，其於上述第2 AlxGa1-xN層之上相互隔開而設；及控制電極，其於上述第2 AlxGa1-xN層之上設於上述第1及第2電極之間。
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