TW201533885A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

Info

Publication number
TW201533885A
TW201533885A TW103122402A TW103122402A TW201533885A TW 201533885 A TW201533885 A TW 201533885A TW 103122402 A TW103122402 A TW 103122402A TW 103122402 A TW103122402 A TW 103122402A TW 201533885 A TW201533885 A TW 201533885A
Authority
TW
Taiwan
Prior art keywords
terminal
semiconductor
semiconductor device
package
present
Prior art date
Application number
TW103122402A
Other languages
English (en)
Inventor
Nobutaka Matsuoka
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of TW201533885A publication Critical patent/TW201533885A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/112—Mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/117—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H01L2224/37012—Cross-sectional shape
    • H01L2224/37013—Cross-sectional shape being non uniform along the connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/40139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/40227—Connecting the strap to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/404—Connecting portions
    • H01L2224/40475—Connecting portions connected to auxiliary connecting means on the bonding areas
    • H01L2224/40499—Material of the auxiliary connecting means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73263—Layer and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

本發明實現安裝有複數個半導體裝置之半導體系統之小型化。 實施形態之半導體裝置具備：半導體晶片；封裝體，其包圍半導體晶片；第1電極端子，其係於封裝體之上側，上端部與封裝體之上表面齊平或自上表面突出而露出，且於封裝體之下側，下端部與封裝體之下表面齊平或自下表面突出而露出；及第2電極端子，其係於封裝體之上側，上端部與上表面齊平或自上表面突出而露出，且於封裝體之下側，下端部與下表面齊平或自下表面突出而露出。

Description

半導體裝置 [相關申請案]
本申請案享有以日本專利申請案2014-37564號(申請日：2014年2月27日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
本發明之實施形態係關於一種半導體裝置。
例如，將封裝體內收容有電晶體、二極體等半導體晶片之半導體裝置安裝於印刷基板上，藉此構築半導體系統。為了實現半導體系統之小型化，較理想為縮小半導體裝置間之配線所需之區域。
本發明實現安裝有複數個半導體裝置之半導體系統之小型化。
實施形態之半導體裝置包括：半導體晶片；封裝體，其包圍半導體晶片；第1電極端子，其係於封裝體之上側，上端部與封裝體之上表面齊平或自上表面突出而露出，且於封裝體之下側，下端部與封裝體之下表面齊平或自下表面突出而露出；第2電極端子，其係於封裝體之上側，上端部與上表面齊平或自上表面突出而露出，且於封裝體之下側，下端部與下表面齊平或自下表面突出而露出。
10‧‧‧半導體晶片
12‧‧‧封裝體
14‧‧‧射極端子(第1電極端子)
16‧‧‧集極端子(第2電極端子)
18‧‧‧閘極端子(第3電極端子)
20‧‧‧散熱板
22‧‧‧樹脂外殼
24‧‧‧樹脂蓋
26‧‧‧絕緣基板
26a‧‧‧導電層
26b‧‧‧絕緣層
26c‧‧‧導電層
30‧‧‧接合線
32‧‧‧矽膠
36‧‧‧支持基板
38‧‧‧塑模樹脂
44‧‧‧陽極端子(第1電極端子)
46‧‧‧陰極端子(第2電極端子)
50‧‧‧第1半導體晶片
52‧‧‧第2半導體晶片
54‧‧‧第1電極端子
56‧‧‧第2電極端子
58‧‧‧閘極端子
60‧‧‧框架
62‧‧‧凹部
64‧‧‧凸部
66‧‧‧螺孔
68‧‧‧螺栓
70‧‧‧貫通孔
72‧‧‧印刷基板
72a‧‧‧下部印刷基板
72b‧‧‧上部印刷基板
73‧‧‧印刷配線
74‧‧‧支持棒
76‧‧‧半導體模組
78‧‧‧焊料
80‧‧‧蝶形螺釘
82‧‧‧電容器
圖1(a)、(b)係第1實施形態之半導體裝置之模式圖。
圖2係第1實施形態之半導體裝置之模式立體圖。
圖3(a)、(b)係第1實施形態之半導體裝置之作用之說明圖。
圖4(a)、(b)係第1實施形態之半導體裝置之作用之說明圖。
圖5係第1實施形態之變化例之半導體裝置之模式立體圖。
圖6(a)、(b)係第2實施形態之半導體裝置之模式圖。
圖7(a)、(b)係第3實施形態之半導體裝置之模式圖。
圖8(a)、(b)係第4實施形態之半導體裝置之模式圖。
圖9(a)、(b)係第5實施形態之半導體裝置之模式圖。
圖10(a)、(b)係第6實施形態之半導體裝置之模式圖。
圖11(a)、(b)係第7實施形態之半導體裝置之模式圖。
圖12係第8實施形態之半導體裝置之模式圖。
圖13係第9實施形態之半導體裝置之模式圖。
圖14係第10實施形態之半導體裝置之模式圖。
圖15係第11實施形態之半導體裝置之模式立體圖。
圖16(a)、(b)係具有第11實施形態之半導體裝置之半導體系統之模式立體圖。
圖17係具有第11實施形態之半導體裝置之半導體系統之模式立體圖。
圖18係第12實施形態之半導體裝置之模式立體圖。
圖19係具有第13實施形態之半導體裝置之半導體系統之模式立體圖。
圖20係具有第13實施形態之半導體裝置之半導體系統之變化例的模式立體圖。
圖21(a)、(b)係第14實施形態之半導體系統之模式圖。
圖22(a)、(b)係第14實施形態之半導體系統之模式圖。
以下，一面參照圖式一面對本發明之實施形態進行說明。再 者，於以下說明中，對相同構件等標註相同符號，且關於已說明過一次之構件等適當省略其說明。
本說明書中，所謂「半導體晶片」，意指將半導體作為材料之主動元件。例如二極體、電晶體、閘流體等。
又，於本說明書中，所謂「封裝體」，意指設於半導體晶片之周圍且保護半導體晶片免受來自物理衝擊、濕氣等之傷害之構件。例如，可考慮應用樹脂、矽膠、陶瓷等材料或其等之組合。
又，於本說明書中，「上側」、「下側」、「上表面」、「下表面」、「上方」、「下方」等用語未必意指相對於重力方向之上下之用語，而是用以規定構件等之相對位置關係之用語。
又，於本說明書中，所謂「半導體系統」，意指將複數個經封裝體化之半導體裝置安裝於印刷基板等電路基板或半導體模組而構成之半導體電路。於半導體系統中，除了安裝半導體裝置外，亦可安裝電阻或電容器等被動零件。
(第1實施形態)
本實施形態之半導體裝置包括：半導體晶片；封裝體，其包圍半導體晶片；第1電極端子，其係於封裝體之上側，上端部與封裝體之上表面齊平或自上表面突出而露出，且於封裝體之下側，下端部與封裝體之下表面齊平或自下表面突出而露出；第2電極端子，其係於封裝體之上側，上端部與封裝體之上表面齊平或自上表面突出而露出，且於封裝體之下側，下端部與封裝體之下表面齊平或自下表面突出而露出。
圖1係本實施形態之半導體裝置之模式圖。圖1(a)係模式剖面圖，圖1(b)係模式俯視圖。圖1(b)係去除半導體晶片上方之樹脂蓋及覆蓋半導體晶片之保護材之狀態之圖。圖2係表示本實施形態之半導體裝置之外觀之模式立體圖。
本實施形態之半導體裝置例如為3端子之立式IGBT(Insulated Gate Bipolar Transistor，絕緣閘雙極性電晶體)。本實施形態之半導體裝置包括半導體晶片10、封裝體12、射極端子(第1電極端子)14、集極端子(第2電極端子)16、及閘極端子(第3電極端子)18。
半導體晶片10係例如將矽作為材料。於半導體晶片10上形成有立式IGBT。
本實施形態之封裝體12包圍半導體晶片10，且包括半導體晶片10下方之散熱板20、半導體晶片10側方之樹脂外殼22、及半導體晶片10上方之樹脂蓋24。散熱板20例如為金屬，例如為銅或鋁。
於散熱板20上設有絕緣基板26。於絕緣基板26上載置有半導體晶片10。絕緣基板26成為導電層26a、絕緣層26b、導電層26c之3層構造。導電層26a、導電層26c例如為銅等金屬。又，絕緣層26b例如為氧化鋁或氮化鋁等陶瓷。
射極端子14之上端部係於封裝體12之上側與封裝體12之上表面齊平或自上表面突出而露出。於本實施形態之情形時，係自樹脂蓋24之上表面突出而露出。
射極端子14之下端部係於封裝體12之下側與封裝體12之下表面齊平或自下表面突出而露出。於本實施形態之情形時，係自散熱板20之下表面突出而露出。
射極端子14係藉由接合線30而連接於半導體晶片10之射極電極。接合線30為金屬，例如為金或鋁。
集極端子16之上端部係於封裝體12之上側與封裝體12之上表面齊平或自上表面突出而露出。於本實施形態之情形時，係自樹脂蓋24之上表面突出而露出。
集極端子16之下端部係於封裝體12之下側與封裝體12之下表面齊平或自下表面突出而露出。於本實施形態之情形時，係自散熱板20 之下表面突出而露出。
集極端子16係藉由接合線30並經由導電層26c而連接於半導體晶片10之集極。接合線30為金屬，例如為金或鋁。
閘極端子18之上端部係於封裝體12之上側與封裝體12之上表面齊平或自上表面突出而露出。於本實施形態之情形時，係自樹脂蓋24之上表面突出而露出。
閘極端子18之下端部係於封裝體12之下側與封裝體12之下表面齊平或自下表面突出而露出。於本實施形態之情形時，係自散熱板20之下表面突出而露出。
閘極端子18係藉由接合線30而連接於半導體晶片10之閘極電極。接合線30為金屬，例如為金或鋁。
半導體晶片10於封裝體12內，例如係由矽膠32密封。矽膠32係半導體晶片10之保護材。矽膠32與樹脂蓋24之間為中空。
本實施形態之半導體裝置係射極端子14及集極端子16亦露出於封裝體12之側方。射極端子14及集極端子16係與封裝體12之側面齊平或自側面突出而露出。
以下，對本實施形態之半導體裝置之作用及效果進行說明。
圖3係本實施形態之半導體裝置之作用之說明圖。圖3(a)係表示將複數個本實施形態之半導體裝置進行組合之構成之圖，圖3(b)係圖3(a)之電路圖。
於圖3(a)中，將本實施形態之IGBT沿縱向積層3段。各個IGBT係射極端子14、集極端子16、閘極端子18自封裝體12之上表面及下表面突出。因此，僅藉由使上下之IGBT之端子接觸而確保各者之端子之電性導通。如圖3(b)所示，藉由將IGBT沿縱向積層3段而實現將3個IGBT並列連接之電路。
圖4係對本實施形態之半導體裝置之作用進行說明之圖。圖4(a) 係表示將複數個本實施形態之半導體裝置進行組合之構成之圖，圖4(b)係圖4(a)之電路圖。
於圖4(a)中，將本實施形態之IGBT沿橫向排列2個。各個IGBT係射極端子14、集極端子16自封裝體12之側面突出。因此，僅藉由使左右之IGBT之端子接觸，確保各者之端子之電性導通。如圖4(b)所示，藉由將IGBT沿橫向排列2個而實現將2個IGBT串聯連接之電路。
本實施形態之IGBT係藉由各端子自封裝體12之上表面、下表面、側面突出，而於將複數個IGBT沿縱向積層或沿橫向排列時，可無需附加性之連接配線而連接各IGBT之端子之間。又，如圖3或圖4所示，可配置立體性之IGBT。因此，例如於構築將複數個IGBT安裝於印刷基板之半導體系統時，可實現半導體系統之尺寸之小型化。
又，藉由適當選擇沿縱向積層或沿橫向排列之情形時之IGBT之個數，可容易地將額定電流或額定電壓等設定為所需之值。因此，半導體系統之設計之自由度提高。
再者，各IGBT之端子之間之電性導通可僅藉由壓接各端子之間而實現。又，於各端子之間亦可設置焊料層等接著層。
(變化例)
圖5係表示本實施形態之變化例之半導體裝置之外觀的模式立體圖。端子之形狀與實施形態之半導體裝置不同。
本變化例之IGBT之射極端子14、集極端子16、閘極端子18顯示為圓柱形狀。藉由本變化例之半導體裝置，與實施形態同樣，亦可實現半導體系統之尺寸之小型化。
(第2實施形態)
本實施形態之半導體裝置中半導體晶片之保護材為塑模樹脂之情況及不包括散熱板，除此以外與第1實施形態相同。因此，關於與第1實施形態重複之內容，省略一部分記載。
圖6係本實施形態之半導體裝置之模式圖。圖6(a)係模式剖面圖，圖6(b)係模式俯視圖。圖6(b)係去除半導體晶片上方之保護材之狀態之圖。
本實施形態之封裝體12包圍半導體晶片10。封裝體12具備半導體晶片10下方之支持基板36、及成為半導體晶片10之保護材之塑模樹脂38。支持基板36為絕緣體，例如為樹脂或陶瓷。
於支持基板36上設置有絕緣基板26。於絕緣基板26上載置有半導體晶片10。絕緣基板26成為導電層26a、絕緣層26b、導電層26c之3層構造。導電層26a、導電層26c例如為銅。又，絕緣層26b例如為氧化鋁或氮化鋁等陶瓷。
本實施形態之IGBT係與第1實施形態相同，各端子自封裝體12之上表面、下表面、側面突出。因此，例如，於構築將複數個IGBT安裝於印刷基板之半導體系統時，可實現半導體系統之尺寸之小型化。
又，與第1實施形態相比，零件件數亦較少，且變得可容易地製造。
(第3實施形態)
於本實施形態之半導體裝置，半導體晶片並非藉由接合線而是藉由接著層直接連接於各端子或導電層，除此以外係與第2實施形態相同。因此，關於與第2實施形態重複之內容，省略一部分記載。
圖7係本實施形態之半導體裝置之模式圖。圖7(a)係模式剖面圖，圖7(b)係模式俯視圖。圖7(b)係去除半導體晶片上方之保護材之狀態之圖。
於本實施形態之IGBT中，射極端子14係藉由未圖示之接著層而與半導體晶片10之射極電極直接連接。又，集極端子16係藉由未圖示之接著層而與導電層26c直接連接。導電層26c係與半導體晶片10之集極連接。又，閘極端子18係藉由未圖示之接著層而與半導體晶片10之 閘極電極直接連接。接著層具備導電性，例如為焊料。
本實施形態之IGBT係與第1實施形態相同，各端子自封裝體12之上表面、下表面、側面突出。因此，例如，於構築將複數個IGBT安裝於印刷基板之半導體系統時，可實現半導體系統之尺寸之小型化。
又，與第2實施形態相比，藉由將各端子與半導體晶片10之電極直接連接，使電流流經之區域之剖面積增加。因此，連接部之電阻降低，IGBT之動作特性提高。
(第4實施形態)
本實施形態之半導體裝置為2端子之半導體裝置，除此以外與第3實施形態相同。因此，關於與第3實施形態重複之內容，省略一部分記載。
圖8係本實施形態之半導體裝置之模式圖。圖8(a)係模式剖面圖，圖8(b)係模式俯視圖。圖8(b)係去除半導體晶片上方之保護材之狀態之圖。
本實施形態之半導體裝置例如為2端子之立式二極體。本實施形態之半導體裝置包括半導體晶片10、封裝體12、陽極端子(第1電極端子)44、陰極端子(第2電極端子)46。
於本實施形態之IGBT中，陽極端子44係藉由未圖示之接著層而與半導體晶片10之陽極電極直接連接。又，陰極端子46係藉由未圖示之接著層而與導電層26c直接連接。導電層26c係連接於半導體晶片10之陰極電極。接著層具備導電性，例如為焊料。
本實施形態之二極體係與第3實施形態同樣，各端子自封裝體12之上表面、下表面、側面突出。因此，例如，於構築將複數個二極體安裝於印刷基板之半導體系統時，可實現半導體系統之尺寸之小型化。
(第5實施形態)
本實施形態之半導體裝置具備2個半導體晶片，除此以外與第3實施形態相同。因此，關於與第3實施形態重複之內容，省略一部分記載。
圖9係本實施形態之半導體裝置之模式圖。圖9(a)係模式剖面圖，圖9(b)係模式俯視圖。圖9(b)去除半導體晶片上方之保護材之狀態之圖。
本實施形態之半導體裝置例如包括第1半導體晶片50與第2半導體晶片52。第1半導體晶片50例如為3端子之立式IGBT。第2半導體晶片52例如為作為回流二極體發揮功能之2端子之立式二極體。
本實施形態之半導體裝置包括第1電極端子54、第2電極端子56、閘極端子58。第1電極端子54係第1半導體晶片50之射極端子與第2半導體晶片52之陽極端子之共用端子。第2電極端子56係第1半導體晶片50之集極端子與第2半導體晶片52之陰極端子之共用端子。
於本實施形態之半導體裝置中，第1電極端子54係藉由未圖示之接著層而直接連接於第1半導體晶片50之射極電極與第2半導體晶片52之陽極電極。又，第2電極端子46係藉由未圖示之接著層而直接連接於導電層26c。導電層26c係連接於第1半導體晶片50之集極與第2半導體晶片52之陰極電極。接著層具備導電性，例如為焊料。
本實施形態之二極體係與第3實施形態同樣，各端子自封裝體12之上表面、下表面、側面突出。因此，例如，於構築將包括IGBT與二極體之2個半導體晶片之複數個半導體裝置安裝於印刷基板之半導體系統時，可實現半導體系統之尺寸之小型化。
再者，2個半導體晶片並非限定於IGBT與二極體之組合。例如亦可為MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor，金屬氧化物半導體場效應電晶體)與二極體等其他組合。又，亦可包括大於等於3個半導體晶片。
(第6實施形態)
本實施形態之半導體裝置中半導體晶片並非形成於絕緣基板上而是形成於與電極端子一體化之框架上，除此以外基本上與第2實施形態相同。因此，關於與第2實施形態重複之內容，省略一部分記載。
圖10係本實施形態之半導體裝置之模式圖。圖10(a)為模式剖面圖，圖10(b)係模式俯視圖。圖10(b)係去除半導體晶片上方之保護材之狀態之圖。
於本實施形態之IGBT中，半導體晶片10係載置於與集極端子16一體化之金屬製之框架60上。半導體晶片10與框架60係由未圖示之接著層、例如焊料而接著。
本實施形態之IGBT係與第2實施形態相同，各端子自封裝體12之上表面、下表面、側面突出。因此，例如，於構築將複數個IGBT安裝於印刷基板之半導體系統時，可實現半導體系統之尺寸之小型化。
又，與第2實施形態相比，零件件數亦較少，且變得可容易地製造。
(第7實施形態)
本實施形態之半導體裝置具備散熱板代替支持基板，除此以外與第2實施形態相同。因此，關於與第2實施形態重複之內容，省略一部分記載。
圖11係本實施形態之半導體裝置之模式圖。圖11(a)為模式剖面圖，圖11(b)係模式俯視圖。圖11(b)係去除半導體晶片上方之保護材之狀態之圖。
本實施形態之IGBT具備散熱板20。於散熱板20上設有絕緣基板26。於絕緣基板26上載置有半導體晶片10。
本實施形態之IGBT係與第2實施形態相同，各端子自封裝體12之 上表面、下表面、側面突出。因此，例如，於構築將複數個IGBT安裝於印刷基板之半導體系統時，可實現半導體系統之尺寸之小型化。
又，藉由具備散熱板20而散熱性提高。因此，實現具備穩定之動作與較高可靠性之半導體裝置。
(第8實施形態)
本實施形態之半導體裝置中，於第1電極端子之上端或下端之一方設有凹部、於另一方設有凸部，且於第2電極端子之上端或下端之一方設有凹部、於另一方設有凸部，除此以外與第1實施形態之變化例相同。因此，關於與第1實施形態及其變化例重複之內容，省略一部分記載。
圖12係本實施形態之半導體裝置之模式圖。表示將本實施形態之半導體裝置沿縱向積層2個之構成。
本實施形態之半導體裝置例如為3端子之立式IGBT。本實施形態之半導體裝置包括內包半導體晶片之封裝體12、射極端子(第1電極端子)14、集極端子(第2電極端子)16、及閘極端子(第3電極端子)18。
於射極端子14、集極端子16、閘極端子18之各者之上端設有凹部62，且於下端設有凸部64。於將IGBT沿上下積層之情形時，係以上側之IGBT之各端子之凸部64與下側之IGBT之各端子之凹部62嵌合之方式而構成。
本實施形態之IGBT係與第1實施形態相同，各端子自封裝體12之上表面、下表面、側面突出。因此，例如，於構築將複數個IGBT安裝於印刷基板之半導體系統時，可實現半導體系統之尺寸之小型化。
進而，藉由於各端子設置嵌合構造，可防止將複數個IGBT沿縱向積層之情形時之對準偏差。因此，可實現製造容易且特性穩定之半導體系統。
(第9實施形態)
本實施形態之半導體裝置中於第1或第2電極端子之一側面設有凹部且於另一側面設有凸部，除此以外與第1實施形態相同。因此，關於與第1實施形態重複之內容，省略一部分記載。
圖13係本實施形態之半導體裝置之模式圖。表示將本實施形態之半導體裝置沿橫向配置2個之構成。
本實施形態之半導體裝置例如為3端子之立式IGBT。本實施形態之半導體裝置包括內包半導體晶片之封裝體12、射極端子(第1電極端子)14、集極端子(第2電極端子)16、及閘極端子(第3電極端子)18。
於集極端子16之側面設有凹部62，且於射極端子14之側面設有凸部64。於將IGBT沿橫向排列配置之情形時，以一個IGBT之射極端子14之凸部64與另一個之集極端子16之凹部62嵌合之方式而構成。
本實施形態之IGBT係與第1實施形態相同，各端子自封裝體12之上表面、下表面、側面突出。因此，例如，於構築將複數個IGBT安裝於印刷基板之半導體系統時，可實現半導體系統之尺寸之小型化。
進而，藉由於端子之側面設置嵌合構造，可防止將複數個IGBT沿橫向排列配置之情形時之對準偏差。因此，可實現製造容易且特性穩定之半導體系統。
(第10實施形態)
本實施形態之半導體裝置中於第1電極端子之上端及下端設有螺孔且於第2電極端子之上端及下端設有螺孔，除此以外與第1實施形態之變化例相同。因此，關於與第1實施形態及其變化例重複之內容，省略一部分記載。
圖14係本實施形態之半導體裝置之模式圖。表示將本實施形態之半導體裝置沿縱向積層2個之構成。
本實施形態之半導體裝置例如為3端子之立式IGBT。本實施形態之半導體裝置包括：內包半導體晶片之封裝體12、射極端子(第1電極 端子)14、集極端子(第2電極端子)16、及閘極端子(第3電極端子)18。
於射極端子14、集極端子16、閘極端子18之各者之上端及下端設有螺孔66。於將IGBT沿上下積層之情形時，於上側之IGBT之各端子之螺孔66與下側之IGBT之各端子之螺孔66之間沿上下插入具備螺紋之螺栓68。藉由該螺栓68固定上下之IGBT。
本實施形態之IGBT係與第1實施形態相同，各端子自封裝體12之上表面、下表面、側面突出。因此，例如，於構築將複數個IGBT安裝於印刷基板之半導體系統之情形時，可實現半導體系統之尺寸之小型化。
進而，於各端子設有螺孔66，且可藉由螺栓68固定上下之IGBT。因此，可防止將複數個IGBT沿縱向積層之情形之對準偏差及分離。因此，可實現製造容易且特性穩定之半導體系統。
(第11實施形態)
本實施形態之半導體裝置中第1及第2電極端子具有自電極端子之上端貫通至下端之貫通孔，除此以外基本與第4實施形態相同。因此，關於與第4實施形態重複之內容，省略一部分記載。
圖15係本實施形態之半導體裝置之模式立體圖。本實施形態之半導體裝置例如為2端子之立式二極體。本實施形態之半導體裝置包括內包半導體晶片之封裝體12、陽極端子(第1電極端子)44、及陰極端子(第2電極端子)46。
陽極端子44及陰極端子46為圓柱形狀。而且，於陽極端子44設有自端子之上端貫通至下端之貫通孔70。又，於陰極端子46亦設有自端子之上端貫通至下端之貫通孔70。再者，陽極端子44及陰極端子46除圓柱形狀以外，例如亦可為角柱形狀。
圖16係具有本實施形態之半導體裝置之半導體系統之模式立體圖。圖16(a)係具備印刷配線73之印刷基板之構成圖，圖16(b)係於印 刷基板安裝本實施形態之半導體裝置之情形時之構成圖。
如圖16(a)所示，於印刷基板72設有用以安裝本實施形態之半導體裝置之支持棒74。支持棒74例如與印刷配線73電性導通。而且，如圖16(b)所示，藉由使支持棒74通過各二極體之端子之貫通孔70而將3個二極體沿縱向積層。根據該構成，3個二極體並列安裝於印刷基板上。
支持棒74例如為金屬。又，支持棒74與二極體之各端子例如係藉由焊料而連接。
圖17係具有本實施形態之半導體裝置之半導體系統之模式立體圖。圖17係於印刷基板安裝本實施形態之半導體裝置之情形時之構成圖。
如圖17所示，藉由使支持棒74通過各二極體之端子之貫通孔70，而將3個二極體沿縱向及橫向配置。根據該構成，3個二極體串聯安裝於印刷基板72上。
本實施形態之二極體藉由各端子自封裝體12之上表面、下表面突出，而於將複數個二極體沿縱向積層時，可無需附加性之連接配線而連接各二極體之端子之間。又，如圖16、圖17所示，可配置立體性之二極體。因此，例如，於構築將複數個二極體安裝於印刷基板之半導體系統時，可實現半導體系統之尺寸之小型化。
又，藉由適當選擇沿縱向或橫向配置之情形時之二極體之個數，可容易地將額定值設為所期望之值。因此，半導體系統之設計之自由度提高。
進而，藉由於各端子設置貫通孔70，可防止將複數個二極體沿縱向積層之情形時之對準偏差。因此，可實現製造容易且特性穩定之半導體系統。
(第12實施形態)
本實施形態之半導體裝置並非2端子而是3端子，除此以外係與第11實施形態之變化例相同。因此，關於與第11實施形態重複之內容，省略一部分記載。
圖18係本實施形態之半導體裝置之模式立體圖。本實施形態之半導體裝置例如為3端子之立式IGBT。本實施形態之半導體裝置包括內包半導體晶片之封裝體12、射極端子(第1電極端子)14、集極端子(第2電極端子)16、及閘極端子(第3電極端子)18。
射極端子14、集極端子16、及閘極端子18為圓柱形狀。而且，於射極端子14、集極端子16及閘極端子18設有自端子之上端貫通至下端之貫通孔70。再者，射極端子14、集極端子16、及閘極端子18除圓柱形狀以外，例如亦可為角柱形狀。
本實施形態之IGBT藉由各端子自封裝體12之上表面、下表面突出，而於將複數個IGBT沿縱向積層時，無需附加性之連接配線便可連接各IGBT之端子之間。又，可配置立體性之IGBT。因此，例如，於構築將複數個IGBT安裝於印刷基板之半導體系統時，可實現半導體系統之尺寸之小型化。
又，藉由適當選擇沿縱向或橫向配置之情形時之IGBT之個數，可容易地將額定值設為所期望之值。因此，半導體系統之設計之自由度提高。
進而，藉由於各端子設置貫通孔70，可防止將複數個IGBT沿縱向積層之情形時之對準偏差。因此，可實現製造容易且特性穩定之半導體系統。
(第13實施形態)
本實施形態之半導體裝置係連接於半導體模組，除此以外基本上與第11實施形態相同。因此，關於與第11實施形態重複之內容，省略一部分記載。
圖19係具有本實施形態之半導體裝置之半導體系統之模式立體圖。如圖19所示，半導體模組76之端子為棒狀之支持棒74。半導體模組76例如為大功率用之模組。又，例如，半導體模組76之信號端子成為支持棒74。於印刷基板72設有用以安裝本實施形態之半導體裝置之支持棒74。
如圖19所示，藉由使支持棒74通過各二極體之端子之貫通孔70，將2個二極體沿縱向積層。根據該構成，2個二極體與半導體模組76之信號端子並列地安裝。
支持棒74例如為金屬。又，支持棒74與二極體之各端子例如係藉由焊料78而連接。
再者，於圖19中，例示將印刷基板72介置於半導體模組76與各二極體之間之情形。亦可設定為省略印刷基板72之構成。
本實施形態之二極體藉由各端子自封裝體12之上表面、下表面突出，而於將複數個二極體沿縱向積層時，可無需附加性之連接配線而連接各二極體之端子之間。又，如圖19所示，可配置立體性之二極體。因此，例如，於構築將複數個二極體安裝於半導體模組上之半導體系統時，可實現半導體系統之尺寸之小型化。
又，藉由適當選擇沿縱向或橫向配置之情形時之二極體之個數，可容易將額定值設為所期望之值。因此，半導體系統之設計之自由度提高。
進而，藉由於各端子設置貫通孔70，可防止將複數個二極體沿縱向積層之情形時之對準偏差。因此，可實現製造容易且特性穩定之半導體系統。
(變化例)
圖20係具有本實施形態之半導體裝置之半導體系統之變化例的模式立體圖。各二極體並非使用焊接而是使用蝶形螺釘80固定於支持 棒74。根據本變化例，可將二極體容易地固定於半導體模組76。
(第14實施形態)
本實施形態係於印刷基板上安裝有二極體或IGBT且包括轉換器電路或反相器電路之半導體系統。關於二極體或IGBT，係與第11或第12實施形態相同。因此，關於與第11或第12實施形態重複之內容，省略一部分記載。
圖21係本實施形態之半導體系統之模式圖。圖21(a)係本實施形態之半導體系統之模式立體圖。圖21(b)係圖21(a)之電路圖。本實施形態之半導體系統包括轉換器電路。
本實施形態之半導體系統於印刷基板72上沿縱向及橫向配置有4個二極體(半導體裝置)，且由支持棒74固定。本實施形態之各二極體包括內包半導體晶片之封裝體12、陽極端子(第1電極端子)44、及陰極端子(第2電極端子)46。
藉由將各二極體如圖21(a)所示般配置，實現包括圖21(b)所示之轉換器電路之半導體系統。
圖22係本實施形態之半導體系統之模式圖。圖22(a)係本實施形態之半導體系統之模式立體圖。圖22(b)係圖22(a)之電路圖。本實施形態之半導體系統包括轉換器電路及反相器電路。
本實施形態之半導體系統包括下部印刷基板72a、使用上部印刷基板72b而被立體性地安裝之4個二極體、4個IGBT及1個電容器82。本實施形態之各二極體包括陽極端子44、及陰極端子46。本實施形態之各IGBT包括：射極端子14、集極端子16、及閘極端子18。
藉由將各二極體、IGBT、電容器82如圖22(a)所示般配置，實現包括圖22(b)所示之轉換器電路及反相器電路之半導體系統。
本實施形態之半導體系統未使用附加性之連接配線而立體性地配置二極體或IGBT等半導體裝置。因此，可實現半導體系統之尺寸 之小型化。
又，藉由適當選擇沿縱向或橫向配置之情形時之半導體裝置之個數，可容易地將額定值設為所期望之值。因此，半導體系統之設計之自由度提高。
進而，藉由於各端子設置貫通孔70，可防止將複數個二極體或IGBT沿縱向積層之情形時之對準偏差。因此，可實現製造容易且特性穩定之半導體系統。
於實施形態中，作為半導體裝置，以立式IGBT、立式二極體為例進行了說明，但本發明亦可應用於包括除立式IGBT或二極體以外之裝置、例如源極端子、汲極端子、閘極端子之立式MOSFET(Metal Oxide Semiconductor Field Effect Transistor)、立式閘流體等。又，本發明亦可應用於僅於半導體裝置之上部或者下部任一面具備電極之橫型裝置。
於實施形態中，以使用矽作為半導體之裝置為例進行了說明。然而，並非限定於矽，亦可應用SiC等碳化物半導體或GaN系半導體等氮化物半導體。
對本發明之若干實施形態進行了說明，但該等實施形態係作為例子而提出者，並非意圖限定發明之範圍。該等新穎之實施形態可以其他各種形態實施，且可於不脫離發明之主旨之範圍內進行各種省略、置換、變更。例如，可將一實施形態之構成要素置換或變更為其他實施形態之構成要素。該等實施形態及其變化包含於發明之範圍及主旨，且包含於申請專利範圍所記載之發明及其均等範圍。
10‧‧‧半導體晶片
12‧‧‧封裝體
14‧‧‧射極端子(第1電極端子)
16‧‧‧集極端子(第2電極端子)
18‧‧‧閘極端子(第3電極端子)
20‧‧‧散熱板
22‧‧‧樹脂外殼
24‧‧‧樹脂蓋
26‧‧‧絕緣基板
26a‧‧‧導電層
26b‧‧‧絕緣層
26c‧‧‧導電層
30‧‧‧接合線
32‧‧‧矽膠

Claims (5)

  1. 一種半導體裝置，其特徵在於包括：半導體晶片；封裝體，其包圍上述半導體晶片；第1電極端子，其係於上述封裝體之上側，上端部與上述封裝體之上表面齊平或自上述上表面突出而露出，且於上述封裝體之下側，下端部與上述封裝體之下表面齊平或自上述下表面突出而露出；及第2電極端子，其係於上述封裝體之上側，上端部與上述上表面齊平或自上述上表面突出而露出，且於上述封裝體之下側，下端部與上述下表面齊平或自上述下表面突出而露出。
  2. 如請求項1之半導體裝置，其中上述第1及上述第2電極端子係於上述封裝體之側方，與上述封裝體之側面齊平或自側面突出而露出。
  3. 如請求項1或2之半導體裝置，其中於上述第1電極端子之上端或下端之一方設有凹部，於另一方設有凸部；且於上述第2電極端子之上端或下端之一方設有凹部，於另一方設有凸部。
  4. 如請求項1或2之半導體裝置，其中上述第1及第2電極端子包含自電極端子之上端貫通至下端之貫通孔。
  5. 如請求項1或2之半導體裝置，其中上述封裝體為樹脂。
TW103122402A 2014-02-27 2014-06-27 半導體裝置 TW201533885A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014037564A JP2015162609A (ja) 2014-02-27 2014-02-27 半導体装置

Publications (1)

Publication Number Publication Date
TW201533885A true TW201533885A (zh) 2015-09-01

Family

ID=53882967

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103122402A TW201533885A (zh) 2014-02-27 2014-06-27 半導體裝置

Country Status (5)

Country Link
US (1) US20150243638A1 (zh)
JP (1) JP2015162609A (zh)
KR (1) KR20150101893A (zh)
CN (1) CN104882423A (zh)
TW (1) TW201533885A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI745530B (zh) * 2017-05-26 2021-11-11 日商瑞薩電子股份有限公司 電子裝置

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6584333B2 (ja) * 2016-01-28 2019-10-02 三菱電機株式会社 パワーモジュール
FR3060243B1 (fr) * 2016-12-12 2019-08-23 Institut Vedecom Module de commutation de puissance, convertisseur integrant celui-ci et procede de fabrication
JP6522243B1 (ja) * 2017-07-14 2019-05-29 新電元工業株式会社 電子モジュール
US11508808B2 (en) * 2018-10-11 2022-11-22 Actron Technology Corporation Rectifier device, rectifier, generator device, and powertrain for vehicle
CN109545597B (zh) * 2018-11-28 2020-10-23 广东电网有限责任公司电力科学研究院 一种固态开关的散热装置
CN111048475B (zh) * 2019-11-29 2021-09-21 广东芯聚能半导体有限公司 绝缘栅双极型晶体管封装模块

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2875139B2 (ja) * 1993-07-15 1999-03-24 株式会社東芝 半導体装置の製造方法
KR100242393B1 (ko) * 1996-11-22 2000-02-01 김영환 반도체 패키지 및 제조방법
US5857858A (en) * 1996-12-23 1999-01-12 General Electric Company Demountable and repairable low pitch interconnect for stacked multichip modules
KR100253363B1 (ko) * 1997-12-02 2000-04-15 김영환 반도체 패키지용 기판과 그 기판을 이용한 랜드 그리드 어레이반도체 패키지 및 그들의 제조 방법
US6114221A (en) * 1998-03-16 2000-09-05 International Business Machines Corporation Method and apparatus for interconnecting multiple circuit chips
US6667544B1 (en) * 2000-06-30 2003-12-23 Amkor Technology, Inc. Stackable package having clips for fastening package and tool for opening clips
US6750545B1 (en) * 2003-02-28 2004-06-15 Amkor Technology, Inc. Semiconductor package capable of die stacking
KR100833589B1 (ko) * 2006-03-29 2008-05-30 주식회사 하이닉스반도체 스택 패키지
JP5358077B2 (ja) * 2007-09-28 2013-12-04 スパンション エルエルシー 半導体装置及びその製造方法
JP2010055310A (ja) * 2008-08-27 2010-03-11 Toshiba Corp 電子機器
WO2010147201A1 (ja) * 2009-06-19 2010-12-23 株式会社安川電機 電力変換装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI745530B (zh) * 2017-05-26 2021-11-11 日商瑞薩電子股份有限公司 電子裝置

Also Published As

Publication number Publication date
US20150243638A1 (en) 2015-08-27
KR20150101893A (ko) 2015-09-04
JP2015162609A (ja) 2015-09-07
CN104882423A (zh) 2015-09-02

Similar Documents

Publication Publication Date Title
TW201533885A (zh) 半導體裝置
US9761567B2 (en) Power semiconductor module and composite module
US9287231B2 (en) Package structure with direct bond copper substrate
US9275930B2 (en) Circuit device and method of manufacturing the same
US9899328B2 (en) Power semiconductor module
US10262948B2 (en) Semiconductor module having outflow prevention external terminals
JP6083109B2 (ja) 半導体装置
US8324025B2 (en) Power semiconductor device packaging
US9852968B2 (en) Semiconductor device including a sealing region
CN104659012A (zh) 具有在再分配结构和装配结构之间的电子芯片的电子部件
JP6439389B2 (ja) 半導体装置
EP3157053A1 (en) Power module
TW201631717A (zh) 功率轉換電路的封裝模組及其製造方法
KR20130115456A (ko) 반도체 패키지, 반도체 모듈, 및 그 실장 구조
US20140054751A1 (en) Semiconductor device
US20150145123A1 (en) Power semiconductor module and method of manufacturing the same
KR101706825B1 (ko) 반도체 패키지
US8823153B2 (en) Semiconductor package
CN109473410B (zh) 具有顶侧冷却部的smd封装
JPWO2015016017A1 (ja) 半導体装置
US8754462B2 (en) Semiconductor device
US10685909B2 (en) Power package having multiple mold compounds
JP6248803B2 (ja) パワー半導体モジュール
US9099451B2 (en) Power module package and method of manufacturing the same
JP6417758B2 (ja) 半導体装置