TW201523106A - 顯示面板及應用其之顯示裝置 - Google Patents

顯示面板及應用其之顯示裝置 Download PDF

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TW201523106A
TW201523106A TW102144112A TW102144112A TW201523106A TW 201523106 A TW201523106 A TW 201523106A TW 102144112 A TW102144112 A TW 102144112A TW 102144112 A TW102144112 A TW 102144112A TW 201523106 A TW201523106 A TW 201523106A
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layer
electrode layer
substrate
display panel
insulating layer
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TWI518430B (zh
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Ming-Chieh Chang
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Innolux Corp
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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    • H01—ELECTRIC ELEMENTS
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract

一種顯示面板，包括薄膜電晶體基板、顯示介質及對向基板。對向基板相對於薄膜電晶體基板。顯示介質位於薄膜電晶體基板及對向基板間。薄膜電晶體基板包括基板、第一電極層、畫素電極層、第一絕緣層、第二電極層、第二絕緣層、通道層及保護層。第一電極層與畫素電極層位於基板上。第一絕緣層覆蓋第一電極層及畫素電極層。第二電極層位於第一絕緣層上。第二絕緣層覆蓋第二電極層。第一通孔及第二通孔貫穿第一、第二絕緣層，以暴露第一電極層。通道層位於第二絕緣層上，並填入第一通孔及第二通孔，以與第一電極層電性連接。保護層覆蓋通道層。

Description

顯示面板及應用其之顯示裝置
本發明是有關於一種顯示面板及應用其之顯示裝置，且特別是有關於一種頂端通道的氧化物半導體顯示面板，及應用其之顯示裝置。
常用於顯示面板中的薄膜電晶體(Thin-Film Transistor,TFT)通道材料包括多晶矽(polysilicon)與非晶矽(amorphous silicon,a-Si)兩種，多晶矽TFT元件的載子遷移率(mobility)較高(>100Vs/cm2)，但生產成本也偏高；非晶矽TFT元件雖然生產成本較低，但載子遷移率也較低(<1Vs/cm2)。
如非晶氧化銦鎵鋅(amorphous indium gallium zinc oxide,a-IGZO)之類的氧化物半導體(oxide semiconductor)由於其優異的電性條件，例如介於10-20Vs/cm2的載子遷移率、臨界電壓變異與元件開關能力等，可作為電子通道層之用，而逐漸引起相當多的注意。然而，例如下閘極式(bottom-gate)的後通道蝕刻(back channel etch,BCE)、通道保護(channel protect,CHP)，或上 閘極式(top-gate)的低溫多晶矽(low temperature polysilicon,LTPS)等現有的TFT設計，在形成通道層還需進行化學氣相沉積成膜(chemical vapor deposition,CVD)或電漿(plasma)之類額外的製程，容易在氧化物半導體中造成氧缺陷，使啟動電壓Vgh漂移或次臨界擺幅(subthreshold swing,SS)過大，影響氧化物半導體電子通道之特性。
本發明係有關於一種顯示面板及其顯示裝置，具有良好的電子通道層特性。
根據本發明之一方面，提出一種顯示面板。顯示面板包括薄膜電晶體基板、顯示介質及對向基板。對向基板係相對於薄膜電晶體基板設置。顯示介質位於薄膜電晶體基板及對向基板之間。薄膜電晶體基板包括基板、第一電極層、畫素電極層、第一絕緣層、第二電極層、第二絕緣層、通道層及保護層。第一電極層與畫素電極層位於基板之上。第一絕緣層覆蓋第一電極層及畫素電極層。第二電極層位於第一絕緣層之上。第二絕緣層覆蓋第二電極層。第一通孔及第二通孔係貫穿第一絕緣層及第二絕緣層，以暴露第一電極層。通道層位於第二絕緣層層之上，並填入第一通孔及第二通孔，以與第一電極層電性連接。保護層覆蓋通道層。
根據本發明之另一方面，提出一種顯示裝置，顯示 裝置包括顯示面板及控制電路。控制電路與顯示面板耦接。顯示面板包括薄膜電晶體基板、顯示介質及對向基板。對向基板係相對於薄膜電晶體基板設置。顯示介質位於薄膜電晶體基板及對向基板之間。薄膜電晶體基板包括基板、第一電極層、畫素電極層、第一絕緣層、第二電極層、第二絕緣層、通道層及保護層。第一電極層與畫素電極層位於基板之上。第一絕緣層覆蓋第一電極層及畫素電極層。第二電極層位於第一絕緣層之上。第二絕緣層覆蓋第二電極層。第二絕緣層具有第一通孔及第二通孔。第一通孔及第二通孔係貫穿第一絕緣層及第二絕緣層，以暴露第一電極層。通道層位於第二絕緣層之上，並填入第一通孔及第二通孔，以與第一電極層電性連接。保護層覆蓋通道層。
藉由將通道層設計在薄膜電晶體基板的頂部，本發明之顯示面板及顯示裝置能避免通道層的半導體特性遭到破壞，進而維持良好的電性，提昇顯示品質。
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式，作詳細說明如下：
1‧‧‧顯示裝置
2‧‧‧顯示面板
10、11‧‧‧薄膜電晶體基板
20‧‧‧顯示介質
30‧‧‧對向基板
40‧‧‧背光模組
50‧‧‧控制電路
100‧‧‧基板
110‧‧‧第一源/汲極
120‧‧‧第二源/汲極
121‧‧‧開口
130‧‧‧畫素電極層
140‧‧‧第一絕緣層
150‧‧‧第二電極層
160‧‧‧第二絕緣層
161‧‧‧第一通孔
162‧‧‧第二通孔
170‧‧‧通道層
180‧‧‧保護層
第1圖繪示依照本發明一實施例之顯示裝置的示意圖。
第2A圖繪示依照本發明一實施例之薄膜電晶體基板的剖面圖，第2B圖繪示第2A圖之薄膜電晶體基板的上視圖。
第3A-8B圖繪示第2A圖之薄膜電晶體基板的一製造實施例，其中標示為A的圖式為剖面圖，標示於B的圖式為上視圖。
第9A圖繪示依照本發明另一實施例之薄膜電晶體基板的剖面圖，第9B圖繪示第9A圖之薄膜電晶體基板的上視圖。
請參照第1圖，其繪示依據本發明一實施例之顯示裝置。顯示裝置1可以是一般的平面顯示器，由顯示面板2及控制電路50組成，控制電路50耦接於顯示面板2，用以傳送顯示訊號及調整電流輸出。顯示面板1有很多種類，可根據成像需不需要外加光源而分為自發光式(例如OLED)或背光式(例如LCD)。當選用背光式的顯示面板1時，顯示裝置1可包括背光模組40，用以提供所需光源。
顯示面板2為顯示裝置1的主要元件，包括了薄膜電晶體基板10、顯示介質20以及對向基板30。薄膜電晶體基板20耦接於控制電路50，根據接受到的顯示訊號調整各個畫素。顯示介質20根據顯示面板的種類而改變。舉例來說，當顯示面板2為LCD面板時，顯示介質便為液晶層；當顯示面板2為OLED面板時，顯示面板便為有機發光層。對向基板30可為一般的透明基板或彩色濾光片基板(color filter)，其與薄膜電晶體基板10相對，並將顯示介質20夾於兩者之間。一實施例中，當對向基板30為透明基板時，彩色濾光片係可形成在薄膜電晶體基板10上，或顯示介質20可具有彩色顯示的功能。
第2A圖繪示一實施例之薄膜電晶體基板的剖面圖，第2B圖繪示第2A圖之薄膜電晶體基板的上視圖，其中第2A圖為第2B圖之薄 膜電晶體基板10於虛線A-A’處的剖面。為使圖式更加清楚，第2B圖的上視圖中忽略部份元件。薄膜電晶體基板10包括基板100、第一電極層(第一源/汲極110及第二源/汲極120)、畫素電極層130、第一絕緣層140、閘極層150、第二絕緣層160、通道層170及保護層180。
以下用第3A圖至第8B圖說明第2A圖之薄膜電晶體基板的一製造實施例，其中標號為A的圖式為剖面圖，標號為B的圖式為上視圖。
請參照第3A圖及3B圖，提供基板100(第3B圖中忽略)，並在基板100上形成圖案化的第一電極層。注意第3A圖之剖面係沿著第3B圖之L形虛線A-A’裁切而成，並非一直線。第一電極層至少包括第一源/汲極110及第二源/汲極120，兩者係互相分開，此處第一源/汲極110係圍出一C字形的凹口，而第二源/汲極120便設置在此凹口中，也就是第一源/汲極110繞過第二源/汲極120。第一源/汲極110在之後可作為資料線使用。第一電極層的材料可包括Al、Al-Nd、MoW、Cu、Cr、Au、Mo、MoAlMo，但並不限制於此，一般用於半導體裝置電極的材料皆可使用。
接著，如第4A圖及第4B圖所示，形成畫素電極層130。畫素電極層130與第一電極層的第二源/汲極120相連接。此外，定義開口121貫穿畫素電極層130，以暴露源極120。畫素電極層為透明電極，材料可包括ITO、IZO或ZnO，但並不限制於此。
再來，如第5A圖及第5B圖所示，沉積第一絕緣層140(第5B圖中忽略)覆蓋薄膜電晶體基板(覆蓋基板110、第一源/汲極110、第二源/汲極120及畫素電極層130)，再形成第二電極層150。第二電極層150可 為一閘極線，設置在第一絕緣層上，以及第一源/汲極110與第二源/汲極120之間(第5A圖)。第二電極層150的延伸方向與第一源/汲極110的延伸方向垂直(第5B圖)，其跨越第一源/汲極110與第二源/汲極120的部份可作為薄膜電晶體元件的閘極使用。也就是說，第5A圖中的第二電極層150作為閘極，與第一源/汲極110、第二源/汲極120三者構成一薄膜電晶體元件。此薄膜電晶體元件位於第一源/汲極(資料線)110與第二電極層150(閘極線)的交叉處，如第5B圖的虛線框T所示。因此，本實施例之薄膜電晶體基板便不需要規劃另外的空間設置薄膜電晶體元件，可以增加組合後顯示面板的開口率。第一絕緣層140的材料可為SiNX、SiOXNX、AlOX或SiOX；第二電極層150的材料可與第一電極層(第一源/汲極110、第二源/汲極120)相同，包括Al、Al-Nd、MoW、Cu、Cr、Au、Mo、MoAlMo，亦可與第一電極層不同，本發明並不對其材料限制。
然後，如第6A圖及第6B圖所示，形成第二絕緣層160(於第6B圖中忽略)覆蓋薄膜電晶體基板(覆蓋被動層140及第二電極層150)，第二絕緣層160主要作為閘極介電層(gate insulator,GI)之用，使閘極線(第二電極層150)與其他結構絕緣。再以光阻(未繪示)作為遮罩定義第一通孔161與第二通孔162，兩者皆貫穿了第一絕緣層140及第二絕緣層160。第一通孔161暴露第二源/汲極120，第二通孔162則暴露第一源/汲極110。特別注意的是，第一通孔161的直徑係小於第4A圖中貫穿畫素電極層130的開口121，且第一通孔161位於開口121之內(第6B圖)，以避免第一通孔161暴露畫素電極層130。第二絕緣層160的材料可為SiNX、SiOXNX、AlOX、SiOX或TiOX，但並不限定於此。
再來，如第7A圖及第7B圖所示，形成通道層170。通道層170位於第二絕緣層160之上，或者說位於第一源/汲極110、第二源/汲極120以及部份之第二電極層150(作為閘極)構成的薄膜電晶體元件之上。通道層170填入第一通孔161及第二通孔162內，以分別與第二源/汲極120與第一源/汲極110電性連接，但通道層170與畫素電極層130及作為閘極的第二電極層150電性絕緣。如第7B圖所示，通道層170的延伸方向與第二電極層150(閘極線)的延伸方向垂直，而與第一源/汲極110的延伸方向(資料線之方向)平行。通道層170位於資料線110與閘極線150交叉處。藉由將通道層170設計成與第二電極層150(閘極線)垂直，本實施例的通道層只須與源極、汲極對位，而不需與閘極對位，可減少對位步驟，降低製程所需的精度。通道層的材料例如是氧化物半導體材料，如a-IGZO或a-IZO。
最後，如第8A圖及第8B圖所示，於通道層170上形成保護層180(Over coating layer,第8B圖中忽略)，即完成薄膜電晶體基板10。保護層180的厚度可依製程需求而調整，也可進行化學機械研磨(chemical mechanic polishing,CMP)之類的打磨使表面平整，如第2A圖所示。保護層180的製作步驟單純，例如僅需對其有機材料進行預烘烤(pre-bake)以及熱烘烤(hot bake)，預烘烤的溫度介於70-80℃，而熱烘烤的溫度約為100℃。相較於化學氣相沉積CVD或電漿製程高於300℃的工作溫度，保護層180的形成不但不會破壞通道層170的電性，更可防止通道層170裸露。
第9A圖及第9B圖繪示依照本發明另一實施例之薄膜電晶體基板的剖面圖及上視圖。薄膜電晶體基板11與第2A及2B圖所述之薄膜 電晶體基板10類似，差異在於畫素電極層130的位置，其餘結構不再贅述。
於第9A圖中，畫素電極層130係先於第一電極層(第一源/汲極110及第二源/汲極120)形成，位於第二源/汲極120與基板100之間，並與第二源/汲極120電性連接。由於畫素電極層130位於第二源/汲極120之下，因此不需要在畫素電極層130上設計通孔(例如第4A及4B圖的開口121)，也不需要如第6A及6B圖的步驟一般將開口121與第一通孔161對位。如此一來，可更加降低製程所需的對位精度，降低成本且使良率提昇。
上述實施例之顯示面板與顯示裝置，其薄膜電晶體基板之通道層設計在架構的頂端，更以保護層加以隔離，能夠避免通道層的元件特性遭到破壞，維持良好的電性。此外，對比於習知將通道層與閘極線設計為平行的後通道蝕刻BCE、通道保護CHP等架構，實施例中將通道層與閘極線設計成相互垂直，能夠降低製程所需的對位精度，減少成本且增加良率。更甚者，實施例之薄膜電晶體元件設置在薄膜電晶體基板之資料線與閘極線的交叉處，不須額外花費空間安置，能提昇顯示面板整體之開口率。
綜上所述，雖然本發明已以實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧薄膜電晶體基板
100‧‧‧基板
110‧‧‧第一源/汲極
120‧‧‧第二源/汲極
130‧‧‧畫素電極層
140‧‧‧第一絕緣層
150‧‧‧第二電極層
160‧‧‧第二絕緣層
170‧‧‧通道層
180‧‧‧保護層

Claims (10)

  1. 一種顯示面板，包括：一薄膜電晶體基板，包括：一基板；一第一電極層，位於該基板之上；一畫素電極層，位於該基板之上；一第一絕緣層，覆蓋該第一電極層及該畫素電極；一第二電極層，位於該第一絕緣層之上；一第二絕緣層，覆蓋該第二電極層，具有一第一通孔及一第二通孔，其中該第一通孔及該第二通孔係貫穿該第一絕緣層及該第二絕緣層，以暴露該第一電極層；一通道層，位於該第二絕緣層之上，並填入該第一通孔及該第二通孔，以與該第一電極層電性連接；及一保護層，覆蓋該通道層；一對向基板，係相對於該薄膜電晶體基板設置；以及一顯示介質，位於該薄膜電晶體基板及該對向基板之間。
  2. 如申請專利範圍第1項所述之顯示面板，其中該第一電極層包括一第一源/汲極及一第二源/汲極，該第一源/汲極為一資料線的一部分，且該第二電極層為一閘極線。
  3. 如申請專利範圍第2項所述之顯示面板，其中該畫素電極層係與該第二源/汲極電性連接，且位於該第二源/汲極及該第一絕緣層之間。
  4. 如申請專利範圍第3項所述之顯示面板，其中該畫素電極層係具有一開口暴露該第二源/汲極。
  5. 如申請專利範圍第4項所述之顯示面板，其中該第一通孔位於該開口之內。
  6. 如申請專利範圍第2項所述之顯示面板，其中該畫素電極層係與該第二源/汲極電性連接，且位於該基板及該第二源/汲極之間。
  7. 如申請專利範圍第2項所述之顯示面板，其中該通道層係位於該資料線與該閘極線交叉處。
  8. 如申請專利範圍第1項所述之顯示面板，其中該通道層的材質為氧化銦鎵鋅(Indium gallium zinc oxide,IGZO)或銦鋅氧化物(indium zinc oxide,IZO)。
  9. 如申請專利範圍第1項所述之顯示面板，其中該顯示介質為一液晶層或一有機發光層。
  10. 一種顯示裝置，包括：一顯示面板，包括：一薄膜電晶體基板，包括：一基板；一第一電極層，位於該基板之上；一畫素電極層，位於該基板之上；一第一絕緣層，覆蓋該第一電極層及該畫素電極層；一第二電極層，位於該第一絕緣層之上； 一第二絕緣層，覆蓋該第二電極層，具有一第一通孔及一第二通孔，其中該第一通孔及該第二通孔係貫穿該第一絕緣層及該第二絕緣層，以暴露該第一電極層；一通道層，位於該第二絕緣層之上，並填入該第一通孔及該第二通孔，以與該第一電極層電性連接；及一保護層，覆蓋該通道層；一對向基板，係相對於該薄膜電晶體基板設置；及一顯示介質，位於該薄膜電晶體基板及該對向基板之間；以及一控制電路，耦接於該顯示面板。
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