TW201515190A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TW201515190A
TW201515190A TW103124390A TW103124390A TW201515190A TW 201515190 A TW201515190 A TW 201515190A TW 103124390 A TW103124390 A TW 103124390A TW 103124390 A TW103124390 A TW 103124390A TW 201515190 A TW201515190 A TW 201515190A
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Taiwan
Prior art keywords
electrode
intermediate structure
semiconductor device
semiconductor
wafer
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TW103124390A
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English (en)
Chinese (zh)
Inventor
Yoshiaki Sugizaki
Akihiro Kojima
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Toshiba Kk
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Publication of TW201515190A publication Critical patent/TW201515190A/zh

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    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Devices (AREA)
  • Led Device Packages (AREA)
  • Die Bonding (AREA)
  • Gyroscopes (AREA)
TW103124390A 2013-07-16 2014-07-16 半導體裝置及其製造方法 TW201515190A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013147867 2013-07-16
JP2014052787A JP2015038957A (ja) 2013-07-16 2014-03-14 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
TW201515190A true TW201515190A (zh) 2015-04-16

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TW103124390A TW201515190A (zh) 2013-07-16 2014-07-16 半導體裝置及其製造方法

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JP (1) JP2015038957A (ja)
TW (1) TW201515190A (ja)
WO (1) WO2015008870A2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI773587B (zh) * 2021-11-17 2022-08-01 友達光電股份有限公司 燈板

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9892944B2 (en) * 2016-06-23 2018-02-13 Sharp Kabushiki Kaisha Diodes offering asymmetric stability during fluidic assembly
DE102016115644B4 (de) 2016-08-23 2020-12-24 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung von optoelektronischen Halbleiterbauteilen und optoelektronisches Halbleiterbauteil
JP2018064077A (ja) * 2016-10-14 2018-04-19 株式会社ディスコ デバイスチップ、収容トレイ、及び、デバイスチップの収容方法
KR102385571B1 (ko) 2017-03-31 2022-04-12 삼성전자주식회사 반도체 발광 소자
WO2019132050A1 (ko) * 2017-12-26 2019-07-04 박일우 Led 디스플레이 장치 및 그 제조 방법
JP7429094B2 (ja) * 2018-09-10 2024-02-07 東レエンジニアリング株式会社 実装基板の製造方法および実装基板
CN111370550B (zh) * 2018-12-25 2021-01-22 山东浪潮华光光电子股份有限公司 一种红光led芯片的封装方法
CN110289279B (zh) * 2019-06-04 2021-09-24 上海天马微电子有限公司 一种转移方法、阵列基板、其制作方法及显示装置
US20220310883A1 (en) * 2019-10-31 2022-09-29 Uldtec Co., Ltd. Semiconductor chip integrated device manufacturing method, semiconductor chip integrated device, semiconductor chip integrated device assembly, semiconductor chip ink, and semiconductor chip ink ejection device
JP6842783B1 (ja) * 2019-10-31 2021-03-17 アルディーテック株式会社 マイクロｌｅｄディスプレイの製造方法およびマイクロｌｅｄディスプレイ
KR20200021968A (ko) * 2020-02-11 2020-03-02 엘지전자 주식회사 자가 조립용 칩 트레이 및 반도체 발광소자의 공급 방법
CN113314446B (zh) * 2020-02-27 2023-06-02 上海微电子装备（集团）股份有限公司 芯片转移装置及芯片转移方法
WO2022249431A1 (ja) * 2021-05-28 2022-12-01 東北マイクロテック株式会社 整列トレイ、整列装置、及び整列方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5545291A (en) * 1993-12-17 1996-08-13 The Regents Of The University Of California Method for fabricating self-assembling microstructures
US20070090387A1 (en) * 2004-03-29 2007-04-26 Articulated Technologies, Llc Solid state light sheet and encapsulated bare die semiconductor circuits
US7542301B1 (en) * 2005-06-22 2009-06-02 Alien Technology Corporation Creating recessed regions in a substrate and assemblies having such recessed regions
US7774929B2 (en) * 2006-03-14 2010-08-17 Regents Of The University Of Minnesota Method of self-assembly on a surface
SG140512A1 (en) * 2006-09-04 2008-03-28 Tinggi Tech Private Ltd Electrical current distribution in light emitting devices
WO2009114787A2 (en) * 2008-03-13 2009-09-17 University Of Utah Researsh Foundation High precision, high speed solar cell arrangement to a concentrator lens array and methods of making the same
KR101092063B1 (ko) * 2009-04-28 2011-12-12 엘지이노텍 주식회사 발광소자 패키지 및 그 제조방법
JP2011009298A (ja) * 2009-06-23 2011-01-13 Citizen Electronics Co Ltd 発光ダイオード光源装置
KR101058880B1 (ko) * 2010-05-07 2011-08-25 서울대학교산학협력단 액티브 소자를 구비한 ｌｅｄ 디스플레이 장치 및 그 제조방법
CN104081545A (zh) * 2011-12-01 2014-10-01 夸克星有限责任公司 固态照明装置及其制造方法
EP2605295A3 (en) * 2011-12-13 2015-11-11 LG Innotek Co., Ltd. Ultraviolet light emitting device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI773587B (zh) * 2021-11-17 2022-08-01 友達光電股份有限公司 燈板

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