TW201508850A - 互連結構及其製造方法 - Google Patents

互連結構及其製造方法 Download PDF

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Publication number
TW201508850A
TW201508850A TW103116348A TW103116348A TW201508850A TW 201508850 A TW201508850 A TW 201508850A TW 103116348 A TW103116348 A TW 103116348A TW 103116348 A TW103116348 A TW 103116348A TW 201508850 A TW201508850 A TW 201508850A
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Taiwan
Prior art keywords
conductive
average particle
layer
particle diameter
electrical conductor
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TW103116348A
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English (en)
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TWI560787B (en
Inventor
Meng-Tse Chen
Hsiu-Jen Lin
Chih-Wei Lin
Ming-Da Cheng
Chih-Hang Tung
Chung-Shi Liu
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Taiwan Semiconductor Mfg
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Publication of TW201508850A publication Critical patent/TW201508850A/zh
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Publication of TWI560787B publication Critical patent/TWI560787B/zh

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Abstract

一種傳導互連結構包含一接觸墊，一導電體之一第一端與該接觸墊相連，以及一導電層位於該導電體之一第二端。該導電體具有一縱向垂直於該接觸墊之一表面。該導電體具有一位於橫截面(面A)之平均粒徑(a)，該橫截面之法線垂直於該導電體之縱向。該導電層包含位於面A之一平均粒徑(b)。該導電體及該導電層皆是由相同材料組成，且該平均粒徑(a)大於該平均粒徑(b)。

Description

互連結構及其製造方法
本揭露涉及一種互連結構，更具體地說，涉及一種半導體封裝之傳導互連結構及其製造方法。
三維(three dimensional，3D)堆疊基板佈局是以物理性及電性彼此互連而具有多個堆疊半導體晶片、半導體晶片或半導體晶圓的電子裝置。封裝上封裝(package on package，PoP)是一種特別的積體電路封裝方法，以各種互連結構來垂直組合個別的邏輯元件，在兩個或多個彼此堆疊的封裝元件之間是藉由一連接介面傳遞訊號。此種基板佈局將帶來更高的元件密度，例如行動電話，個人數位助理(personal digital assistants，PDA)及數位相機的應用。
在電學上，PoP之效益係減少相異部件之間互相操作之跡線長度，例如減少控制器及記憶體之間的跡線長度。由於電路之間較短路徑跡線的互連可產生更快的信號傳播並減少雜訊及干擾，此種互連裝置將產生更好的電學性能。
隨著每一世代的演進，由於元件的操作趨向低電壓及高頻，晶片到晶片及/或晶片到封裝的互連介面，其電流位準也隨之增加。球柵陣列(BGA)封裝種廣泛應用的互連焊錫，其最大允許電流密度將受到嚴重的挑戰。
本揭露提供一種傳導互連結構。該傳導互連結構包含有一接觸墊，一導電體之一第一端與該接觸墊相連，一導電體之縱向垂直於該接觸墊之一表面，導電體包含位於一橫截面之一平均粒徑(a)，一橫截面之法線垂直於該導電體之縱向，以及一導電層包含一位於橫截面之平均粒徑(b)，一導電層位於該導體相對於第一端之一第二端，其中該導電體及該導電層為相同材料組成，且該平均粒徑(a)大於該平均粒徑(b)。
本揭露提供一種半導體封裝。該半導體封裝包含有一具有第一表面之一第一半導體封裝，其中一第一接觸墊置放於該第一表面上，一具有一第二表面之一第二半導體封裝，其中一第二接觸墊置放於該第二表面上，以及傳導互連結構電性耦合該第一接觸墊及該第二接觸墊。傳導互連結構包含一第一導電體，其一第一端與該第一接觸墊相連，該第一導電體之一縱向垂直於一第一接觸墊之一表面，以及第一導電體包含一位於橫截面之平均粒徑(a)，一橫截面之法線垂直於第一導電體之一縱向，以及導電層包含一位於橫截面之平均粒徑(b)，一導電層位於第一導體相對於第一端之一第二端，其中該第一導電體及該導電層是由相同材料組成，以及其中該平均粒徑(a)大於該平均粒徑(b)。
本揭露提供一種傳導互連結構之製造方法。該方法包含有(1)置放一蓋層於一半導體封裝上；(2)於該蓋層中形成一通穿孔，(3)依據一第一操作於該通穿孔中填入一第一導電材料，其中該第一操作是配置產生該第一導電材料之一平均粒徑(a)；以及(4)依據一第二操作於該第一導電材料之一外表面上形成一第二導電材料，其中該第二操作是配置產生該第二導電材料之一平均粒徑(b)，其中該平均粒徑(a)大於該平均粒徑(b)，且該第一導電材料及該第二導電材料實質上相 同。
雖然本揭露以數個較佳實施例揭露如上，然其並非用以限定本揭露，任何所屬技術領域中具有通常知識者，在不脫離本揭露之精神和範圍內，當可作任意之更動與潤飾，因此本揭露之保護範圍當視後附之申請專利範圍所界定者為準。
此外，熟知本領域技藝人士將可依照本揭露所揭示之現有或未來所發展之特定程序、機器、製造、物質之組合、功能、方法或步驟達成相同的功能或相同的結果。因此本揭露之保護範圍包含這些程序、機器、製造、物質之組合、功能、方法或步驟，以及每一申請專利範圍所建構出各別的實施例，各申請專利範圍及實施例的結合亦在本揭露之範疇中。
10‧‧‧互連結構
30‧‧‧互連結構
40A‧‧‧互連結構
40B‧‧‧互連結構
50‧‧‧三維堆疊封裝
60‧‧‧三維堆疊封裝佈局
80A‧‧‧互連結構
80B‧‧‧互連結構
90A‧‧‧互連結構
90B‧‧‧互連結構
101‧‧‧導電體
101a‧‧‧第一端
101b‧‧‧第二端
102‧‧‧導電層
103‧‧‧縱向
103'‧‧‧遮罩層
104‧‧‧接觸墊
105‧‧‧側壁
107‧‧‧第一導電材料
107a‧‧‧第一端
107b‧‧‧第二端
108‧‧‧間隙
109‧‧‧第二導電材料
201‧‧‧晶粒
202‧‧‧晶粒
301‧‧‧導電體
301a‧‧‧第一端
301b‧‧‧第二端
302‧‧‧導電層
303‧‧‧縱向
304‧‧‧接觸墊
306‧‧‧晶核層
307‧‧‧載體
308a‧‧‧阻隔層
308b‧‧‧晶核層
401‧‧‧導電體
401a‧‧‧第一端
401b‧‧‧第二端
404‧‧‧接觸墊
405‧‧‧側壁
407‧‧‧載體
503‧‧‧縱向
510‧‧‧塑封料
511‧‧‧單片半導體晶片
512‧‧‧半導體封裝
603‧‧‧縱向
610‧‧‧塑封料
611‧‧‧單片半導體晶片
612‧‧‧半導體封裝
613‧‧‧半導體封裝
620‧‧‧互連結構
807‧‧‧半導體封裝
809‧‧‧半導體封裝
907‧‧‧半導體封裝
909‧‧‧半導體封裝
1075‧‧‧側壁
4021‧‧‧導電層
4023‧‧‧導電層
4061‧‧‧晶核層
4063‧‧‧晶核層
5111‧‧‧導電體
5112‧‧‧導電層
5113‧‧‧接觸墊
6111‧‧‧導電體
6112‧‧‧導電層
6113‧‧‧接觸墊
6121‧‧‧導電體
6121a‧‧‧第三端
6121b‧‧‧第四端
6121‧‧‧導電體
6123‧‧‧接觸墊
6131‧‧‧導電體
6131a‧‧‧第一端
6131b‧‧‧第二端
6132‧‧‧導電層
6132‧‧‧導電層
6133‧‧‧接觸墊
8071‧‧‧導電體
8071a‧‧‧第一端
8071b‧‧‧第二端
8072‧‧‧導電層
8073‧‧‧導電層
8074‧‧‧接觸墊
8075‧‧‧側壁
8091‧‧‧導電體
8091a‧‧‧第三端
8091b‧‧‧第四端
8092‧‧‧導電層
8094‧‧‧接觸墊
8095‧‧‧側壁
9071‧‧‧導電體
9071a‧‧‧第一端
9071b‧‧‧第二端
9072‧‧‧導電層
9073‧‧‧導電層
9074‧‧‧接觸墊
9075‧‧‧側壁
9076‧‧‧晶核層
9091‧‧‧導電體
9091a‧‧‧第三端
9091b‧‧‧第四端
9091‧‧‧導電體
9092‧‧‧導電層
9092‧‧‧導電層
9094‧‧‧接觸墊
9095‧‧‧側壁
9096‧‧‧晶核層
A‧‧‧面
A1‧‧‧寬度
A2‧‧‧寬度
B‧‧‧面
C‧‧‧面
H1‧‧‧高度
H2‧‧‧高度
H2A‧‧‧高度
H2B‧‧‧高度
下列圖示是併入說明書內容之一部分，以供闡述本揭露之各種實施例，進而清楚解釋本揭露之技術原理。
為了使本揭露之敘述更加詳盡與完備，可參照下列描述並配合下列圖式，其中類似的元件符號代表類似的元件。然以下實施例中所述，僅用以說明本揭露之技術內容，而非是用來限制本揭露的範圍。
圖1是根據本揭露某些實施例之獨立的傳導互連結構的剖視圖；圖2A是對應於圖1線段A-A之橫截面(面A)的微結構圖；圖2B是對應於圖1線段B-B之橫截面(面B)的微結構圖；圖2C是對應於圖1線段C-C之橫截面(面C)的微結構圖；圖3是根據本揭露某些實施例之傳導互連結構的剖視圖；圖4A和圖4B是根據本揭露一些實施例對應於圖1線段A-A之橫截面(面A)的微結構圖；圖5是根據本揭露某些實施例之半導體封裝的剖視圖；圖6是根據本揭露某些實施例之半導體封裝的剖視圖； 圖7是根據本揭露某些實施例對應於圖1線段A-A之截面平面(面A)的微結構圖；圖8A和圖8B是根據本揭露某些實施例對應於圖1線段A-A方向之橫截面(面A)的微結構；圖9A和圖9B是根據本揭露某些實施例對應於圖1線段A-A之橫截面(面A)的微結構圖；圖10A到圖10D是根據本揭露某些實施例中某些製成傳導互連結構之片段操作；圖11A到圖11E是根據本揭露某些實施例中某些製成傳導互連結構之片段操作；圖12A到圖12E是根據本揭露某些實施例中某些製成傳導互連結構之片段操作；以及圖13A到圖13F是根據本揭露某些實施例中某些製成傳導互連結構之片段操作。
本揭露於在相關的圖式中，參考符號可以重複出現在整個實施例中，但不必然某一實施例之特徵就非得適用於另一實施例中不可，即使這些特徵共用相同的參考符號。本揭露之圖式僅供參考，但這些圖式並不需要按比例來繪製，甚至在一些情況下，圖式可被放大和/或簡化。本揭露所屬技術領域中具有通常知識者，可以在本實施例描述中思慮到的任何變化及修飾，以及在此文件當中做出任何更進一步原理的應用。
銅對銅(Cu-to-Cu)直接鍵結是一種電流密度限定球閘陣列封裝(Ball grid array，BGA)技術的互連選擇。銅對銅直接鍵結可形成於任一積體電路上的銅佈線與基板上的銅佈線之間，或可形成在二個獨立封裝的銅佈線之間。銅對銅直接鍵結技術可以提供高導電率之電性連 接點、優異抗電移能力、以及無脆性之金屬間化合物。高深寬比的銅對銅直接鍵結機械強度，可以省略底部填充結構。
銅對銅合成通常是被採用來實現銅對銅直接鍵結，銅對銅合成的關鍵參數包含：(i)建立二個潔淨銅表面之間的緊密鍵結；(ii)鍵結溫度及壓力；(iii)鍵結時間。為了取得介於二個銅表面適當的鍵結，必須在壓力之下進行高溫退火(正常是介於350℃至450℃之間)。鍵結時間是整體通過銅對銅直接鍵結的一限制因素。為確保鍵結介面的品質，更高的鍵結溫度為較佳。然而，需要之溫度對於節省成本的有機板或基板而言太高。有鑑於此，如何減少銅對銅直接鍵結溫度，仍在持續地尋求解決之道。
擴散製程是實現銅對銅直接鍵結的關鍵機制。由於銅是屬於面心立方晶體結構(face-centered cubic crystal structure，FCC)金屬，在銅熔點溫度低於0.8倍的範圍中，晶界擴散效應是主要的質量擴散機制。在銅對銅直接鍵結中，有效擴散係數(effective diffusion coefficient)可由下列的式1說明：Deff=fDgb+(1-f)D1 [式1]
其中，Deff為有效擴散係數，Dgb為晶界擴散係數，D1為晶格擴散係數，以及f為晶片幾何形狀及粒徑尺寸相關常數。具體而言，式1中的晶片幾何及粒徑相關常數f尚可進一步定義如式2：f=(q/d)δ [式2]
其中，q值取決於晶片幾何形狀，d為平均粒徑，以及δ是晶界寬度。考慮上述之式1及式2，為了達到較低的鍵結溫度，需要較大的Deff值。因此，較佳的鍵結介面應具有較小平均粒徑以及均勻的粒徑分佈，以促進晶界擴散及整體擴散過程。
在一些實施例中，本揭露某些實施例提供的銅對銅互連結構係一銅柱體(copper post)，該銅柱體本體具有一較粗大的平均粒徑，而 該銅柱體外表面具有一較細的平均粒徑。該銅柱體之一部分外表面與另一銅表面相互接觸、經過加壓以及加熱，實現銅對銅鍵結。本揭露亦公開上揭銅柱體之銅對銅互連結構的製造方法。
定義
本揭露所揭示之專利範圍及說明內容，將根據下文所闡述的定義來使用相關的術語。
如本文所稱「平均粒徑」是藉由任何常規粒徑測量技術，例如是X光射線技術(X-ray diffraction，XRD)、電子束散射圖案(electron beam scattering pattern，EBSP)、穿透式電子顯微鏡(transmission electron microscopy，TEM)或電子顯微鏡(scanning electron microscopy，SEM)來量測。一樣品的預處理橫截面是用上述任何一種測量方式來準備。圖1顯示一具有導電體101及導電層102一獨立的互連結構10置放於該導電體101之一上表面。一接觸墊104置放於該導電體101之該下方。該互連結構10之一縱向103藉由虛線來標記。該縱向是用來參考互連結構最大尺寸至平行方向。在一些實施例當中，用任何上述量測方法的橫截面是：(1)任何通過互連結構10之平面，其法線垂直於互連結構10之縱向103，以及(2)任何通過互連結構10之平面，其法線平行於互連結構10之縱向103。
如本文所稱，用於平均粒徑量測的「電子束散射圖案」(electron beam scattering pattern，EBSP)，係藉由電腦分析程式輔助(例如TSL、OIM分析)。電腦分析程式的設定包含但不限於以晶向15度錯位認定為晶界，CI值等於或大於0.1，以及最小粒徑至少需具有5個測試點的。在一些實施例中，該電子束散射圖案量測之該平均粒徑是藉由在橫截面的至少三個不同的檢測位置上的平均粒徑來取得。每個檢測位置具有一預定面積。該預定面積是依據具不同實施例的特徵而變化。每個檢測位置與該相鄰檢測位置相隔至少1mm。在某些實施例 中，一個檢測位置的各測量點之間的間隔為至少為5微米。在某些實施例中，用於電子束散射圖案量測的該樣品是在20kV的加速電壓以及100倍至500倍的倍率來觀察。在一些實施例中，該樣品可放置在70度的傾斜角。
本文所稱「穿透式電子顯微鏡」(transmission electron microscopy，TEM)或「電子顯微鏡」(scanning electron microscopy，SEM)用於平均粒徑是藉由圖像分析程式來分析(例如，CLEMEX圖像分析軟體)來測量。在一些實施例中，該電子顯微鏡或電子顯微鏡測量之該平均粒徑是藉由橫截面的至少三個不同的檢測位置上的平均粒徑來取得。一預定區域在每一個檢測位置被量測。該預定區域依據具有數個特徵的不同實施例而變化。每個檢測位置與相鄰檢測位置為至少相距1mm。在一些實施例中，在一個檢測位置的各測量點之間的間隔至少為5微米。在一些實施例中，用於穿透式電子顯微鏡或電子顯微鏡測量的製備樣品在於20kV的加速電壓及100倍至500倍的放大倍率之下可被觀察。
如本文所稱的「預處理」(pretreatment)，係包含晶界蝕刻操作，以用於樣品橫截面的平均粒徑測量。在一些實施例中，用於晶界蝕刻操作係應用下列的蝕刻條件：利用稀磷酸作為電解溶液，電流密度為0.1mA/cm2、蝕刻時間30秒、蝕刻溫度25℃。在某些實施例中，由於晶界的蝕刻速率較晶粒本身的蝕刻速率快約10倍，因此預處理有助於呈現晶粒邊界的外觀特徵。
如本文所稱「晶核層」，是指在形成一較厚層之前沉積的一較薄層。在某些實施例中，晶核層之材料包含銅或銅/鈦，且其厚度大約是10奈米。晶核層的形成的方法包含但不限於電鍍、化學鍍、物理氣相沉積、化學氣相沉積或其組合。
如本文所稱「阻隔層」是指一薄層沉積於一載體與一晶核層之 間。阻隔層可增進其底層載體及其後形成在晶核層上的較厚導電層之間的粘附強度。在一些實施例中，阻隔層之材質是為氮化鉭(TaN)、鉭(Ta)、鉭-矽-氮(TaSiN)、氮化鈦(TiN)或其組合，且其厚度大約是10奈米。阻隔層形成的方法包含但不限於電鍍、化學鍍、物理氣相沉積、化學氣相沉積或其組合。
如本文所稱「半導體封裝」係指在先進三維封裝方式裡的組件封裝，其包含但不限於利用打線及/或倒裝晶片鍵結之電性連接技術。三維(3D)晶片整合具有矽通孔(TSV)，且該整合係有不同形式，例如晶圓-晶圓接合、晶片-晶圓接合及晶片-晶片接合等；堆疊封裝，例如封裝對封裝(package-to-package)或封裝內封裝(package-in-package)等。
如本文所稱的「氣相沉積」是指利用一氣相材料或其前驅物沉積於基板上的操作步驟。氣相沉積作業包含任何作業，且不限於化學氣相沉積(chemical vapor deposition，CVD)和物理氣相沉積(PVD)。氣相沉積之實施方式包含有熱絲化學氣相沉積(hot filament chemical vapor deposition，CVD)、射頻化學氣相沉積(rf-CVD)雷射化學氣相沉積(laser CVD，LCVD)、保形鑽石塗覆作業、有機金屬化學氣相沉積(metal-organic CVD，MOCVD)法、濺鍍、熱壓蒸發物理氣相沉積(thermal evaporation PVD)、離子化金屬物理氣相沉積(ionized metal PVD，IMPVD)、電子束物理氣相沉積(electron beam PVD，EBPVD)、反應式物理氣相沉積、原子層沉積(atomic layer deposition，ALD)、電漿輔助化學氣相沉積(plasma enhanced，PECVD)、高密度電漿化學氣相沉積(high density plasma CVD，HDPCVD)、低壓化學氣相沉積(low pressure CVD，LPCVD)等等。
如本文所稱「塑封料」係指一由複合材料組成之化合物。塑封料可包含環氧樹脂、酚醛硬化劑、二氧化矽、催化劑、顏料、脫模劑 等。用於形成塑封料之材料具有一高熱傳導性、一低吸濕率、一在基板安裝溫度下的高抗彎強度，或其組合。
如本文所稱「導電柱」是指置放於一載體、一基板、或是一嵌入於塑封料中一填滿的導電孔或是一導電栓塞。該填滿的導電孔或導電栓塞延伸至封裝或塑封料的頂表面上。數個導電柱可以提供該封裝的一頂表面及一底表面之一電連通，或是提供該封裝之一頂表面到該封裝中的一晶片之間的一電連通。
如本文所稱「接觸墊」是置放在一個晶片或一基板的一表面上。該接觸墊之一表面可用於接收一錫球、一錫膏或一導電柱作為一端點，並電性連接該晶片到一外部電路或一重配層(redistribution layer，RDL)。該接觸墊的相對表面連接到另一重配層或是該晶片之一有源區。在一些實施例中，該接觸墊是一凸塊下冶金層(under bump metallurgy，UBM)。在一些實施例中，該凸塊下冶金層是由一導電材料如金，銀，銅，鎳，鎢，鋁，以及/或其合金所組成。
如本文所稱一「光罩層」或一「覆蓋層」係用於本揭露一圖案化操作中的一物件。該圖案化操作包含各種步驟和作業，並依據實施例的不同特徵而改變。在一些實施例中，一圖案化操作是圖案化一存在的薄膜。該圖案化操作包含：於該存在的薄膜上形成一光罩，以及利用蝕刻或其他移除步驟進行移除薄膜的未被光罩覆蓋之部分。該光罩層或一覆蓋層是一光阻或一硬光罩。在一些實施例中，一圖案化操作直接形成一圖案化層在一表面上。該圖案化操作包含形成一光敏薄膜於該表面上，進行一蝕刻微影操作。殘餘的光敏薄膜可以被移除或保留，並納入封裝中。
如本文所稱「填充中」或「被填充」，是用於描述在孔洞中形成導電材料之一操作。該填充操作包含各種步驟和作業，且依據實施例不同特徵而改變。在某些實施例中，一填充操作包含在一個孔洞中形 成一導電材料。在某些實施例中，填充操作包含電鍍作業。在某些實施例中，填充操作包含氣相沉積作業。
該些問題及需求藉由本揭露實施例以上的概述來解決。圖1是具有一導電體101及一導電層102之一獨立的互連結構10，該導電層102置放於導電體101之第二端101b。一接觸墊104置放在第一端101a上，且該第一端101a相對於該導電體101的第二端101b。在一些實施例中，該接觸墊104置放在一半導體封裝的一載體上(未示出)。一晶核層和一阻隔層(未示出)皆置放在接觸墊104和導電體101之間來增加彼此之間的粘附性。在一些實施例中，導電體101係為一導電銅柱，且導電層102是一導電銅層。
該互連結構10的一縱向103以虛線來標記。該縱向103是指平行於互連結構10中最大尺寸之方向。如圖1所示，該互連結構10的最大尺寸是沿著導電體101的側壁105。圖1顯示出三個剖面方向，剖面後會形成三個具有不同的微結構的橫截面。
該第一剖面方向穿通線段A-A且遵循該導電體101之該縱向103。該橫截面之該法線垂直於該導電體101之該縱向103。於下文中，該橫截面將標記為面A。該第二剖面方向穿通線段B-B且垂直於該導電體101之該縱向103之方向。該橫截面之該法線平行於該導電體101之該縱向103。於下文中，該橫截面將標記為面B。第三剖面方向穿通線段C-C且垂直於該導電體101之該縱向103之方向，該橫截面之該法線平行於該導電體101之該縱向103。於下文中，該橫截面將標記為面C。惟須注意圖1中，面B和面C是相互平行，且面B和面C橫越互連結構10的不同部分，面B穿過導電層102，而面C穿過互連結構10的導電體101。
圖2A到圖2C分別是經過預處理的面A、面B及面C的微結構圖。在一電子顯微鏡下檢視時，在經過預處理的面A、面B及面C上的晶粒 結構是很容易觀察到的。前揭三個平面中，面A顯示導電體101之該些晶粒和導電層102之該些晶粒之間存在一明顯粒徑差異。在圖2A中，在導電體101的一晶粒201和導電層102的一晶粒202皆標記有陰影線。在一些實施例中，一平均粒徑(a)由該互連結構10之導電體101的面A量測而得。一平均粒徑(b)由該互連結構10之導電層102的面A上量測而得。在一些實施例中，於該面A中之該平均粒徑(a)大於該面A之該平均粒徑(b)。該平均粒徑的測量方式可參照本文定義中的「平均粒徑」之詳述內容。在某些實施例中，該面A中的該平均粒徑(a)約1.5倍大於該面A的該平均粒徑(b)。
如圖2B所示之面B具有遍及整個面B的區域的一均勻粒徑多晶薄膜。在某些實施例中，該粒徑尺寸均勻分佈並具有一小於0.45的標準差。如圖2C所示之面C具有遍及整個面B的區域的一均勻粒徑多晶薄膜。在某些實施例中，面B的平均粒徑(d)與面A的平均粒徑(b)相近，但實質上不相同。在其他實施例中，將面C的平均粒徑(e)與面A的平均粒徑(a)相近，但實質上不相同。在某些實施例中，面B的平均粒徑(d)小於面C的平均粒徑(e)。
圖3係具有一導電體301及一導電層302之一互連結構30，該導電層302置放於該導電體301之一第二端301b。一接觸墊304置放在該導電體301的第一端301a，且第一端301a相對於導電體301的第二端301b。在一些實施例中，該接觸墊304置放在半導體封裝的載體307上。一阻隔層308a和一晶核層308b置放在該接觸墊304和該導電體301之間，以增加接觸墊304和導電體301之間的粘附。在一些實施例中，該導電體301是為一導電銅柱，且該導電層302是一導電銅層。
在一些實施例中，該導電層302是用於直接鍵結另一導電表面(未示出)。在一些實施例中，該導電層302是一具有低於200奈米平均粒徑(b)的導電銅層，該導電體301是一具有介於200奈米至800奈米之間 平均粒徑(a)的導電銅柱。該導電層302在前揭實施例中直接鍵結至另一導電銅層(未示出)，該另一導電銅層置放在另一半導體封裝(未示出)的一導電銅柱上。
在某些實施例中，如圖3所示，除了該晶核層308b接近於該導電體301的該第一端301a，另一個晶核層306置放在接近於該導電體301的該第二端301b。當沉積薄膜時，上層薄膜的粒徑及織構會被下層的粗糙度及織構影響。例如，該上層沉積顯示在一個特定方向的織構與該下層的織構相同。再舉例而言，該下層的表面粗糙度越大，該上層的平均粒徑越小。在圖3中，為了取得比導電體301之平均粒徑(a)更小的導電層302平均粒徑(b)，置放一晶核層306於導電體301與導電層302之間，以便於控制導電層302的平均粒徑(b)。
如圖3所示，在縱向303上導電層302的高度標記為H1，以及在縱向303上導電體301的高度標記為H2。高度H1至少大於導電層302經受加壓及加熱之直接鍵結操作而產生原子相互擴散的長度。在一些實施例中，高度H1小於高度H2。在一些實施例中，高度H1大約為5奈米，而高度H2大約是500奈米。在一些實施例中，高度H1大約為50奈米，而高度H2大約是0.8微米。在一些實施例中，高度H1大約是1微米，而高度H2大約是2微米。然而，在一些實施例中，高度H1等於或大於高度H2。在一些實施例中，高度H1大約為5微米左右，而高度H2大約是5微米。在一些實施例中，高度H1大約為10微米左右，而高度H2大約為8微米。
圖4A和圖4B是本揭露於一些實施例中面A的微結構圖。如圖4A所示，一載體407設置在靠近該互連結構40A的第一端401a。一導電體401置放在一接觸墊404上。如圖4A所示，該導電體401具有側壁405，。惟圖4A中並未示出該載體407和該接觸墊404的微結構。在一些實施例中，該導電體401是一圓柱體，因此，該導電體401的側壁 405是一連續表面。導電層4021置放在該導電體401的第二端401b，另一導電層4023置放在該導電體401的側壁405。在一些實施例中，導電層4021中的平均粒徑(b)基本上相同於導電層4023中的平均粒徑(b)。
在一些實施例中，導電體401之該平均粒徑(a)大於導電層(4021、4023)之該平均粒徑(b)約5倍。在一些實施例中，該平均粒徑(a)和該平均粒徑(b)之間的差異約80奈米。
如圖4B所示，一載體407置放於接近一互連結構40B的一第一端401a。一導電體401置放在一接觸墊404。如圖4B所示，導電體401具有一側壁405。在一些實施例中，導電體401是一四角柱，因此，導電體401的側壁405是一個連續表面。一導電層4021置放在導電體401的第二端401b，另一導電層4023置放在導電體401的側壁405。在一些實施例中，導電層4021之平均粒徑(b)與導電層4023之平均粒徑(b)實質相同。
如圖4B所示，一晶核層4061置放在靠近導電體401的第一端401b，以及一晶核層4063置放靠近在導電體401的側壁405。如圖4所示之該晶核層(4061、4063)置放在該導電體401和該導電層(4021、4023)之間。惟圖4B中並未示出該載體407、該接觸墊404及該晶核層(4061、4063)的微結構。
圖5是一具有晶片封裝組件之三維堆疊封裝50。一具有多個接觸墊5113之單片半導體晶片511置放在該單片半導體晶片511之一表面上。一具有多個接觸墊5123之半導體封裝512置放在接觸墊5123的一表面上。為求簡化起見，於圖5中僅標記在該單片半導體晶片511上的一接觸墊5113以及該半導體封裝512上的一接觸墊5123在。位於該單片半導體晶片511和該半導體封裝512之間之該互連結構包括一導電體5111和一導電層5112。
在圖5中，導電體5111的一端連接到該單片半導體晶片511的該接 觸墊5113，且導電體5111的該另一端連接到導電層5112。導電層5112置放在半導體封裝512之一表面上，並連接至其中之一接觸墊5123。該導電體5111之縱向503如圖5所示垂直於單片半導體晶片511及半導體封裝512。一塑封料510填充在複數導電體5111之間的空間以封裝單片半導體晶片511。
圖6是具有一晶片封裝及一封裝上封裝組件之一三維堆疊封裝60。一單片半導體晶片611具有置放在該單片半導體晶片611之一表面的多個接觸墊6113。一半導體封裝612具有多個接觸墊6123設置於其一表面上。一半導體封裝613具有多個接觸墊6133設置於其一表面上。只是為簡單起見，圖6僅標記有在該單片半導體晶片611上的一個接觸墊6113，於該半導體封裝612上的一接觸墊6123，以及於該半導體封裝613上的一接觸墊6133。
位於該單片半導體晶片611和該半導體封裝612之間的該互連結構，包括一導電體6111和一導電層6112。該半導體封裝612和該半導體封裝613之間的該互連結構包括二導電體(6131，6121)和一導電層6132。在圖6中，該導電體6111之縱向603垂直於該單片半導體晶片611及該半導體封裝612。多個導電體(6131、6121)之縱向603垂直於該半導體封裝612和該半導體封裝613。在某些實施例中，塑封料610填充在複數導導電體6111之間的空間，且部分地填充在多個導電體(6131、6121)之間的空間。
圖7是為圖6之一互連結構620的放大圖。該互連結構620包括與半導體封裝612相連之導電體6121，與半導體封裝613相連之導電體6131，以及導電層6132。導電層6132夾設於二導電體(6131、6121)之間。該導電體6131之第一端6131a以及該導電體6121之第三端6121a皆個別連接到接觸墊(6133、6123)。該導電體6131的一第二端6131b及該導電體6121的一第四端6121b接觸該導電層6132。惟圖7中並未示出 接觸墊(6133，6123)的微結構。
在一些實施例中，導電體6121於面A上具有一平均粒徑(a)，導電體6131於面A上具有一平均粒徑(c)，導電層6132於面A上具有一平均粒徑(b)。該平均粒徑的測量方式可詳細參照在本文中論述定義之「平均粒徑」。該面A之相關敘述可詳細參照圖2A。
在一些實施例中，如圖7所示，在該導電體6121之平均粒徑(a)與導電體6131之該平均粒徑(c)實質相同。平均粒徑(a)或該平均粒徑(c)其中之一大於在導電層6132之平均粒徑(b)。在某些實施例中，平均粒徑(a)大於平均粒徑(b)約8倍。
在圖7中，具有一均勻粒徑分佈之面B橫過該導電層6132如圖2B所示。面B的相關細節同如前文之圖1及圖2B之詳述內容。在一些實施例中，導電體6131沿縱向603的高度H2A或導電體6121沿縱向603之高度H2B均大於導電體6132沿縱向603的高度H1'。在某些實施例中，高度H2A大於高度H1'約300倍。在一些實施例中，高度H2B大於高度'約500倍。然而，高度H2A和高度H2B並非一定相同，高度H2A不同於高度H2B均屬於本揭露的範圍。
圖8A及圖8B皆顯示本揭露在一些實施例中面A的微結構。如圖8A所示，該互連結構80A包括一與半導體封裝807相連之一導電體8071，與該半導體封裝809相連之一導電體8091，以及夾設於二導電體(8071、8091)之間的一導電層8072。導電體8071的第一端8071a及導電體8091的第三端8091a皆個別連接到接觸墊(8074、8094)。導電體8071的第二端8071b及導電體8091的第四端8091b皆與導電層8072接觸。惟圖8A中並未示出該些接觸墊(8074、8094)的微結構。
在一些實施例中，導電體(8071、8091)皆為圓柱體，因此，導電體(8071、8091)之側壁(8075、8095)皆為連續表面。然而，該些導電體(8071、8091)無須皆為相同形狀。在一些實施例中，導電體8071是 一圓柱體，然而導電體8091是一四角柱。數個導電層(8073、8092)分別置放在數個導電體(8071、8091)之數個側壁(8075、8095)。
圖8B是本揭露某些實施例中的面A之微結構。與圖8A中相同的參考符號皆適用於圖8B。圖8B的互連結構80B結合如圖8A所示的該互連結構80A之上半部(導電體8091和導電層8092)，以及如圖7中所示互連結構620的下半部(導電體6121和導電層6132)。
圖9A和圖9B是本揭露在某些實施例中之面A之微結構。如圖9A所示，互連結構90A包括與一半導體封裝907相連之一導電體9071，與該半導體封裝909相連之一導電體9091，以及夾設於二導電體(9071，9091)之間的一導電層9072。導電體9071的第一端9071a及導電體9091的第三端9091a皆個別連接到數個接觸墊(9074、9094)。導電體9071的第二端9071b及導電體9091的第四端9091b與導電層9072接觸。惟在圖9A中並未示出數個接觸墊(9074，9094)的微結構。
在一些實施例中，如圖9A所示，數個晶核層9076置放在導電體9071之第二端9071b及側壁9075，數個晶核層9096置放在導電體9091之該第四端9091b及側壁9095。晶核層(9076、9096)皆置放在導電體(9071、9091)和導電層(9073、9092)之間。
圖9B是本揭露的一些實施例中面A之微結構。與圖9A中相同的參考符號皆適用於圖9B。圖9B的互連結構90B結合圖9A中的該互連結構90A的上半部(導電體9091和導電層9092)，以及在圖7中的互連結構620的下半部(導電體6121和導電層6132)。在一些實施例中，一附加的晶核層(未示出)置放在導電體9071的第二端9071b。
圖10A到圖10D描述本揭露某些實施例中製作導電互連結構的若干步驟。圖10A係置放一覆蓋層103在半導體封裝100上之一操作步驟。在一些實施例中，晶核層101係於形成覆蓋層103之前，被置放在該半導體封裝100上。晶核層101之構成材質是鈦/銅/鈦(30/1000/10奈 米)疊層，以直流電(Direct Current，DC)濺鍍在該半導體封裝100上。在一些實施例中，藉由圖案化作業形成一通孔105於覆蓋層103中。覆蓋層103在該實施例中係為光阻，在其它實施例中，覆蓋層103係為二氧化矽硬光罩。
圖10B是藉由一第一操作在該覆蓋層103中填入第一導電材料107於通孔105中之操作。在一些實施例中，該第一導電材料107是導電銅。然而，在本揭露的範圍之中，可使用其它的導電材料。該第一銅電鍍作業之該電鍍液中含有0.5M的硫酸，0.5M硫酸銅，0.25M拋光劑和0.25M的載劑。該電鍍作業在室溫及2.5安培恆定電流下進行1600秒。
圖10C是藉由一第二操作在第一導電材料107的一外表面形成一第二導電材料109的一操作。如圖10C所示，該外表面位於一第二端107b，相對於該第一導電材料107之一第一端107a。在一些實施例中，該第二導電材料109為導電銅。在一些實施例中，該第二操作亦是一電鍍操作。該第一操作和該第二操作中除了操作參數之外，皆是使用相同的沉積形式。該第二操作銅電鍍作業的該電鍍液中含有0.5M的硫酸、0.5M硫酸銅、0.25M拋光劑和0.25M的載劑。該電鍍作業在室溫以及7安培的恆定電流下進行120秒。
覆蓋層103隨後被移除，如圖10D所示。在一些實施例中，第一導電材料107相應圖1中之導電體101，第二導電材料109相應圖1之導電層102，。
在一些實施例中，如圖10D所示的二個互連結構可進一步使用一覆晶焊接機對準並形成示例於圖6，三維堆疊封裝60中的互連結構620。界於180度及350度之間的一操作溫度，界於10MPa及100MPa之間的一壓力，以及界於10秒至100秒的操作時間係施配在要被鍵結之該第二導電材料109之表面。在某些實施例中，鍵結作業之後，電鍍 銅的平均粒徑(a)大約界於500奈米到2500奈米之間，而電鍍銅的平均粒徑(b)大約界於200奈米到800奈米之間。因此，上述實施例中，平均粒徑(a)大於該平均粒徑(b)約1.5倍至5倍。
在一些實施例中，為了減小在第二導電材料109的平均粒徑(b)，一沉積後退火操作可被省略。鍵結操作過程中的高溫處理(本揭露一些實施例中使用溫度為400度)係用以達到沉積後退火作操作的目的，亦即降低該剛完成之電鍍層的內部應力。
圖11A到圖11E描述了本揭露的某些實施例中製造一導電互連結構的若干操作。圖11A係為置放一覆蓋層103於一半導體封裝100的一操作。在一些實施例中，一晶核層101係於形成覆蓋層103之前，被置放在該半導體封裝100上。在一些實施例中，一穿孔105藉由圖案化作業形成於覆蓋層103之中。
圖11B是藉由一第一操作在覆蓋層103的通孔105中填入一第一導電材料107於的操作。在某些實施例中，第一導電材料107係為導電銅。然而，在本揭露的範圍中，可使用其它的導電材料。該第一電鍍銅作業的該電鍍液中含有0.5M的硫酸、0.5M硫酸銅、0.25M拋光劑和0.25M的載劑。該電鍍作業在室溫及2.5安培恆定電流下進行1500秒。
圖11C是形成一晶核層106在該第一導電材料107之一外表面的一作業。在某些實施例中，該晶核層106係藉由一濺鍍作業形成。透過濺鍍作業，該晶核層106不僅沉積在該第一導電材料107的一第二端107b上，也沉積於覆蓋層103的頂表面上。然而，在其它沉積方法，例如電鍍、化學鍍或原子層沉積(ALD)，皆能夠形成具有所需表面粗糙度之晶核層106，因此皆在本揭露的範圍之中。
圖11D是藉由一第二操作形成第二導電材料109於第一導電材料107之一外表面上。同圖11D所示，該外表面置放在一第二端107b， 相對於該第一導電材料107的第一端107a。在一些實施例中，該第二導電材料109為導電銅。在一些實施例中，該第二操作是一無電鍍作業。該第二銅沉積作業的該無電鍍液中包含硫酸銅，乙二胺四乙酸，以及甲醛。化學鍍係於40度的環境中進行1.5小時。該經由無電鍍形成的第二導電材料109覆蓋在第一導電材料107的頂表面及覆蓋層103的頂表面上。
在圖11E中，覆蓋層103隨後被移除，留在覆蓋層103上的該第二導電材料109同時被剝離。在一些實施例中，第一導電材料107相應於圖1中之導電體101，第二導電材料109相應於圖1中之導電層102。
在一些實施例中，如圖11E所示的二個互連結構可進一步使用一覆晶焊接機對準並形成示例於圖6，三維堆疊封裝60中的互連結構620。界於150度至350度的一操作溫度，界於10MPa至100MPa之間的一壓力，以及界於10秒至100秒的操作時間係施配在要被鍵結之該第二導電材料109之表面。在某些實施例中，鍵結作業之後，電鍍銅的平均粒徑(a)大約界於200奈米到800奈米之間，而無電鍍銅的平均粒徑(b)約於200奈米以下。因此，實施例中平均粒徑(a)和平均粒徑(b)之間的差值超過100奈米。
圖12A到圖12E描述本揭露某些實施例中製作導電互連結構的若干步驟步驟。圖12A係置放一覆蓋層103在半導體封裝100上之一操作步驟。在一些實施例中，一晶核層101係於形成覆蓋層103之前，被置放在該半導體封裝100上。在一些實施例中，藉由一圖案化作業，一具有寬度A1之一通孔105形成在覆蓋層103中。在某些實施例中，通孔105是一圓柱體，因此，通孔105之底部區域實質上為圓形。因此寬度A1是該圓形的直徑。
圖12B是藉由一第一操作在覆蓋層103中填入一第一導電材料107進入一具有寬度A1之通孔105的一操作。在一些實施例中，該第一導 電材料107是導電銅，然而，本揭露的範圍中，尚可使用其它的導電材料。在一些實施例中，該第一操作是一電鍍作業。該第一銅電鍍作業的該電鍍液中含有0.5M的硫酸、0.5M硫酸銅、0.25M拋光劑和0.25M的載劑。該電鍍作業在室溫及2.5安培恆定電流下進行800秒。
圖12C是形成一遮罩層103'圍繞該第一導電材料107的一操作。在一些實施例中，遮罩層103'係藉由一後續的圖案化作業施配在圖12B所示之該覆蓋層103而形成。遮罩層103'的通孔105'具有一寬度A2，其大於圖12A所示的寬度A1。由於通孔105'的尺寸大於通孔105，間隙108形成於遮罩層103'及第一導電材料107的側壁1075之間。
在某些實施例中，該遮罩層103'是藉由完全移除圖12B所示的覆蓋層103，並再形成一具有如圖12C所示之通孔105'的一遮罩層103'。該遮罩層103'中的該通孔105'具有一寬度A2，其大於圖12A所示之寬度A1。由於該通孔105'的尺寸大於該通穿孔105'的尺寸，一間隙108形成於該遮罩層103'該及第一導電材料107之一側壁1075之間。
圖12D是藉由一第二操作在該第一導電材料107的外表面形成一第二導電材料109。如圖12D所示，該外表面包括一第二端107b(相對於第一端107a)以及該第一導電材料107的一側壁1075。在一些實施例中，該第二導電材料109之材質為導電銅。在一些實施例中，該第二操作亦為一電鍍作業。第一操作和第二操作是相同的沉積方法，但作業參數可不相同。該第二銅電鍍作業的該電鍍液中含有0.5M的硫酸、0.5M硫酸銅、0.25M拋光劑和0.25M的載劑。該電鍍作業在室溫及7安培恆定電流下進行250秒。在一些實施例中，該第二導電材料109完全填入於該間隙108。在一些實施例中，該第二導電材料109可部分地填入該間隙108。
如圖12E所示，遮罩層103'隨後被移除。在一些實施例中，該第一導電材料107相應於圖1中的導電體101，該第二導電材料109相應於 圖1中的導電層102。
在一些實施例中，如圖12E所示的二個互連結構可進一步使用一覆晶焊接機對準並形成示例於圖6，三維堆疊封裝60中的互連結構620。界於150度到350度之間的一操作溫度，界於10MPa到100MPa之間的一壓力，以及界於10秒至100秒的操作時間係施配在要被鍵結之該第二導電材料109之表面。在一些實施例中，鍵結作業之後，電鍍銅的平均粒徑(a)界於500奈米到2500奈米之間，而電鍍銅的平均粒徑(b)大約界於200奈米到500奈米之間。因此，上述實施例中，平均粒徑(a)和該平均粒徑(b)之間的差值超過100奈米。
圖13A到圖13F描述本揭露某些實施例中的製作導電互連結構的若干步驟。圖13A係置放一覆蓋層103在半導體封裝100上之一操作步驟。在一些實施例中，晶核層101係於形成覆蓋層103之前，被置放在該半導體封裝100上。在一些實施例中，藉由一圖案化作業，一具有寬度A1之一通孔105形成在覆蓋層103之中。
圖13B是藉由一第一操作在覆蓋層103中填入一第一導電材料107於該通孔105的一操作。在一些實施例中，該第一導電材料107為導電銅。然而，其它的導電材料可以被使用，且皆在本揭露的範圍之中。在一些實施例中，該第一操作是一電鍍作業。該第一銅電鍍作業的該電鍍液中含有0.5M的硫酸、0.5M硫酸銅、0.25M拋光劑和0.25M的載劑。該電鍍作業在室溫及2.5安培恆定電流下進行1600秒。
圖13C係形成一晶核層106於第一導電材料107之一外表面。在一些實施例中，形成晶核層106的包含一濺鍍作業。藉由一濺鍍作業，該晶核層106不僅沉積在第一導電材料107的該第二端107b上，也沉積在該覆蓋層103的頂表面上。然而，其它沉積方法，例如，電鍍，化學鍍，或原子層沉積(ALD)，皆能夠形成具有所需表面粗糙度之晶核層106，因此皆在本揭露的範圍之中。
圖13D是形成一遮罩層103'圍繞該第一導電材料107。在一些實施例中，如圖13C所示，該遮罩層103'是藉由完全移除圖13C所示之覆蓋層103，並再形成具有通孔105'(具寬度A2)的一遮罩層103'。置放在覆蓋層103上的部分晶核層106會隨著覆蓋層103移除作業而剝離。遮罩層103'之中的通孔105'中具有一寬度A2，其大於圖13A及13B所示之寬度A1。由於通孔105'的尺寸大於圖13A通穿孔105的尺寸，間隙108會於遮罩層103'及第一導電材料107之一側壁1075之間形成。
圖13E是藉由一第二操作形成一第二導電材料109於該第一導電材料107的一外表面上。如圖13E所示，該外表面包含有一第二端107b(相對於第一端107a)以及該第一導電材料107之一側壁。在一些實施例中，該第二導電材料109之材質是為導電銅。在一些實施例中，該第二操作是一濺鍍作業。
在某些實施例中，該濺鍍作業係操作於沉積溫度100度、操作功率200瓦、以及沉積速率約為1.2奈米/秒。該被濺鍍的樣品置放於一負載鎖系統(load lock system)之超高真空(~4×10-8帕)中。氬離子加速電壓為2kV，且工作氣體(氬氣)的壓力大約是1.5×10-4帕，濺鍍之第二導電材料109形成一覆蓋層，覆蓋在第一導電材料107之頂表面以及遮罩層103'之頂表面上。在一些實施例中，第二導電材料109實質上填充於第一導電材料107之側壁1075和遮罩層103'之間的數個間隙108中。在一些實施例中，第二導電材料109可部分地填充於間隙108中。
如圖13F所示，該遮罩層103'隨後被移除，位於該遮罩層103'上的部分第二導電材料109同時被剝離。在一些實施例中，該第一導電材料107相應於圖1的導電體101，第二導電材料109相應於圖1的導電層102。
在一些實施例中，13F圖所示的二個互連結構可進一步使用一覆 晶焊接機對準並形成示例於圖6，三維堆疊封裝60中的互連結構620。界於150度至350度之間的一操作溫度，界於壓力由10MPa至100MPa之間的一壓力，以及界於10秒至100秒的操作時間係施配在要被鍵結之該第二導電材料109之表面。在一些實施例中，鍵結作業之後，電鍍銅的平均粒徑(a)大約界於500奈米到2500奈米之間，而電鍍銅的該平均粒徑(b)大約界於200奈米到500奈米之間。因此，上述實施例中，平均粒徑(a)及平均粒徑(b)的差值超過100奈米。
本揭露之技術內容及技術特點雖然已揭示如上，然而本揭露所屬技術領域中具有通常知識者應瞭解，在不背離後附申請專利範圍所界定之本揭露精神和範圍內，本揭露之教示及揭示可作種種之替換及修飾。例如，上文揭示之許多裝置或結構可以不同之方法實施或以其它結構予以取代，或者採用上述二種方式之組合。
10‧‧‧互連結構
101‧‧‧導電體
101a‧‧‧第一端
101b‧‧‧第二端
102‧‧‧導電層
103‧‧‧縱向
104‧‧‧接觸墊
105‧‧‧側壁
A‧‧‧面
B‧‧‧面
C‧‧‧面

Claims (10)

  1. 一種傳導互連結構，包含：一接觸墊；一導電體，其一第一端與該接觸墊相連，該導電體之一縱向垂直於該接觸墊之一表面，且該導電體包含位於一橫截面之一平均粒徑(a)，該橫截面之法線垂直於該導電體之該縱向；以及一導電層，包含位於該橫截面之一平均粒徑(b)，該導電層位於該導體相對於該第一端之一第二端；其中該導電體及該導電層係由相同材料組成，且該平均粒徑(a)大於該平均粒徑(b)。
  2. 根據請求項1所述之傳導互連結構，其中該導電層包含位於一橫截面上之一均勻粒徑多晶薄膜，該橫截面之法線平行於該導電體之該縱向。
  3. 根據請求項1所述之傳導互連結構，其中該平均粒徑(a)及該平均粒徑(b)之比值範圍大約為1.25至10之間。
  4. 根據請求項1所述之傳導互連結構，更包含一晶核層位於該導電體及該導電層之間。
  5. 一種半導體封裝結構，包含：一第一半導體封裝，具有一第一表面，其中一第一接觸墊置放於該第一表面上；一第二半導體封裝，具有一第二表面，其中一第二接觸墊置放於該第二表面上；以及一傳導互連結構，電性連接該第一接觸墊及該第二接觸墊，其中該傳導互連結構包含：一第一導電體，其一第一端與該第一接觸墊相連，該第一導 電體之一縱向垂直於該第一接觸墊之一表面，且該第一導電體包含位於一橫截面之一平均粒徑(a)，該橫截面之法線垂直於該第一導電體之該縱向；以及一導電層，包含位於該橫截面之一平均粒徑(b)，該導電層位於該第一導體相對於該第一端之一第二端；其中該第一導電體及該導電層係由相同材料組成，且該平均粒徑(a)大於該平均粒徑(b)。
  6. 根據請求項5所述之半導體封裝結構，更包含一第二導電體，其一第三端與該第二接觸墊相連，該第二導電體之一縱向垂直於該第二接觸墊之一表面，且該第二導電體包含位於一橫截面之一平均粒徑(c)，該橫截面之法線垂直於該第二導電體之該縱向，其中該第二導電體之一第四端連接該導電層，且該第四端相對於該第二導電體之該第三端。
  7. 根據請求項5所述之半導體封裝結構，其中該平均粒徑(a)及該平均粒徑(b)之間的差異等於100奈米或大於100奈米。
  8. 一種傳導互連結構之製造方法，包含：置放一蓋層於一半導體封裝結構上；於該蓋層形成一穿孔；依據一第一操作於該穿孔填入一第一導電材料，其中該第一操作係配置產生該第一導電材料之一平均粒徑(a)；以及依據一第二操作於該第一導電材料之一外表面上形成一第二導電材料；其中該第二操作係配置產生該第二導電材料之一平均粒徑(b)；其中該平均粒徑(a)大於該平均粒徑(b)，且該第一導電材料及該第二導電材料實質上相同。
  9. 根據請求項8所述之傳導互連結構之製造方法，更包含於該第二導電材料形成之前，在該第一導電材料之該外表面上形成一晶核層。
  10. 根據請求項8所述之傳導互連結構之製造方法，更包含形成圍繞該第一導電材料之一遮罩層，其中該遮罩層及該第一導電材料之一側壁間存在一間隙。
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