TW202244329A - 銅-銅直接接合之方法及集成 - Google Patents
銅-銅直接接合之方法及集成 Download PDFInfo
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- TW202244329A TW202244329A TW111107979A TW111107979A TW202244329A TW 202244329 A TW202244329 A TW 202244329A TW 111107979 A TW111107979 A TW 111107979A TW 111107979 A TW111107979 A TW 111107979A TW 202244329 A TW202244329 A TW 202244329A
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- copper
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- 239000010949 copper Substances 0.000 title claims abstract description 152
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Abstract
本發明係關於用於銅-銅直接接合之方法,其包含以下步驟:
a)提供第一基板,其包含具有接合表面之第一純銅沈積物;
b)提供第二基板,其包含具有接合表面之第二純銅沈積物;
c)連接該第一沈積物之該接合表面與該第二沈積物之該接合表面且獲得經連接沈積物;及
d)轉換該經連接沈積物之該第一沈積物及該第二沈積物,成為經連接且經轉換沈積物,
-其中該第一沈積物及該第二沈積物藉由電化學銅沈積步驟形成且具有晶粒尺寸小於在步驟d)中之該轉換後之晶粒尺寸的銅晶粒,
-其中該經連接且經轉換沈積物具有晶粒,該等晶粒的晶粒尺寸大於在步驟d)中之該轉換前之該第一沈積物及該第二沈積物的晶粒尺寸;且係關於由該方法產生之集成及裝置。
Description
本發明係關於一種用於集成製造之銅-銅直接接合的新穎方法,尤其本發明係關於在半導體行業中之晶圓-晶圓製程(wafer-to-wafer process)、晶粒-晶圓製程(die-to-wafer process)或晶粒-晶粒製程中之互連導電銅結構的集成製造。
對於對提高小型化之需求,現代電子元件製造商不得不追求愈來愈密集之電氣互連的趨勢。異質整合被視為滿足半導體行業之當前及即將出現之要求的關鍵技術。其涉及將單獨產生之組件整合至集成中,此提供增強之功能性及改良之操作特性。銅構成個別組件之主要互連材料以及其封裝。在此情形下,在封裝內之組件的3D堆疊允許增加互連密度、減小外觀尺寸及提高效率。
在如晶圓-晶圓製程、晶粒-晶圓製程或晶粒-晶粒製程的不同製程中需要個別組件的接合。習知接合技術涉及銅凸塊及支柱(pillar)以及焊接材料,且廣泛用於當前封裝應用中。此類銅支柱通常藉由電解銅沈積產生。然而,常見製程通常具有在若干微米範圍內之相對較大的非均一性,尤其在共面性及總厚度變化方面。通常為錫或錫-銀合金之焊接材料允許在一定程度上補償此等非均一性。
互連密度的增加涉及縮小銅凸塊與柱之間的距離。由於可在接合期間自結構擠壓出焊料材料且產生電氣短路,因此習知焊料技術可能不適用於精細間距應用。銅-銅互連件之直接形成可藉由省略用於微凸塊之習知焊蓋,且藉此將凸塊之間的間距按比例縮小至明顯低於20 µm之值來克服此等問題。因此,提議若干嘗試以改良接合形成,包括藉由離子束之表面活化、化學機械拋光(CMP)、藉由使銅與其他元素摻合之表面鈍化、金屬及有機修整以及結構設計。
由於許多應用包括溫度敏感裝置,因此需要低溫替代性接合技術。提議涉及藉由二氧化矽囊封之直接銅-銅互連件的混合接合作為有前景的替代方案。
WO 2020046677 A1描述一種混合接合製程,其中結構提供藉由具有幾何結構及熱膨脹特徵之周圍介電質限制的垂直堆疊導電層,該等幾何結構及熱膨脹特徵經設計以在低溫下在精確凹槽距離上方垂直地擴展堆疊,以在無焊料或黏著劑之接合介面處產生直接銅-銅接合。在第一階段中,無機介電質之氧化物表面直接接合在一起,且其中在第二階段中,由周圍介電質限制之金屬直接接合在一起。銅-銅接合基於擴散在介面上之銅原子的表面擴散,以形成永久性接合。
US 9 881 888 B2揭示一種Cu-Cu互連結構在一個銅柱(post)之主體處的較粗糙平均晶粒尺寸及在該銅柱之外表面處的較精細平均晶粒尺寸。隨後接觸、加壓及加熱銅柱之一部分外表面及另一銅表面以達成銅銅熔融(copper to copper fusion)。
Chuan Seng Tan:「Recent progress in copper-based wafer bonding for 3-D ICs application」, 2008 INTERNATIONAL CONFERENCE ON ELECTRONIC MATERIALS AND PACKAGING: (EMAP 2008) IEEE, 2008年10月22日(2008-10-22),第45-48頁,揭示了金屬銅及其在IC之3-D堆疊中之應用的熱壓縮接合(亦被稱作擴散接合),其中發現置於兩個氧化晶圓上之毯覆式Cu膜以在適合接合條件下(亦即,在300至400℃溫度範圍及226 kPa接觸壓力下)合併及形成均勻層。
然而,上述方法並不滿足即將出現之提高小型化的要求。仍需要改良接合形成及接合強度以及延性。由於許多應用包括溫度敏感裝置,因此亦需要低退火溫度以避免損害組件及損耗導電性。
發明目標
因此,本發明之目標為克服先前技術的缺點且提供用於改良接合形成及接合強度的手段。
本發明之另一目標為提供用於在銅-銅直接接合期間降低退火溫度之手段。
本發明之又一目標為減少方法步驟之數目且提供用於待接合沈積物之經改良的接合表面。
本發明之又一目標為改良所形成之銅-銅接合內的電遷移。
發明概述
藉由本發明解決此等目標。
在本發明之一個態樣中,一種用於銅-銅直接接合之方法,其包含以下步驟:
a)提供第一基板,其包含具有接合表面之第一純銅沈積物,較佳第一基板為晶圓樣或晶粒樣基板;
b)提供第二基板,其包含具有接合表面之第二純銅沈積物,較佳第二基板為晶圓樣基板或晶粒樣基板;
c)連接第一沈積物之接合表面與第二沈積物之接合表面且獲得經連接沈積物;
d)轉換該經連接沈積物之該第一沈積物及該第二沈積物,成為經連接且經轉換沈積物,
-其中第一沈積物及第二沈積物藉由電化學銅沈積步驟形成且具有晶粒尺寸小於在步驟d)中之轉換後之晶粒尺寸的銅晶粒,較佳晶粒尺寸為奈米晶,更佳晶粒尺寸平均小於0.8 µm,更佳在0.01 µm至0.70 µm,最佳在0.01至0.3 µm;
-其中經連接且經轉換沈積物具有晶粒,其中晶粒尺寸大於在步驟d)中之轉換前的晶粒尺寸,較佳晶粒尺寸平均在0.1 µm至13 µm,更佳1至10 µm
其中步驟d)藉由施加退火步驟來進行,該退火步驟之退火溫度等於或低於200℃,較佳150℃至200℃。
在本發明之另一態樣中,一種集成,其包含:
i)經連接且經轉換沈積物,其係藉由以下獲得:
-將第一基板之第一純銅沈積物的接合表面與第二基板之第二純銅沈積物的第二接合表面連接,及
-轉換該經連接沈積物之該第一沈積物及該第二沈積物,成為經連接且經轉換沈積物,
-其中第一沈積物及第二沈積物藉由電化學銅沈積步驟形成,且具有與施加退火步驟之後具有較大晶粒尺寸之經連接且經轉換沈積物的銅晶粒相比,晶粒尺寸較小的銅晶粒,該退火步驟之退火溫度等於或低於200℃,較佳150℃至200℃,較佳第一沈積物之晶粒延伸穿過第一及第二沈積物之接合表面進入第二沈積物中,且反之亦然。
在本發明之又一態樣中,一種包含集成之裝置,該集成包含:
i)經連接且經轉換沈積物,其係藉由以下獲得:
-將第一基板之第一純銅沈積物的接合表面與第二基板之第二純銅沈積物的第二接合表面連接,及
-轉換該經連接沈積物之該第一沈積物及該第二沈積物,成為經連接且經轉換沈積物,
-其中第一沈積物及第二沈積物藉由電化學銅沈積步驟形成,且具有與施加退火步驟之後具有較大晶粒尺寸之經連接且經轉換沈積物的銅晶粒相比,晶粒尺寸較小的銅晶粒,該退火步驟之退火溫度等於或低於200℃,較佳150℃至200℃;
其中第一及第二基板為微電子裝置之部分,較佳晶圓或晶粒。
尤其,本發明避免了額外方法步驟,例如在接合步驟之前接合表面結構的改質,且提供了平滑的接合表面及額外步驟以降低接合溫度,如避免使用超高真空(UHV)條件的表面活化接合或使用銅奈米棒陣列作為接合中間層的Cu奈米棒方法。
本發明,其中避免將某些結構插入至接合表面中的複雜步驟,有助於減少CMP步驟之需要以便使接合表面進一步平滑化以提供具有極低表面粗糙度的均勻/平滑表面。在此情形下,平滑表面意謂表面粗糙度Ra低於300 nm,較佳低於50 nm。較佳地,表面粗糙度Ra在5 nm至200 nm、更佳在10 nm至50 nm、甚至更佳在10 nm至40 nm範圍內,及/或沈積物之平均厚度的偏差為5至10%。
因為金屬沈積物係藉由電化學銅沈積步驟形成,所以金屬沈積物之接合表面已為極平滑的。然而,在一些情況下,若需要小於10 nm之表面粗糙度Ra,及/或CMP用作短清洗步驟以製備基板之接合表面,尤其短CMP用於移除例如氧化銅及/或用於移除呈微觀粉塵形式粒子,則短CMP步驟可為有用的。
另外,在高度改良接合強度、接合形成及電遷移效能之轉換步驟之後,無相異介面(接合表面彼此接觸之區域)可偵測。該情形意謂,前接合表面之平滑表面(其將在轉換之前形成相異介面)在轉換之後不相異或或多或少不再為可偵測的。替代地,前接合表面之表面正變得模糊(indistinct)且被合併(至少部分地進入彼此),此係因為沈積物之晶粒自兩側經由表面生長至另一側。
可自隨附申請專利範圍或以下描述獲悉本發明之其他態樣。
現將詳細參考實施例,在隨附圖式中說明之實施例的實例。將參考隨附圖式描述例示性實施例的作用及特徵及其實施方法。在圖式中,相同參考編號表示相同要素,且省略冗餘描述。如本文中所使用,術語「及/或」包括相關所列項目中之一或多者的任一者及所有組合。另外,在描述本發明之實施例時,使用「可(may)」係指「本發明之一或多個實施例」。
在本發明之實施例的以下描述中,除非上下文另外清楚地指示,則單數形式之術語可包括複數形式,例如若下文中使用『一種沈積物(deposit)』,則包括『多種沈積物(deposits)』。另外,「平均」意謂數目為若干個數目之平均數目,其中某些數目可高於或低於平均數目。
在本發明之上下文中,純銅表示銅沈積物之純度,其意謂沈積99重量%、較佳99.9重量%、更佳99.99重量%之銅沈積物的銅含量,或各別純銅沈積物意謂至少99重量%銅含量、較佳至少99.9重量%、更佳至少99.99重量%之銅沈積物。純銅尤其不含有具有前述重量%之任何合金金屬或有機殘餘物。
第一基板及第二基板在應用本發明方法之後可為集成的部分及/或可為待用本發明處理之作為晶圓樣基板或晶粒樣基板之微電子裝置的部分。連接根據本發明方法之接合表面可為晶圓-晶圓(wafer to wafer,W2W)製程、晶粒-晶圓(die-to-wafer,D2W)製程或晶粒-晶粒(die-to-die,D2D)製程中的一個步驟。
第一基板及第二基板可進一步彼此獨立地包含具有不同金屬組合物(例如銅合金)及形成垂直堆疊的額外金屬沈積物。第一基板之額外金屬沈積物與第一沈積物連接且第二基板之額外金屬沈積物與第二沈積物連接。各額外金屬沈積物具有各別熱膨脹係數(COE)。第一及第二沈積物以及額外金屬沈積物可受限於介電材料。熟習此項技術者大體上已知此等基板之製造。
第一基板可進一步包含具有接合表面且至少部分地限制第一沈積物的第一非導電材料,例如介電材料,且其中第二基板進一步包含具有接合表面且至少部分地限制第二沈積物的第二非導電材料,例如介電材料,其中第一及第二沈積物之接合表面在第一及第二非導電材料之接合表面的表面下方或甚至與其水平(在該表面的同一位準處)。
第一基板之第一沈積物及第二基板之第二沈積物可獨立地選自由以下組成之群:通孔(via)、凸塊、支柱及/或襯墊。
雖然先前技術集中於CMP之最佳化、連接限制銅通孔之介電材料的氧化物-氧化物接合製程步驟以及在待接合基板之接合表面之間之銅表面處的銅原子的經改良擴散,但考慮到銅晶粒之晶粒尺寸及銅沈積物在電沈積製程方面的純度,以及用於後續銅-銅接合製程在混合接合程序中相關時間及退火溫度的經改良條件,本發明研究了銅沈積物在接合之前及之後的不同態樣。
本發明主要基於兩種發現,首先,沈積物之結晶結構不應在電鍍之後經改質且經保存直至銅-銅接合製程起始為止,且其次,銅-銅製程(主要步驟d))內之晶粒的起始晶粒生長產生晶粒,該等晶粒穿過一種沈積物之前均勻接合表面(former even bonding surface)至另一沈積物,其中前均勻接合表面消失或大部分消失。此經連接且經轉換沈積物顯示經連接(且經轉換)沈積物之經改良的接合強度及經高度改良的可靠性。
吾人自身實驗已展示,發現在室溫下維持小晶粒之時間標度取決於電解銅製程且可藉由恰當調整沈積參數來控制。尤其,銅沈積物之純度及銅沈積所用之溫度允許在室溫下長時間保留類似於初始形態之微觀結構。所得時間標度應足夠用於實施至工業混合接合程序中。不受理論束縛,介面(沈積物之接合表面)上方之晶粒生長根據本發明在藉由例如退火步驟緩解之轉換期間施加熱負荷後較佳自初始結構開始。
尤其,發現銅電沈積之退火溫度可隨共沈積雜質變化而受影響,該等雜質尤其取決於有機電鍍添加劑及電鍍條件,且可降低彼退火溫度以考慮到接合製程流程及所得封裝品質之要求。
尤其,在電化學銅沈積步驟之後應用本發明之轉換步驟以提供純銅沈積物,尤其在於基板上提供作為通孔之導電銅結構之後。較佳地,在不進行進一步熱處理之情況下,例如在應用本發明之前不進行退火步驟之情況下,在電化學銅沈積步驟之後應用轉換步驟。這意謂銅沈積物僅在電解法之後暴露於低於或等於環境(室內)溫度之溫度。
較佳地,在步驟a)及b)之後直至進行步驟c)及/或d)的時段不超過3週,更佳不超過120小時,甚至更佳不超過72小時。較佳地,步驟a)及b)之基板在時段期間在環境溫度(在18至25℃範圍內)下儲存,其溫度較佳低於或等於25℃,更佳在5℃至25℃範圍內。
根據本發明,步驟c) -將第一沈積物之接合表面與第二沈積物之接合表面連接且獲得經連接沈積物-被理解為例如藉由將基板面對面對準且在接合夾盤上將基板夾持在一起而使基板之沈積物的至少部分接合表面與彼此直接接觸。
倘若第一基板可包含具有接合表面且至少部分地限制第一沈積物的第一非導電材料,且其中第二基板進一步包含具有接合表面且至少部分地限制第二沈積物的第二非導電材料,其中第一及第二沈積物之接合表面在第一及第二非導電材料之接合表面的表面下方(或部分在下方)或與其處在同一位準,則步驟c)包含例如藉由將基板面對面對準且在接合夾盤上將基板夾持在一起而使基板之非導電材料的至少部分接合表面與彼此直接接觸。此連接可藉由在某一壓力下一起按壓第一及第二基板之非導電材料的第一及第二接合表面來達成。在此實施例中,第一及第二基板之第一及第二沈積物的接合表面如非導電材料之接合表面同時與彼此接觸,或在接合非導電材料之接合表面之後至少部分地接觸。
壓力可藉由1至5,000 N之接觸力施加。在一個實施例中,當基板完全接觸時,步驟c)中之接觸力可為3,500至4,500 N。
步驟c)可在不施加較高溫度之情況下進行,尤其在100℃之溫度下進行,較佳在環境溫度或室溫下(較佳在18至25℃範圍內)進行。
根據本發明之方法可用於封裝應用中之集成及/或裝置的製造。
藉由本發明,有可能改良待接合之基板之間之銅沈積物的接合形成及接合強度。
在接合介面(與彼此接觸之第一及第二沈積物之接合表面的區域)上方實現晶粒生長且該晶粒生長對於良好及足夠的銅-銅接合形成及高可靠性係非常重要的。避免晶粒尺寸(藉由電化學沈積提供之小晶粒作為開始點)之生長,轉換步驟之前至少延遲或減緩且直至開始轉換步驟。
在電化學銅沈積步驟之後,第一及第二沈積物之銅晶粒具有晶粒尺寸,其較佳為奈米晶的,此意謂晶粒尺寸小於1 µm,更佳晶粒尺寸平均小於0.8 µm,更佳0.01 µm至0.70 µm,最佳0.01至0.3 µm。
經經連接且經轉換沈積物之銅晶粒具有晶粒尺寸,其平均為0.1 µm至13 µm,更佳1至10 µm,最佳1 µm至5 µm。大體上,經連接且經轉換沈積物之銅晶粒的晶粒尺寸僅受經連接且經轉換沈積物的厚度(第一及第二沈積物之區域一起的長度)限制。
在連接步驟c)之後,第一沈積物之晶粒尺寸及第二沈積物之晶粒尺寸現為所連接沈積物的部分,且在轉換步驟d)期間,晶粒尺寸正生長且所形成之銅晶粒延伸穿過第一沈積物及第二沈積物之接合表面(亦稱為兩個接合表面彼此接觸之介面)進入各別其他沈積物中,此意謂來自第一沈積物之晶粒進入第二沈積物,且反之亦然。反之亦然意謂,在此情形下,第二沈積物之晶粒尺寸亦正生長且第二沈積物之所形成的銅晶粒延伸穿過第二沈積物之接合表面(再次亦被稱為兩個接合表面彼此接觸之介面)進入第一沈積物中。因此,先前具有均勻趨勢(形成介面)之沈積物的經連接接合表面消失,且銅晶粒經由經連接且經轉換沈積物(之區域)延長,較佳經由至少75%或更大的經連接且經轉換沈積物(之區域),更佳經由整個經連接且經轉換沈積物(之區域)。例如,若經連接且經轉換沈積物之區域的最大長度(第一及第二沈積物之區域一起的長度)為5 µm,則銅晶粒的長度較佳可為至多5 µm,例如4至5 µm。
較佳地,在轉換步驟之前,具有較小晶粒尺寸之第一沈積物及第二沈積物的晶粒幾乎完全(意謂多於90%之較小晶粒尺寸)轉換成經連接沈積物之較大晶粒尺寸的晶粒,其中較大晶粒尺寸之晶粒穿過經連接沈積物。
較佳地,經連接且經轉換沈積物不可偵測到或至少部分不可偵測到在前第一沈積物與前第二沈積物之間的接合表面(介面)。在轉換之後,藉由例如FIB SEM顯微法不再能至少部分地看到前均勻平滑表面。
在一個實施例中,具有較小晶粒尺寸之第一沈積物及第二沈積物的晶粒幾乎完全(意謂多於90%之較小晶粒尺寸)轉換成經連接沈積物之具有較大晶粒尺寸的晶粒,其中較大晶粒尺寸之晶粒穿過經連接沈積物,且經連接沈積物在轉換步驟d)之後在前第一沈積物與前第二沈積物之間無可偵測的接合表面(介面)。
在本發明之上下文中,在前第一沈積物與前第二沈積物之間無可偵測接合表面(在轉換之後兩個接合表面之間的介面)意謂在進行步驟a)、b)或c)之後,第一及第二沈積物之前存在的接合表面,在進行步驟d)之前,將不可再偵測為平滑/均勻表面,此係因為各沈積物之晶粒尺寸藉由自奈米晶生長至平均為0.1 µm至13 µm的晶粒尺寸而生長至各別其他沈積物中。換言之,接合表面或至少部分接合表面(亦稱為此等接合表面之間的介面)不可再偵測為屬於前沈積物。替代地,前相異表面或其至少部分現經合併在一起且進入另一者。此與其中使用沈積物之先前技術形成對比,其中晶粒尺寸無法生長,或晶粒尺寸在接合步驟或轉換步驟之前已經轉換,例如比較實施例中所示。
在此情形下,無「可偵測」接合表面(介面)意謂在步驟d)中轉換之前,銅沈積物之接合表面或至少部分表面(具有均勻趨勢)的偵測藉由如EBSD (電子反向散射繞射)或在步驟d)中轉換之後之FIB SEM顯微法的已知方法,並非可見/可觀察為屬於前沈積物,或部分地不可見/不可觀察為為屬於前沈積物。
轉換步驟d)藉由施加退火步驟來進行,該退火步驟之退火溫度等於或低於200℃,較佳150℃至低於200℃。較佳地,退火時間為10分鐘至90分鐘。
在D2W或D2D製程之情況下,在150℃至低於200℃之退火溫度下,退火時間較佳為45分鐘至75分鐘,最佳60分鐘。在W2W製程之情況下,在150℃至低於200℃之退火溫度下,退火時間較佳為10分鐘至20分鐘。
在另一實施例中,步驟c)連同步驟d)一起進行,其中步驟c)中之所用溫度為步驟d)之退火溫度。在此實施例中,連接步驟及轉換步驟藉由施加退火步驟同時進行,該退火步驟之退火溫度等於或低於200℃,更佳150℃至200℃。在此實施例中,第一沈積物及第二沈積物經歷熱膨脹,且第一沈積物及第二沈積物之銅晶粒亦開始分別轉換且延伸且使第一沈積物之接合表面與第二沈積物之接合表面彼此接觸,且最後因此,第一及第二沈積物之生長的銅晶粒接觸且穿透彼此且形成經連接且經轉換的沈積物。在特定實施例中,溫度逐步增加至上述退火溫度。
熱膨脹可由附接至第一及第二沈積物之第一及第二基板在接合表面之相對側上(不附接至接合表面)的額外金屬沈積物支撐。額外金屬沈積物可以具有多於一種金屬組合物,例如銅合金,且各額外金屬沈積物具有各別熱膨脹係數(COE)。此亦將緩解連接步驟c),且因此使第一及第二沈積物之接合表面接觸。
較佳地,本發明之方法為直接混合接合方法,其中第一基板進一步包含具有接合表面且至少部分地限制第一沈積物的第一非導電材料,例如介電材料,且其中第二基板進一步包含具有接合表面且至少部分地限制第二沈積物的第二非導電材料,例如介電材料,其中第一及第二沈積物之接合表面在第一及第二非導電材料之接合表面的平面表面下方或與其水平。在此實施例中,首先連接非導電材料之接合表面(若第一及第二沈積物之接合表面在下方),其藉由使基板之非導電材料的至少部分接合表面彼此直接接觸,例如藉由在如上文所解釋之條件下將基板面對面對準且在接合夾盤上將基板夾持在一起,且隨後接著連接沈積物之接合表面與步驟d)。若第一及第二沈積物之接合表面與非導電材料之接合表面處於相同高度,則兩個接合步驟(連接步驟)同時發生。較佳地,步驟c)及d)一起進行,其中在連接期間將基板之(非導電材料及沈積物的)接合表面自環境溫度加熱至上文之退火溫度。藉由加熱溫度,幾乎同時進行步驟d)或若達到退火溫度,則開始步驟d)。原則上,用於直接混合接合之製程流程包括在電解銅沈積之後CMP及步驟c)內之兩個接合步驟。因此,介電材料之第一接合,及第一及第二沈積物之第二或同時接合。此混合接合方法按此原則上為技術人員已知的且例如在WO 2020046677 A1中解釋。非導電材料可為基於SiO2、SiCN、SiN或呈聚醯亞胺(PI)形式之聚合物的材料。因為銅沈積物係藉由電化學銅沈積步驟形成,所以金屬沈積物之接合表面已為極平滑的(較佳具有10 nm至30 nm之表面粗糙度Ra)。然而,在一些情況下,若需要小於10 nm之表面粗糙度Ra及/或需要清潔,則短CMP步驟可為有用的。
或者,步驟c)可在不施加較高溫度之情況下進行,尤其在低於100℃之溫度下進行,較佳在環境溫度或室溫下(較佳在18至25℃範圍內)進行且較佳隨後直接進行步驟d)。
可使用提供具有小晶粒尺寸、較佳奈米晶之銅晶粒的第一及第二純銅沈積物的每一電化學水性銅沈積浴。藉由將電流施加至基板及至少一個陽極,較佳在根據本發明之方法中在15℃至40℃範圍內之溫度下、更佳在20℃至35℃範圍內之溫度下操作水性酸性銅鍍浴。
如開始時所解釋,本發明之最重要一點為必須維持第一及第二沈積物之小晶粒尺寸直至本發明方法之步驟d)開始為止。較佳地,在提供第一及第二銅沈積物之電化學銅沈積步驟之後且在步驟d)中轉換之前,不進行可能改變第一沈積物及第二沈積物之銅晶粒之晶粒尺寸的其他轉換步驟,較佳不進行退火步驟或包含加熱之任何其他步驟,例如不進行具有高於100℃之退火溫度的退火步驟,較佳不進行100℃至200℃之退火步驟持續1小時。較佳地,在步驟a)及b)之後直至進行步驟c)及/或d)的時段不超過3週,更佳不超過120小時,甚至更佳不超過72小時。較佳地,步驟a)及b)之基板在該時段期間在環境溫度(在18至25℃範圍內)下,較佳低於或等於25℃,更佳在5℃至25℃範圍內儲存。
另外,在電化學銅沈積步驟之後及/或在連接步驟c)之前,本發明不需要藉由額外處理步驟進行第一沈積物及第二沈積物之接合表面的表面改質以便使接合表面變粗糙,且因此不應用表面改質且將其自本發明之方法排除。尤其,第一沈積物之接合表面及第二沈積物之接合表面具有平滑表面,不具有產生之奈米紋理結構。此等額外結構產生數百奈米之表面粗糙度Ra。換言之,不例如藉由極稀酸沖洗、蝕刻、拋光或其他方法在第一及第二沈積物之接合表面上產生銅表面內的奈米結構(nanostructured)表面,如奈米紋理表面。
然而,視需要,可藉由化學機械拋光(CMP)進一步降低在步驟a)及/或b)之後之接合表面的表面粗糙度。進一步短CMP持續時間可用於清潔接合表面。
電化學銅沈積步驟可為製程之部分以將結構以第一沈積物及第二沈積物形式提供至第一及第二基板上,其中第一及第二沈積物可獨立地選自由以下組成之群:通孔、凸塊、支柱及/或墊。因此,原則上可使用每一種電化學銅沈積步驟,只要步驟提供待填充結構之良好的填充效能且提供第一及第二沈積物之較佳平滑的接合表面。原則上提供結構之製程為熟習此項技術者已知且可為例如金屬鑲嵌製程或其中用銅填充結構化抗蝕劑的製程。
電化學銅沈積步驟較佳包含使用水性酸銅沈積浴,該浴包含銅離子源;含硫增亮劑化合物;抑制劑化合物;調平劑,其係選自由含胍化合物、含脲化合物、含咪唑化合物及含吡啶化合物組成之群;以及鹵素離子。浴之pH值較佳≤ 2,更佳≤ 1。所有化合物可作為來自Atotech Deutschland公司之產品購買。
銅離子源較佳選自包含硫酸銅及烷基磺酸銅(諸如甲烷磺酸銅)之群。水性酸性銅鍍浴中之銅離子濃度較佳在4 g/l至90 g/L範圍內,更佳在10至70 g/L範圍內,仍更佳在30至65 g/L範圍內。
酸較佳選自包含以下之群:硫酸、氟硼酸、磷酸及甲磺酸,且較佳以10 g/L至400 g/L、更佳20 g/L至300 g/L、仍更佳30 g/L至300 g/L之濃度添加。
含硫增亮劑化合物較佳選自由以下組成之群:3-(苯并噻唑基-2-硫基)-丙基磺酸、3-巰基丙烷-1-磺酸、伸乙基二硫代二(ethylendithiodi)-丙基磺酸、3-N,N-二甲基胺基二硫代胺甲醯基-1-丙磺酸及3,3'-二硫代雙-1-丙磺酸(SPS)或其鹽,較佳二硫代雙-1-丙磺酸(SPS)。視情況存在於水性酸性銅浴組合物中之所有促進-增亮添加劑的濃度(總計)較佳在0.01 mg/L至100 mg/L,更佳0.05 mg/L至20 mg/L,仍更佳0.1至10 mg/L範圍內。
抑制劑化合物較佳選自由以下組成之群:聚乙二醇(PEG)、聚丙二醇、聚(乙二醇-無規(ran)-丙二醇)、聚乙二醇/聚-丙二醇-共聚物、聚(乙二醇)-嵌段-聚(丙二醇)-嵌段-聚-(乙二醇)及聚(丙二醇)-嵌段-聚(乙二醇)-嵌段-聚(丙二醇),較佳聚乙二醇或聚乙二醇/聚丙二醇-共聚物(PEG/PPG)。較佳地,抑制劑之分子量(MW,以[公克/莫耳]為單位)為4,000至8,000。該視情況選用之載劑-抑制添加劑的濃度(總計)較佳在0.005 g/L至20 g/L,更佳0.01 g/L 至20 g/L,仍更佳0.01 g/L至5 g/L範圍內。
含胍化合物為具有胍殘基及二價殘基之重複單元的聚合物化合物。實例揭示於EP 3286358 B1中,其以引用的方式併入且可購自Atotech Deutschland公司。水性酸性銅鍍浴中之胍化合物的濃度在0.01 mg/L至1000 mg/L,更佳0.1 mg/L至100 mg/L,仍更佳在0.5 mg/L至50 mg/L範圍內。
鹵素離子較佳選自Cl、Br及/或I。在氯離子之情況下,較佳以10至200 mg/L、更佳20至80 mg/L或仍更佳30至60 mg/L範圍內之濃度添加鹵素離子。若選擇其他鹵素離子,則較佳選擇各別莫耳量,或若選擇不同鹵素,則選擇各別總莫耳量。
較佳地,電化學銅沈積步驟藉由施加1至2 ASD之電流密度來進行,以便獲得第一沈積物及第二沈積物,其中可使用直流(DC)電鍍及脈衝電鍍。在一個實施例中,藉由脈衝電鍍,例如正向及反向脈衝,或正向及關閉脈衝電流及時間,進行電化學銅沈積步驟。
現將參考以下圖式及非限制性實例來說明本發明。
實例圖1說明根據先前技術(a)及根據本發明(b)之銅-銅直接接合的形成。
已知先前技術電化學沈積之銅在沈積之後最初亦由精細晶粒組成,但將易於隨溫度及時間而再結晶為較大晶粒。未進一步生長之晶粒推測會使得經接合組件之間形成介面(圖1a)。相比之下,若以更接近沈積後之初始狀態的晶粒尺寸進行接合,則可在介面消失的同時看到第一及第二沈積物之接合表面(介面)上的晶粒生長(圖1b)。
以下圖2至圖4將支持圖1中之發現,其可轉移至直接銅-銅接合且產生經改良之接合強度及經改良之導電性。
圖2模擬本發明之轉換步驟d),其中一個銅層(第一沈積物)經退火。圖2說明退火溫度隨時間推移的影響,在不同溫度下施加退火步驟1小時之後,基板上的4.5 µm厚銅沈積物(具有約2,500 ppm之有機雜質(比較實例)及基板上的純銅沈積物(本發明實例))的平均晶粒尺寸。
銅沈積物之退火溫度可藉由無機及有機的其他元素之共沈積來調節。無機元素,尤其其他金屬之共沈積使得形成合金,其與純銅相比可具有較低導電性。有機雜質通常來源於有機電鍍添加劑之共沈積。適當添加設計經展示可產生顯著更純的沈積物。此方法用於降低銅材料之退火所需的溫度。藉由EBSD測定在不同溫度下退火1小時之後的藉由電沈積製備之不同層的晶粒尺寸(圖2a)。相比於電解質2,由電解質1製備之沈積物需要顯著較高的溫度以獲得最終晶粒尺寸。兩種電解質在高溫下退火之後產生類似的晶粒尺寸,該晶粒尺寸為約沈積物厚度(4.5 μm)。藉由動態次級離子質譜分析(DSIMS)測定共沈積雜質的各別量且結果證實電解質1之較高值(下表I)。差示掃描熱量測定(DSC)研究顯示放熱峰值,且進一步支持具有較大量雜質之銅需要較高溫度以結晶(下表I)。電解質1係基於傾向於顯著共沈積之習知的電鍍有機添加劑,而電解質2由允許高純度最終層之最佳化添加劑組成。
用於混合接合應用之銅-銅接合形成的上限論述為200℃。因此,銅材料應在此類溫度下達至其最大晶粒尺寸。圖2a表明,來自兩種電解質之沈積物最終達到約3.5 μm之晶粒尺寸,其接近沈積物厚度。然而,電解質1需要大於300℃的溫度。相比之下,電解質2產生在約200℃之溫度下達至最大晶粒尺寸的銅。200℃下包括孿晶之平均晶粒尺寸達至電解質1之誤差範圍內的最大值,然而即使在230℃下仍保持在值1.1 μm。相應EBDS影像描繪於圖2b中。電解質1及2在此溫度範圍下之晶粒尺寸的比較證實了電解質2之潛在適合性。
圖2a直接顯示在不同溫度下退火1小時之後藉由EBSD測定的自電解質1 (灰色)及2 (黑色)獲得之4.5 μm厚銅沈積物的包括孿晶的平均晶粒尺寸(頂部)。分別在110℃及400℃下退火1小時之後,電解質2之對應EBSD影像的實例(底部)。
圖2b直接顯示在230℃下退火1小時之後,自電解質1 (頂部)及2 (底部)獲得之4.5 μm厚銅沈積物的EBSD影像。
由電解質1 (比較實例- (Comp. Ex))製備沈積物,相較於電解質2 (本發明實例1 - (Inv. Ex1))需要顯著較高的溫度以獲得最終晶粒尺寸。兩種電解質在高溫下退火之後產生類似的晶粒尺寸,該晶粒尺寸為約沈積物厚度(4.5 μm)。藉由動態次級離子質譜分析(DSIMS)測定共沈積雜質的各別量且結果證實電解質1之較高值(表I)。差示掃描熱量測定(DSC)研究顯示放熱峰值,且進一步支持具有較大量雜質之銅需要較高溫度以結晶(表I)。電解質1係基於傾向於顯著共沈積之習知的電鍍有機添加劑,而電解質2由允許高純度最終層之最佳化添加劑組成。
表1:由不同電解質製備之沈積物的總雜質及結晶溫度TC
a藉由DSIMS測定
b藉由DSC測定
電解質1 (Comp. Ex):
2 mg/L含硫增亮劑SPS
300 mg/L抑制劑化合物PEG (MW 6000)
0.1 mg/L調平劑PEI (MW 600)
以5 ASD,溫度25℃沈積
沈積之後高於200℃退火
電解質2 (Inv. Ex):
4 mg/L含硫增亮劑SPS
10 mL/L抑制劑化合物PEG/PPG共聚物(MW 6000)
20 mL/L含胍化合物Atotech® Spherolyte調平劑DB
以1 ASD,溫度25℃沈積
在步驟d)中沈積之後200℃退火1小時
系統 | 總雜質 a[ppm] | T C b[℃] |
電解質1 (Comp. Ex) | 2694 | 153 |
電解質2 (Inv. Ex1) | 55 | 115 |
圖3說明銅合金(比較實例)及純銅沈積物(本發明實例)之標準化晶粒尺寸,其中在室溫下隨時間推移研究一個銅層(第一沈積物)。圖3展示室溫下隨時間變化的由電解質2以參數集1 (5 ASD DC,25℃) (灰色)及2 (1 ASD DC,25℃) (黑色)製備的沈積物之標準化晶粒尺寸(頂部)。沈積之後立即(左)、12小時之後(中間)及24小時之後(右)的對應微觀結構之實例。
步驟d之前的所有製程步驟
在室內(環境)溫度或更低溫度下進行9個步驟,尤其沈積製程自身、連接步驟c)及例如CMP製程。因此,應儘可能長地維持與沈積之後初始結構類似的形態,以允許具有在高溫下的步驟d)銅-銅接合之前進行所有必需製程步驟的足夠時間。
為了研究微觀結構變化之時序表,在室溫下不同時間之後測定由電解質2 (上文)製備之沈積物的晶粒尺寸(圖3)。在室溫下之晶粒生長通常指示為自退火。獲得最大晶粒尺寸之時間可藉由電解沈積之製程參數來修改。使用參數1在約9小時之後獲得最大晶粒尺寸。此可能不足以在生產程序中實施。相比之下,用參數2製備之沈積物直至在室溫下未觀測到進一步晶粒生長需要超過24小時。此時間長得多,且因此更適合於當前工業生產製程流程。
圖4模擬接合製程中沈積物之轉換,其中隨時間推移及以不同溫度研究不同沈積物。圖4說明在不同時間及溫度參數下沈積之純銅沈積物的FIB SEM顯微圖,其中其顯示在參數2 1 (ASD DC,25℃)之情況下自電解質2沈積之銅的FIB SEM顯微圖,其中其可見於以下:
圖4a)沈積之後的單一4.5 µm層(模擬第一基板之第一沈積物)。
圖4b)在室溫下24小時之後的單一4.5 µm層(模擬第一基板之第一沈積物)。
圖4c)在200℃下退火1小時之後的兩個連續經沈積4.5 µm層,其中第二層在第一層在室溫下自退火24小時之後沈積(模擬根據非本發明實例之第一基板之第一沈積物及第二基板之第二沈積物的轉換)。
圖4d)在200℃下退火1小時之後的兩個連續經沈積4.5 µm層,其中第二層在第一層沈積之後立即沈積(模擬根據本發明之第一基板之第一沈積物及第二基板之第二沈積物的轉換)。
藉由其間具有不同退火條件的兩個連續電化學沈積步驟探測初始小晶粒微觀結構的沈積物進一步橫跨介面(連接的第一及第二沈積物之接合表面)生長的能力。4.5 µm厚的第一沈積物以製程參數2由電解質2製備,最初展現小晶粒(圖4a),該等晶粒在室溫下在24小時內以自退火顯著生長(圖b)。在相同條件下,對初始以及自退火微觀結構進行第二電沈積步驟。在兩個層之沈積之後,整體堆疊在200℃下退火1小時以模擬銅-銅接合期間之熱負荷。在第二層沈積於自退火第一層上之情況下,在退火之後觀測到介面。(圖4c -非本發明)。相比之下,若第二層沈積於仍呈其初始微觀結構之第一層上,則在由兩個連續沈積層組成之整個沈積物上不可偵測到介面及晶粒生長(圖4d)。
圖5說明根據本發明及根據比較實例的在晶圓對內形成銅-銅直接接合的FIB SEM顯微圖。
根據本發明之步驟a)及b),四個300 mm DBI5晶圓作為兩個第一基板及兩個第二基板提供,其中第一基板進一步包含具有接合表面且限制第一沈積物的第一非導電材料,且其中第二基板包含具有接合表面且限制第二沈積物的第二非導電材料。兩個基板由相同的非導電材料製成,且第一及第二銅沈積物由相同的電化學銅沈積步驟形成。用電解質2 (本發明實例1 - (Inv. Ex1))進行電化學銅沈積步驟。所有步驟均在24小時內進行。
本發明實例在電化學銅沈積之後60分鐘,用短CMP步驟處理兩個晶圓(第一及第二基板)。如一般描述中所解釋,短暫進行CMP步驟,主要用以清潔銅沈積物之表面。然而,可減少拋光時間及廢料。隨後,在環境溫度下連接兩個晶圓(步驟c)且根據步驟d)在低於200℃下使其退火60分鐘。
圖5a顯示2k倍數下所得銅-銅接合之晶圓對的FIB SEM顯微圖。
可以看出,經連接且經轉換沈積物係由穿過第一沈積物至第二沈積物且反之亦然之晶粒形成,其中在第一及第二沈積物之間無明顯介面將要消失且至少部分地不可見。
圖5b顯示20k倍數下此銅-銅接合之晶圓對的另一FIB SEM顯微圖,其中將圖5a之視圖旋轉了90°,且圖5c顯示在倍數50k下同一晶圓對的FIB SEM顯微圖。
可以看出,經轉換沈積物在前第一沈積物與前第二沈積物之間無明顯可偵測的接合表面(介面)。此意謂在轉換步驟d)期間,晶粒之晶粒尺寸增長且所形成之銅晶粒延伸穿過第一沈積物及第二沈積物之接合表面進入各別另一沈積物中。
比較實例在電化學銅沈積之後60分鐘,在200℃下用退火步驟處理晶圓(第一及第二基板) 60分鐘以迫使晶粒由於熱處理生長。在此步驟之後,用短CMP步驟處理兩個晶圓(第一及第二基板)。隨後,根據步驟c)及d)連接兩個晶圓且再使其在200℃下退火60分鐘。
圖6a顯示2k倍數下所得銅-銅接合之晶圓對的FIB SEM顯微圖。
可見,所形成之經連接沈積物展示第一與第二沈積物之間之可見的明顯介面,其中沈積物之表面未顯示併至沈積物之另一表面中的部分。
圖6b顯示20k倍數下此銅-銅接合之晶圓對的另一FIB SEM顯微圖,其中將圖6a之視圖旋轉了90°,且圖6c顯示在50k倍數下同一晶圓對的FIB SEM顯微圖。
可見,所形成沈積物具有前第一沈積物與前第二沈積物之間可見的接合表面(介面),且所生長晶粒並不穿過沈積物之接合表面,或換言之,無晶粒在第一及第二沈積物之整個區域上延長。
此意謂轉換在第一熱處理(步驟c之前的第一退火步驟)期間發生且在各沈積物(第一及第二沈積物)內完成。步驟d)中之進一步退火步驟不可引發進一步晶粒尺寸生長。尤其,晶粒之尺寸未進一步增加,且銅晶粒未延伸穿過第一沈積物及第二沈積物之接合表面進入各別另一沈積物中,此係因為晶粒尺寸生長已在第一退火步驟內完成。
藉由參考隨附圖式詳細描述例示性實施例,特徵將對於一般熟習此項技術者變得顯而易見,其中:
圖1(a)至圖1(b) 說明銅-銅直接接合之形成。
圖2(a)至圖2(b) 說明轉換步驟d)之模擬。
圖3 說明銅合金及純銅沈積物之標準化晶粒尺寸。
圖4a)至圖4d) 說明在時間及溫度之不同參數下所沈積之純銅的FIB SEM顯微圖。
圖5a至圖5c 說明在根據本發明之在晶圓對內形成銅-銅直接接合的FIB SEM顯微圖。
圖6a至圖6c 說明根據比較實例在晶圓對內形成銅-銅直接接合的FIB SEM顯微圖。
Claims (15)
- 一種用於銅-銅直接接合之方法,其包含以下步驟: a)提供第一基板,其包含具有接合表面之第一純銅沈積物,較佳該第一基板為晶圓樣或晶粒樣基板; b)提供第二基板,其包含具有接合表面之第二純銅沈積物,較佳該第二基板為晶圓樣基板或晶粒樣基板; c)連接該第一沈積物之該接合表面與該第二沈積物之該接合表面且獲得經連接沈積物;及 d)轉換該經連接沈積物之該第一沈積物及該第二沈積物,成為經連接且經轉換沈積物, 其中該第一沈積物及該第二沈積物藉由電化學銅沈積步驟形成且具有晶粒尺寸小於在步驟d)中之該轉換後之晶粒尺寸的銅晶粒,較佳該晶粒尺寸為奈米晶的, 其中該經連接且經轉換沈積物具有晶粒,該等晶粒的晶粒尺寸大於在步驟d)中之該轉換前之該第一沈積物及該第二沈積物的晶粒尺寸,較佳該晶粒尺寸為0.1 µm至13 µm,更佳1至10 µm,且其中該步驟d)藉由施加退火步驟進行,該退火步驟之退火溫度等於或低於200℃,較佳150℃至200℃。
- 如請求項1之方法,其中該退火步驟進行10分鐘至90分鐘之時段。
- 如請求項1或2之方法,其中該第一沈積物及該第二沈積物之該接合表面的表面粗糙度Ra小於200 nm,較佳在5 nm至200 nm範圍內。
- 如前述請求項中一項之方法,其中在轉換步驟d)期間該晶粒尺寸增長且所形成之銅晶粒延伸穿過該第一沈積物及第二沈積物之該接合表面進入該第二沈積物中,且反之亦然。
- 如請求項1至3中一項之方法,其中具有較小晶粒尺寸之該第一沈積物及該第二沈積物的晶粒幾乎完全(意謂多於90%之較小晶粒尺寸)轉換成該經連接沈積物之較大晶粒尺寸的晶粒,其中該較大晶粒尺寸之晶粒穿過該經連接沈積物。
- 如請求項1至3及5中一項之方法,其中在轉換步驟d)後,該經連接沈積物藉由FIB SEM顯微法不可偵測到或至少部分不可偵測到在前第一沈積物與前第二沈積物之間的接合表面(介面)。
- 如前述請求項中一項之方法,其中在該電化學銅沈積步驟後且在步驟c)的連接前,不進行改變該第一沈積物及該第二沈積物之該等銅晶粒之晶粒尺寸的轉換步驟,較佳不進行退火溫度高於100℃、較佳100℃至200℃之退火步驟。
- 如前述請求項中一項之方法,其中該方法為直接混合接合方法,其中該第一基板進一步包含具有接合表面且至少部分地限制該第一沈積物的第一非導電材料,且其中該第二基板進一步包含具有接合表面且至少部分地限制該第二沈積物的第二非導電材料,其中該第一沈積物及該第二沈積物之該接合表面在該第一非導電材料及該第二非導電材料之該接合表面的表面下方。
- 如前述請求項中一項之方法,其中該電化學銅沈積步驟包含使用在15℃至40℃之溫度範圍內操作的水性酸銅沈積浴。
- 如前述請求項中一項之方法,其中該電化學銅沈積步驟包含使用酸銅沈積浴,該酸銅沈積浴包含銅離子源;含硫增亮劑化合物;抑制劑化合物;調平劑(leveller),其係選自由含胍化合物、含脲化合物、含咪唑化合物及含吡啶化合物組成之群;以及鹵素離子。
- 如前述請求項中一項之方法,其中該電化學銅沈積步驟藉由施加1至2 ASD之電流密度進行,以便獲得該第一沈積物及/或第二沈積物。
- 如前述請求項中一項之方法,其中該第一沈積物之該接合表面及該第二沈積物之該接合表面具有平滑表面,較佳不具有奈米紋理(nanotexture)結構,較佳該平滑表面具有低於200 nm、較佳低於50 nm之表面粗糙度Ra。
- 如前述請求項中一項之方法,其中在該電化學銅沈積步驟後及/或在連接步驟c)前,不施加該第一沈積物及第二沈積物之該接合表面的表面改質。
- 一種集成,其包含: i)經連接且經轉換沈積物,其係藉由以下獲得: 將第一基板之第一純銅沈積物的接合表面與第二基板之第二純銅沈積物的第二接合表面連接,及 轉換該經連接沈積物之該第一沈積物及該第二沈積物,成為經連接且經轉換沈積物 其中第一沈積物及該第二沈積物藉由電化學銅沈積步驟形成,且具有與施加退火步驟之後具有較大晶粒尺寸之該經連接且經轉換沈積物的銅晶粒相比,晶粒尺寸較小的銅晶粒,該退火步驟之退火溫度等於或低於200℃,較佳150℃至200℃,較佳該第一沈積物之該等晶粒延伸穿過該第一沈積物及該第二沈積物的該接合表面進入該第二沈積物中,且反之亦然。
- 一種包含集成之裝置,該集成包含: i)經連接且經轉換沈積物,其係藉由以下獲得: 將第一基板之第一純銅沈積物的接合表面與第二基板之第二純銅沈積物的第二接合表面連接,及 轉換該經連接沈積物之該第一沈積物及該第二沈積物,成為經連接且經轉換沈積物 其中第一沈積物及該第二沈積物藉由電化學銅沈積步驟形成,且具有與施加退火步驟之後具有較大晶粒尺寸之該經連接且經轉換沈積物的銅晶粒相比,晶粒尺寸較小的銅晶粒,該退火步驟之退火溫度等於或低於200℃,較佳150℃至200℃; 其中該第一基板及該第二基板為微電子裝置之部分,較佳晶圓或晶粒。
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