TW201503230A - 基板處理方法、程式及電腦記憶媒體 - Google Patents

基板處理方法、程式及電腦記憶媒體 Download PDF

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Publication number
TW201503230A
TW201503230A TW103105856A TW103105856A TW201503230A TW 201503230 A TW201503230 A TW 201503230A TW 103105856 A TW103105856 A TW 103105856A TW 103105856 A TW103105856 A TW 103105856A TW 201503230 A TW201503230 A TW 201503230A
Authority
TW
Taiwan
Prior art keywords
polymer
block copolymer
wafer
pattern
substrate processing
Prior art date
Application number
TW103105856A
Other languages
English (en)
Chinese (zh)
Inventor
Makoto Muramatsu
Takahiro Kitano
Tadatoshi Tomita
Keiji Tanouchi
Soichiro Okada
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of TW201503230A publication Critical patent/TW201503230A/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
TW103105856A 2013-02-28 2014-02-21 基板處理方法、程式及電腦記憶媒體 TW201503230A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013039666A JP5837525B2 (ja) 2013-02-28 2013-02-28 基板処理方法、プログラム及びコンピュータ記憶媒体

Publications (1)

Publication Number Publication Date
TW201503230A true TW201503230A (zh) 2015-01-16

Family

ID=51428266

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103105856A TW201503230A (zh) 2013-02-28 2014-02-21 基板處理方法、程式及電腦記憶媒體

Country Status (3)

Country Link
JP (1) JP5837525B2 (ja)
TW (1) TW201503230A (ja)
WO (1) WO2014133004A1 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9396958B2 (en) * 2014-10-14 2016-07-19 Tokyo Electron Limited Self-aligned patterning using directed self-assembly of block copolymers
JP2017157632A (ja) 2016-02-29 2017-09-07 東芝メモリ株式会社 半導体装置の製造方法及びパターン形成方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4673266B2 (ja) * 2006-08-03 2011-04-20 日本電信電話株式会社 パターン形成方法及びモールド
JP2012004434A (ja) * 2010-06-18 2012-01-05 Toshiba Corp パターン形成方法およびパターン形成装置
JP5171909B2 (ja) * 2010-09-16 2013-03-27 株式会社東芝 微細パターンの形成方法
JP2012109322A (ja) * 2010-11-15 2012-06-07 Toshiba Corp パターン形成方法
JP5112500B2 (ja) * 2010-11-18 2013-01-09 株式会社東芝 パターン形成方法

Also Published As

Publication number Publication date
WO2014133004A1 (ja) 2014-09-04
JP2014168001A (ja) 2014-09-11
JP5837525B2 (ja) 2015-12-24

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