TW201418730A - 半導體封裝件之測試方法 - Google Patents

半導體封裝件之測試方法 Download PDF

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Publication number
TW201418730A
TW201418730A TW101140943A TW101140943A TW201418730A TW 201418730 A TW201418730 A TW 201418730A TW 101140943 A TW101140943 A TW 101140943A TW 101140943 A TW101140943 A TW 101140943A TW 201418730 A TW201418730 A TW 201418730A
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Taiwan
Prior art keywords
interposer
testing
semiconductor package
semiconductor wafer
semiconductor
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TW101140943A
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English (en)
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TWI487921B (zh
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黃品誠
林畯棠
曾文聰
賴顗喆
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矽品精密工業股份有限公司
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Priority to TW101140943A priority Critical patent/TWI487921B/zh
Priority to US13/845,698 priority patent/US8987012B2/en
Publication of TW201418730A publication Critical patent/TW201418730A/zh
Application granted granted Critical
Publication of TWI487921B publication Critical patent/TWI487921B/zh

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Abstract

一種半導體封裝件之測試方法，係包括：將至少一中介板接置於一膠層之頂面上，該中介板係具有相對之第一表面與第二表面，該第二表面上設有複數導電元件，該中介板係藉該導電元件接置於該膠層上；於該中介板之第一表面上接置至少一半導體晶片，並經由該導電元件對半導體晶片進行電性測試步驟，其中，若該半導體晶片之數量為複數，則重複接置該半導體晶片與電性測試之步驟；以及移除該膠層。本發明係可節省半導體封裝件之製程成本與設備成本，並增進製程良率。

Description

半導體封裝件之測試方法
本發明係有關於一種測試方法，尤指一種半導體封裝件之測試方法。
覆晶(flipchip)技術由於具有縮小晶片封裝面積及縮短訊號傳輸路徑等優點，目前已經廣泛應用於晶片封裝領域，例如晶片尺寸構裝(Chip Scale Package，CSP)、晶片直接貼附(Direct Chip Attached，DCA)封裝以及多晶片模組(Multi-Chip Module，MCM)封裝等封裝型態，其均利用覆晶技術而達到封裝的目的。
在覆晶封裝製程中，由於體積較小的半導體晶片與線路基板間之熱膨脹係數的差異甚大，因此半導體晶片外圍的導電凸塊無法與線路基板上對應的電性接點形成良好的接合(半導體晶片體積較小時，其導電凸塊體積相對較小，故與線路基板之接著強度變小)，使得導電凸塊可能自線路基板上剝離。
另一方面，隨著半導體晶片上的積體電路之積集度的增加，體積較小的半導體晶片與線路基板之間的熱膨脹係數不匹配(mismatch)所產生的熱應力(thermal stress)與翹曲(warpage)現象也日漸嚴重，其結果將導致半導體晶片與線路基板之間的可靠度(reliability)下降，並且造成信賴性測試的失敗。
此外，習知封裝基板表面係以二維(2D)方式佈設複數 個晶片於封裝基板上，隨者佈設數目越多，其封裝基板面積亦須隨之擴大，現今為迎合終端產品體積微型化及高效能的需求，其習知之封裝方式及封裝結構已不敷使用。
為了解決上述問題，習知遂提出了一種半導體封裝件，如第1圖所示，其係於一整片矽晶圓中形成有矽穿孔(Through silicon via，TSV)111後，再將該矽晶圓欲接置半導體晶片之一側形成線路重佈層12，再將欲接置基板之一側之表面形成有銲球13，並在經過切單製程後，成為複數矽中介板(Si interposer)11，之後再藉由凸塊18將半導體晶片14接置於該矽中介板11上，後續於該半導體晶片14與矽中介板11之間形成底膠15，最後再將該矽中介板11接置於基板16上，且該矽中介板11與基板16之間亦須填充有底膠17，該基板16之底面設置有複數銲球19，而完成一半導體封裝件，由於該矽中介板11與半導體晶片14的材質相近，因此可以有效避免熱膨脹係數不匹配所產生的問題，且矽中介板11與半導體晶片14接置之一側係以半導體晶圓製程製作出之線路，該半導體晶片14欲接置該線路之接點或線路亦為半導體晶圓製程製作出，故該矽中介板11可在不放大面積的情況下，容置複數半導體晶片14；又為了符合功能設計或電路設計需要，該等半導體晶片14亦可用堆疊方式達成，故可符合現今終端產品輕薄短小及高功能之需求。又該底膠15,17係可保護銲球13與凸塊18不受外界環境影響或污染。
此外，相較於直接將體積較小之半導體晶片接置於基 板之舊有技術，前述半導體封裝件係以該矽中介板11做為一轉接板，而該矽中介板11係使用半導體製程而能達到與該半導體晶片14相近之細線寬/線距，因此能有效將細線寬/線距之半導體晶片14藉由接置至該矽中介板11以連接至基板16，以縮小整體半導體封裝件之體積，且由於該矽中介板11之細線寬/線距特性會使得電性連接距離縮短，所以亦能增進整體電性傳輸速度。
惟，習知業界之電性測試方式係先將一半導體晶片14接置於該基板16上的矽中介板11上，並經由該銲球19進行第一次電性測試，第一次電性測試通過後再於該矽中介板11上接置另一半導體晶片14，並進行第二次電性測試，如此則可避免一次將所有半導體晶片14接置於矽中介板11上後再進行最終電性測試時，僅因該矽中介板11或其中一半導體晶片14製作不良而使得其他正常的半導體晶片14必須連同報廢之缺點，此外，前述習知之電性測試方式仍需花費許多時間，使得整體產能(throughput)下降。
因此，如何避免上述習知技術中之種種問題，實已成為目前亟欲解決的課題。
有鑒於上述習知技術之缺失，本發明提供一種半導體封裝件之測試方法，係包括：將至少一中介板接置於一膠層之頂面上，該中介板係具有相對之第一表面與第二表面，該第二表面上設有複數導電元件，該中介板係藉該導 電元件接置於該膠層上；於該中介板之第一表面上接置至少一半導體晶片，並經由該導電元件對半導體晶片進行電性測試步驟，其中，若該半導體晶片之數量為複數，則重複接置該半導體晶片與電性測試之步驟；以及移除該膠層。
於前述之半導體封裝件之測試方法中，於進行該電性測試步驟之前，復包括形成複數對應外露該導電元件的膠層通孔，該膠層通孔係藉由熱燒灼移除或機械鑽孔方式形成，且該熱燒灼移除方式係使用雷射。
依上所述之方法，該膠層通孔之孔徑係大於25微米，且小於75微米，並於接置該中介板於膠層之後與接置該半導體晶片之前，或者，於進行電性測試步驟之後與移除該膠層之前，復包括對該中介板進行切單步驟，且復包括藉由空氣吸力或靜電力使該膠層之底面平貼於一載台上。
又於本發明之半導體封裝件之測試方法中，於移除該膠層之後，復包括使該中介板係藉該導電元件結合於一基板之頂面上，且該中介板與該基板之結合係藉由回焊方式。
於前述之半導體封裝件之測試方法中，該中介板係為含矽之材質，且該中介板中具有複數個連接半導體晶片及導電元件之導電穿孔，該基板之底面復具有複數銲球，且復包括經由該等銲球進行電性測試步驟。
由上可知，因為本發明於電性測試時無須存在有基板，而直接測試中介板與半導體晶片，以提前檢驗出不良之半導體晶片或中介板，所以可降低製程成本，且本發明可將中介板與半導體晶片視為一傳統倒裝晶片製程中的半 導體晶片，而能直接使用既有之倒裝晶片製程機台，以節省設備成本；此外，本發明可藉由將膠層平坦化或藉由提供未經切單之中介板以減少中介板之翹曲問題，進而增進半導體晶片接合至中介板的良率。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「底」、「頂」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2H圖所示者，係本發明之半導體封裝件之測試方法的剖視圖。
如第2A圖所示，將一中介板21接置於一膠層20之頂面上，該中介板21係具有相對之第一表面21a與第二表面21b，該中介板21係為含矽之材質，該第二表面21b上 設有複數導電元件22，該中介板21係藉該導電元件22接置於該膠層20上，又該膠層20之周緣可附接至一圓環件(未圖示)，且可藉由空氣吸力或靜電力使該膠層20之底面平貼於一載台(未圖示)上，使該膠層20維持平整，以提升後續製程之良率。
如第2B圖所示，於該中介板21之第一表面21a上接置一半導體晶片23a，該中介板21中具有複數個連接半導體晶片23a及導電元件22之導電穿孔(未圖示)，該半導體晶片23a係藉其上的金屬凸塊231a連接該中介板21，該中介板21與半導體晶片23a之間係形成有底部填充材24a，例如毛細底膠(capillary underfill)或非導電膏(Non-Conductive Paste，NCP)，該半導體晶片23a係可使用熱壓結合(Thermal Compression Bonding，TCB)之方式將其上之金屬凸塊231a與該中介板21的凸塊墊(bump pad)(未圖示)做結合；接著，使用傳統倒裝晶片之回焊製程，使該金屬凸塊231a上的銲料(未圖示)完全熔融，並與該中介板21的凸塊墊完全結合，並生成金屬間化合物(Inter-Metallic Compound，IMC)(未圖示)。
如第2C圖所示，形成複數對應外露該導電元件22的膠層通孔200a，其中，該膠層通孔200a係可藉由熱燒灼移除或機械鑽孔方式形成，且該熱燒灼移除方式係可使用雷射，又該膠層通孔200a之孔徑係大於25微米以容許後續之電性測試用探針通過，且小於75微米以避免該導電元件22掉入。
如第2D圖所示，重複第2B圖之步驟，以於該中介板21之第一表面21a上接置另一半導體晶片23b。
如第2E圖所示，重複第2C圖之步驟，以形成複數對應外露該導電元件22的另一膠層通孔200b。
如第2F圖所示，運用加熱、化學或機械方式，以去除或降低該膠層20的黏性，並移除該膠層20。
如第2G圖所示，使用傳統倒裝晶片之回焊製程，使該中介板21係藉該導電元件22結合於一基板25之頂面上，且該基板25之頂面上設有圍繞該中介板21之框體26，其中，於該中介板21結合於該基板25上之過程中，其周遭環境係維持在100℃以上，以有效減低該基板25的翹曲程度。
如第2H圖所示，於該框體26上接置一連接該半導體晶片23a,23b之頂面的蓋體27，該框體26與蓋體27係構成一散熱件，以將該半導體晶片23a,23b的熱量傳導至外界，接著，於該基板25之底面設置複數銲球28，並經由該等銲球28進行電性測試步驟(例如以電性測試用探針接觸該銲球28)。
要補充說明的是，本實施例係以經切單後之中介板21為例，於其他實施例中，可於該膠層20上接置一未經切單之中介板21，並於進行第2F圖之步驟後，對該中介板21進行切單步驟；此外，復可於接置該中介板21於膠層20之後與接置該半導體晶片23a,23b之前，或者，於進行電性測試步驟之後與移除該膠層20之前，對該中介板21進 行切單步驟，惟此係所屬技術領域中具有通常知識者依據本說明書而能理解，故不在此贅述。
綜上所述，相較於習知技術，由於本發明於電性測試時無須存在有基板，而直接測試中介板與半導體晶片，以提前檢驗出不良之半導體晶片或中介板，所以可降低製程成本，且本發明可將中介板與半導體晶片視為一傳統倒裝晶片(Flip chip)製程中的半導體晶片，而能直接使用既有之倒裝晶片製程機台，以節省設備成本；此外，本發明可藉由將膠層平坦化或藉由提供未經切單之中介板以減少中介板之翹曲問題，進而增進半導體晶片接合至中介板的良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
11‧‧‧矽中介板
111‧‧‧矽穿孔
12‧‧‧線路重佈層
13、19、28‧‧‧銲球
14‧‧‧半導體晶片
15、17‧‧‧底膠
16、25‧‧‧基板
18‧‧‧凸塊
20‧‧‧膠層
200a、200b‧‧‧膠層通孔
21‧‧‧中介板
21a‧‧‧第一表面
21b‧‧‧第二表面
22‧‧‧導電元件
23a、23b‧‧‧半導體晶片
231a‧‧‧金屬凸塊
24a‧‧‧底部填充材
26‧‧‧框體
27‧‧‧蓋體
第1圖所示者係習知之半導體封裝件之剖視圖；以及第2A至2H圖所示者係本發明之半導體封裝件之測試方法的剖視圖。
20‧‧‧膠層
200a‧‧‧膠層通孔
21‧‧‧中介板
21a‧‧‧第一表面
21b‧‧‧第二表面
22‧‧‧導電元件
23a‧‧‧半導體晶片
231a‧‧‧金屬凸塊
24a‧‧‧底部填充材

Claims (11)

  1. 一種半導體封裝件之測試方法，係包括：將至少一中介板接置於一膠層之頂面上，該中介板係具有相對之第一表面與第二表面，該第二表面上設有複數導電元件，該中介板係藉該導電元件接置於該膠層上；於該中介板之第一表面上接置至少一半導體晶片，並經由該導電元件對半導體晶片進行電性測試步驟，其中，若該半導體晶片之數量為複數，則重複接置該半導體晶片與電性測試之步驟；以及移除該膠層。
  2. 如申請專利範圍第1項所述之半導體封裝件之測試方法，於進行該電性測試步驟之前，復包括形成複數對應外露該導電元件的膠層通孔。
  3. 如申請專利範圍第2項所述之半導體封裝件之測試方法，其中，該膠層通孔係藉由熱燒灼移除或機械鑽孔方式形成。
  4. 如申請專利範圍第3項所述之半導體封裝件之測試方法，其中，該熱燒灼移除方式係使用雷射。
  5. 如申請專利範圍第2項所述之半導體封裝件之測試方法，其中，該膠層通孔之孔徑係大於25微米，且小於75微米。
  6. 如申請專利範圍第1項所述之半導體封裝件之測試方法，於接置該中介板於膠層之後與接置該半導體晶片 之前，或者，於進行電性測試步驟之後與移除該膠層之前，復包括對該中介板進行切單步驟。
  7. 如申請專利範圍第1項所述之半導體封裝件之測試方法，復包括藉由空氣吸力或靜電力使該膠層之底面平貼於一載台上。
  8. 如申請專利範圍第1項所述之半導體封裝件之測試方法，於移除該膠層之後，復包括使該中介板係藉該導電元件結合於一基板之頂面上。
  9. 如申請專利範圍第8項所述之半導體封裝件之測試方法，其中，該中介板與該基板之結合係藉由回焊方式。
  10. 如申請專利範圍第1項所述之半導體封裝件之測試方法，其中，該中介板係為含矽之材質，且該中介板中具有複數個連接半導體晶片及導電元件之導電穿孔。
  11. 如申請專利範圍第8項所述之半導體封裝件之測試方法，其中，該基板之底面復具有複數銲球，且復包括經由該等銲球進行電性測試步驟。
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