TW201411799A - An assembly method of die with thick metal - Google Patents
An assembly method of die with thick metal Download PDFInfo
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- TW201411799A TW201411799A TW102116613A TW102116613A TW201411799A TW 201411799 A TW201411799 A TW 201411799A TW 102116613 A TW102116613 A TW 102116613A TW 102116613 A TW102116613 A TW 102116613A TW 201411799 A TW201411799 A TW 201411799A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
本發明涉及一種功率半導體器件的製備方法，更確切的說，本發明旨在提供一種帶有底部金屬基座的半導體器件及其製備方法。The present invention relates to a method of fabricating a power semiconductor device, and more particularly to a semiconductor device with a bottom metal pedestal and a method of fabricating the same.
功率器件的功耗一般比較大，基於提高器件電氣性能和散熱性能的考慮，通常是將器件的一部分金屬電極從包覆晶片的塑封材料中外露出來，以期獲得最佳的散熱效果。例如美國專利申請US2003/0132531A1中就展示了一種晶片底部電極外露並用於支援表面貼裝技術的半導體封裝結構24，如圖1A所示，金屬罐狀結構12的凹槽內設置有功率晶片MOSFET 10，MOSFET 10一側的漏極通過導電銀漿14粘貼在金屬罐狀結構12的凹槽底部，從而其漏極被傳導到金屬罐狀結構12的凸起邊緣22上，而MOSFET 10另一側的源極接觸端18和柵極接觸端則剛好與凸起邊緣22位於同一側。在金屬罐狀結構12的凹槽內的圍繞在MOSFET10周圍的空隙處還填充有低應力高粘合能力的導電材料16。雖然該封裝結構24在一定程度上解決了散熱問題，但要製備金屬罐狀結構12這樣的物體，在實際生產中其成本不菲，而且要求MOSFET 10被剛好放置並粘貼在罐狀結構12內是比較難以操作和控制的。The power consumption of power devices is generally large. Based on the consideration of improving the electrical performance and heat dissipation performance of the device, a part of the metal electrodes of the device are usually exposed from the plastic packaging material covering the wafer, in order to obtain the best heat dissipation effect. A semiconductor package structure 24 in which a wafer bottom electrode is exposed and used to support surface mount technology is shown, for example, in US Patent Application No. 2003/0132531 A1. As shown in FIG. 1A, a power chip MOSFET 10 is disposed in a recess of the metal can structure 12. The drain of the MOSFET 10 side is pasted to the bottom of the recess of the can-like structure 12 by the conductive silver paste 14, so that its drain is conducted to the raised edge 22 of the can-like structure 12, and the other side of the MOSFET 10 The source contact end 18 and the gate contact end are just on the same side as the raised edge 22. A low stress and high adhesion ability conductive material 16 is also filled in the void around the MOSFET 10 in the recess of the metal can structure 12. Although the package structure 24 solves the heat dissipation problem to a certain extent, the preparation of an object such as the metal can structure 12 is costly in actual production, and the MOSFET 10 is required to be placed and pasted in the can structure 12. It is more difficult to operate and control.
在如圖1B所示的另一些功率器件的封裝類型中，除了MOSFET 30正面原本就已經設計的焊墊35b之外，MOSFET 30背面的電極33通過額外設計的通孔32及其內部填充的導電材料連接到其正面的焊墊35a上，MOSFET 30被塑封層36和一個帶有中空的腔體的塑封外殼34所密封，焊墊35a、35b通過金屬凸塊37與外部電路互連。但是由於電極33為一較薄的金屬化層，其相對於外殼34的厚度來說就顯得非常薄，導致其散熱效果不佳。In the package type of other power devices as shown in FIG. 1B, in addition to the pad 35b originally designed on the front side of the MOSFET 30, the electrode 33 on the back side of the MOSFET 30 passes through the additionally designed via 32 and its internally filled conductive The material is connected to the pad 35a on the front side thereof, and the MOSFET 30 is sealed by a molding layer 36 and a plastic case 34 having a hollow cavity, and the pads 35a, 35b are interconnected with external circuits by metal bumps 37. However, since the electrode 33 is a thin metallization layer, it is very thin relative to the thickness of the outer casing 34, resulting in poor heat dissipation.
正是基於這些問題，提出了本發明的各種實施方式。Based on these problems, various embodiments of the present invention have been proposed.
本發明提供一種帶有底部金屬基座的半導體器件的製備方法，包括以下步驟：The invention provides a method for preparing a semiconductor device with a bottom metal pedestal, comprising the following steps:
提供包含多個金屬基座的一引線框架，相鄰的金屬基座通過一個或多個連接部相互連接，每個連接部均包括其背面設置的以沿著遠離該背面的方向延伸的支撐部，所有支撐部的端面均共面；Providing a lead frame including a plurality of metal pedestals, the adjacent metal pedestals being connected to each other by one or more connecting portions, each connecting portion including a supporting portion disposed on a back surface thereof to extend in a direction away from the back surface The end faces of all the support portions are coplanar;
在每個金屬基座的正面粘貼一個正面覆蓋有頂部塑封層和背面覆蓋有背部金屬層的晶片，且所述背部金屬層粘貼至金屬基座的正面；Attaching a front surface of each metal base to a front surface of the wafer covered with a top plastic layer and a back surface covered with a back metal layer, and the back metal layer is pasted to the front surface of the metal base;
形成將各金屬基座、連接部、帶有頂部塑封層與背部金屬層的晶片予以包覆的塑封體，其包覆方式為使頂部塑封層的上表面、支撐部的端面從塑封體中外露；Forming a plastic body covering each of the metal base, the connecting portion, the wafer with the top plastic sealing layer and the back metal layer, and coating the upper surface of the top plastic sealing layer and the end surface of the supporting portion from the plastic sealing body ;
對相鄰金屬基座之間的疊層實施切割，該疊層包括塑封體和連接部，以將塑封體、各金屬基座及各帶有頂部塑封層與背部金屬層的晶片分離成多個單獨的半導體器件。Cutting the laminate between adjacent metal pedestals, the laminate comprising a molding body and a connecting portion to separate the molding body, the metal pedestals and the wafers each having the top molding layer and the back metal layer into a plurality of A separate semiconductor device.
上述的方法，形成所述塑封體之前，先將一層粘貼膜粘附至各支撐部的端面及將另一粘貼膜粘附至各頂部塑封層的上表面，並在形成所述塑封體之後，將該兩層粘貼膜剝離掉。In the above method, before the molding body is formed, a bonding film is adhered to the end faces of the respective supporting portions and another bonding film is adhered to the upper surface of each of the top molding layers, and after the molding body is formed, The two-layer adhesive film was peeled off.
上述的方法，利用塑封料形成所述塑封體之後，還包括在所述塑封體的與頂部塑封層的上表面共面的表面上實施研磨的步驟，以除去塑封料覆蓋在頂部塑封層的上表面的溢料部分。The above method, after the molding body is formed by using a molding compound, further comprising the step of performing grinding on a surface of the molding body coplanar with the upper surface of the top molding layer to remove the molding compound over the top molding layer The flash portion of the surface.
上述的方法，每個晶片及其頂部塑封層、背部金屬層各自周邊外側所包覆的所述塑封體經切割後形成包覆在它們周邊外側的一個第一側部塑封體。In the above method, the molded body covered by the outer periphery of each of the wafer and the top plastic layer and the back metal layer is cut to form a first side molding body coated on the outer side of the periphery thereof.
上述的方法，每個金屬基座周邊外側所包覆的所述塑封體經切割後形成包覆在它周邊外側的一個第二側部塑封體。In the above method, the molding body covered on the outer side of each metal base is cut to form a second side molding body covering the outer side of the periphery thereof.
上述的方法，每個金屬基座周邊外側所包覆的所述塑封體被完全切割掉，使金屬基座的側面是裸露的。In the above method, the plastic body covered on the outer side of each metal base is completely cut off, so that the side of the metal base is bare.
上述的方法，所述金屬基座的厚度小於支撐部的端面到金屬基座的正面所在平面間的距離，使每個金屬基座的背面被所述塑封體包覆住，且包覆在該背面處的塑封體經切割後形成一底部塑封層。In the above method, the thickness of the metal base is smaller than the distance between the end surface of the support portion and the plane of the front surface of the metal base, so that the back surface of each metal base is covered by the plastic body, and is covered by the method. The molding body at the back side is cut to form a bottom molding layer.
上述的方法，所述金屬基座的厚度等於支撐部的端面到金屬基座的正面所在平面間的距離，金屬基座的背面與所述端面共面，且塑封體的包覆方式為使金屬基座的背面從塑封體中外露。In the above method, the thickness of the metal base is equal to the distance between the end surface of the support portion and the plane of the front surface of the metal base, the back surface of the metal base is coplanar with the end surface, and the plastic body is covered by a metal The back of the base is exposed from the molded body.
上述的方法，在金屬基座的背面靠近其周邊處形成有凹陷於其背面的並且豎截面呈臺階狀的一環形凹槽，並在完成對所述疊層實施切割後，填充在該凹槽內的塑封體被分割形成一個環形塑封體。In the above method, an annular groove recessed on the back surface thereof and having a stepped shape in a vertical section is formed near the periphery of the metal base, and is filled in the groove after the cutting is completed. The inner molding body is divided to form an annular molding body.
上述的方法，所述連接部及其支撐部為一“T”形結構。In the above method, the connecting portion and the supporting portion thereof have a "T" shape structure.
上述的方法，所述支撐部為一個溝道形結構，包括一平行於金屬基座的沉降部分以及連接在其兩側的並將其連接在連接部上的兩個側翼。In the above method, the support portion is a channel-shaped structure including a sinker portion parallel to the metal base and two side flaps connected to both sides thereof and connected to the joint portion.
在一些實施方式中，本發明提供一種帶有底部金屬基座的半導體器件，包括：In some embodiments, the present invention provides a semiconductor device with a bottom metal pedestal comprising:
一正面覆蓋有頂部塑封層和背面覆蓋有背部金屬層的晶片，並在所述晶片正面設置有多個金屬凸塊，以及頂部塑封層包覆在各金屬凸塊側壁的周圍並使金屬凸塊從頂部塑封層中予以外露；a front surface is covered with a top plastic sealing layer and a back surface covered with a back metal layer, and a plurality of metal bumps are disposed on the front surface of the wafer, and a top plastic sealing layer is wrapped around the sidewalls of the metal bumps and the metal bumps are Exposed from the top plastic seal;
一金屬基座，所述晶片以其背部金屬層粘貼至金屬基座的正面的方式安裝在所述金屬基座上；a metal base, the wafer is mounted on the metal base with a metal layer of the back attached to the front surface of the metal base;
一包覆在所述金屬基座的背面的底部塑封層；a bottom molding layer covering the back side of the metal base;
一包覆在晶片和頂部塑封層及背部金屬層各自周邊外側的第一側部塑封體。A first side molding body covering the wafer and the outer periphery of each of the top plastic layer and the back metal layer.
上述的帶有底部金屬基座的半導體器件，每個金屬基座周邊外側包覆有一個第二側部塑封體，並且第一、第二側部塑封體和所述底部塑封層是一體化的結構。In the above semiconductor device with a bottom metal base, each of the metal bases is coated on the outer side with a second side molding body, and the first and second side molding bodies and the bottom molding layer are integrated. structure.
上述的帶有底部金屬基座的半導體器件，每個金屬基座的側面是裸露的，並且第一側部塑封體、底部塑封層被金屬基座隔離開。In the above semiconductor device with a bottom metal base, the side of each metal base is bare, and the first side molding body and the bottom plastic sealing layer are separated by the metal base.
在一些實施方式中，本發明提供一種帶有底部金屬基座的半導體器件，包括：In some embodiments, the present invention provides a semiconductor device with a bottom metal pedestal comprising:
一正面覆蓋有頂部塑封層和背面覆蓋有背部金屬層的晶片，並在所述晶片正面設置有多個金屬凸塊，以及頂部塑封層包覆在各金屬凸塊側壁的周圍並使金屬凸塊從頂部塑封層中予以外露；a front surface is covered with a top plastic sealing layer and a back surface covered with a back metal layer, and a plurality of metal bumps are disposed on the front surface of the wafer, and a top plastic sealing layer is wrapped around the sidewalls of the metal bumps and the metal bumps are Exposed from the top plastic seal;
一金屬基座，所述晶片以其背部金屬層粘貼至金屬基座的正面的方式安裝在所述金屬基座上；a metal base, the wafer is mounted on the metal base with a metal layer of the back attached to the front surface of the metal base;
其中，在金屬基座的背面靠近其周邊處形成有凹陷於其背面的並且豎截面呈臺階狀的一環形凹槽，在該凹槽內填充有一個環形塑封體；Wherein, an annular groove is formed on the back surface of the metal base near the periphery thereof and has a stepped shape in a vertical section, and the groove is filled with an annular molding body;
一包覆在晶片和頂部塑封層及背部金屬層各自周邊外側的第一側部塑封體。A first side molding body covering the wafer and the outer periphery of each of the top plastic layer and the back metal layer.
上述的帶有底部金屬基座的半導體器件，每個金屬基座周邊外側包覆有一個第二側部塑封體，並且第一、第二側部塑封體和所述底部塑封層是一體化的結構。In the above semiconductor device with a bottom metal base, each of the metal bases is coated on the outer side with a second side molding body, and the first and second side molding bodies and the bottom molding layer are integrated. structure.
上述的帶有底部金屬基座的半導體器件，每個金屬基座的側面是裸露的，並且第一側部塑封體和環形塑封體被金屬基座隔離開。In the above semiconductor device with a bottom metal base, the side of each metal base is bare, and the first side molding body and the annular molding body are separated by the metal base.
本領域的技術人員閱讀以下較佳實施例的詳細說明，並參照附圖之後，本發明的這些和其他方面的優勢無疑將顯而易見。These and other advantages of the present invention will no doubt become apparent to those skilled in the <RTIgt;
100．．．晶圓100. . . Wafer
110．．．焊墊110. . . Solder pad
111．．．金屬凸塊111. . . Metal bump
120．．．第一塑封層120. . . First plastic seal
103．．．第一環形區103. . . First annular zone
121．．．基準線121. . . Baseline
150．．．凹槽150. . . Groove
100a．．．支撐環100a. . . Support ring
130．．．金屬層130. . . Metal layer
140．．．粘貼膜140. . . Adhesive film
200A．．．半導體器件200A. . . Semiconductor device
240．．．切割刀240. . . Cutting knife
115．．．切口115. . . incision
101．．．晶片101. . . Wafer
120'．．．頂部塑封層120'. . . Top plastic layer
130'．．．底部金屬層130'. . . Bottom metal layer
200A．．．初級器件200A. . . Primary device
3000．．．引線框架3000. . . Lead frame
300．．．金屬基座300. . . Metal base
301．．．連接部301. . . Connection
302．．．支撐部302. . . Support
302a．．．端面302a. . . End face
305．．．粘合材料305. . . Adhesive material
311．．．粘貼膜311. . . Adhesive film
312．．．粘貼膜312. . . Adhesive film
307．．．塑封體307. . . Plastic body
350．．．半導體器件350. . . Semiconductor device
307a．．．第一側部塑封體307a. . . First side plastic body
355．．．切囗355. . . Cut
307c．．．第二側部塑封體307c. . . Second side plastic body
307b．．．底部塑封層307b. . . Bottom plastic seal
350'．．．半導體器件350'. . . Semiconductor device
3000'．．．引線框架3000'. . . Lead frame
3021a．．．端面3021a. . . End face
3020．．．支撐部3020. . . Support
3021．．．沉降部分3021. . . Settling part
3022．．．側翼3022. . . flank
3021a．．．端面3021a. . . End face
4000．．．引線框架4000. . . Lead frame
300a．．．環形凹槽300a. . . Annular groove
307d．．．塑封體307d. . . Plastic body
450．．．半導體器件450. . . Semiconductor device
參考所附附圖，以更加充分的描述本發明的實施例。然而，所附附圖僅用於說明和闡述，並不構成對本發明範圍的限制。Embodiments of the present invention are described more fully with reference to the accompanying drawings. However, the attached drawings are for illustration and illustration only and are not intended to limit the scope of the invention.
圖1A~1B是背景技術涉及的封裝類型。1A to 1B are package types related to the background art.
圖2A~2J是本發明減薄晶圓並獲得正面帶有頂部塑封層和背面帶有背部金屬層的晶片的流程示意圖。2A-2J are schematic views showing the process of thinning a wafer of the present invention and obtaining a wafer having a top molding layer on the front side and a back metal layer on the back side.
圖3A是本發明中第一種引線框架的俯視圖。Figure 3A is a top plan view of a first lead frame in the present invention.
圖3B~3E是圖3A中引線框架的剖面圖。3B to 3E are cross-sectional views of the lead frame of Fig. 3A.
圖4A~4D是利用圖3A中引線框架實施封裝的流程示意圖。4A-4D are schematic flow diagrams of implementing a package using the lead frame of FIG. 3A.
圖5A~5C是利用圖3A中引線框架的另一種結構類型實施封裝的流程示意圖。5A-5C are schematic flow diagrams of implementing a package using another type of structure of the lead frame of FIG. 3A.
圖6A~6B是利用圖3A中引線框架形成的半導體器件的剖面結構示意圖。6A-6B are schematic cross-sectional views of a semiconductor device formed using the lead frame of Fig. 3A.
圖7A是本發明中第二種引線框架的俯視圖。Figure 7A is a top plan view of a second lead frame in the present invention.
圖7B~7E是圖7A中引線框架的剖面圖。7B to 7E are cross-sectional views of the lead frame of Fig. 7A.
圖8A~8D是利用圖7A中引線框架實施封裝的流程示意圖。8A-8D are schematic flow diagrams of implementing a package using the lead frame of FIG. 7A.
圖9A~9B是利用圖7A中引線框架形成的半導體器件的剖面結構示意圖。9A to 9B are schematic cross-sectional views of a semiconductor device formed using the lead frame of Fig. 7A.
參見圖2A所示的晶圓100的豎截面圖，晶圓100通常包含有大量鑄造連接在一起的晶片，其正面設置有多條縱向及橫向的切割道（scribe line），來界定相鄰晶片之間的邊界，並可以據此作為切割參照目標而在後續的切割工藝中將各晶片從晶圓上分離下來。而且任意一個晶片的正面均預先製備有若干個金屬焊墊110來作為晶片接電源、GND的電極，或是與外界電路進行信號傳輸的埠等。一般通常會先在各焊墊110上鍍上一層凸點下金屬層UBM（未示出），例如Ni/Au，然後再將金屬凸塊111焊接在各焊墊110上，典型的金屬凸塊111如焊錫球，或球狀或柱狀或楔形等各種形狀的銅塊或其他金屬體等，然後形成第一塑封層120覆蓋在晶圓100的正面，第一塑封層120通常是利用環氧樹脂類的塑封料作為原料來製備。在一個可選實施例中，第一塑封層120僅僅是覆蓋在晶圓100正面的中心區域，並沒有將其正面的所有區域完全覆蓋住，如圖2C的豎截面圖，第一塑封層120的橫截面大體上也是圓形，其半徑小於晶圓的半徑，所以會在晶圓100正面靠近其邊緣處留下未被第一塑封層120所覆蓋的一個第一環形區103，並且每條切割道的兩端籍此而延伸至第一環形區103內。Referring to the vertical cross-sectional view of the wafer 100 shown in FIG. 2A, the wafer 100 generally includes a plurality of wafers that are cast together, and a plurality of longitudinal and lateral scribe lines are disposed on the front surface to define adjacent wafers. The boundaries between and can be used as a cutting reference target to separate the wafers from the wafer in a subsequent dicing process. Moreover, a plurality of metal pads 110 are prepared in advance on the front surface of any one of the wafers as electrodes for connecting the power source to the GND, or for transmitting signals to the external circuit. Generally, each of the pads 110 is first plated with a sub-bump metal layer UBM (not shown), such as Ni/Au, and then the metal bumps 111 are soldered to the pads 110, typical metal bumps. 111 such as solder balls, or copper or other metal bodies of various shapes such as spherical or columnar or wedge-shaped, etc., and then forming a first plastic sealing layer 120 covering the front surface of the wafer 100, and the first plastic sealing layer 120 is usually made of epoxy. A resin type molding compound is prepared as a raw material. In an alternative embodiment, the first molding layer 120 is only covered in the central area of the front side of the wafer 100, and does not completely cover all areas of the front surface thereof, as shown in the vertical cross-sectional view of FIG. 2C, the first molding layer 120. The cross section is also generally circular in shape with a radius smaller than the radius of the wafer, so that a first annular region 103 not covered by the first plastic encapsulation layer 120 is left near the edge of the wafer 100, and each Both ends of the scribe line extend into the first annular zone 103 by this.
如圖2C~2D所示，如果第一塑封層120完全將各金屬凸塊111包覆住，還需要研磨減薄第一塑封層120，直至金屬凸塊111從第一塑封層120中外露出來。之後可沿每條切割道延伸至第一環形區103內的兩端構成的直線對第一塑封層120實施切割，如圖2E所示在第一塑封層120上切割出多條長條狀的槽體結構來作為基準線121。由於第一塑封層120的物理支撐作用，增加了晶圓100的機械強度，所以晶圓100可以研磨得足夠薄。在圖2F中，翻轉晶圓100至其背面的一側朝上，利用未示意出的研磨輪在晶圓100背面的中心區域進行研磨，形成一圓形凹槽150並籍此獲得晶圓的薄型化區域，此步驟中，同時保留晶圓100周邊部分的原始厚度，所以在其背面的一側，靠近其邊緣處形成了一支撐環100a。設定圓形凹槽150的半徑小於第一塑封層120的半徑，則支撐環100a具有與第一塑封層120形成交疊的部分，這進一步提高了晶圓的機械強度。As shown in FIG. 2C to FIG. 2D, if the first plastic sealing layer 120 completely covers the metal bumps 111, it is necessary to polish and thin the first plastic sealing layer 120 until the metal bumps 111 are exposed from the first plastic sealing layer 120. . Then, the first plastic sealing layer 120 can be cut along a straight line extending from each of the cutting paths to the two ends in the first annular region 103, and a plurality of strips are cut on the first plastic sealing layer 120 as shown in FIG. 2E. The trough structure is used as the reference line 121. Due to the physical support of the first mold layer 120, the mechanical strength of the wafer 100 is increased, so the wafer 100 can be ground sufficiently thin. In FIG. 2F, the side of the wafer 100 is turned upside down, and the center of the back surface of the wafer 100 is ground by an unillustrated grinding wheel to form a circular groove 150. The thinned region, in this step, retains the original thickness of the peripheral portion of the wafer 100, so that on one side of the back side, a support ring 100a is formed near the edge thereof. Setting the radius of the circular groove 150 to be smaller than the radius of the first plastic seal layer 120, the support ring 100a has a portion overlapping the first plastic seal layer 120, which further improves the mechanical strength of the wafer.
之後如圖2G~2H所示，在減薄背面沉積一層金屬層130，然後利用鐳射切割的方式將晶圓100的帶有支撐環100a的周邊部分切割掉。如圖2I所示，翻轉晶圓100至其帶有的金屬層130的減薄背面的一側朝下，並在金屬層130上粘附一層粘貼膜140，沿著基準線121對第一塑封層120及晶圓100和金屬層130實施切割，從而將它們分離成多顆單獨的初級半導體器件200A，以備對其進行二次封裝。如圖2J所示，切割刀240在它們中形成了切口115，並且晶圓100經切割後形成多顆獨立的晶片101，第一塑封層120經切割後形成覆蓋在晶片101正面的頂部塑封層120'，金屬層130經切割後形成位於晶片101背面的底部金屬層130'。在初級器件200A中，包含晶片101、頂部塑封層120'、底部金屬層130'，和焊接在晶片101的焊墊110上的金屬凸塊111，其頂部塑封層120'包覆在各金屬凸塊111的側壁的周圍，金屬凸塊111均從頂部塑封層120'中外露。Thereafter, as shown in FIGS. 2G to 2H, a metal layer 130 is deposited on the thinned back surface, and then the peripheral portion of the wafer 100 with the support ring 100a is cut by laser cutting. As shown in FIG. 2I, the wafer 100 is flipped to the side of the thinned back side of the metal layer 130 with the side facing down, and a layer of adhesive film 140 is adhered to the metal layer 130, and the first plastic package is adhered along the reference line 121. Layer 120 and wafer 100 and metal layer 130 are diced to separate them into a plurality of individual primary semiconductor devices 200A for secondary packaging. As shown in FIG. 2J, the dicing blade 240 forms a slit 115 therein, and the wafer 100 is diced to form a plurality of individual wafers 101, and the first plastic sealing layer 120 is diced to form a top molding layer covering the front surface of the wafer 101. 120', the metal layer 130 is diced to form a bottom metal layer 130' on the back side of the wafer 101. In the primary device 200A, a wafer 101, a top plastic encapsulation layer 120', a bottom metal layer 130', and a metal bump 111 soldered on the pad 110 of the wafer 101 are coated with a top plastic encapsulation layer 120' overlying each metal bump. Around the sidewalls of the block 111, the metal bumps 111 are all exposed from the top molding layer 120'.
在圖3A中，引線框架3000包含了多個金屬基座300，這些基座300呈陣列式排列，並且相鄰的金屬基座300通過一個或多個連接部301相互連接，每個連接部301均包括設置在其背面一側的以沿著遠離該背面的方向延伸的支撐部302，其延伸的方向與引線框架3000所在的平面正交，並且所有支撐部302的端面302a也即各底面均共面。為了更詳盡的介紹引線框架3000的結構，其中，圖3B、3C、3D、3E分別是引線框架3000沿著虛線AA、BB、CC、DD的豎截面圖。在該實施方式中，基座300的正面及相對的背面之間的厚度值T1，要小於支撐部302的端面302a到基座302的正面所在的平面之間的距離T2。In FIG. 3A, the lead frame 3000 includes a plurality of metal pedestals 300, which are arranged in an array, and adjacent metal pedestals 300 are connected to each other by one or more connecting portions 301, each of which is connected to each other. Each includes a support portion 302 disposed on a side of the back side thereof in a direction away from the back surface, the direction of extension thereof being orthogonal to the plane in which the lead frame 3000 is located, and the end faces 302a of all the support portions 302, that is, the respective bottom surfaces are Coplanar. In order to introduce the structure of the lead frame 3000 in more detail, FIGS. 3B, 3C, 3D, and 3E are vertical sectional views of the lead frame 3000 along the broken lines AA, BB, CC, and DD, respectively. In this embodiment, the thickness value T1 between the front surface and the opposite back surface of the susceptor 300 is smaller than the distance T2 between the end surface 302a of the support portion 302 and the plane where the front surface of the susceptor 302 is located.
在圖4A中，將初級半導體器件200A安裝到基座302上，即通過粘合材料305，在每個金屬基座302的正面粘貼一個正面覆蓋有頂部塑封層120'和背面覆蓋有背部金屬層130'的晶片101，並且晶片101以其背部金屬層130'粘貼至金屬基座302的正面的方式安裝在基座302上。然後如圖4B~4C所示，先將一粘貼膜311粘附至各支撐部302的端面302a上，並將另一粘貼膜312粘附在各頂部塑封層120'的上表面，實際上，在塑封的步驟中，在合攏的模腔內，平鋪張開的粘貼膜311、312分別被抵壓在塑封設備的模腔頂壁和模腔底部，塑封料被注入在粘貼膜311、312之間，待塑封料受熱固化之後，便形成了如圖所示的塑封體307。塑封體307將各金屬基座300、連接部301、帶有頂部塑封層120'與背部金屬層130'的晶片101予以包覆，其包覆方式為使頂部塑封層120'的上表面、支撐部302的端面302a從塑封體307中外露。因為固化前呈熔融態的塑封料在受到壓力的條件下很容易侵入到頂部塑封層120'的上表面與粘貼膜312之間，以致形成溢料部分（未示出），導致將金屬凸塊111被覆蓋住，所以形成塑封體307之後，通常還包括在塑封體307的與頂部塑封層120'的上表面共面的表面上實施輕度研磨的步驟，以除去塑封料覆蓋在頂部塑封層120'的上表面的溢料部分。在剝離粘貼膜311、312之後，如圖4D，對相鄰金屬基座300之間的疊層實施切割，該疊層包括了塑封體307和連接部301，以將塑封體307、各金屬基座300及帶有頂部塑封層120'與背部金屬層130'的各晶片101分離成多個單獨的半導體器件350。In FIG. 4A, the primary semiconductor device 200A is mounted on the pedestal 302, that is, by bonding material 305, a front surface of each metal pedestal 302 is pasted with a top plastic layer 120' and a back surface covered with a back metal layer. The wafer 101 of 130' is mounted on the susceptor 302 in such a manner that its back metal layer 130' is affixed to the front side of the metal pedestal 302. Then, as shown in FIGS. 4B to 4C, an adhesive film 311 is adhered to the end surface 302a of each support portion 302, and another adhesive film 312 is adhered to the upper surface of each of the top plastic sealing layers 120'. In the step of molding, in the closed cavity, the flattened adhesive films 311, 312 are respectively pressed against the top wall of the cavity of the molding device and the bottom of the cavity, and the molding compound is injected into the bonding films 311, 312. After the molding compound is cured by heat, a molding body 307 as shown in the drawing is formed. The molding body 307 coats each metal base 300, the connecting portion 301, and the wafer 101 with the top molding layer 120' and the back metal layer 130' in such a manner as to support the upper surface of the top molding layer 120' and support The end surface 302a of the portion 302 is exposed from the molded body 307. Since the molding compound which is in a molten state before curing easily invades between the upper surface of the top molding layer 120' and the bonding film 312 under pressure, a flash portion (not shown) is formed, resulting in the metal bumps. 111 is covered, so after forming the molding body 307, it is usually further included to perform a light grinding step on the surface of the molding body 307 that is coplanar with the upper surface of the top molding layer 120' to remove the molding compound over the top molding layer. The flash portion of the upper surface of 120'. After the adhesive films 311, 312 are peeled off, as shown in FIG. 4D, the laminate between the adjacent metal bases 300 is cut, and the laminate includes a molded body 307 and a connecting portion 301 to seal the molded body 307 and each of the metal bases. The holder 300 and each wafer 101 with the top molding layer 120' and the back metal layer 130' are separated into a plurality of individual semiconductor devices 350.
上述實施例中，如果使用的粘合材料305為導電銀膠，則在執行晶片的粘貼步驟之前，引線框架3000本身就會帶有一個粘貼膜311附著在各端面302a上。另一種情況是，如果使用的粘合材料305為焊錫膏，則需要在完成晶片的粘貼步驟之後，才在各端面302a上粘附一層粘貼膜311。而粘貼膜312則是先行被附著在模腔的頂壁，待完成晶片粘貼步驟之後，引線框架3000被傳送至上下模腔間，上下模腔在合模之後粘貼膜312自然就會粘附在各頂部塑封層120'的上表面。In the above embodiment, if the adhesive material 305 used is a conductive silver paste, the lead frame 3000 itself has an adhesive film 311 attached to each end surface 302a before the wafer bonding step is performed. Alternatively, if the adhesive material 305 used is a solder paste, it is necessary to adhere a paste film 311 to each end surface 302a after the wafer bonding step is completed. The adhesive film 312 is first attached to the top wall of the cavity. After the wafer bonding step is completed, the lead frame 3000 is transferred between the upper and lower mold cavities, and the adhesive film 312 is naturally adhered to the upper and lower mold cavities after the mold clamping. The upper surface of each top molding layer 120'.
參見圖4D，顯示了半導體器件350沿著前述圖3A中虛線AA的方向的豎截面示意圖，而圖6A~6B則顯示了半導體器件350沿著圖3A中虛線DD的方向的豎截面示意圖。每個晶片101及其頂部塑封層120'、背部金屬層130'各自周邊外側所包覆的所述塑封體307經切割後，形成包覆在它們周邊外側的一個第一側部塑封體307a。通常，切口355的寬度取決於切割刀的寬度，也是一個可以人為控制和調節的值，這也決定了基座300的周邊側面是裸露的還是被包覆住。例如在圖6A中，每個金屬基座300周邊外側所包覆的所述塑封體307沒有被完全去除，並且經切割後形成包覆在它周邊外側的一個第二側部塑封體307c。其中，彼此鄰接的第一側部塑封體307a、第二側部塑封體307c均是方筒狀的外殼結構，前者的厚度大於後者。鑒於每個金屬基座300的背面在塑封步驟中也被塑封體307包覆住，並且包覆在該背面處的塑封體307經切割後形成一個底部塑封層307b，此時其與第二側部塑封體307c連接，並且在形成圖6A的器件的切割步驟中，第一側部塑封體307a、第二側部塑封體307c、底部塑封層307b為一體成形的結構。在另一些可選實施方式中，如圖6B，在半導體器件350'中，每個金屬基座300周邊外側所包覆的塑封體307被毫無保留的切割掉，使得金屬基座300的側面是裸露的，此時第一側部塑封體307a、底部塑封層307b被金屬基座300隔離開。在圖6A~6B這樣的實施方式中，金屬基座300無須作為與外部電路進行電性連接的接觸端，此時晶片101可以是共漏極雙MOSFET類的垂直式功率晶片。Referring to FIG. 4D, a vertical cross-sectional view of the semiconductor device 350 along the direction of the broken line AA in FIG. 3A is shown, and FIGS. 6A to 6B are vertical cross-sectional views showing the semiconductor device 350 in the direction of the broken line DD in FIG. 3A. The molding body 307 coated on the outer periphery of each of the wafer 101 and its top plastic sealing layer 120' and the back metal layer 130' is cut to form a first side molding body 307a coated on the outer side of the periphery thereof. Generally, the width of the slit 355 depends on the width of the cutter and is also a value that can be manually controlled and adjusted, which also determines whether the peripheral side of the base 300 is bare or covered. For example, in Fig. 6A, the molding body 307 coated on the outer side of each metal base 300 is not completely removed, and is cut to form a second side molding body 307c coated on the outer side of its periphery. The first side molding body 307a and the second side molding body 307c adjacent to each other are each a square tubular outer casing structure, and the thickness of the former is larger than the latter. Since the back surface of each metal base 300 is also covered by the molding body 307 in the molding step, and the molding body 307 coated at the back surface is cut to form a bottom molding layer 307b, at this time, the second side is The partial molding body 307c is joined, and in the cutting step of forming the device of FIG. 6A, the first side molding body 307a, the second side molding body 307c, and the bottom molding layer 307b are integrally formed structures. In other alternative embodiments, as shown in FIG. 6B, in the semiconductor device 350', the molding body 307 coated on the outer side of each metal base 300 is cut without any reservation, so that the side of the metal base 300 It is bare, in which case the first side molding body 307a and the bottom molding layer 307b are separated by the metal base 300. In the embodiment of FIGS. 6A-6B, the metal pedestal 300 does not need to be a contact end electrically connected to an external circuit. At this time, the wafer 101 may be a vertical power DRAM of a common drain double MOSFET type.
在圖4A~4D的方式中，引線框架3000的結構類型可以通過對原始厚度為T2的金屬平板實施刻蝕來製備，此時連接部301及其支撐部302為一“T”形結構，而在圖5A~5B的實施方式中，另一種結構的引線框架3000'的結構類型可以通過對原始厚度為T1的金屬平板實施壓印或衝壓來製備。原始厚度T1小於端面3021a到基座300正面所在平面的距離T2。在圖5A中，連接部301所包含的支撐部3020為一個溝道形結構，包括一平行於金屬基座300的沉降部分3021以及連接在其兩側的兩個側翼3022，該側翼3022將沉降部分3021連接在連接部301上，沉降部分3021的底面即端面3021a。如圖5C，任何兩個相鄰的基座300間的支撐部3020具有的溝道所延伸的方向，與該兩個基座300之間的對稱中心線相重合或平行。帶有支撐部3020的連接部301在類似圖4D的後續切割步驟中同樣被切割掉。In the manner of FIGS. 4A-4D, the structure type of the lead frame 3000 can be prepared by etching a metal plate having an original thickness of T2, in which case the connecting portion 301 and its supporting portion 302 are a "T"-shaped structure, and In the embodiment of FIGS. 5A to 5B, the structure type of the lead frame 3000' of another structure can be prepared by imprinting or stamping a metal plate having an original thickness of T1. The original thickness T1 is smaller than the distance T2 from the end surface 3021a to the plane of the front surface of the susceptor 300. In FIG. 5A, the supporting portion 3020 included in the connecting portion 301 is a channel-shaped structure including a sinking portion 3021 parallel to the metal base 300 and two side flaps 3022 connected to both sides thereof, and the side flap 3022 will settle. The portion 3021 is connected to the connecting portion 301, and the bottom surface of the settling portion 3021 is the end surface 3021a. As shown in FIG. 5C, the support portion 3020 between any two adjacent pedestals 300 has a direction in which the channel extends, coincident or parallel with the symmetrical centerline between the two susceptors 300. The connection portion 301 with the support portion 3020 is also cut away in a subsequent cutting step similar to that of Fig. 4D.
如圖7A~7E所示，引線框架4000與圖3A的引線框架在結構上並無較大的區別，差異僅僅在於，引線框架4000中金屬基座300的厚度等於支撐部302的端面302a到金屬基座300的正面所在平面間的距離T2，換言之，金屬基座300的背面與端面302a共面。其中，圖7B、7C、7D、7E分別是引線框架4000沿著虛線AA、BB、CC、DD的豎截面圖，引線框架4000也可以通過對原始厚度為T2的金屬平板實施刻蝕來製備。As shown in FIGS. 7A-7E, the lead frame 4000 is not significantly different in structure from the lead frame of FIG. 3A except that the thickness of the metal base 300 in the lead frame 4000 is equal to the end surface 302a of the support portion 302 to the metal. The distance T2 between the planes of the front surface of the susceptor 300, in other words, the back surface of the metal pedestal 300 is coplanar with the end surface 302a. 7B, 7C, 7D, and 7E are vertical cross-sectional views of the lead frame 4000 along the broken lines AA, BB, CC, and DD, respectively, and the lead frame 4000 can also be prepared by etching a metal plate having an original thickness of T2.
在一些實施方式中，在每個金屬基座300的背面靠近其周邊處形成有凹陷於其背面的並且豎截面呈臺階狀的一環形凹槽300a，如圖7D~7E。圖8A~8D是利用引線框架4000來製備半導體器件的方法示意圖，其封裝流程與圖4A~4D大致相同，但是塑封體307的包覆方式為使金屬基座300的背面從塑封體307中外露，並且在完成對前述疊層實施切割後，填充在該凹槽300a內的塑封體307被分割形成了一個環形塑封體307d。與圖6A~6B類似，圖9A~9B是半導體器件450沿著圖7A中虛線DD的方向的豎截面示意圖。在一些實施方式中，每個晶片101及其頂部塑封層120'、背部金屬層130'各自周邊外側所包覆的所述塑封體307經切割後，形成包覆在它們周邊外側的一個第一側部塑封體307a，每個金屬基座300周邊外側所包覆的所述塑封體307經切割後，形成包覆在它周邊外側的一個第二側部塑封體307c。其中，相互鄰接的第一側部塑封體307a、第二側部塑封體307c均是方筒狀的外殼結構，前者的厚度大於後者，而且環形塑封體307d與第二側部塑封體307c連接，並且在圖8D的切割步驟中，第一側部塑封體307a、第二側部塑封體307c、環形塑封體307d為一體成形的結構。在另一些可選實施方式中，如圖9B，每個金屬基座300周邊外側所包覆的塑封體307被毫無保留的切割掉，使金屬基座300的側面是裸露的，此時第一側部塑封體307a、環形塑封體307d被金屬基座300隔離開。此時金屬基座300背面是外露的，可以作為與外部電路進行電性及機械連接的接觸端，在一些實施方式中，晶片101為垂直式的功率晶片，電流由其正面流向背面或相反的方向，典型的如MOSFET等，其多個焊墊110中至少分別包括作為源極、柵極的焊墊，而底部金屬層130'則為漏極。In some embodiments, an annular groove 300a recessed in the back surface thereof and having a stepped vertical section is formed near the periphery of each of the metal bases 300, as shown in FIGS. 7D to 7E. 8A-8D are schematic views showing a method of fabricating a semiconductor device using the lead frame 4000. The packaging process is substantially the same as that of FIGS. 4A to 4D, but the molding body 307 is coated in such a manner that the back surface of the metal substrate 300 is exposed from the molding body 307. And after the cutting of the aforementioned laminate is completed, the molding body 307 filled in the groove 300a is divided to form an annular molding body 307d. Similar to FIGS. 6A to 6B, FIGS. 9A to 9B are vertical sectional views of the semiconductor device 450 in the direction of the broken line DD in FIG. 7A. In some embodiments, the molding body 307 coated on the outer periphery of each of the wafer 101 and the top plastic layer 120' and the back metal layer 130' is cut to form a first coating on the outer side of the periphery thereof. The side molding body 307a, the molding body 307 coated on the outer side of each metal base 300 is cut to form a second side molding body 307c coated on the outer side of the periphery thereof. The first side molding body 307a and the second side molding body 307c adjacent to each other are each a square tubular outer casing structure. The former has a larger thickness than the latter, and the annular molding body 307d is connected to the second side molding body 307c. Further, in the cutting step of FIG. 8D, the first side molding body 307a, the second side molding body 307c, and the annular molding body 307d are integrally formed. In other optional embodiments, as shown in FIG. 9B, the plastic body 307 coated on the outer side of each metal base 300 is cut without any reservation, so that the side of the metal base 300 is bare. The one side molding body 307a and the ring molding body 307d are separated by the metal base 300. At this time, the back surface of the metal base 300 is exposed and can serve as a contact end for electrical and mechanical connection with an external circuit. In some embodiments, the wafer 101 is a vertical power chip, and current flows from the front side to the back side or vice versa. The direction, typically such as a MOSFET, includes at least a pad as a source and a gate, respectively, of the plurality of pads 110, and the bottom metal layer 130' is a drain.
以上，通過說明和附圖，給出了具體實施方式的特定結構的典型實施例，上述發明提出了現有的較佳實施例，但這些內容並不作為局限。對於本領域的技術人員而言，閱讀上述說明後，各種變化和修正無疑將顯而易見。因此，所附的申請專利範圍書應看作是涵蓋本發明的真實意圖和範圍的全部變化和修正。在申請專利範圍書範圍內任何和所有等價的範圍與內容，都應認為仍屬本發明的意圖和範圍內。The exemplary embodiments of the specific structures of the specific embodiments have been described above by way of illustration and the accompanying drawings. Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are intended to cover all such modifications and Any and all equivalent ranges and contents within the scope of the claims are intended to be within the spirit and scope of the invention.
120'．．．頂部塑封層120'. . . Top plastic layer
307．．．塑封體307. . . Plastic body
312．．．粘貼膜312. . . Adhesive film
311．．．粘貼膜311. . . Adhesive film
301．．．連接部301. . . Connection
101．．．晶片101. . . Wafer
Claims (17)
提供包含多個金屬基座的一引線框架，相鄰的金屬基座通過一個或多個連接部相互連接，每個連接部均包括其背面設置的以沿著遠離該背面的方向延伸的支撐部，所有支撐部的端面均共面；
在每個金屬基座的正面粘貼一個正面覆蓋有頂部塑封層和背面覆蓋有背部金屬層的晶片，且所述背部金屬層粘貼至金屬基座的正面；
形成將各金屬基座、連接部、帶有頂部塑封層與背部金屬層的晶片予以包覆的塑封體，其包覆方式為使頂部塑封層的上表面、支撐部的端面從塑封體中外露；
對相鄰金屬基座之間的疊層實施切割，該疊層包括塑封體和連接部，以將塑封體、各金屬基座及各帶有頂部塑封層與背部金屬層的晶片分離成多個單獨的半導體器件。A method of fabricating a semiconductor device with a bottom metal pedestal, comprising the steps of:
Providing a lead frame including a plurality of metal pedestals, the adjacent metal pedestals being connected to each other by one or more connecting portions, each connecting portion including a supporting portion disposed on a back surface thereof to extend in a direction away from the back surface The end faces of all the support portions are coplanar;
Attaching a front surface of each metal base to a front surface of the wafer covered with a top plastic layer and a back surface covered with a back metal layer, and the back metal layer is pasted to the front surface of the metal base;
Forming a plastic body covering each of the metal base, the connecting portion, the wafer with the top plastic sealing layer and the back metal layer, and coating the upper surface of the top plastic sealing layer and the end surface of the supporting portion from the plastic sealing body ;
Cutting the laminate between adjacent metal pedestals, the laminate comprising a molding body and a connecting portion to separate the molding body, the metal pedestals and the wafers each having the top molding layer and the back metal layer into a plurality of A separate semiconductor device.
一正面覆蓋有頂部塑封層和背面覆蓋有背部金屬層的晶片，並在所述晶片正面設置有多個金屬凸塊，以及頂部塑封層包覆在各金屬凸塊側壁的周圍並使金屬凸塊從頂部塑封層中予以外露；
一金屬基座，所述晶片以其背部金屬層粘貼至金屬基座的正面的方式安裝在所述金屬基座上；
一包覆在所述金屬基座的背面的底部塑封層；
一包覆在晶片和頂部塑封層及背部金屬層各自周邊外側的第一側部塑封體。A semiconductor device with a bottom metal pedestal, comprising:
a front surface is covered with a top plastic sealing layer and a back surface covered with a back metal layer, and a plurality of metal bumps are disposed on the front surface of the wafer, and a top plastic sealing layer is wrapped around the sidewalls of the metal bumps and the metal bumps are Exposed from the top plastic seal;
a metal base, the wafer is mounted on the metal base with a metal layer of the back attached to the front surface of the metal base;
a bottom molding layer covering the back side of the metal base;
A first side molding body covering the wafer and the outer periphery of each of the top plastic layer and the back metal layer.
一正面覆蓋有頂部塑封層和背面覆蓋有背部金屬層的晶片，並在所述晶片正面設置有多個金屬凸塊，以及頂部塑封層包覆在各金屬凸塊側壁的周圍並使金屬凸塊從頂部塑封層中予以外露；
一金屬基座，所述晶片以其背部金屬層粘貼至金屬基座的正面的方式安裝在所述金屬基座上；
其中，在金屬基座的背面靠近其周邊處形成有凹陷於其背面的並且豎截面呈臺階狀的一環形凹槽，在該凹槽內填充有一個環形塑封體；
一包覆在晶片和頂部塑封層及背部金屬層各自周邊外側的第一側部塑封體。A semiconductor device with a bottom metal pedestal, comprising:
a front surface is covered with a top plastic sealing layer and a back surface covered with a back metal layer, and a plurality of metal bumps are disposed on the front surface of the wafer, and a top plastic sealing layer is wrapped around the sidewalls of the metal bumps and the metal bumps are Exposed from the top plastic seal;
a metal base, the wafer is mounted on the metal base with a metal layer of the back attached to the front surface of the metal base;
Wherein, an annular groove is formed on the back surface of the metal base near the periphery thereof and has a stepped shape in a vertical section, and the groove is filled with an annular molding body;
A first side molding body covering the wafer and the outer periphery of each of the top plastic layer and the back metal layer.
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Also Published As
| Publication number | Publication date |
|---|---|
| TWI529893B (en) | 2016-04-11 |
| TW201411743A (en) | 2014-03-16 |
| TWI512851B (en) | 2015-12-11 |
| CN103681535A (en) | 2014-03-26 |
| CN103681377A (en) | 2014-03-26 |
| CN103681377B (en) | 2016-09-14 |
| CN103681535B (en) | 2016-10-19 |
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