TWI447798B - Method of avoiding resin outflow from the wafer scribe line in wlcsp - Google Patents

Description

Method for avoiding wafer damage in a wafer level package molding process

The present invention generally relates to a method of fabricating a wafer level package. More specifically, the present invention relates to a method for preventing wafers from being damaged in a wafer level package molding process during preparation of a wafer level package. method.

Unlike traditional chip packaging methods, Wafer Level Chip Scale Packaging (WLCSP) is packaged and tested on a whole wafer before being cut into individual IC particles, so the packaged package is The volume is almost identical to the original size of the bare wafer.

Typically, a wafer (Wafer Saw) is used to separate a plurality of wafers (Die) from the wafer, during which the cutting line of the cutting blade is dependent on a Scribe Line disposed on the wafer.

In the wafer-level packaging molding technique, the molding material is initially in a liquid state or in a liquid state after heating and is solidified after cooling. In order to ensure that the molding compound injection molded on the surface of the wafer has a predetermined molding density, the liquid molding material must have a certain injection pressure in the molding mold. However, the problem of the existence of the cutting channel is that Molding compound with fluidity before curing tends to overflow from the scribe line, resulting in Molding Bleeding at the edge of the wafer, if spilled The mold material bonds the wafer and the mold of the mold mold together, and after the mold is finished, the wafer is broken when the mold is separated from the wafer. Moreover, since part of the molding material overflows from the scribe line of the wafer, the remaining molding material is insufficient to completely cover the front side of the wafer, or the molding density thereof is low.

On the other hand, in the current wafer-level packaging molding technique, the ring-shaped jig of the mold-molding die is pressed at the edge of the front side of the wafer and used to fix the wafer, and the ring-shaped jig is separated from the wafer after the molding is completed. As such, the edge portion of the front side of the wafer is still bare without being covered by the molding compound, which is extremely fragile and affects the normal wafer at the edge of the adjacent wafer when the subsequent wafer is thinned.

U.S. Patent No. 6,107,164 discloses a wafer-level packaged semiconductor device and a semiconductor device manufacturing method. For the fabrication process, see FIG. 1A to FIG. 1D of the present application (refer to the original application, Appendix 3B, 3D, respectively). Fig. 4B, Fig. 4C), this method is an example of fabricating a wafer level package. The electrode 4 is fabricated on the pad 2 on the wafer 10, and the electrode 4 and the pad 2 are connected by a copper interconnect layer 3. The surface of the wafer 10 with the bump electrodes 4 is completely sealed by the resin 23, and the resin 23 is polished until the bump electrodes 4 are exposed and the balls are implanted on the bump electrodes 4. Thereafter, the molded wafer 10 is further diced and separated according to the previous dicing groove 22 to form the wafer level package 1. In this process, the resin 23 is liquid and fluid before being completely cured, and is easy to overflow from the cutting groove 22. If the overflowed resin bonds the wafer 10 and the mold of the mold, the wafer 10 and the jig are separated to cause crystals. The round 10 is broken. Further, it is difficult for the resin 23 having a reduced total amount to completely cover the wafer 10. The technical solution disclosed in this patent cannot avoid the drawback that the wafer 10 is easily broken in its molding process.

U.S. Patent Application Publication No. US20080044984 discloses a backside illumination device technology. In one method, the production flow is referred to in the attached drawings 2A to 2D (refer to the original application, attached to FIG. 4A, FIG. 4B, FIG. 4C, and FIG. 4D, respectively). Before the wafer 2 and the carrier substrate 4 are bonded, the edge 13 of the wafer 2 is processed to cut the edge 13 of the wafer 2 into a vertical section 20 to avoid sharp edges. In another method, the edge processing of the wafer is arranged after the wafer is bonded to the carrier substrate, and the portion of the edge of the wafer that is not well bonded to the carrier substrate is removed by grinding before polishing the back surface of the wafer. The technical solution of this patent application is to deal with the problem of poor adhesion between the edge of the wafer and the carrier substrate, but does not involve the technique of patterning the wafer in a wafer level package.

The areas we focus on: the die-sealing technology of wafer-level packaging, in the reduction of mold material spillage, prevention of wafer breakage, and in solving the problem that the edge of the wafer is not completely covered by the molding material, the above patent application It is difficult to effectively improve the solution or the existing technology.

In view of the above problems, the present invention provides a method for avoiding wafer breakage in a wafer molding process, comprising the steps of: providing a wafer having a wafer having a plurality of wafers whose boundaries are defined by dicing lines; The wafer is diced to form a dicing groove at the scribe line; the front side of the wafer is ground around the edge of the wafer to form an annular grinding groove that is recessed at the edge of the wafer and recessed on the front side of the wafer; A molding technique is performed to mold the wafer on the front side of the wafer and form a molding compound covering the front side of the wafer.

The above method further includes the following steps: Grinding the molding compound to reduce the thickness of the molding compound; grinding the back surface of the wafer to reduce the thickness of the wafer, and exposing the cutting groove on the back side of the thinned wafer; the wafer and the mold along the cutting groove The sealant is cut to form a plurality of wafer level packages that are overmolded with the mold body.

In the above method, the depth of the grinding groove formed during the grinding of the edge of the wafer is greater than the depth of the cutting track.

In the above method, the top of any of the wafers is provided with a plurality of pads connecting the internal circuits of the wafer and a plurality of bump electrodes protruding from the front surface of the wafer; and the bump electrodes and the pads pass through the metal disposed on the top of the wafer Connected layerically and electrically.

In the above method, in the process of molding a wafer level package, the bump electrode is encapsulated by the mold material.

In the above method, the bump electrode is exposed from the molding compound during the process of grinding the molding compound.

The above method, after the completion of the grinding of the molding compound, further comprises the steps of ball implantation and reflow on the bump electrode exposed to the molding compound.

The above method further comprises the step of plating a layer of underlying metal on the bump electrode exposed to the molding compound before the ball is implanted.

In the above method, after the polishing of the back surface of the wafer is completed, the bottom surface of the wafer is formed on the back surface of the thinned wafer, and further, the following technical steps are performed on the bottom surface of the wafer: etching; ion implantation and laser annealing; Evaporation to form a bottom metal layer on the bottom surface of the wafer that connects the internal circuitry of the wafer.

In the above method, forming the bottom metal layer includes the following technical steps: performing metal evaporation to form a metal film on the back surface of the thinned wafer; and performing a dry film technique by adhering to the metal film The dry film is subjected to lithography, and the dry film after lithography is used as a mask to etch the metal film, and only the metal film on the bottom surface of the wafer is left to constitute the bottom metal layer.

These and other advantages of the present invention will no doubt become apparent to those skilled in the <RTIgt;

1, 500‧‧‧ wafer level package

2, 101‧‧‧ solder pads

3‧‧‧ copper interconnect layer

4‧‧‧Electrode

10, 100‧‧‧ wafer

13‧‧‧The edge of the wafer

20‧‧‧Vertical section

22‧‧‧Cutting trough

23‧‧‧Resin

100a‧‧‧ wafer front

100b, 100c‧‧‧ wafer back

101‧‧‧ solder pads

102‧‧‧Metal interconnect layer

103‧‧‧Bump electrode

104‧‧‧ solder balls

105a‧‧‧Bottom metal layer

110‧‧‧Multiple wafers

110a‧‧‧The bottom surface of the wafer

115‧‧‧ cutting road

115a‧‧‧Cutting trough

116‧‧‧ cutting channel

120‧‧‧ edge

120A‧‧‧Pre-grinding part

120B‧‧‧Reserved part

125a‧‧‧faced

125b‧‧‧ bottom surface of the grinding groove

200‧‧‧ grinding wheel

300‧‧‧ring fixture

400‧‧‧Mold sealing material

400a‧‧·封封体

400b‧‧‧ top

D ₁ , D ₂ ‧‧‧ Depth

Embodiments of the present invention are described more fully with reference to the accompanying drawings. However, the attached drawings are for illustration and illustration only and are not intended to limit the scope of the invention.

1A to 1D are wafer-level packaged semiconductor devices and methods of fabricating semiconductor devices disclosed in U.S. Patent No. 6,107,164.

2A-2D is a technical flow of a backside illumination device disclosed in U.S. Patent Application Publication No. US20080044,984.

Figure 3 is a top plan view of the wafer front side and the wafer on the wafer of the present invention.

Figure 4 is a schematic cross-sectional view showing a partial structure of a wafer and a wafer.

Figure 5 is a schematic cross-sectional view showing the formation of a cutting groove along the cutting path.

Figure 6 is a schematic cross-sectional view of the grinding groove formed by the edge portion of the abrasive wafer.

Figure 7 is a top plan view of the grinding groove formed by the edge portion of the wafer.

Figure 8 is a top plan view showing that the jig of the mold mold is pressed into the grinding tank to form a molding compound on the front surface of the wafer.

Figure 9 is a schematic cross-sectional view showing the jig of the mold mold being placed in the grinding bath and the molding compound being formed on the front side of the wafer.

Figure 10 is a schematic cross-sectional view of the wafer and the molding compound after the jig of the mold is separated from the wafer.

Figure 11 is a schematic cross-sectional view showing the polishing of the molding compound and exposing the bump electrodes in the molding compound.

Figure 12 is a schematic cross-sectional view of the ball implanted on the bump electrode exposed in the molding compound.

Figure 13 is a schematic cross-sectional view of the wafer being back-polished to thin the wafer.

Fig. 14 is a schematic cross-sectional view showing a metal film formed on the back surface of the thinned wafer after metal deposition.

Figure 15 is a schematic cross-sectional view of the wafer and molding compound cut along the exposed cutting grooves.

Referring to FIG. 3, the front side 100a of the wafer 100 includes a plurality of wafers 110. The plurality of wafers 110 are connected to each other. The adjacent wafers 110 define boundaries between each other through the dicing streets 115. The peripheral portion of the circle is the edge 120.

Referring to FIG. 4, in the schematic cross-sectional view of the wafer 100 and the wafer 110, the integrated circuit is formed on the front surface 100a of the wafer 100, and the other surface of the wafer 100 is the back surface 100b. The bond pad 101 serves as an input/output contact terminal (I/O Pad) of the internal circuit of the chip 110, and can be an input/output of a signal or an interface of Power and Ground. In wafer-level packaging, the aluminum pad, which is arranged around the top of the existing wafer, can be redesigned into a matrix arrangement using the redistribution technology RDL (Redistribution Technology). In the wafer 100, a plurality of pads 101 connecting the internal circuits of the wafer 110 and a plurality of bump electrodes 103 protruding from the front surface 100a of the wafer 100 are disposed on the top of any of the wafers 110, and the pads 101 are usually Aluminum electrode. The pad 101 is redistributed to form a matrix-arranged bump electrode 103 by RDL technology, and the bump electrode 103 is electrically connected to the pad 101 through a metal interconnect layer 102 disposed on the top of the wafer 110. The path of the layer 102 is a redistributed metal layer. In the RDL technology, the formation of the metal interconnect layer 102 is usually performed by exposure and development of a polyimide material, followed by metal sputtering, such as an alloy layer of a metal Ti/Cu. Referring to Figure 5, the wafer 100 is typically cut along the scribe line 115 in Figure 4 using a diamond cutter to form a cutting groove 115a at the scribe line 115. The wafer 110 is not completely cut and cut, cutting The groove 115a has a cutting depth of D ₁ . As shown in FIG. 3, since the cutting groove 115a is cut along the cutting path 115, and the cutting path 115 extends to the edge 120 of the wafer 100, the cutting groove 115a also extends to the edge 120 of the wafer 100.

Referring to FIGS. 6-7, a Grinding Wheel 200 is used to polish the edge 120 of the wafer 100 around the edge 120 of the wafer 100, and the edge 120 in the broken line portion of FIG. 5 is used. The included pre-polished portion 120A is ground away to form an annular grinding groove 125 recessed on the wafer front side 100a at the edge 120 of the wafer 100 in FIGS. 6-7, and the pre-polished portion 120A which is ground away is originally formed. Located at the grinding groove 125 in Fig. 7. As shown in Fig. 7, on the front side 100a of the wafer 100, the grinding wheel 200 is ground around the edge 120 of the wafer 100 to form a face 125a and a bottom face 125b of the grinding groove 125 as shown in Fig. 6, and the height of the face 125a is also That is, the depth D2 of the grinding groove 125. In this process, as shown in FIG. 6, the remaining portion 120B of the edge 120 on the side of the back surface 100b of the wafer 100 is not ground, that is, the remaining portion contained in the edge 120 below the bottom surface 125b of the grinding groove 125. 120B is still retained during the grinding process. Wherein, the depth D _{2 of the} grinding groove 125 is greater than the depth D _{1 of the} cutting groove 115a. Referring to FIGS. 8-9, a wafer level packaging molding technique is performed to mold the wafer 100 on the front side 100a of the wafer 100 and form a molding compound 400 covering the front side 100a. The annular jig 300 included in the molding die (not shown) of the molding device is located in the grinding groove 125, and the bottom of the jig 300 is pressed against the bottom surface 125b of the grinding groove 125, and the inner wall and the bottom of the jig 300 are bonded to each other. The tape is removed to prevent the jig 300 from coming into direct contact with the molding compound or the wafer 100, which is easily detached from the molding compound. The initial state of the molding compound 400 is liquid or liquid after heating and solidifies upon cooling. Since the dicing groove 115a extends to the edge 120 of the wafer 100, the liquid molding compound 400 easily overflows from the dicing groove 115a to the outside of the edge 120 of the wafer 100, creating an overflow. Once the overflow gel flows to the outside of the fixture 300 without the adhesive tape or other parts of the mold, the cured glue adheres the wafer 100 to these portions firmly, and any attempt to remove the fixture 300 from the wafer The action of separation on 100 will cause the wafer to break. Meanwhile, if the depth D _{2 of the} grinding groove 125 is smaller than the depth D _{1 of the} cutting groove 115a, the above-mentioned overflow problem may also occur, but the amount of overflow is different. The design of the grinding tank 125 of the present invention preferably solves such problems, avoiding the occurrence of overflow, and all of the molding material flowing out of the cutting groove 115a is cut off in the grinding tank 125.

On the other hand, if there is no grinding groove 125, the jig 300 will directly contact the pre-polished portion 120A (refer to FIG. 5) included in the edge 120 of the front surface 100a of the wafer 100, and cause the pre-polished portion 120A to be unmolded. The sealing material 400 is covered. However, since the pre-polished portion 120A is ground away, the pre-polished portion 120A is no longer present in the subsequent art, that is, the edge 120 is not broken due to the fact that the pre-polished portion 120A is not covered by the molding compound 400. .

Referring to FIG. 10, after the molding compound 400 is completely cured by heat, the jig 300 is separated from the wafer 100, and the jig 300 is removed from the grinding groove 125. A molding compound 400 covering the front side 100a of the wafer 100 is formed, and the molding compound 400 completely encapsulates the bump electrode 103 and forms a top surface 400a of the molding compound 400. Referring to Figures 10-11, the molding compound 400 is ground from the top surface 400a to reduce the thickness of the molding compound 400 to form the top surface 400b of the thinned molding compound 400, and the bump electrode 103 is at the top. The molding compound 400 is exposed outside the face 400b. Moreover, after the completion of the polishing of the molding compound 400, it is also necessary to perform a ballet (Solder Balls Attach) and a reflow (Solder Balls Reflow) on the bump electrodes 103 exposed to the molding compound 400. As shown in Fig. 12, after the ball is finished, the solder ball 104 is welded to the bump electrode 103. In order to maintain good adhesion between the bump electrode 103 and the solder ball 104 and low contact resistance, as well as oxidation resistance and high conductivity, the bump electrode 103 and the solder ball 104 also contain a layer of underlying metal (not shown). , such as an alloy layer of metal Ti/Ni/Cu, at Before the ball is implanted, the underlying metal is plated on the bump electrode 103 exposed to the molding compound 400. The underlying metal is formed by the under bump metallization (UBM) technique.

Referring to FIG. 12 to FIG. 13, polishing is performed on the back surface 100b of the wafer 100 to thin the thickness of the wafer 100, and the cutting groove 115a is exposed outside the back surface 100c of the thinned wafer 100, which also means The depth D1 of the cutting groove 115a exceeds the thickness D3 of the final wafer 100 after being thinned. During this grinding process, the remaining portion 120B of the front edge 120, which is located below the bottom surface 125b, is now ground. Further, after the back surface 100b of the wafer 100 is polished, the bottom surface 110a of the wafer 110 is formed on the back surface 100c of the thinned wafer 100, and the wafer 110 is cast and joined to each other by the molding compound 400.

Referring to FIG. 13 to FIG. 14, the polishing of the back surface 100b of the wafer 100 is completed. After the bottom surface 110a of the wafer 110 is obtained on the back surface 100c, etching is further performed on the bottom surface 110a of the wafer 110, such as wet etching, to remove The stress layer remaining on the bottom surface 110a of the wafer 110 after grinding repairs the lattice damage caused to the bottom surface 110a of the wafer 110 during the grinding process; then ion implantation is performed on the bottom surface 110a of the wafer 110, and is used for low temperature after ion implantation. Annealing or laser annealing eliminates some of the lattice defects generated in the bottom surface 110a of the wafer 110; metal evaporation is then performed to form a metal film 105 on the back surface 100c of the thinned wafer 100, such as Ti/Ni/ Ag alloy, this process is the process of back metallization; after the dry film technology, a dry film (Dry Film Resists) not shown is applied to the metal film 105, and the dry film is lithographically dried. After exposure and development, the remaining dry film is only present on the metal film in a partial region of the bottom surface 110a, that is, the dry film is removed as a mask by the lithography, and the metal film 105 is etched only to remain on the bottom surface 110a of the wafer 110. Up Points of the metal film, the metal film constituting the bottom part of the metal layer 105a (FIG. 15). In Fig. 15, the bottom metal layer 105a on the bottom surface 110a of the wafer 110 It is connected to the internal circuit of the wafer 110. In the above steps, spin-on-PR coating is formed to form a lithography process in which the dry glue is directly adhered to the metal film 105.

Referring to Fig. 15, the wafer 100 and the molding compound 400 are cut along the cutting groove 115a exposed on the back surface 100c, and the diamond cutting blade used at this time is thinner. Finally, a plurality of wafer-level packages 500 are obtained by molding the package 110 with the mold body 400a. The cutting channel 116 is a cutting mark left by cutting in the cutting groove 115a, and the mold body 400a is derived from the mold. The sealing of the sealing material 400 is performed, and the bottom metal layer 105a is exposed outside the molding body 400a. In accordance with the spirit of the present invention, in one embodiment, the wafer 110 is a metal oxide semiconductor field effect transistor (MOSFET) of a vertical device structure, the metal layer 105a constitutes a drain electrode of the MOSFET, and the plurality of pads 101 includes at least a gate. Polar and source electrodes.

Exemplary embodiments of specific structures of the specific embodiments are given by way of illustration and drawings. Although the above invention proposes a prior preferred embodiment, these are not intended to be limiting.

Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are intended to cover all such modifications and modifications Any and all equivalent ranges and contents within the scope of the claims are considered to be within the spirit and scope of the invention.

100‧‧‧ wafer

100a‧‧‧ wafer front

100b‧‧‧ back of the wafer

101‧‧‧ solder pads

102‧‧‧Metal interconnect layer

103‧‧‧Bump electrode

115a‧‧‧Cutting trough

120B‧‧‧Reserved part

125a‧‧‧faced

125b‧‧‧ bottom surface of the grinding groove

300‧‧‧ring fixture

400‧‧‧Mold sealing material

D ₁ , D ₂ ‧‧‧ Depth

Claims (10)

A method for avoiding wafer breakage in a wafer molding process, comprising the steps of: Step 1: providing a wafer having a wafer having a plurality of wafers whose boundaries are defined by dicing lines; Step 2: cutting along the cutting lane Wafer to form a cutting groove at the scribe line; Step 3: grinding the edge of the wafer around the edge of the wafer to form an annular grinding groove that is recessed on the front side of the wafer at the edge of the wafer; Step 4 : performing a molding technique to mold the wafer on the front side of the wafer and form a molding material covering the front side of the wafer, and in the molding technique, a ring fixture is provided in the annular grinding groove, and the bottom of the ring holder is pressed at a bottom surface of the annular grinding groove. The method of claim 1, further comprising the steps of: step 5: grinding the molding compound to reduce the thickness of the molding compound; and step 6: grinding the back surface of the wafer to thin the wafer. Thickness, and the cutting groove is exposed outside the back surface of the thinned wafer; Step 7: cutting the wafer and the molding material along the cutting groove to form a plurality of wafers that are molded and encapsulated by the mold body Class package. The method of claim 1, wherein the grinding groove is formed to have a depth greater than a depth of the cutting groove during the grinding of the edge of the wafer. The method of claim 2, wherein the top of any of the wafers is provided with a plurality of pads connecting the internal circuits of the wafer and a plurality of bump electrodes protruding from the front side of the wafer; The bump electrodes and the pads are electrically connected by a metal interconnect layer disposed on the top of the wafer. The method of claim 4, wherein the bump electrode is overmolded with the molding compound during the molding process. The method of claim 5, wherein the bump electrode is exposed from the molding compound during the process of grinding the molding compound. The method of claim 6, wherein after the grinding of the molding compound, the step of balling and reflowing on the bump electrode exposed to the molding compound is further included. The method of claim 7, wherein the step of plating a layer of the underlying metal on the bump electrode exposed to the molding compound is further included before the ball is implanted. The method of claim 4, wherein after the polishing of the back side of the wafer is completed, the bottom surface of the wafer is formed on the back surface of the thinned wafer, and the following technical steps are further performed on the bottom surface of the wafer: etching is performed. Performing ion implantation and laser annealing; performing metal evaporation to form a bottom metal layer on the bottom surface of the wafer connecting the internal circuits of the wafer. The method of claim 9, wherein the forming the bottom metal layer comprises the following technical step: the metal evaporation forms a metal film on the back surface of the thinned wafer; Dry film technology is carried out by lithography of a dry film adhered to a metal film, using a dry film after lithography as a mask to etch a metal film, leaving only a metal film on the bottom surface of the wafer to constitute the bottom metal layer .