TWI567889B - A wafer process for molded chip scale package (mcsp) with thick backside metallization - Google Patents

Description

Wafer fabrication method for molded wafer level package with thick back metallization 【0001】

The present invention generally relates to a method of packaging a semiconductor device. Specifically, the present invention is directed to improving the wafer fabrication process of a molded wafer level package (MCSP) to obtain an ultra-thin wafer package with a very thick back metal and a molded plastic on the front and/or back side of the device.

【0002】

Wafer-level wafer scale package (WLCSP) technology refers to the process of fabricating a semiconductor wafer on a wafer and separating the individual wafer package from the wafer to directly package the semiconductor wafer at the wafer level. Therefore, the size of the wafer package is the same as the size of the original semiconductor wafer. In general, WLCSP technology is widely used in semiconductor devices. It is well known that vertical power devices (such as common drain MOSFETs) have a large device internal resistance Rdson. Therefore, thinning the wafer can reduce the substrate resistance, thereby reducing Rdson. However, due to the thinner wafers and the lack of mechanical protection, thin wafers are difficult to handle. In addition, in order to reduce the Rdson of the vertical power device, a thick back metal is required to reduce the spread resistance. Conventional processes typically use a very thick leadframe and then mount the semiconductor wafer on a thick leadframe. However, this method cannot achieve 100% wafer level packaging.

[0003]

In addition, in conventional wafer level packaging technology, the wafer is directly diced along the scribe line of the front surface of the wafer to separate the individual wafer package from the wafer. However, prior to thinning the wafer, the front surface of the wafer is typically encapsulated with molding compound to enhance mechanical support of the wafer to avoid rupture of the wafer after thinning. Therefore, the scribe line is covered by the mold plastic, so it will be difficult to cut the wafer along the scribe line on the front surface of the wafer.

[0004]

Based on the above description of the disadvantages and limitations of the prior art, it is therefore necessary to prepare an ultra-thin wafer with a very thick back metal through the WLCSP on the front and/or back of the device.

[0005]

It is an object of the present invention to provide a wafer fabrication method for molding a wafer level package, which forms a thick metal layer on the back side of the wafer separated from the wafer, has the advantages of reducing chip resistance and facilitating heat dissipation, and can provide integration of wafer and semiconductor wafer. Mechanical support to improve one or more of the deficiencies and limitations of the prior art.

[0006]

Based on the above object, the present invention provides a wafer fabrication method for molding a wafer level package for packaging semiconductor wafers formed on a semiconductor wafer, each semiconductor wafer having a plurality of metal pads formed on a front surface thereof; The manufacturing method comprises the steps of: preparing a metal bump on each metal pad; preparing a first encapsulation layer on the front surface of the wafer, covering the metal bump; thinning the first encapsulation layer to make the metal bump The first encapsulation layer is exposed; the thickness of the wafer is polished on the back side of the wafer, a recess is formed on the back surface of the wafer, and a support ring is formed on the edge of the wafer; a metal seed layer is deposited on the back side of the wafer in the recess; deposition a thick metal layer covering the metal seed layer, the thickness of the thick metal layer being at least 1/10 of the thickness of the thinned wafer; cutting the first encapsulation layer, the wafer, the metal seed layer, and the thick metal layer to separate the single semiconductor wafer from the crystal Circular separation, wherein the first encapsulation layer is cut into a plurality of package top layers, and the front surface of each semiconductor wafer is covered with a package top layer, and the metal bumps are from the package top layer Exposed, the thick metal layer is cut into a plurality of thick metal layers, and the back surface of each semiconductor wafer is covered with a thick metal layer of the wafer.

【0007】

In a preferred embodiment of the present invention, the first encapsulation layer has a radius smaller than the radius of the wafer, and an uncovered ring is formed at the edge of the wafer, located at each end of each of the two adjacent semiconductor wafers. All extending on the front surface of the uncovered ring; the wafer fabrication method further includes: cutting along each scribe line on the first encapsulation layer, forming a cut on the front surface of the thinned first encapsulation layer The step of the slot.

[0008]

In a preferred embodiment of the present invention, after the step of forming a thick metal layer, further comprising: cutting a support ring at an edge portion of the wafer.

【0009】

In a preferred embodiment of the present invention, the radius of the recess is smaller than the radius of the first encapsulation layer, a portion of the first encapsulation layer is overlapped with a portion of the support ring, and the step of cutting the support ring of the edge portion of the wafer The method includes cutting off an overlapping portion of the first encapsulation layer and the support ring.

[0010]

In a preferred embodiment of the present invention, before the step of depositing a metal seed layer, further comprising: depositing a metal layer on the bottom surface of the wafer in the recess for ohmic contact and as a barrier of the metal seed layer The layer is diffused into the semiconductor wafer.

[0011]

In a preferred embodiment of the present invention, after the step of cutting the support ring at the edge portion of the wafer, the method further comprises: preparing a second encapsulation layer on the thick metal layer; wherein separating the individual semiconductor wafer from the wafer includes The dicing trench cuts the first encapsulation layer, the wafer, the seed layer, the thick metal layer and the second encapsulation layer, wherein the second encapsulation layer is diced into a plurality of package underlayers, and each of the thick metal layers of the semiconductor wafer is covered with a package underlayer .

[0012]

In a preferred embodiment of the invention, the metal seed layer is deposited by evaporation or sputtering.

[0013]

In a preferred embodiment of the invention, the metal seed layer is made of TiNiAg, TiNi or TiNiAl.

[0014]

In a preferred embodiment of the invention, the thick metal layer is deposited by electroplating and/or electroless plating.

[0015]

In a preferred embodiment of the invention, the thick metal layer is made of silver, copper or nickel.

[0016]

In a preferred embodiment of the invention, the thickness of the thinned first encapsulation layer is greater than the thickness of the thinned wafer.

[0017]

The present invention also provides a molded wafer level package device comprising: a semiconductor wafer comprising a plurality of metal pads formed on a front surface thereof; a metal bump on each metal pad; a first encapsulation layer Covering a front surface of the semiconductor wafer, wherein the metal bumps are exposed from the first encapsulation layer; a metal seed layer formed on the bottom surface of the semiconductor wafer; and a thick metal layer formed on the bottom of the metal seed layer; The thickness of the metal layer is equal to or greater than 1/10 of the thickness of the semiconductor wafer.

[0018]

Other objects and advantages of the present invention will become more apparent from the following description and appended claims.

[0043]

100‧‧‧ wafer

101‧‧‧ wafer

102‧‧‧dick

110‧‧‧ bumps

120‧‧‧First encapsulation layer

103‧‧‧Uncovered ring

121‧‧‧Cutting trough

130‧‧‧ dent

104‧‧‧Support ring

140‧‧‧thin metal layer

140‧‧‧metal seed layer

124‧‧‧Thick metal layer

105‧‧‧Edge section

104‧‧‧Support ring

122‧‧‧ overlap

105‧‧‧cutting part

180‧‧‧Tools

1200‧‧‧Package top layer

1400‧‧‧ wafer metal seed layer

1240‧‧‧ Chip thick metal layer

200A‧‧‧ wafer level package structure

200A‧‧‧Package structure

1200‧‧‧Package top layer

200B‧‧‧Package structure

1300‧‧‧Package bottom layer

130‧‧‧Second encapsulation layer

124‧‧‧Thick metal layer

[0019]

1A is a front plan view of a semiconductor wafer in the present invention, in which a semiconductor wafer is formed on a semiconductor wafer.

[0020]

1B is a schematic cross-sectional view of a semiconductor wafer in accordance with the present invention, in which metal bumps are formed on metal pads of a semiconductor wafer.

[0021]

2A-2B is a schematic view of the steps of depositing a first encapsulation layer in the present invention to cover the front side of the wafer.

[0022]

3A-3B is a schematic view showing the step of grinding and thinning the first encapsulating layer and forming a cutting groove on the first encapsulating layer in the present invention.

[0023]

Fig. 4 is a schematic cross-sectional view showing the step of polishing and thinning from the back surface of the wafer in the present invention.

[0024]

Figure 5 is a schematic cross-sectional view showing the step of depositing a thin metal layer on the back side of the thinned wafer in the present invention.

[0025]

Figure 6 is a schematic cross-sectional view showing the steps of depositing a thick metal layer on a thin metal layer on the back of a thinned wafer in the present invention.

[0026]

Fig. 7 is a schematic cross-sectional view showing the step of cutting the edge portion of the wafer in the present invention.

[0027]

Figure 8 is a schematic cross-sectional view showing the steps of exposing the backside metal by cutting the first encapsulation layer, the wafer, and the metal layer, and separating the separate package structure from the back metal in the present invention.

[0028]

Figure 9 is a cross-sectional view showing the steps of forming a second encapsulation layer on a thick metal layer prior to separating the individual package structures of the device structure shown in Figure 7 of the present invention.

[0029]

FIG. 10 is a view showing the separation of the first package layer, the wafer, the metal layer and the second package layer in the present invention by separating the individual package structure of the device structure shown in FIG. 9 from the mold plastic on the top surface and the bottom surface of the package structure. A schematic cross-sectional view of the steps.

[0030]

The present invention will be further described below in detail with reference to the accompanying drawings.

[0031]

1A shows a top view of a wafer 100 having a plurality of semiconductor wafers 101 formed on a front surface of a wafer with a scribe line 102 between two adjacent wafers 101. As is well known, cutting along the scribe line 102 separates the individual wafers 101 from the wafer 100. Generally, a plurality of metal pads (not shown) are formed on the front surface of each of the wafers 101 to constitute electrodes of the wafers, connected to a power source, a ground terminal, or a signal for signal transmission with an external circuit.

[0032]

As shown in FIG. 1B, conductive bumps 110 (e.g., metal bumps) are formed on each of the metal pads on the front surface of each of the wafers 101. The metal bumps 110 may be made of a conductive metal such as copper, gold, silver, aluminum or the like or an alloy thereof. The metal protrusions 110 may be spherical, elliptical, cuboidal, cylindrical or wedge-shaped or the like.

[0033]

As shown in FIG. 2A, a packaging material (for example, an epoxy resin or the like) is deposited to constitute a first encapsulation layer 120 of a specific thickness covering the front surface of the wafer 100 and all of the metal bumps 110. As shown in FIGS. 2A and 2B, the radius of the first encapsulation layer is slightly smaller than the radius of the wafer 100, so the first encapsulation layer 120 cannot cover the entire front surface of the wafer 100, such as an uncovered ring near the edge of the wafer. 103 cannot be covered by the first encapsulation layer 120.

[0034]

As shown in FIG. 3A, the first encapsulation layer 120 is ground to expose the metal bumps 110. In one embodiment, the first encapsulation layer 120 has a thickness after polishing of from about 50 microns to about 100 microns. The metal bumps 110 are preferably made of a relatively hard metal such as copper or the like so that when the first encapsulation layer is ground, dust on the metal bumps is prevented from adhering to the grinding wheel, causing the abrasive surface of the first encapsulation layer 120. Unnecessary pollution. In FIG. 3A, a plurality of cutting grooves 121 are formed on the front surface of the thinned first encapsulation layer 120. As shown in FIG. 2B, the radius of the first plastic encapsulation layer 120 is smaller than the radius of the wafer 100 to ensure that both ends of each of the scribe lines 102 in the uncovered ring 103 are not covered by the first plastic encapsulation layer 120. Then, a shallow line is cut on the front surface of the first encapsulation layer 120, aligned with the scribe line 102, and a dicing groove 121 is formed, and the scribe line 102 extends from the exposed ends of the uncovered ring 103. Specifically, each of the shallow lines or the cutting grooves 121 overlaps with the corresponding scribe lines 102 shown in FIG. 3B. The depth of the cutting groove 121 can be adjusted. In one embodiment, the dicing trench can penetrate the first encapsulation layer 120 to reach the front surface of the wafer.

[0035]

As shown in Figure 4, wafers of the original thickness of 760 microns are ground on the back side to a predefined thickness of 50 to 100 microns. In a preferred embodiment, the ground first plastic encapsulation layer is thicker than the ground thinned wafer for mechanical support. In addition, to provide mechanical support for the thinned wafer, the support ring at the edge of the wafer cannot be ground. As shown in FIG. 4, the back surface of the wafer 100 is polished by a grinding wheel having a radius smaller than the radius of the wafer 100 to form a recess 130. The radius of the recess 130 is as large as possible to maximize wafer throughput near the edge of the wafer. In this step, the support ring 104 is formed at the edge of the wafer 100, and the width of the support ring 104 is the difference between the radius of the wafer 100 and the radius of the recess 130. In this step, the thickness of the thin wafer 100 can be designed by adjusting the depth of the recess 130. The support ring 104 and the thinned encapsulation layer 120 provide mechanical support for the thinned wafer 100 such that the thinned wafer does not break easily. In one embodiment, the radius of the recess 130 is less than the radius of the first encapsulation layer 120 to further maintain the mechanical strength of the thinned wafer 100 such that a portion of the first encapsulation layer 120 may partially overlap a portion of the support ring 104.

[0036]

As shown in FIG. 5, it is also possible to dope heavily doped the bottom surface of the wafer 100 exposed inside the recess 130, and then anneal the dopant to diffuse it. A thin metal layer 140 (eg, TiNiAg, TiNi, TiNiAL, etc.) is deposited (eg, by evaporation or sputtering) on the bottom surface of the wafer 100. A thin metal layer 140 can be used as the metal seed layer 140 to deposit a thick metal layer in the next step. In one embodiment, a metal layer for ohmic contact may be deposited on the bottom surface of the wafer in the recess prior to depositing the metal seed layer 140, and diffused to the semiconductor wafer as a barrier layer of the metal seed layer 140. in.

[0037]

As shown in FIG. 6, a thick metal layer 124 is deposited over the metal seed layer 140 by electroplating and/or electroless plating. The thick metal layer 124 may be a metal such as silver, copper, nickel or the like. The thickness of the thick metal layer 124 is from about 10 microns to about 100 microns, depending on the size of the semiconductor wafer formed on the wafer. Generally, when the thickness of the thinned wafer after grinding is 100 micrometers or less, the thick metal layer 124 should be at least 1/10 of the thickness of the thinned wafer. For a 50 micron polished wafer, the thickness of the thick metal layer 124 should be at least 1/5 of the thickness of the thinned wafer, preferably 1/2 or more of the thickness of the thinned wafer. In one embodiment, the thickness of the wafer (shown in Figure 4) is reduced by about 50 microns and the bottom surface is deposited with a metal underlayer having a thickness of 50 microns or more. For thinned wafers below 50 microns, the thickness of the thick metal layer 124 should be more than 1/2 of the thickness of the wafer. Since the thick metal layer 124 is formed by transmission deposition, there is no bonding material such as solder or epoxy between the bottom surface of the wafer and the surface of the thick metal layer. The thick metal layer 124 not only has the benefit of reducing electrical resistance and facilitating heat dissipation, but also provides mechanical support for wafer and semiconductor wafer integration during fabrication, especially after the wafer thickness has dropped below 100 microns.

[0038]

As shown in FIG. 7, the edge portion 105 of the thinned wafer 100 and the support ring 104 are cut away, so that the overlapping portion 122 of the first encapsulation layer 120 is also cut off, so that the width of the cut portion 105 of the wafer is equal to or slightly larger than the support. The width of the ring 104.

[0039]

As shown in FIG. 8, the first encapsulation layer 120, the wafer 100, the metal seed layer 140, and the thick metal layer 124 may be cut by the cutter 180 along the dicing trench 121 to separate the individual wafer 101 from the wafer 100. Therefore, the first encapsulation layer 120 is divided into a plurality of package top layers 1200, the metal seed layer 140 is divided into a plurality of wafer metal seed layers 1400, and the thick metal layers 124 are divided into a plurality of wafer thick metal layers 1240, thereby obtaining a plurality of wafer levels. Package structure 200A. Each package structure 200A includes a package top layer 1200 covering the front surface of each wafer 101, a wafer metal seed layer 1400 covering the back side of the wafer 101, and a thick metal layer 1240 covering the metal seed layer 1400, the metal bumps 110 The package top layer 1200 is exposed as a contact terminal of the package structure 200A to electrically connect an external circuit. The thick metal layer 1240 of the wafer is exposed at the bottom of the package structure 200A, and serves as a contact terminal of the package structure 200A for heat dissipation.

[0040]

In one embodiment, wafer 101 is a vertical MOSFET (metal-oxide-semiconductor field effect transistor) in which current flows from the front surface of the wafer to the back side, or vice versa. Therefore, a plurality of metal pads formed on the front surface of the wafer include one pad constituting a source electrode of the wafer, one pad constituting a gate electrode, and a thick metal layer 1240 of the wafer constituting a drain electrode. With the thick metal layer 1240 of the wafer, the resistance of the package structure 200A can be significantly reduced.

[0041]

In another embodiment, as shown in Figures 9-10, a package structure 200B with a package bottom layer 1300 can be fabricated. After the edge portion 105, the overlapping portion 122, and the support ring 104 of the thinned wafer are cut as shown in FIG. 7, a second encapsulation layer 130 is prepared to cover the thick metal layer 124 as shown in FIG. Then, the first encapsulation layer 120, the wafer 100, the metal seed layer 130, the thick metal layer 124, and the second encapsulation layer 130 are cut to separate the individual wafers 101 from the wafer 100. Thus, as shown in FIG. 10, the first encapsulation layer 120 is diced into a plurality of package top layers 1200, the metal seed layer 140 is diced into a plurality of wafer metal seed layers 1400, and the thick metal layers 124 are diced into a plurality of wafer thick metal The layer 1240, the second encapsulation layer 130 is diced into a plurality of package underlayers 1300, thereby obtaining a plurality of package structures 200B. Each package structure 200B includes a package top layer 1200 covering the front surface of each wafer 101, a wafer metal seed layer 1400 covering the back side of the wafer 101, a thick metal layer 1240 covering the wafer metal seed layer 1400, and a package bottom layer 1300 covering A thick metal layer 1240 is formed, and the metal bumps 110 are exposed from the top surface of the package top layer 1200 as contact terminals of the package structure 200B to electrically connect external circuits. Therefore, when the wafer 101 is a vertical MOSFET, a plurality of metal pads are formed on the front surface of the wafer, including one pad constituting a source electrode of the wafer, one pad constituting a gate electrode, and the pad electrically connected to the wafer thick metal Layer 1240 passes through a metal interconnect structure (not shown) formed in the wafer.

[0042]

While the present invention has been described in detail by the preferred embodiments thereof, it should be understood that Various modifications and alterations of the present invention will be apparent to those skilled in the art. Therefore, the scope of the invention should be limited by the scope of the appended claims.

Domestic registration information [please note according to the registration authority, date, number order]

no

Foreign deposit information [please note according to the country, organization, date, number order]

no

no

200B‧‧‧Package structure

110‧‧‧ bumps

180‧‧‧Tools

1200‧‧‧Package top layer

101‧‧‧ wafer

1240‧‧‧ Chip thick metal layer

1300‧‧‧Package bottom layer

Claims (14)

[Item 1] A wafer fabrication method for molding a wafer level package for packaging semiconductor wafers formed on a semiconductor wafer, each semiconductor wafer having a plurality of metal pads formed on a front surface thereof, wherein the manufacturing method comprises The following steps:
Preparing a metal bump on each metal pad;
Preparing a first encapsulation layer on the front surface of the wafer to cover the metal protrusion;
Thinning the first encapsulation layer to expose the metal bumps from the first encapsulation layer;
Grinding and thinning the wafer back surface, forming a recess on the back surface of the wafer, forming a support ring at the edge of the wafer;
Depositing a metal seed layer on the back side of the wafer in the recess;
Depositing a thick metal layer covering the metal seed layer, the thick metal layer having a thickness of at least 1/10 of the thickness of the wafer after thinning; Cutting the first encapsulation layer, the wafer, the metal seed layer and the thick metal layer to separate a single semiconductor wafer from the wafer, wherein the first encapsulation layer is cut into a plurality of package top layers, each of the semiconductor wafers The front surface is covered by a package top layer that is exposed from the top layer of the package, wherein the thick metal layer is diced into a plurality of thick metal layers, each of which is covered with a thick metal layer of the wafer. [Item 2] The wafer fabrication method of claim 1, wherein the first encapsulation layer has a radius smaller than a radius of the wafer, and an uncovered ring is formed at the edge of the wafer, and the two adjacent semiconductors are located. Each of the two scribe lines between the wafers extends on the front surface of the uncovered ring; the wafer fabrication method further includes: cutting along each of the scribe lines on the first encapsulation layer, after the thinning A step of forming a cutting groove on the front surface of the first encapsulation layer. [Item 3] The wafer fabrication method of claim 1, wherein after the step of forming the thick metal layer, further comprising: cutting a support ring of the edge portion of the wafer. [Item 4] The wafer fabrication method of claim 3, wherein the radius of the recess is smaller than a radius of the first encapsulation layer, a portion of the first encapsulation layer overlaps a portion of the support ring, and the wafer is diced The step of the support ring of the edge portion includes cutting away the overlapping portion of the first encapsulation layer and the support ring. [Item 5] The method of fabricating a wafer according to claim 1, wherein the step of depositing the metal seed layer further comprises: depositing a metal layer on the bottom surface of the wafer in the recess for ohmic contact, and The barrier layer of the metal seed layer is diffused into the semiconductor wafer. [Item 6] The method of fabricating a wafer according to claim 1, wherein after the step of cutting the support ring of the edge portion of the wafer, the method further comprises: preparing a second encapsulation layer on the thick metal layer; Separating the single semiconductor wafer from the wafer includes cutting the first encapsulation layer, the wafer, the metal seed layer, the thick metal layer, and the second encapsulation layer along the dicing trench, wherein the second encapsulation layer is diced into a plurality of The bottom layer of the package is covered on the thick metal layer of each semiconductor wafer. [Item 7] The wafer fabrication method of claim 1, wherein the metal seed layer is deposited by evaporation or sputtering. [Item 8] The wafer fabrication method of claim 7, wherein the metal seed layer is made of TiNiAg, TiNi or TiNiAl. [Item 9] The wafer fabrication method of claim 7, wherein the metal layer is deposited by electroplating and/or electroless plating. [Item 10] The wafer fabrication method of claim 9, wherein the thick metal layer is made of silver, copper or nickel. [Item 11] The wafer fabrication method of claim 1, wherein the thickness of the thinned first encapsulation layer is greater than the thickness of the thinned wafer. [Item 12] A molded wafer level package device, comprising:
a semiconductor wafer comprising a plurality of metal pads formed on a front surface thereof;
There is a metal bump on each metal pad;
a first encapsulation layer covering a front surface of the semiconductor wafer, wherein the metal bump is exposed from the first encapsulation layer;
a metal seed layer formed on a bottom surface of the semiconductor wafer; A thick metal layer is formed at the bottom of the metal seed layer; the thick metal layer has a thickness equal to or greater than 1/10 of the thickness of the semiconductor wafer.