TWI536507B - A ultrathin semiconductor device - Google Patents

Description

Ultrathin semiconductor device and preparation method

The present invention generally relates to a semiconductor device and a method of fabricating the same, and more particularly to a power semiconductor device having a smaller size and a thinned wafer and a method of fabricating the same.

In a DC-DC-like conversion device, the power consumption of the power device is generally large. Based on the consideration of improving the electrical performance and heat dissipation performance of the device, a part of the metal electrode of the device is usually coated with the molding material of the wafer. The Chinese and foreign are exposed to get the best heat dissipation effect. A semiconductor package structure 24 in which a wafer bottom electrode is exposed and used to support surface mount technology is shown, for example, in US Patent Application No. 2003/0132531 A1. As shown in FIG. 1, a power chip MOSFET 10 is disposed in a recess of the metal can structure 12. The drain on one side of the MOSFET 10 is pasted to the bottom of the recess of the can-like structure 12 by the conductive silver paste 14, so that its drain is conducted to the raised edge 22 of the can-like structure 12 while the source on the other side of the MOSFET 10 The pole contact end 18 and the gate contact end are just on the same side as the raised edge 22. A low stress and high adhesion ability conductive material 16 is also filled in the void around the MOSFET 10 in the recess of the metal can structure 12. Although the package structure 24 solves the heat dissipation problem to a certain extent, it is costly to produce an object such as the metal can-like structure 12 in actual production. On the other hand, the positions of the source contact end 18 and the gate contact end are fixed, for example, the gate contact end thereof cannot be adjusted to be in the same column as the bump edge 22, thereby making it difficult to fit the pad layout on the PCB. This package is incompatible with conventional PCB pads, which undoubtedly inhibits the application of package structure 24. In addition, the substrate resistance of a wafer used in a power device is generally large, which leads to an increase in the on-resistance RDson of the device. In the existing wafer level packaging technology, the wafer is usually thinned. The way to thin the wafer, but this will still cause the risk of wafer cracking, so how to thin the wafer to properly reduce the substrate resistance of the wafer is still a problem we need to solve.

In one embodiment of the present invention, there is provided a semiconductor device comprising: a wafer mounting unit having a plurality of pedestals, wherein a top surface of each pedestal is provided with a protrusion protruding from a side edge thereof a top surface of the base; a flip-chip mounted on the top surface of each of the bases and disposed in a staggered manner with the base structure, the plurality of electrodes on the front side of the wafer are electrically connected one to one to the plurality of On the pedestal; an inner plastic package covering the wafer mounting unit and the wafer, the top end surface of the base structure and the back surface of the wafer are exposed on the top surface of the inner plastic package; A plurality of top electrodes are separated from each other on the top surface, and the plurality of top electrodes are electrically connected to the respective body structures and the back surface of the wafer.

In the above semiconductor device, the bottom surface of the pedestal is exposed from the bottom surface of the inner plastic package.

The semiconductor device further includes: an interconnect unit having a plurality of carrier pins, wherein the plurality of top electrodes are respectively adhered to the plurality of carrier pins one-to-one; and an interconnect unit, a top electrode, and an inner plastic package The outer plastic sealing body is covered by coating the bottom surface of each of the bearing pins to the bottom surface of the outer plastic sealing body.

In the above semiconductor device, the bottom surface of the pedestal is exposed from the bottom surface of the inner plastic sealing body, and the bottom surfaces of the pedestal and the inner plastic sealing body are exposed from the top surface of the outer plastic molding body.

In the above semiconductor device, the bottom surface of the susceptor is exposed from the bottom surface of the inner plastic package but is covered by the outer plastic package.

In the above semiconductor device, the bottom surface of the susceptor is covered by the inner plastic sealing body, and the bottom surface of the inner plastic sealing body is not exposed from the top surface of the outer plastic sealing body, and the inner plastic sealing body is completely sealed without exposed portions.

In the above semiconductor device, the bottom surface of the susceptor is covered by the inner molding, and the bottom surface of the inner molding is exposed from the outer surface of the outer molding.

In one embodiment, the present invention also provides a method of fabricating a semiconductor device, comprising the steps of: providing an inner lead frame having a plurality of wafer mounting units, each wafer mounting unit comprising a plurality of pedestals, each The top surface of each of the pedestals is provided with a pedestal structure near one side of the pedestal; a wafer is flip-chip mounted on the top surface of each pedestal of the wafer mounting unit, and a plurality of electrodes on the front side of the wafer are one-to-one Geoelectrically connected to the plurality of pedestals, the wafer and the pedestal structure are disposed in a staggered manner; performing a plastic encapsulation process, using a plastic sealing layer to coat the inner lead frame and the plurality of wafers adhered thereto; The top surface of the plastic sealing layer is ground to thin the plastic sealing layer and the wafer until the top surface of the base structure and the thinned back surface of the wafer are exposed to the plastic sealing layer; forming a metal layer covering the top surface of the plastic sealing layer and the thinned back surface of each wafer Cutting the metal layer, and cutting the metal layer over the area above each of the wafer mounting units to form a plurality of top electrodes electrically contacting the respective body structures and the back surface of the wafer; Comprising the lead frame, and a plastic layer laminated metal layer is cut to form a plurality of semiconductor devices.

In the above method, in the step of performing the laminating process, the bottom surface of each of the susceptors of each of the wafer mounting units is covered with a plastic sealing layer.

In the above method, in the step of performing the molding process, the bottom surface of each of the susceptors of each of the wafer mounting units is exposed on the bottom surface of the plastic sealing layer.

In the above method, after the metal layer is cut, the plastic sealing layer is cut along the cutting opening formed in the metal layer to form a cutting groove in the plastic sealing layer.

The above method is characterized in that: further comprising: providing an outer lead frame comprising a plurality of interconnecting units, each interconnecting unit comprising a plurality of carrying pins; respectively mounting a semiconductor device on an interconnecting unit, each semiconductor device a plurality of the top electrodes are respectively adhered one by one to a plurality of the carrier pins of each interconnection unit; another plastic sealing process is performed, and the outer lead frame is adhered to and adhered thereto by another plastic sealing layer The plurality of semiconductor devices are coated such that the bottom surface of each of the carrier pins is exposed on the bottom surface of the other plastic sealing layer; and the laminate including the outer lead frame and the other plastic sealing layer between adjacent semiconductor devices is cut, A plurality of outer moldings are formed, wherein each outer molding encloses one interconnecting unit and one semiconductor device.

In the above method, the inner lead frame is covered with a plastic sealing layer so that the bottom surface of each of the pedestals is exposed from the bottom surface of the plastic sealing layer; and the outer plastic layer is coated with another plastic sealing layer. The method is such that the bottom surfaces of the base and the inner plastic seal are exposed from the top surface of the other plastic seal layer.

In the above method, the inner lead frame is covered with a plastic sealing layer so that the bottom surface of each of the pedestals is exposed from the bottom surface of the plastic sealing layer; and the outer plastic layer is coated with another plastic sealing layer. The method is such that the bottom surface of each of the base and the inner plastic sealing body is covered by the other plastic sealing layer.

In the above method, the plastic sealing layer covered by the inner lead frame is coated in such a manner that the bottom surface of each of the pedestals is covered by the plastic sealing layer; and the coating manner of another plastic sealing layer covering the outer lead frame In order for the inner plastic seal to be covered by the other plastic seal layer, there is no exposed portion.

In the above method, the plastic sealing layer covered by the inner lead frame is coated in such a manner that the bottom surface of each of the pedestals is covered by the plastic sealing layer; and the coating manner of another plastic sealing layer covering the outer lead frame In order to expose the bottom surface of the inner plastic sealing body from the top surface of the other plastic sealing layer.

These and other advantages of the present invention will no doubt become apparent to those skilled in the <RTIgt;

(previous technology)
10‧‧‧MOSFET
12‧‧‧Metal cans
14‧‧‧ Conductive silver paste
16‧‧‧Electrical materials
18‧‧‧Source contact
22‧‧‧ raised edges
24‧‧‧Semiconductor package structure (invention)
100'‧‧‧ lead frame
100‧‧‧ wafer mounting unit
101, 102‧‧‧ Pedestal
110‧‧‧ wafer
110a‧‧‧ source
110b‧‧‧ gate
101-1, 101-3‧‧‧ longitudinally opposite
101-2, 101-4‧‧‧ lateral sides
100A‧‧‧central symmetry line
101a‧‧‧Terbo structure
102a‧‧‧Terbo structure
102-1‧‧‧ longitudinal edge
120‧‧‧plastic layer
101‧‧‧Adhesive materials
130‧‧‧metal layer
130'‧‧‧Area
130''‧‧‧ cutting mouth
130a‧‧‧Top electrode
130b‧‧‧Top electrode
130c‧‧‧Top electrode
120a‧‧‧Cutting trough
150‧‧‧Cutting knife
180‧‧‧Power semiconductor devices
120'‧‧‧plastic body
200‧‧‧Interconnect unit
200'‧‧‧ lead frame
201, 202, 203‧‧‧ carrying pins
115‧‧‧ Conductive bonding materials
140‧‧‧plastic layer
140'‧‧‧Broken body
280‧‧‧Semiconductor devices

Embodiments of the present invention are described more fully with reference to the accompanying drawings. However, the attached drawings are for illustration and illustration only and are not intended to limit the scope of the invention. 1 is a schematic cross-sectional view of a semiconductor package structure in the background art. 2A-2I are schematic diagrams showing the flow of a method for preparing a power device according to the present invention. 3A to 3E are schematic views showing the flow of remolding the primary device obtained in Figs. 2A to 2I. 4A-4C are schematic illustrations of whether the back side of the primary device can be selectively exposed after the primary device is again molded.

2A shows a portion of the structure of a lead frame 100' of a metal material. In the present invention, for convenience of description, the lead frame 100' may be referred to as an inner lead frame or a first lead frame for use in another process for subsequent processes. The lead frame is distinguished. The lead frame 100' includes a plurality of wafer mounting units 100, each of which includes at least a pedestal 101, 102, and the substantially symmetrical bases 101, 102 are connected to the lead frame 100' by unillustrated ribs in the figure. Some of the support bars. The pedestals 101, 102 adjacent to each other but separated from each other are arranged side by side. The wafer 110 of FIG. 2B is typically a vertical MOSFET, for example, the current flows from the front side to the back side or vice versa, in order to better fit the wafer mounting unit 100 to the wafer mounting unit 100. The wafer 110 is provided with a larger area to receive the source 110a of the bonded MOSFET. The pedestal 102 has a smaller area relative to the pedestal 101 to receive the gate 110b of the bonded MOSFET.

An important invention of the present invention is to require the construction of a compact final device to the utmost extent, so that it is necessary to optimally arrange the structure of the wafer mounting unit 100, which is first set in the plane in which the wafer mounting unit 100 is located, and the susceptor 101 has The opposite set of longitudinally opposite sides 101-1, 101-3 and the opposite set of laterally opposite sides 101-2, 101-4. The susceptor 102 extends from the vicinity of the extension line of the edge 101-1 along the length direction of the edge 101-2 or 101-4 to the vicinity of the center symmetry line 100A between the edges 101-1 and 101-3. An elongated land structure 101a is provided on the top surface of the susceptor 101 near the edge 101-1, and the pedestal structure 101a extends along the length direction of the edge 101-1. Also provided on the top surface of the base 102 is a body structure 102a disposed on the top surface adjacent a longitudinal edge 102-1 of the base 102 and extending along the length of the longitudinal edge 102-1. This edge 102-1 is aligned with the edge 101-1 of the pedestal 101 or near the extension of the edge 101-1 to provide a preferred way to make the pedestal structures 101a, 102a substantially collinear. For the sake of brevity, the other edges of the pedestal 102 are not labeled one by one in the figures. With this configuration of the wafer mounting unit 100, a large space can be reserved above the respective top surfaces of the pedestals 101, 102 to accommodate the wafer 110.

In FIG. 2C, the wafer 110 is flip-chip mounted on the wafer mounting unit 100, and the respective electrodes on the front side are respectively adhered to the top surfaces of the pedestals 101, 102, and the top surfaces of the pedestals 101, 102 are required to be coplanar. In this patching step, the wafers 110 are not overlapped over the land structures 101a, 102a, but are disposed in a staggered manner with them, and the wafers 110 are left with a gap therebetween. Thereafter, a conventional plastic sealing process is performed, and a plastic sealing layer 120 covering the front surface of the lead frame 100' is formed by using an epoxy resin molding compound, and the plastic sealing layer 120 may be referred to as a first plastic sealing layer so as to be the other one appearing later. The plastic layer is distinguished. The molding layer 120 molds the lead frame 100' and the plurality of wafers 110 adhered to the lead frame 100' as shown in Fig. 2D-1. For a more detailed understanding, FIG. 2D-2 is a schematic vertical cross-sectional view showing a portion of the broken line in FIG. 2D-1, and the wafer 110 is adhered to the wafer mounting unit 100 by an adhesive material 101 such as solder paste or conductive silver paste. . Alternatively, the molding layer 120 may be selected to completely mold the lead frame 100', that is, the bottom surface of the pedestals 101, 102 is covered by the molding layer 120, and the bottom surface of each of the pedestals 101, 102 may be selected from the plastic sealing layer. The bottom surface of 120 is exposed. It should be noted that the present invention deliberately scales the dotted frame structure (for example, FIG. 2D-1) (for example, FIG. 2D-2) only to meet the needs of the reader for visual reference, which does not mean that the frame is fixed. The structure is separated at this point in time, unless otherwise stated, as is the similar description referred to in the present invention.

The initial thickness of the wafer 110 is generally relatively large, and its on-resistance RDSon is far from what we would expect, but directly grinding the wafer 110 poses a potential hazard to crack it, and the present invention is very good in the steps of Figure 2E-1. solved this problem. Grinding is performed on the top surface of the molding layer 120, so that the molding layer 120 is continuously thinned to a certain extent to expose the wafer 100, and then the back surface of the wafer 110 is also ground, thereby achieving the purpose of simultaneously thinning the molding layer 120 and the wafer 110. To achieve a reduced device size and a lower RDSon, the wafer 100 is susceptible to chipping due to the physical support of the plastic encapsulation layer 120 and the leadframe 100'. The top end faces of the mesa structures 101a, 102a are coplanar, and their thickness is smaller than the thickness of the wafer 110, and the polishing is terminated at the top end faces of the mesa structures 101a, 102a, so that the final thickness of the wafer 110 is substantially equal to the mesa structure. The height of the 101a, 102a can be seen, and the final thickness of the wafer 110 can be adjusted by setting the height values of the mesa structures 101a, 102a. For a more detailed understanding, FIG. 2E-2 is a schematic vertical sectional view showing a part of the structure framed by the broken line in FIG. 2E-1, and FIG. 2E-3 is a bird's-eye view of the structure in FIG. 2E-2, which is easy to understand. The top end faces of the mesa structures 101a, 102a will eventually be coplanar with the thinned back side of the wafer 110.

In FIG. 2F-1, a metal layer 130 is deposited or sputtered over the thinned top surface of the polished plastic encapsulation layer 120, and the metal layer 130 naturally covers both the mesa structures 101a, 102a and the back surface of the wafer 110. At this time, the metal layer 130 is in electrical contact with the top end faces of the respective mesa structures 101a and 102a, and at the same time forms electrical contact with the thinned back surface of each of the wafers 110. Please refer to FIG. 2F-2, which is FIG. 2F-1. An enlarged bird's-eye view of a portion of the structure in the middle of the dashed line defines a metal layer 130 having a region 130' that overlaps each wafer mounting unit 100. Although not explicitly illustrated, in some embodiments, heavily doped dopants may also be implanted on the thinned backside of wafer 110 to form between metal layer 130 and the drain region on the back side of wafer 110. Better ohmic contact. Next, as shown in FIG. 2G-1, the metal layer 130 is cut. Essentially, in particular, each of the regions 130' is cut to form a plurality of lateral and/or longitudinal slits 130" to separate a region of each region 130' that is in electrical contact with the thinned back side of the wafer 110. The top electrode 130c, and a top electrode 130a that is electrically connected to the top end surface of the mesa structure 101a, and a top electrode 130b that is electrically connected to the top end surface of the mesa structure 102a, the cutting step may be It is implemented using tools such as lasers and cutting knives. Note that in this cutting step, any two adjacent regions 130' may or may not be cut apart, in other words, a circular cutting opening that is rectangular in shape may be cut around each region 130' (not Shown) to separate a designated area 130' from the other four areas 130' that surround the outside of it, but such an annular cut is not necessary because of another cut as shown in Figure 2H. In the step, the metal layer 130 is cut and the adjacent regions 130' are naturally separated. The description of FIG. 2H will be described in detail in the following. After the cutting of the metal layer 130 is completed, as an optional but unnecessary step, as shown in FIG. 2G-2, the plastic sealing layer 120 under the cutting opening 130'' may be further cut along the cutting opening 130'' to form a plastic seal. The cutting groove 120a in the layer 120 has a cutting groove 120a overlapping each other directly under each cutting opening 130''.

In FIG. 2H, there is another cutting step in which the dicing blade 150 cuts a stack including the lead frame 100', the mold layer 120, and the metal layer 130 between adjacent wafers 110, and thus each wafer mounting unit 100 is connected to the leads. The ribs on the frame 100' are cut and broken, and the plastic sealing layer 120 is cut into a plurality of molding bodies 120'. The metal layer 130 overlaps the area 130' above each wafer mounting unit 100 and is located around it. The other metal layer 130 regions are divided to form a power semiconductor device 180 as shown in FIGS. 2H-2I. In order to distinguish from the subsequent other plastic bodies, the molded body 120' may be referred to as an inner plastic seal or a first plastic seal. A molding body 120' coats one wafer mounting unit 100 and one wafer 110, and the top end faces of the mesa structures 101a, 102a and the thinned back surface of the wafer 110 are exposed on the top surface of the molding body 120' (see the figure). 2E-3), and a plurality of top electrodes 130a-130c separated from each other are disposed on the top surface of the molded body 120', the top electrode 130a is electrically connected to the base structure 101a, and the top electrode 130b is electrically connected to the base structure 102a, the top electrode 130c is electrically connected to the back side of the wafer 110, that is, the drain. The cutting groove 120a formed in the molding body 120' below the cutting opening 130" is an alternative embodiment. In addition, it is easy to understand that when the plastic sealing layer 120 completely covers the lead frame 100', the bottom surfaces of the pedestals 101, 102 are covered by the molding body 120', and the bottom surfaces of the pedestals 101, 102 are all from the plastic sealing layer. When the bottom surface of the 120 is exposed, the bottom surfaces of the pedestals 101, 102 are exposed from the bottom surface of the molding body 120'.

The semiconductor device 180 of Figure 2I is already a complete power device, in other words, it can be directly mounted on a PCB board for use. However, in the embodiment of FIGS. 3A-3D, we will continue to perform a series of additional fabrication processes for the semiconductor device 180 of FIG. 2I, in which case the semiconductor device 180 may be referred to as a primary device, and these additional introduced processes may rearrange the top electrode The way 130a~130c is connected to an external circuit also allows the secondary device based on the primary device to take into account some of the current package types (see Figure 3E). 3A shows another lead frame 200' including a plurality of interconnecting units 200, again with only a portion of the structure of the lead frame 200' being taken as an exemplary illustration, which may be referred to as an outer lead frame or a second lead frame, each The interconnect unit 200 each includes a plurality of carrier pins 201, 202, 203. When the semiconductor device 180 of FIG. 2I is flip-chip mounted on the interconnection unit 200, the top electrodes 130a, 130b, and 130c and the carrier pins 201, 202, and 203 are respectively disposed in the layout manner of the respective carrier pins. An alignment coincides and the top electrode 130a is adhered to the top surface of the carrier pin 201 by a conductive adhesive material 115 (see the vertical cross-sectional view of FIG. 3C-2) coated on the top surface of each pin. The top electrode 130b is adhered to the top surface of the carrier pin 202, and the top electrode 130c is adhered to the top surface of the carrier pin 203. The semiconductor device 180 is flip-chip mounted as shown in FIG. 3B, and the figure also shows the case where the bottom surfaces of the pedestals 101, 102 are each exposed from the bottom surface of the molding body 120'.

As shown in FIG. 3C-1, another plastic sealing process is performed, and another plastic sealing layer 140 is formed by using a molding compound. The plastic sealing layer 140 may be referred to as a second plastic sealing layer to bond the lead frame 200' and a plurality of semiconductor devices adhered thereto. 180 is coated while the bottom surfaces of the respective load pins 201, 202, 203 are exposed on the bottom surface of the plastic seal layer 140. The structure shown in Fig. 3C-2 is an enlarged schematic view of a portion taken by a broken line in Fig. 3C-1. If the molding groove 120a is formed in the molding body 120', and the molding compound for forming the plastic sealing layer 140 has fluidity before being completely cured, the molding compound will invade and fill in the cutting groove 120a at this timing, and after the molding compound is cured, The portion of the molding layer 140 that is located within the cutting groove 120a functions as a mold clamping. Thereafter, the dicing step shown in FIG. 3D is performed to dicing the stack including the lead frame 200' and the mold layer 140 between the adjacent semiconductor devices 180 to form a plurality of semiconductor devices 280, that is, secondary devices. The plastic sealing layer 140 is cut to form a plurality of plastic sealing bodies 140', which may be referred to as an outer plastic sealing body or a second plastic sealing body. After the lead frame 200' is cut, the connecting ribs of the interconnection unit 200 connected to the lead frame 200' are cut and broken. . One of the molding bodies 140' encapsulates an interconnection unit 200 and a semiconductor device 180 in such a manner that the bottom surfaces of the respective supporting pins 201 to 203 are exposed on the bottom surface of the molding body 140', as shown in FIG. 3E. The map is intentionally placed with the bottom surface of the molded body 140' facing upward for viewing. In the embodiment of FIG. 3C-2, although the bottom surfaces of the pedestals 101, 102 are exposed from the bottom surface of the molding body 120', they are all covered by the molding layer 140 in the step of forming the plastic sealing layer 140. Therefore, the bottom surface of the subsequent pedestals 101, 102 is also covered by the molding body 140' cut by the plastic sealing layer 140.

The embodiments of Figures 4A-4C are all based on the method flow of Figures 3A-3D, but with slight differences. The main difference between the semiconductor device of FIG. 4A and FIG. 3C-2 is that the bottom surface of the pedestals 101, 102 is completely covered by the molding body 120', and the molding body 120' is subsequently molded by the molding layer 140. The 140' is covered, but the bottom surface of the molded body 120' is not exposed from the top surface of the molded body 140'. The main difference between the semiconductor device of FIG. 4B and FIG. 3C-2 is that the bottom surfaces of the pedestals 101, 102 are exposed from the bottom surface of the molding body 120', and in the step of forming the plastic sealing layer 140, the bottom surface of the molding body 120' Exposed from the top surface of the plastic sealing layer 140, the bottom surfaces of the pedestals 101, 102 are also exposed from the top surface of the plastic sealing layer 140 at the same time, so that the bottom surfaces of the pedestals 101, 102 and the molding body 120' are respectively molded from the plastic sealing layer. The top surface of the molded body 140' cut from the layer 140 is exposed to the outside. In addition, FIG. 4C illustrates another case where the bottom surface of the susceptors 101, 102 is covered by the molding body 120' without being exposed. In the step of forming the plastic sealing layer 140, the bottom surface of the molding body 120' is from the plastic sealing layer. The top surface of the molding body 120' is exposed, and the bottom surface of the molding body 120' can be exposed from the top surface of the molding body 140' cut from the molding layer 140 in a subsequent step.

The exemplary embodiments of the specific structures of the specific embodiments have been described above by way of illustration and the accompanying drawings. Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are intended to cover all such modifications and Any and all equivalent ranges and contents within the scope of the claims are intended to be within the spirit and scope of the invention.

180‧‧‧Power semiconductor devices

120'‧‧‧plastic body

130"‧‧‧ cutting mouth

130a‧‧‧Top electrode

130b‧‧‧Top electrode

130c‧‧‧Top electrode

Claims (13)

A semiconductor device, comprising: a wafer mounting unit having a plurality of pedestals, wherein a top surface of the pedestal is provided with a pedestal structure protruding from a top surface thereof; a flip-chip mounted on the top surface of the pedestal and arranged in a staggered manner with the mesa structure, the plurality of electrodes on the front side of the wafer are electrically connected to the plurality of pedestals one-to-one; An inner plastic package covering the wafer mounting unit and the wafer, a top end surface of the base structure and a back surface of the wafer are exposed on a top surface of the inner plastic package; and a top surface of the inner plastic package is disposed a plurality of top electrodes separated from each other on the surface, the plurality of top electrodes being electrically connected to the mesa structures and the back side of the wafer, respectively; and an interconnecting unit having a plurality of carrying pins, wherein the top portions Electrodes are respectively adhered to the load-bearing pins one-to-one; and an outer plastic package covering the interconnection unit, the top electrode and the inner plastic body, and the coating is carried out in such a manner as to carry the load The bottom surface of the pin is exposed to the outer plastic Body bottom surface; a bottom surface of the base are to be exposed from the inner bottom surface of the plastic body. The semiconductor device of claim 1, wherein a bottom surface of the pedestal is exposed from a bottom surface of the inner plastic sealing body, and a bottom surface of each of the susceptor and the inner plastic sealing body is from the outer plastic sealing body. Exposed in the top surface. The semiconductor device according to claim 1, wherein the bottom surface of the susceptor is exposed from the bottom surface of the inner plastic package but is covered by the outer plastic package. The semiconductor device according to claim 1, wherein a bottom surface of the susceptor is covered by the inner plastic package, and a bottom surface of the inner plastic package is not exposed from a top surface of the outer plastic package. The semiconductor device according to claim 1, wherein a bottom surface of the susceptor is covered by the inner molding body, and a bottom surface of the inner molding body is exposed from a top surface of the outer molding body. A method of fabricating a semiconductor device, comprising the steps of: providing an inner lead frame having a plurality of wafer mounting units, each of the wafer mounting units comprising a plurality of pedestals on a top surface of the pedestals a tray structure is disposed at one edge; a wafer is flip-chip mounted on the top surface of each of the wafer mounting units, and a plurality of electrodes on the front surface of the wafer are electrically connected one to one to the first On the susceptor, the wafer and the pedestal structure are disposed in a staggered manner; a plastic sealing process is performed to coat the inner lead frame and the wafers adhered thereto by a plastic sealing layer; from the top surface of the plastic sealing layer Grinding to thin the plastic encapsulation layer and the wafer until the top end surface of the mesa structure and the thinned back surface of the wafer are exposed to the plastic encapsulation layer; forming a metal layer over the top surface of the plastic encapsulation layer; Cutting the layer, the region overlapping the metal layer on the wafer mounting unit is cut into electrical contact with the plurality of top electrodes respectively on the back of the substrate structure and the back surface of the wafer; Leading the lead frame, the lamination layer and the lamination of the metal layer to form a plurality of semiconductor devices; further providing an outer lead frame comprising a plurality of interconnecting units, each of the interconnecting units comprising a plurality of carrying pins; The devices are respectively mounted on one of the interconnecting units, and the top electrodes of the semiconductor devices are respectively adhered one by one to the plurality of the carrying pins of the interconnecting units; another plastic sealing process is performed, using another The plastic sealing layer coats the outer lead frame and the semiconductor devices adhered thereto, such that the bottom surface of each of the carrier pins is exposed on the bottom surface of the other plastic sealing layer; The laminate including the outer lead frame and the other of the plastic seal layers is cut to form a plurality of outer plastic seals, wherein the outer plastic seal covers one of the interconnect unit and one of the semiconductor devices. The method of claim 6, wherein in the step of performing a molding process, the bottom surface of the susceptors of the wafer mounting units is covered by the plastic sealing layer. The method of claim 6, wherein in the step of performing a plastic sealing process, The bottom surfaces of the susceptors of the wafer mounting unit are exposed on the bottom surface of the plastic sealing layer. The method of claim 6, wherein after the metal layer is cut, the plastic sealing layer is cut along a cutting opening formed in the metal layer to form a lower portion of the plastic sealing layer below the cutting opening. Cutting groove. The method of claim 6, wherein the plastic sealing layer covered by the inner lead frame is coated such that the bottom surfaces of the pedestals are exposed from the bottom surface of the plastic sealing layer; The other plastic sealing layer covered by the outer lead frame is coated in such a manner that the bottom surfaces of the base and the inner plastic sealing body are exposed from the top surface of the other plastic sealing layer. The method of claim 6, wherein the plastic sealing layer covered by the inner lead frame is coated such that the bottom surfaces of the pedestals are exposed from the bottom surface of the plastic sealing layer; The other plastic sealing layer covered by the outer lead frame is coated in such a manner that the bottom surfaces of the respective base and the inner plastic sealing body are covered by the other plastic sealing layer. The method of claim 6, wherein the plastic sealing layer covered by the inner lead frame is coated in such a manner that the bottom surface of the base is covered by the plastic sealing layer; Another of the plastic sealing layers covered by the lead frame is coated in such a manner that the inner plastic sealing body is covered by the other plastic sealing layer without an exposed portion. The method of claim 6, wherein the plastic sealing layer covered by the inner lead frame is coated in such a manner that the bottom surface of the base is covered by the plastic sealing layer; The other of the plastic sealing layers covered by the lead frame is coated such that the bottom surface of the inner plastic sealing body is exposed from the top surface of the other plastic sealing layer.