CN106024646A - Full-coating wafer-level packaging method for semiconductor device - Google Patents
Full-coating wafer-level packaging method for semiconductor device Download PDFInfo
- Publication number
- CN106024646A CN106024646A CN201610382921.8A CN201610382921A CN106024646A CN 106024646 A CN106024646 A CN 106024646A CN 201610382921 A CN201610382921 A CN 201610382921A CN 106024646 A CN106024646 A CN 106024646A
- Authority
- CN
- China
- Prior art keywords
- wafer
- semiconductor device
- resin
- disk
- metal terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004806 packaging method and process Methods 0.000 title abstract description 11
- 239000011248 coating agent Substances 0.000 title abstract 6
- 238000000576 coating method Methods 0.000 title abstract 6
- 239000002184 metal Substances 0.000 claims abstract description 64
- 229910052751 metal Inorganic materials 0.000 claims abstract description 64
- 229920005989 resin Polymers 0.000 claims abstract description 44
- 239000011347 resin Substances 0.000 claims abstract description 41
- 239000002313 adhesive film Substances 0.000 claims abstract description 24
- 238000005253 cladding Methods 0.000 claims description 19
- 238000005538 encapsulation Methods 0.000 claims description 18
- 239000010408 film Substances 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 14
- 235000008429 bread Nutrition 0.000 claims description 9
- 230000010355 oscillation Effects 0.000 claims description 8
- 239000007788 liquid Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 238000007639 printing Methods 0.000 claims description 5
- 238000012360 testing method Methods 0.000 claims description 5
- 229910021642 ultra pure water Inorganic materials 0.000 claims description 4
- 239000012498 ultrapure water Substances 0.000 claims description 4
- 239000004840 adhesive resin Substances 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 238000007711 solidification Methods 0.000 claims description 3
- 230000008023 solidification Effects 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005485 electric heating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention discloses a full-coating wafer-level packaging method for a semiconductor device. The full-coating wafer-level packaging method comprises the following steps of (1) performing front surface coating on a metal terminal; (2) grinding resin and processing the surface of the metal terminal; (3) fixing a metal support plate; (4) coating the three surfaces of a chip; (5) coating the four surfaces of the chip; (6) separating the metal support plate; and (7) separating an adhesive film. By adoption of the packaging method, a half groove is manufactured; then the resin and the metal terminal are bonded and fixed on the thin metal support plate through a layer of the adhesive film; and the warping force on the front surface of the wafer is counteracted by the bonding force, so that the surface of the wafer is kept flat and leveled without being warped.
Description
Technical field
The present invention relates to field of semiconductor package, be specifically related to the full cladding of a kind of semiconductor device
Wafer-level encapsulation method.
Background technology
The shell of semiconductor integrated circuit chip is installed, plays and lay, fix, seal, protect
Protect chip and strengthen the effect of electric heating property, but also being to link up the chip internal world and external electrical
The bridge on road, the contact on chip is wired on the pin of package casing, these pins
It is connected with the foundation of other devices further through the wire in printed board.Therefore, the envelope of semiconductor device
Central processing unit and other large scale integrated circuits are played an important role by dress.
In chip-packaging structure, wafer-level packaging is to carry out packaging and testing on full wafer wafer,
Again it is carried out plastic packaging, be then cut to single-chip.
In existing wafer-level packaging method, disk warpage can cause inequality of being heated, road after disk
Technique cannot be normally carried out, and the particularly vac sorb of disk loosely, is easily caused in technical process
Fragment.Excessive warpage can make packaging body in surface soldered (SMT) assembling process, bottom
Encapsulation cannot be connected with the scolding tin between motherboard, open circuit occurs.
Summary of the invention
In view of drawbacks described above of the prior art or deficiency, it is desirable to provide circle in a kind of encapsulation process
Sheet surface warp-free semiconductor devices be entirely coated with wafer-level encapsulation method.
To achieve these goals, the present invention adopts the technical scheme that:
A kind of semiconductor device be entirely coated with wafer-level encapsulation method, comprise the following steps:
(1) the front cladding of metal terminal:
Form metal terminal in disk surfaces, disk carried out cutting groove scribing and forms half groove,
Around metal terminal and disk surfaces and covering resin, form the front cladding of metal terminal；
(2) grind resin and process metal terminal surface:
Grind resin exposes to metal terminal surface, then metal terminal is carried out surface process；
(3) fixing metal support plate:
By one layer of adhesive film, resin and metal terminal bonding are fixed on metal support plate, make gold
Belong to support plate and disk forms an entirety；
(4) three bread of chip cover:
By the thinning back side of disk, in being ground to the groove of cutting, resin exposes always, forms core
Three bread of sheet cover；
(5) the four sides cladding of chip:
At one layer of resin protection film of disk back up；
(6) metal support plate is separated:
Disk is cut by the scribe line shown by the resin protection film at the disk back side, by one
Whole disk is divided into single chips product array formula arrangement, by heating, separates on adhesive film
Metal support plate；
(7) adhesive film is separated:
The device having adhered to adhesive film being put into ultra-pure water and carries out supersonic oscillations, adhesive film is peeled off,
Dry test printing and form semiconductor device product.
Compared with prior art, the invention has the beneficial effects as follows:
Use the method for packing of the present invention, owing to having made half groove, rear by one layer of adhesive film
Resin and metal terminal are bonded and are fixed on thin metal support plate, just offsetting disk by bonding force
Face buckling force, keeps disk surfaces smooth without warpage.
Accompanying drawing explanation
By reading retouching in detail with reference to made non-limiting example is made of the following drawings
Stating, other features, purpose and advantage will become more apparent upon:
The structural representation of the front cladding of the metal terminal that Fig. 1 provides for the embodiment of the present invention；
Grind resin that Fig. 2 provides for the embodiment of the present invention and process the structure on metal terminal surface
Schematic diagram；
Fig. 3 for the embodiment of the present invention provide structural representation；
The structural representation that three bread of the chip that Fig. 4 provides for the embodiment of the present invention cover；
The structural representation of the four sides cladding of the chip that Fig. 5 provides for the embodiment of the present invention；
The structural representation separating metal support plate that Fig. 6 provides for the embodiment of the present invention；
The structural representation separating adhesive film that Fig. 7 provides for the embodiment of the present invention.
Detailed description of the invention
With embodiment, the application is described in further detail below in conjunction with the accompanying drawings.It is appreciated that
, specific embodiment described herein is used only for explaining related invention, rather than to this
Bright restriction.It also should be noted that, for the ease of describe, accompanying drawing illustrate only with
The part that invention is relevant.
It should be noted that in the case of not conflicting, the embodiment in the application and embodiment
In feature can be mutually combined.Describe this below with reference to the accompanying drawings and in conjunction with the embodiments in detail
Application.
A kind of semiconductor device be entirely coated with wafer-level encapsulation method, comprise the following steps:
(1) the front cladding of metal terminal:
Form metal terminal in disk surfaces, disk carried out cutting groove scribing and forms half groove,
Around metal terminal and disk surfaces and covering resin, form the front cladding of metal terminal；
(2) grind resin and process metal terminal surface:
Grind resin exposes to metal terminal surface, then metal terminal is carried out surface process；
(3) fixing metal support plate:
By one layer of adhesive film, resin and metal terminal bonding are fixed on metal support plate, make gold
Belong to support plate and disk forms an entirety；
(4) three bread of chip cover:
By the thinning back side of disk, in being ground to the groove of cutting, resin exposes always, forms core
Three bread of sheet cover；
(5) the four sides cladding of chip:
At one layer of resin protection film of disk back up；
(6) metal support plate is separated:
Disk is cut by the scribe line shown by the resin protection film at the disk back side, by one
Whole disk is divided into single chips product array formula arrangement, by heating, separates on adhesive film
Metal support plate；
(7) adhesive film is separated:
The device having adhered to adhesive film being put into ultra-pure water and carries out supersonic oscillations, adhesive film is peeled off,
Dry test printing and form semiconductor device product.
Preferably, in described step (2), utilize the method for electroless chemical plating to metal terminal
Carry out surface process.
Preferably, in described step (5), at disk back up layer of transparent liquid resin material
Material, forms resin film after solidification.
Preferably, the thickness of described transparent liquid resin material is 25-35um.
Preferably, in described step (6), the temperature of heating is 50-70 DEG C, and the time is 20s～40s,
The mode of heating is Hot-blast Heating.
Preferably, the temperature of described heating is 60 DEG C.
Preferably, in described step (7), the frequency of described supersonic oscillations more than 20kHz,
Time is 10-30s.
Preferably, frequency 20-100kHz of described supersonic oscillations, the time is 20s.
Preferably, described resin is epoxy resin.
Preferably, described adhesive film is temperature-sensitive biadhesive film.
Below by specific embodiment, the present invention is described further:
Embodiment 1
See Fig. 1, the front cladding of metal terminal:
Metal terminal 102 is formed at disk 101 electroplating surface by the method for wafer level packaging,
The method using half scribing forms half groove 104 to disk cutting groove scribing, and resin printing will circle
Sheet 101 surface metal terminal 102 all covers liquid or powdered form resin 103, is formed
The front cladding of metal terminal 102, resin is epoxy resin.
See Fig. 2, grind resin and process metal terminal surface:
Resin 103 is ground to metal terminal 102 surfacing and exposes, and utilizes electroless chemical plating
Method metal terminal 102 is carried out surface process, improve terminal weldability.
See Fig. 3, fixing metal support plate:
By disk by one layer of temperature-sensitive biadhesive film 201 by resin 103 and metal terminal 102
Bonding is fixed on thin metal support plate 202, offsets disk front buckling force by bonding force, protects
Hold disk 101 surfacing without warpage, thin metal support plate 202 and disk 101 formed one whole
Body.
Seeing Fig. 4, three bread of chip cover:
To disk 101 thinning back side, it is ground to resin dew in half groove 104 of cutting groove always
Going out, three bread forming chip cover.
See Fig. 5, the four sides cladding of chip:
The transparent liquid resin material of disk 101 one layer of about 30um of back up, shape after solidification
Resin thin film 105, resin film 105 protects the back side of disk 101 not collapse limit, draw
Wound, forms the four sides cladding of chip.
See Fig. 6, separation metal support plate:
By the scribe line 106 of disk 101 back-protective resin film 105 display to disk 101
Cut, one whole disk is divided into single chips product array formula arrangement, passes through hot blast
The temperature of heating is to 60 DEG C, and the time is 30s, thin metal support plate 202 and biadhesive film 201
Separate.
See Fig. 7, separation adhesive film:
The biadhesive film having adhered to semiconductor device is put into ultra-pure water and carries out supersonic oscillations,
Frequency 80kHz, the time is 20s, and semiconductor device is peeled off, and dries test printing and forms product.
Embodiment 2
Essentially identical with the full cladding wafer-level encapsulation method of embodiment 1, except that:
Separate in metal support plate: Hot-blast Heating to temperature is 50 DEG C, and the time is 40s；
Separate in adhesive film: frequency 20kHz, the time is 30s.
Embodiment 3
Essentially identical with the full cladding wafer-level encapsulation method of embodiment 1, except that:
Separate in metal support plate: Hot-blast Heating to temperature is 70 DEG C, and the time is 20s；
Separate in adhesive film: frequency 100kHz, the time is 10s.
Above description is only the preferred embodiment of the application and saying institute's application technology principle
Bright.It will be appreciated by those skilled in the art that invention scope involved in the application, do not limit
In the technical scheme of the particular combination of above-mentioned technical characteristic, also should contain simultaneously without departing from
In the case of described inventive concept, above-mentioned technical characteristic or its equivalent feature carry out combination in any
And other technical scheme formed.Such as features described above and (but not limited to) disclosed herein
The technical characteristic with similar functions is replaced mutually and the technical scheme that formed.
Claims (10)
1. a semiconductor device be entirely coated with wafer-level encapsulation method, it is characterised in that include
Following steps:
(1) the front cladding of metal terminal:
Form metal terminal in disk surfaces, disk carried out cutting groove scribing and forms half groove,
Around metal terminal and disk surfaces and covering resin, form the front cladding of metal terminal；
(2) grind resin and process metal terminal surface:
Grind resin exposes to metal terminal surface, then metal terminal is carried out surface process；
(3) fixing metal support plate:
By one layer of adhesive film, resin and metal terminal bonding are fixed on metal support plate, make gold
Belong to support plate and disk forms an entirety；
(4) three bread of chip cover:
By the thinning back side of disk, in being ground to the groove of cutting, resin exposes always, forms core
Three bread of sheet cover；
(5) the four sides cladding of chip:
At one layer of resin protection film of disk back up；
(6) metal support plate is separated:
Disk is cut by the scribe line shown by the resin protection film at the disk back side, by one
Whole disk is divided into single chips product array formula arrangement, by heating, separates on adhesive film
Metal support plate；
(7) adhesive film is separated:
The device having adhered to adhesive film being put into ultra-pure water and carries out supersonic oscillations, adhesive film is peeled off,
Dry test printing and form semiconductor device product.
Semiconductor device the most according to claim 1 be entirely coated with wafer-level encapsulation method, it is special
Levy and be, in described step (2), utilize the method for electroless chemical plating that metal terminal is carried out
Surface processes.
Semiconductor device the most according to claim 1 be entirely coated with wafer-level encapsulation method, it is special
Levy and be, in described step (5), at disk back up layer of transparent liquid resin material,
Resin film is formed after solidification.
Semiconductor device the most according to claim 3 be entirely coated with wafer-level encapsulation method, it is special
Levying and be, the thickness of described transparent liquid resin material is 25-35um.
Semiconductor device the most according to claim 1 be entirely coated with wafer-level encapsulation method, it is special
Levying and be, in described step (6), the temperature of heating is 50-70 DEG C, and the time is 20s～40s,
The mode of heating is Hot-blast Heating.
Semiconductor device the most according to claim 5 be entirely coated with wafer-level encapsulation method, it is special
Levying and be, the temperature of described heating is 60 DEG C.
Semiconductor device the most according to claim 1 be entirely coated with wafer-level encapsulation method, it is special
Levying and be, in described step (7), the frequency of described supersonic oscillations is more than 20kHz, time
For 10-30s.
Semiconductor device the most according to claim 7 be entirely coated with wafer-level encapsulation method, it is special
Levying and be, in described step (7), the frequency of described supersonic oscillations is 20-100kHz, time
Between be 20s.
9. according to the full cladding wafer level envelope of the semiconductor device described in any one of claim 1-8
Dress method, it is characterised in that described resin is epoxy resin.
Semiconductor device the most according to claim 9 be entirely coated with wafer-level encapsulation method,
It is characterized in that, described adhesive film is temperature-sensitive biadhesive film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610382921.8A CN106024646A (en) | 2016-06-01 | 2016-06-01 | Full-coating wafer-level packaging method for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610382921.8A CN106024646A (en) | 2016-06-01 | 2016-06-01 | Full-coating wafer-level packaging method for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106024646A true CN106024646A (en) | 2016-10-12 |
Family
ID=57093192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610382921.8A Pending CN106024646A (en) | 2016-06-01 | 2016-06-01 | Full-coating wafer-level packaging method for semiconductor device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107611077A (en) * | 2017-09-21 | 2018-01-19 | 深圳市环基实业有限公司 | A kind of IC package processing unit and processing method |
| CN108117042A (en) * | 2016-11-28 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method, electronic device |
| CN109326528A (en) * | 2017-08-01 | 2019-02-12 | 台虹科技股份有限公司 | Die package method |
| CN110328211A (en) * | 2019-06-19 | 2019-10-15 | 东莞高伟光学电子有限公司 | It is a kind of for separating the separation method and chemical reagent of nonmetallic sensor |
| CN111199906A (en) * | 2018-11-16 | 2020-05-26 | 典琦科技股份有限公司 | Method for manufacturing chip package |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040113283A1 (en) * | 2002-03-06 | 2004-06-17 | Farnworth Warren M. | Method for fabricating encapsulated semiconductor components by etching |
| JP2009016378A (en) * | 2007-06-29 | 2009-01-22 | Fujikura Ltd | Multilayer wiring board and multilayer wiring board manufacturing method |
| TW200915453A (en) * | 2007-06-19 | 2009-04-01 | Vertical Circuits Inc | Wafer level surface passivation of stackable integrated circuit chips |
| CN103681535A (en) * | 2012-09-01 | 2014-03-26 | 万国半导体股份有限公司 | Wafer level packaging element with thick bottom pedestal and making method thereof |
| CN103904045A (en) * | 2014-04-18 | 2014-07-02 | 江阴长电先进封装有限公司 | Wafer-level CSP structure with insulated side wall and packaging method thereof |
| US20150170987A1 (en) * | 2013-12-18 | 2015-06-18 | Infineon Technologies Ag | Semiconductor Devices and Methods for Manufacturing Semiconductor Devices |
-
2016
- 2016-06-01 CN CN201610382921.8A patent/CN106024646A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040113283A1 (en) * | 2002-03-06 | 2004-06-17 | Farnworth Warren M. | Method for fabricating encapsulated semiconductor components by etching |
| TW200915453A (en) * | 2007-06-19 | 2009-04-01 | Vertical Circuits Inc | Wafer level surface passivation of stackable integrated circuit chips |
| JP2009016378A (en) * | 2007-06-29 | 2009-01-22 | Fujikura Ltd | Multilayer wiring board and multilayer wiring board manufacturing method |
| CN103681535A (en) * | 2012-09-01 | 2014-03-26 | 万国半导体股份有限公司 | Wafer level packaging element with thick bottom pedestal and making method thereof |
| US20150170987A1 (en) * | 2013-12-18 | 2015-06-18 | Infineon Technologies Ag | Semiconductor Devices and Methods for Manufacturing Semiconductor Devices |
| CN103904045A (en) * | 2014-04-18 | 2014-07-02 | 江阴长电先进封装有限公司 | Wafer-level CSP structure with insulated side wall and packaging method thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108117042A (en) * | 2016-11-28 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method, electronic device |
| CN109326528A (en) * | 2017-08-01 | 2019-02-12 | 台虹科技股份有限公司 | Die package method |
| CN107611077A (en) * | 2017-09-21 | 2018-01-19 | 深圳市环基实业有限公司 | A kind of IC package processing unit and processing method |
| CN107611077B (en) * | 2017-09-21 | 2020-02-21 | 深圳市环基实业有限公司 | IC packaging processing device and processing method |
| CN111199906A (en) * | 2018-11-16 | 2020-05-26 | 典琦科技股份有限公司 | Method for manufacturing chip package |
| CN111199906B (en) * | 2018-11-16 | 2022-06-07 | 典琦科技股份有限公司 | Method for manufacturing chip package |
| CN110328211A (en) * | 2019-06-19 | 2019-10-15 | 东莞高伟光学电子有限公司 | It is a kind of for separating the separation method and chemical reagent of nonmetallic sensor |
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| CB02 | Change of applicant information |
Address after: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant before: Fujitsu Microelectronics Co., Ltd., Nantong |
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Application publication date: 20161012 |