CN111199906B - Method for manufacturing chip package - Google Patents
Method for manufacturing chip package Download PDFInfo
- Publication number
- CN111199906B CN111199906B CN201811366789.7A CN201811366789A CN111199906B CN 111199906 B CN111199906 B CN 111199906B CN 201811366789 A CN201811366789 A CN 201811366789A CN 111199906 B CN111199906 B CN 111199906B
- Authority
- CN
- China
- Prior art keywords
- wafer
- layer
- microns
- chip
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
Abstract
The invention relates to a manufacturing method of a chip package body, which comprises the following operations. A wafer is provided, which has a first surface and a second surface opposite to each other, and includes a plurality of conductive bumps on the first surface. The wafer is thinned from the second surface toward the first surface. The wafer is cut to form a plurality of chips, wherein each chip is provided with a third surface and a fourth surface opposite to the third surface, and the conductive bumps are positioned on the third surface. The chips are disposed on the substrate such that the conductive bumps are located between the substrate and the first surface, wherein a gap is formed between any two adjacent chips, and the gap is 50-140 μm. An insulating layer is formed to fill the gaps and cover the chips. The insulating layer is cut along the gaps to form a plurality of chip packages. The method can avoid the problem of contraposition deviation.
Description
Technical Field
The invention relates to a manufacturing method of a chip packaging body.
Background
The conventional chip packaging process is to package the semiconductor chips cut from the wafer one by one, which is time-consuming and labor-consuming. Or, the semiconductor chips cut from the wafer are arranged on the carrier one by one and packaged, and then cut into the chip packages again.
Disclosure of Invention
In view of the above, the present invention is directed to a method for manufacturing a chip package that solves the above problems.
The method of the invention provides a manufacturing method of a chip packaging body, which comprises the following steps: first, a wafer is provided, which has a first surface and a second surface opposite to the first surface, and includes a plurality of conductive bumps on the first surface. The wafer is thinned from the second surface toward the first surface. The wafer is cut to form a plurality of chips, wherein each chip is provided with a third surface and a fourth surface opposite to the third surface, and the conductive bumps are positioned on the third surface. The chips are arranged on the substrate, so that the conductive bumps are positioned between the substrate and the first surface, wherein a gap is formed between any two adjacent chips, and the gap is 50-140 micrometers. An insulating layer is formed to fill the gaps and cover the chips. The insulating layer is cut along the gaps to form a plurality of chip packages.
According to an embodiment of the present invention, the wafer further includes a surface treatment layer on each of the conductive bumps.
According to an embodiment of the present invention, after the step of forming the surface treatment layer and before the step of thinning the wafer, the method further includes: forming a first adhesion layer to cover the first surface and the surface treatment layer; and forming a first carrier on the first adhesive layer.
According to an embodiment of the present invention, after the step of thinning the wafer and before the step of cutting the wafer, the method further includes: and forming a second adhesion layer and a second carrier plate to cover the second surface, wherein the second adhesion layer is positioned between the second carrier plate and the second surface.
According to an embodiment of the present invention, after the step of forming the second carrier and before the step of dicing the wafer, the method further includes: heating the first adhesive layer to a first temperature to remove the first carrier plate and the first adhesive layer; and cleaning the conductive bumps and the surface treatment layer of the wafer.
According to an embodiment of the present invention, the first temperature is 70 ℃ to 90 ℃.
According to an embodiment of the present invention, after the step of cleaning the wafer and before the step of dicing the wafer, the method further comprises: heating the second adhesive layer to a second temperature to remove the second carrier and the second adhesive layer; and providing a first adhesive tape to cover the second surface of the wafer.
According to an embodiment of the present invention, the second temperature is 110 ℃ to 130 ℃.
According to an embodiment of the present invention, after the step of dicing the wafer and before the step of disposing the chips on the substrate, the method further includes: providing a second adhesive tape to cover the third surface of the chips; and removing the first tape.
According to an embodiment of the present invention, after the step of forming the insulating layer and before the step of cutting the insulating layer along the gaps, the method further includes: the substrate is removed.
The method can avoid the problem of contraposition deviation.
Drawings
In order to make the aforementioned and other objects, features, advantages and embodiments of the invention more comprehensible, the following description is given:
fig. 1 shows a flowchart of a method for manufacturing a chip package according to an embodiment of the present invention.
Fig. 2A to 2K are schematic cross-sectional views illustrating various processing stages in a method for manufacturing a chip package according to an embodiment of the invention.
100: the method 20 comprises the following steps: wafer
20 a: chip 20T 1: thickness of
20T 2: thickness 201: first surface
201 a: third surface 202: second surface
202 a: fourth surface 203: conductive bump
203H: height 204: surface treatment layer
204H: height 220: a first adhesive layer
230: the first carrier 240: the second adhesive layer
250: second carrier 260: first adhesive tape
270: second tape 280: substrate
282: polymer adhesive layer 284: metal layer
286: dielectric layer 290: insulating layer
d: distance CW: width of cut
GP: gap T1: first temperature
T2: second temperature Tf: total thickness of
Detailed Description
In order to make the description of the present disclosure more complete and complete, the following description is given for illustrative purposes of the present invention; it is not intended to be the only form in which the embodiments of the invention may be practiced or utilized. The various embodiments disclosed below may be combined with or substituted for one another where appropriate, and additional embodiments may be added to one embodiment without further recitation or description.
In the following description, numerous specific details are set forth to provide a thorough understanding of the following embodiments. However, embodiments of the invention may be practiced without these specific details. In other instances, well-known structures and devices are shown schematically in the drawings to simplify the drawing.
The invention provides a method for manufacturing a chip package, which can avoid the problem of alignment deviation. Fig. 1 is a flowchart illustrating a method of manufacturing a chip package according to an embodiment of the present invention. Fig. 2A to 2K are schematic cross-sectional views illustrating various processing stages in a method for manufacturing a chip package according to an embodiment of the invention. As shown in fig. 1, the method 100 includes step S110, step S120, step S130, step S140, step S150, and step S160.
In step S110, a wafer 20 is provided, as shown in fig. 2A. Specifically, the wafer 20 has a first surface 201 and a second surface 202 opposite to the first surface 201, and the wafer 20 includes a plurality of conductive bumps 203 on the first surface 201. In one embodiment, the wafer 20 may include silicon (silicon), Germanium (Germanium), or a group III-V element, but is not limited thereto. In various embodiments, the conductive bump 203 comprises gold (gold), tin (tin), copper (copper), nickel (nickel), or other suitable metal material. In one embodiment, the conductive bumps 203 each have a height 203H of 20-45 microns, such as 22 microns, 24 microns, 26 microns, 28 microns, 30 microns, 32 microns, 34 microns, 36 microns, 38 microns, 40 microns, or 42 microns.
Please continue to refer to fig. 2A. In various embodiments, the wafer 20 further includes a surface treatment layer 204. Specifically, the surface treatment layer 204 is disposed on each of the conductive bumps 203. In some embodiments, the surface treatment layer 204 may be a single layer structure such as a nickel layer or a tin layer, or a multi-layer structure composed of sub-layers of different materials such as a nickel layer and a gold layer, but is not limited thereto. In many examples, the surface finish 204 has a height 204H of 2 to 10 microns, e.g., 3 microns, 4 microns, 5 microns, 6 microns, 7 microns, 8 microns, or 9 microns. The surface treatment layer 204 can be formed by a physical method such as Nickel-Gold electroplating and tin spraying, or a chemical method such as Nickel Immersion Gold (ENIG). The surface treatment layer 204 may prevent the conductive bump 203 from being oxidized by contacting air. In some embodiments, the wafer 20 has a first thickness 20T1 of 525 to 725 microns, such as may be 550 microns, 575 microns, 600 microns, 625 microns, 650 microns, 675 microns, or 700 microns.
Referring to fig. 2B, in various embodiments, after the step of forming the surface treatment layer 204 and before the step S120, a first adhesive layer 220 is formed to cover the first surface 201 and the surface treatment layer 204, and then a first carrier 230 is formed on the first adhesive layer 220. The first adhesive layer 220 can reduce stress generated in the subsequent thinning process, thereby reducing the risk of wafer cracking. In one embodiment, the first adhesive layer 220 includes a UV release adhesive (UV release adhesive) or a thermal release adhesive (thermal release adhesive). Here, it should be noted that the pyrolysis temperature of the first adhesive layer 220 is about 70 ℃ to 90 ℃, such as 72 ℃, 75 ℃, 77 ℃, 80 ℃, 82 ℃, 85 ℃ or 87 ℃. In one embodiment, the first adhesive layer 220 may be formed by spin coating (spin coating), but is not limited thereto. The first carrier 230 can provide better protection effect for the wafer 20, and therefore, the first carrier 230 can be a hard insulating substrate, such as a glass substrate, a ceramic substrate, a sapphire substrate, or a quartz substrate, but is not limited thereto.
In step S120, the wafer 20 is thinned from the second surface 202 toward the first surface 201, as shown in fig. 2C. In various embodiments, the wafer 20 may be thinned by using a chemical-mechanical polishing (cmp) method, a dry etching method, or other suitable processing methods, so as to make the chip package have a smaller size. In some embodiments, after the step S120 of thinning the wafer 20, the conductive bumps 203 and the surface treatment layer 204 have a second total thickness 20T2 of 100 to 150 microns, such as 110 microns, 115 microns, 120 microns, 125 microns, 130 microns, 135 microns, 140 microns or 145 microns.
Referring to fig. 2D, in various embodiments, after the step S120 of thinning the wafer 20 and before the step S130, a second adhesive layer 240 and a second carrier 250 may be formed to cover the second surface 202, wherein the second adhesive layer 240 is located between the second carrier 250 and the second surface 202. Since the thinned wafer 20 is fragile, the second carrier 250 can provide a supporting force for the wafer 20, thereby reducing the risk of cracking the wafer 20. Accordingly, the second carrier 250 may be a hard insulating substrate, such as a glass substrate, a ceramic substrate, a sapphire substrate, or a quartz substrate, but is not limited thereto. The second adhesive layer 240 can provide adhesion between the wafer 20 and the second carrier 250. In one embodiment, the second adhesive layer 240 includes a UV release adhesive (UV release adhesive) or a thermal release adhesive (thermal release adhesive). Here, it should be noted that the pyrolysis temperature of the second adhesive layer 240 is about 110 ℃ to 130 ℃, for example, 112 ℃, 115 ℃, 117 ℃, 120 ℃, 122 ℃, 125 ℃ or 127 ℃. In one embodiment, the second adhesive layer 240 may be formed by spin coating (spin coating), but is not limited thereto.
Referring to fig. 2E, in various embodiments, after the step of forming the second carrier 250 and before the step S130, the first adhesive layer 220 may be heated to the first temperature T1 to remove the first carrier 230 and the first adhesive layer 220. In one embodiment, the first temperature T1 is 70 ℃ to 90 ℃, and may be, for example, 72 ℃, 75 ℃, 77 ℃, 80 ℃, 82 ℃, 85 ℃ or 87 ℃. In more detail, since the pyrolysis temperature of the first adhesive layer 220 is about 70 ℃ to 90 ℃ and the pyrolysis temperature of the second adhesive layer 240 is about 110 ℃ to 130 ℃, when the first temperature T1(70 ℃ to 90 ℃) is heated, the first carrier 230 can fall off together with the decrease of the viscosity of the first adhesive layer 220, and the second carrier 250 is still adhered to the second surface 202 through the second adhesive layer 240. In addition, after the first carrier 230 and the first adhesive layer 220 are removed, the conductive bumps 203 and the surface treatment layer 204 of the wafer 20 can be cleaned to remove the adhesive residues or dust on the conductive bumps 203 and the surface treatment layer 204 on the first surface 201 of the wafer 20, thereby avoiding the problem of poor electrical contact at the application end.
Referring to fig. 2F, in various embodiments, after the step of cleaning the wafer 20 and before the step S130, the second adhesive layer 240 may be heated to the second temperature T2 to remove the second carrier 250 and the second adhesive layer 240. In one embodiment, the second temperature T2 is 110 ℃ to 130 ℃, and may be, for example, 112 ℃, 115 ℃, 117 ℃, 120 ℃, 122 ℃, 125 ℃ or 127 ℃. Next, a first tape 260 is provided to cover the second surface 202 of the wafer 20 for fixing the wafer 20 in a subsequent dicing process. In various embodiments, the first adhesive Tape 260 is an elastic dicing Tape, such as an ultraviolet Tape (UV Tape).
In step S130, the wafer 20 is diced to form a plurality of chips 20a, as shown in fig. 2G. In various embodiments, step S130 may be implemented using cutter wheel cutting, laser cutting or water jet cutting. As described above, since the first tape 260 is a dicing tape having elasticity, after the wafer 20 is diced, any two adjacent chips 20a are spaced apart by a distance d. In one embodiment, the distance d is 50 to 60 microns, such as 52 microns, 54 microns, 56 microns, or 58 microns, but not limited thereto. After the step S130 is completed, the wafer 20 is separated into a plurality of chips 20a, and the chips 20a are not scattered around by the first tape 260. Each chip 20a has a third surface 201a and a fourth surface 202a opposite to the third surface 201a, and each chip 20a includes at least one conductive bump 203 on the third surface 201 a. It is understood that the third surface 201a is a portion of the first surface 201, and the fourth surface 202a is a portion of the second surface 202. In some embodiments, each chip 20a may further include a surface treatment layer 204 on the conductive bump 203.
Next, referring to fig. 2H, in various embodiments, after the step S130 of dicing the wafer 20 and before the step S140, a second tape 270 may be provided to cover the third surfaces 201a of the chips 20 a. In various embodiments, the second Tape 270 is a transpose Tape, such as a Blue Tape (Blue Tape). Then, the first tape 260 is removed. The second adhesive tape 270 is disposed to facilitate the chips 20a to be removed one by one without contaminating the conductive bumps 203 and the surface treatment layer 204 on the third surface 201 a.
In step S140, the chip 20a is disposed on a substrate 280, as shown in fig. 2I. It should be noted that the conductive bump 203 of the chip 20a is disposed downward on the substrate 280, and therefore, the conductive bump 203 is located between the substrate 280 and the third surface 201 a. There is a gap GP between any two adjacent chips 20a, and each gap GP is 50 to 140 micrometers, but not limited thereto. For example, the gap GP may be 50 to 60 micrometers, 60 to 70 micrometers, 70 to 80 micrometers, 80 to 90 micrometers, 90 to 100 micrometers, 100 to 110 micrometers, 110 to 120 micrometers, 120 to 130 micrometers or 130 to 140 micrometers, but not limited thereto. Since the chips 20a are rearranged on the substrate 280 after the step S140 is completed, and the relative position between two adjacent chips 20a is redefined, the problem of alignment shift in the prior art can be solved in the subsequent dicing process. In various embodiments, the substrate 280 may include a polymer adhesive layer 282, a metal layer 284, and a dielectric layer 286. Specifically, the metal layer 284 is sandwiched between the polymer adhesive layer 282 and the dielectric layer 286, and the conductive bump 203 of the chip 20a is located between the polymer adhesive layer 282 and the third surface 201 a. It should be noted that the third surface 201a of the chip 20a must be spaced apart from the polymer adhesive layer 282 by a specific distance so that the subsequent insulating layer can smoothly cover the third surface 201a of the chip 20 a. In one embodiment, the surface treatment layer 204 on the conductive bump 203 is immersed in the polymer adhesive layer 282. In various embodiments, the polymer adhesive layer 282 comprises Polyimide (PI) or epoxy (epoxy); metal layer 284 includes copper (Cu); and the dielectric layer 286 includes, but is not limited to, glass fiber FR 4.
In step S150, an insulating layer 290 is formed to fill the gap GP and cover the chip 20a, as shown in fig. 2J. The insulating layer 290 may serve as an encapsulation layer of the chip 20a to protect the exposed outer surface of the chip 20 a. In various embodiments, the material used for the insulating layer 290 may be polyimide (polyimide), Epoxy (Epoxy), or other suitable insulating material. In some embodiments, the insulating layer 290 may be formed by printing (printing), coating (coating) or molding (molding). In the present embodiment, after the step S150 of forming the insulating layer 290, the chip 20a, the insulating layer 290, the conductive bump 203 and the surface treatment layer 204 have a total thickness Tf of 120 to 210 microns, such as 125 microns, 130 microns, 135 microns, 140 microns, 145 microns, 150 microns, 155 microns, 160 microns, 165 microns, 170 microns, 175 microns, 180 microns, 185 microns, 190 microns, 195 microns, 200 microns or 205 microns. In one embodiment, the substrate 280 may be removed after the step S150 of forming the insulating layer 290.
In some embodiments, after the step S150 of forming the insulating layer 290, a Laser Mark (not shown) may be disposed on the insulating layer 290 of each corresponding chip 20a for indicating a product name of a chip package to be formed subsequently.
In step S160, the insulating layer 290 is cut along each gap GP to form a plurality of chip packages, as shown in fig. 2K. In one embodiment, the insulating layer 290 may be cut along the center of each gap GP, for example, to form a plurality of chip packages. In various embodiments, this step S160 can be achieved using cutter wheel cutting, laser cutting, or water jet cutting. In the present embodiment, the cutting width CW of the insulating layer 290 along each gap GP is 15 to 100 micrometers, such as 15 to 20 micrometers, 25 to 30 micrometers, 35 to 40 micrometers, 45 to 50 micrometers, 55 to 60 micrometers, 65 to 70 micrometers, 75 to 80 micrometers, 85 to 90 micrometers or 95 to 100 micrometers. It should be noted that, since the cutting width CW is smaller than the width of the gap GP, the sidewall of each chip package obtained after performing step S160, which is adjacent to the center of the gap GP, still has a portion of the insulating layer 290 to protect the chip 20 a. In other words, each outer surface of each chip package is protected by the insulating layer 290, and only the surface treatment layer 204 is exposed for external electrical connection.
In various examples, the chip package may be used to package a light sensing element or a light emitting element. However, the application is not limited thereto, and for example, the present invention may be applied to various electronic components (electronic components) including integrated circuits such as discrete devices, active or passive devices (active or passive devices), digital circuits or analog circuits (digital or analog circuits), for example, optoelectronic devices (opto-electronic devices), Micro-Electro-Mechanical systems (MEMS), Micro-fluidic systems (Micro fluidic systems), or Physical sensors (Physical sensors) which measure changes in Physical quantities such as heat, light, and pressure. In particular, a Wafer Scale Package (WSP) process may be used to package semiconductor chips such as image sensors, light-emitting diodes (LEDs), diodes (diodes), solar cells (solar cells), radio frequency devices (RF circuits), accelerometers (accelerometers), gyroscopes (gyroscopes), micro actuators (micro actuators), surface acoustic wave devices (surface acoustic wave devices), pressure sensors (process sensors), or inkjet heads (ink printer heads).
In summary, the manufacturing method of the chip package of the present invention can avoid the problem of misalignment.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method of manufacturing a chip package, comprising:
providing a wafer, wherein the wafer is provided with a first surface and a second surface opposite to the first surface, and the wafer comprises a plurality of conductive bumps positioned on the first surface;
thinning the wafer from the second surface toward the first surface;
before cutting the wafer, providing a first adhesive tape to cover the second surface of the wafer;
cutting the wafer to form a plurality of chips, wherein each chip is provided with a third surface and a fourth surface opposite to the third surface, and the conductive bumps are positioned on the third surface;
disposing the chips on a substrate such that the conductive bumps are located between the substrate and the third surface, wherein a gap is formed between any two adjacent chips, and each gap is 50-140 μm;
forming an insulating layer to fill the gap and cover the third surface of the chip; and
and cutting the insulating layer along the gaps to form a plurality of chip packages.
2. The method of claim 1, wherein the wafer further comprises a surface treatment layer on each of the conductive bumps.
3. The method of manufacturing a chip package according to claim 2, wherein after the step of forming the surface treatment layer and before the step of thinning the wafer, the method further comprises:
forming a first adhesion layer to cover the first surface and the surface treatment layer; and
forming a first carrier on the first adhesive layer.
4. The method of manufacturing a chip package according to claim 3, wherein after the step of thinning the wafer and before the step of cutting the wafer, further comprising:
and forming a second adhesion layer and a second carrier plate to cover the second surface, wherein the second adhesion layer is positioned between the second carrier plate and the second surface.
5. The method of claim 4, wherein after the step of forming the second carrier and before the step of dicing the wafer, the method further comprises:
heating the first adhesive layer to a first temperature to remove the first carrier and the first adhesive layer; and
and cleaning the conductive bumps and the surface treatment layer of the wafer.
6. The method of claim 5, wherein the first temperature is 70-90 ℃.
7. The method of claim 5, further comprising, after the step of cleaning the wafer and before the step of dicing the wafer:
heating the second adhesive layer to a second temperature to remove the second carrier and the second adhesive layer.
8. The method of claim 7, wherein the second temperature is in a range of 110 ℃ to 130 ℃.
9. The method of claim 7, further comprising, after the step of dicing the wafer and before the step of disposing the chips on the substrate:
providing a second adhesive tape covering the third surface of the chip; and
removing the first adhesive tape.
10. The method of claim 1, further comprising, after the step of forming the insulating layer and before the step of cutting the insulating layer along the gaps:
the substrate is removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811366789.7A CN111199906B (en) | 2018-11-16 | 2018-11-16 | Method for manufacturing chip package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811366789.7A CN111199906B (en) | 2018-11-16 | 2018-11-16 | Method for manufacturing chip package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111199906A CN111199906A (en) | 2020-05-26 |
| CN111199906B true CN111199906B (en) | 2022-06-07 |
Family
ID=70745512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811366789.7A Active CN111199906B (en) | 2018-11-16 | 2018-11-16 | Method for manufacturing chip package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111199906B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1993809A (en) * | 2004-08-03 | 2007-07-04 | 古河电气工业株式会社 | Method of producing a semiconductor device, and wafer-processing tape |
| CN102270610A (en) * | 2010-06-02 | 2011-12-07 | 台湾积体电路制造股份有限公司 | Integrated circuit device and packaging assembly |
| CN105489510A (en) * | 2014-10-02 | 2016-04-13 | 住友电木株式会社 | Method for manufacturing semiconductor device and semiconductor device |
| CN106024646A (en) * | 2016-06-01 | 2016-10-12 | 南通富士通微电子股份有限公司 | Full-coating wafer-level packaging method for semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI303870B (en) * | 2005-12-30 | 2008-12-01 | Advanced Semiconductor Eng | Structure and mtehod for packaging a chip |
| JP5235829B2 (en) * | 2009-09-28 | 2013-07-10 | 株式会社東芝 | Semiconductor device manufacturing method, semiconductor device |
-
2018
- 2018-11-16 CN CN201811366789.7A patent/CN111199906B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1993809A (en) * | 2004-08-03 | 2007-07-04 | 古河电气工业株式会社 | Method of producing a semiconductor device, and wafer-processing tape |
| CN102270610A (en) * | 2010-06-02 | 2011-12-07 | 台湾积体电路制造股份有限公司 | Integrated circuit device and packaging assembly |
| CN105489510A (en) * | 2014-10-02 | 2016-04-13 | 住友电木株式会社 | Method for manufacturing semiconductor device and semiconductor device |
| CN106024646A (en) * | 2016-06-01 | 2016-10-12 | 南通富士通微电子股份有限公司 | Full-coating wafer-level packaging method for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111199906A (en) | 2020-05-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI575779B (en) | Chip package and method for forming the same | |
| TWI687986B (en) | Method for manufacturing chip package | |
| US9006896B2 (en) | Chip package and method for forming the same | |
| US9355881B2 (en) | Semiconductor device including a dielectric material | |
| TWI539538B (en) | Semiconductor device and manufacturing method thereof | |
| KR20150104467A (en) | Manufacturing method of semiconductor device and semiconductor device thereof | |
| US9153528B2 (en) | Chip package and method for forming the same | |
| CN102386197A (en) | Image sensor chip package and method for forming the same | |
| US20160351608A1 (en) | Chip package and method of manufacturing the same | |
| CN102544101B (en) | Chip package and manufacturing method thereof | |
| US9024437B2 (en) | Chip package and method for forming the same | |
| US9275958B2 (en) | Chip package and method for forming the same | |
| US20160079110A1 (en) | Semiconductor package, carrier structure and fabrication method thereof | |
| TWI677035B (en) | Semiconductor package and method for forming thereof | |
| TWI458058B (en) | Chip package and method for forming the same | |
| CN111199906B (en) | Method for manufacturing chip package | |
| CN110970361B (en) | Method for manufacturing chip package | |
| US10665509B2 (en) | Method for manufacturing chip packages | |
| CN111199887B (en) | Method for manufacturing chip package | |
| TWI670779B (en) | Method for manufacturing chip package | |
| CN110970362B (en) | Method for manufacturing chip package | |
| US8836134B2 (en) | Semiconductor stacked package and method of fabricating the same | |
| US10937760B2 (en) | Method for manufacturing a chip package | |
| US10777461B2 (en) | Method for manufacturing a chip package | |
| CN111463134A (en) | Method for manufacturing chip package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |