CN111199887B - Method for manufacturing chip package - Google Patents

Method for manufacturing chip package Download PDF

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Publication number
CN111199887B
CN111199887B CN201811366788.2A CN201811366788A CN111199887B CN 111199887 B CN111199887 B CN 111199887B CN 201811366788 A CN201811366788 A CN 201811366788A CN 111199887 B CN111199887 B CN 111199887B
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Prior art keywords
adhesive layer
insulating layer
wafer
temperature
layer
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CN201811366788.2A
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CN111199887A (en
Inventor
赖建志
林泓彣
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Comchip Technology Corp
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Comchip Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Dicing (AREA)

Abstract

The invention relates to a manufacturing method of a chip package, which provides a wafer with a first surface and a second surface which are opposite. A first adhesive layer and a first carrier are formed to cover the first surface. The wafer is thinned from the second surface toward the first surface. And forming a first insulating layer to cover the second surface. Forming a second adhesive layer and a second carrier plate to cover the first insulating layer. The first adhesive layer is heated to a first temperature to remove the first carrier and the first adhesive layer. A plurality of grooves are formed through the wafer. And forming a third adhesion layer and a third carrying plate to cover the first surface. And heating the second adhesive layer to a second temperature to remove the second carrier and the second adhesive layer. And forming a second insulating layer to fill the groove and cover the first surface. And heating the third adhesion layer to a third temperature to remove the third carrier and the third adhesion layer. The first insulating layer and the second insulating layer are cut along the grooves. The method can avoid the problem of contraposition deviation.

Description

Method for manufacturing chip package
Technical Field
The invention relates to a manufacturing method of a chip packaging body.
Background
The conventional chip packaging process is to package the semiconductor dies cut from the wafer one by one, which is time-consuming and labor-consuming. Or, the semiconductor dies cut from the wafer are arranged on the carrier one by one for packaging and then cut into the chip packages again, and the manufacturing method of the chip packages is time-consuming and labor-consuming and is easy to cause the problem of alignment deviation.
Disclosure of Invention
In view of the above, the present invention is directed to a method for manufacturing a chip package that solves the above problems.
The method of the invention provides a manufacturing method of a chip packaging body, which comprises the following steps: first, a wafer is provided, which has a first surface and a second surface opposite to the first surface, and includes a plurality of conductive bumps on the first surface. And forming a first adhesion layer and a first carrier plate to cover the conductive bumps and the first surface, wherein the first adhesion layer is positioned between the first carrier plate and the first surface. The wafer is thinned from the second surface toward the first surface. And forming a first insulating layer to cover the second surface. And forming a second adhesion layer and a second carrier plate to cover the first insulating layer, wherein the second adhesion layer is positioned between the second carrier plate and the first insulating layer. The first adhesive layer is heated to a first temperature to remove the first carrier and the first adhesive layer. A plurality of grooves are formed through the wafer. And forming a third adhesion layer and a third carrier plate to cover the conductive bumps, wherein the third adhesion layer is positioned between the third carrier plate and the conductive bumps. And heating the second adhesive layer to a second temperature to remove the second carrier and the second adhesive layer. A second insulating layer is formed to fill the groove and cover the first surface and expose the conductive bump. And heating the third adhesion layer to a third temperature to remove the third carrier and the third adhesion layer. And cutting the first insulating layer and the second insulating layer along the grooves to form a plurality of chip packages.
According to an embodiment of the present invention, in the step of forming the second insulating layer, the second insulating layer further extends over the sidewalls of the wafer and the sidewalls of the second insulating layer.
According to an embodiment of the invention, the first temperature is 70 ℃ to 90 ℃.
According to an embodiment of the invention, the second temperature is in the range of 110 ℃ to 130 ℃.
According to an embodiment of the invention, the third temperature is 140 ℃ to 160 ℃.
Another method of the present invention is to provide a method for manufacturing a chip package, comprising the steps of: first, a wafer is provided, which has a first surface and a second surface opposite to the first surface, and includes a plurality of conductive bumps on the first surface. And forming a first adhesion layer and a first carrier plate to cover the conductive bumps and the first surface, wherein the first adhesion layer is positioned between the first carrier plate and the first surface. The wafer is thinned from the second surface toward the first surface. And forming a first insulating layer to cover the second surface. And forming a second adhesion layer and a second carrier plate to cover the first insulating layer, wherein the second adhesion layer is positioned between the second carrier plate and the first insulating layer. The first adhesive layer is heated to a first temperature to remove the first carrier and the first adhesive layer. A plurality of grooves are formed through the wafer. A second insulating layer is formed to fill the groove and cover the first surface, and the conductive bump is exposed outside the second insulating layer. And forming a third adhesion layer and a third carrier plate to cover the conductive bumps, wherein the third adhesion layer is positioned between the third carrier plate and the conductive bumps. And heating the second adhesive layer to a second temperature to remove the second carrier and the second adhesive layer. And heating the third adhesion layer to a third temperature to remove the third carrier and the third adhesion layer. And cutting the first insulating layer and the second insulating layer along the grooves to form a plurality of chip packages.
According to an embodiment of the present invention, in the step of forming the second insulating layer, the second insulating layer further extends to cover the sidewall of the wafer.
According to an embodiment of the present invention, after the step of heating the second adhesive layer to the second temperature and before the step of heating the third adhesive layer to the third temperature, forming a laser mark on the first insulating layer is further included.
According to an embodiment of the invention, the first temperature is 70 ℃ to 90 ℃.
According to an embodiment of the invention, the second temperature is in the range of 110 ℃ to 130 ℃.
According to an embodiment of the invention, the third temperature is 140 ℃ to 160 ℃.
The method can avoid the problem of contraposition deviation.
Drawings
In order to make the aforementioned and other objects, features, advantages and embodiments of the invention more comprehensible, the following description is given:
fig. 1 shows a flowchart of a method for manufacturing a chip package according to an embodiment of the present invention.
Fig. 2 shows a flowchart of a method of manufacturing a chip package according to another embodiment of the present invention.
Fig. 3 to 14 are schematic cross-sectional views illustrating various process stages in a method for manufacturing a chip package according to an embodiment of the invention.
Fig. 15 to 18 are schematic cross-sectional views illustrating stages in a method for manufacturing a chip package according to another embodiment of the invention.
Description of the symbols
100. 200: the method 30 comprises the following steps: wafer
30S: side wall 30T 1: thickness of
30T 2: thickness 301: first surface
302: second surface 303: conductive bump
303H: height 304: side wall
312: first adhesive layer 314: first carrier plate
320: first insulating layer 322: side wall
332: second adhesive layer 334: second carrier plate
340: groove 340C: center of a ship
340W: width 352: a third adhesive layer
354: third carrier plate 360: a second insulating layer
370: cutting the adhesive tape CW: width of cut
Tf: total thickness T1: first temperature
T2: second temperature T3: third temperature
S101, S102, S103, S104, S105, S106: step (ii) of
S107, S108, S109, S110, S111, S112: step (ii) of
S208, S209, S310, S211, S212: step (ii) of
Detailed Description
In order to make the description of the present invention more thorough and complete, an illustrative description is provided below of embodiments of the present invention; it is not intended to be the only form in which the embodiments of the invention may be practiced or utilized. The embodiments disclosed below may be combined with or substituted for one another as desired, or additional embodiments may be added to the embodiments, without further recitation or description.
In the following description, numerous specific details are set forth to provide a thorough understanding of the following embodiments. However, embodiments of the invention may be practiced without these specific details. In other instances, well-known structures and devices are shown schematically in the drawings to simplify the drawing.
The method of the present invention provides a method for manufacturing a chip package, which can reduce the manufacturing time and cost and avoid the problem of alignment deviation. Fig. 1 shows a flowchart of a method of manufacturing a chip package according to an embodiment of the present invention. Fig. 3 to 14 are schematic cross-sectional views illustrating various processing stages in a method for manufacturing a chip package according to an embodiment of the invention. As shown in fig. 1, the method 100 includes step S101, step S102, step S103, step S104, step S105, step S106, step S107, step S108, step S109, step S110, step S111, and step S112.
In step S101, a wafer 30 is provided, as shown in fig. 3. Specifically, the wafer 30 has a first surface 301 and a second surface 302 opposite to the first surface 301, and the wafer 30 includes a plurality of conductive bumps 303 on the first surface 301. In an embodiment, the wafer 30 may include silicon (silicon), Germanium (Germanium), or a group III-V element, but not limited thereto. In various embodiments, the wafer 30 includes a plurality of conductive pads (not shown) on the first surface 301, and the conductive bumps 303 are disposed on the conductive pads. In some embodiments, the wafer 30 has a thickness 30T1 of 525 to 725 microns, such as 550 microns, 575 microns, 600 microns, 625 microns, 650 microns, 675 microns, or 700 microns.
In embodiments, the conductive bumps 303 each have a height 303H of 20 to 45 microns, which may be, for example, 22 microns, 24 microns, 26 microns, 28 microns, 30 microns, 32 microns, 34 microns, 36 microns, 38 microns, 40 microns, 42 microns, or 44 microns. In various embodiments, a method of forming the conductive bump 303 includes the following steps, for example. First, a patterned mask (not shown) is formed on the first surface 301 of the wafer 30, and the patterned mask has a plurality of openings (not shown) such that a portion of the first surface 301 of the wafer 30 is exposed from the openings. Thereafter, a conductive bump 303 is formed in the opening by an electroplating process. In some embodiments, the conductive bump 303 includes gold (gold), tin (tin), copper (copper), nickel (nickel), or other suitable metal material.
In some embodiments, a surface treatment layer (not shown) may be formed on the surface of the conductive bump 303 over the conductive bump 303. In some embodiments, the surface treatment layer may be a single layer or a multi-layer structure composed of sub-layers of different materials, such as a metal layer including a nickel layer and a gold layer on the nickel layer, or a tin layer, but not limited thereto. The surface treatment layer can be formed by physical methods such as Nickel-Gold electroplating and tin spraying, or chemical methods such as Nickel Immersion Gold (ENIG). The surface treatment layer may prevent the conductive bump 303 from being oxidized by contacting air.
In step S102, a first adhesive layer 312 and a first carrier 314 are formed to cover the conductive bumps 303 and the first surface 301, as shown in fig. 4. Specifically, the first adhesive layer 312 is located between the first carrier 314 and the first surface 301. The first adhesive layer 312 can reduce stress generated in the subsequent thinning process, thereby reducing the risk of wafer cracking. In an embodiment, the first adhesive layer 312 includes a UV release adhesive (UV release adhesive) or a thermal release adhesive (thermal release adhesive). Here, it should be noted that the pyrolysis temperature of the first adhesive layer 312 is about 70 ℃ to 90 ℃, such as 72 ℃, 75 ℃, 77 ℃, 80 ℃, 82 ℃, 85 ℃ or 87 ℃. In an embodiment, the first adhesion layer 312 is formed by spin coating (spinning), but not limited thereto. The first carrier 314 can provide better protection for the wafer 30, and therefore, the first carrier 314 can be a hard insulating substrate, such as a glass substrate, a ceramic substrate, a sapphire substrate, or a quartz substrate, but is not limited thereto.
In step S103, the wafer 30 is thinned from the second surface 302 toward the first surface 301, as shown in fig. 5. The wafer 30 may be thinned by using a chemical-mechanical polishing (cmp) method, a dry etching method, or other suitable processing methods, so as to form a chip package with a smaller size. In some embodiments, after step S103 of thinning the wafer 30, the thickness 30T2 of the wafer 30 is 100 to 200 microns, such as 110 microns, 120 microns, 130 microns, 140 microns, 150 microns, 160 microns, 170 microns, 180 microns, or 190 microns.
In step S104, a first insulating layer 320 is formed to cover the second surface 302, as shown in fig. 6. The first insulating layer 320 may serve as a packaging layer of the chip package for protecting the second surface 302 of the wafer 30. In various embodiments, the material used for the first insulating layer 320 may be polyimide (polyimide), Epoxy (Epoxy), or other suitable insulating material. In an embodiment, the first insulating layer 320 may be formed by printing or spin coating, but is not limited thereto. In the present embodiment, after the step S104 of forming the first insulating layer 320, the wafer 30 and the first insulating layer 320 have a total thickness Tf of 120 to 210 microns, such as 125 microns, 130 microns, 135 microns, 140 microns, 145 microns, 150 microns, 155 microns, 160 microns, 165 microns, 170 microns, 175 microns, 180 microns, 185 microns, 190 microns, 195 microns, 200 microns, or 205 microns.
In step S105, a second adhesive layer 332 and a second carrier 334 are formed to cover the first insulating layer 320, as shown in fig. 7. Specifically, the second adhesive layer 332 is disposed between the second carrier 334 and the first insulating layer 320. The second adhesive layer 332 can reduce stress generated during subsequent formation of the groove, thereby reducing the risk of wafer cracking. In an embodiment, the second adhesive layer 332 includes a UV release adhesive (UV release adhesive) or a thermal release adhesive (thermal release adhesive). Here, it should be noted that the pyrolysis temperature of the second adhesive layer 332 is about 110 ℃ to 130 ℃, for example, 112 ℃, 115 ℃, 117 ℃, 120 ℃, 122 ℃, 125 ℃ or 127 ℃. In an embodiment, the second adhesive layer 332 may be formed by spin coating (spin coating), but is not limited thereto. The second carrier 334 can provide better protection for the wafer 30, and therefore, the second carrier 334 can be a hard insulating substrate, such as a glass substrate, a ceramic substrate, a sapphire substrate, or a quartz substrate, but is not limited thereto.
In step S106, the first carrier 314 and the first adhesive layer 312 are removed by heating at a first temperature T1, as shown in fig. 8. In embodiments, the first temperature T1 is 70 ℃ to 90 ℃, and may be, for example, 72 ℃, 75 ℃, 77 ℃, 80 ℃, 82 ℃, 85 ℃ or 87 ℃. In more detail, since the pyrolysis temperature of the first adhesive layer 312 is about 70 ℃ to 90 ℃ and the pyrolysis temperature of the second adhesive layer 332 is about 110 ℃ to 130 ℃, when the first temperature T1(70 ℃ to 90 ℃) is heated, the first carrier 314 can fall off together with the decrease of the viscosity of the first adhesive layer 312, and the second carrier 334 is still adhered under the first insulating layer 320 by the second adhesive layer 332.
In step S107, a plurality of grooves 340 are formed through the wafer 30, as shown in fig. 9. Specifically, the grooves 340 penetrate from the first surface 301 to the second surface 302 of the wafer 30, but do not penetrate through the first insulating layer 320. After completing step S107, the wafer 30 is separated into a plurality of chips, and the chips maintain the relative positions of the chips through the first insulating layer 320. Therefore, the problem of alignment offset in the prior art can be solved. In various embodiments, this step S107 may be achieved using knife wheel cutting, laser cutting, or water jet cutting. In the embodiment, each groove 340 has a width 340W of 50 to 60 microns, for example, the width 340W may be 51 microns, 52 microns, 53 microns, 54 microns, 55 microns, 56 microns, 57 microns, 58 microns or 59 microns, but is not limited thereto.
In step S108, a third adhesive layer 352 and a third carrier 354 are formed to cover the conductive bumps 303, as shown in fig. 10. Specifically, the third adhesive layer 352 is located between the third carrier plate 354 and the conductive bumps 303. In some embodiments, the third adhesive layer 352 as shown in fig. 10 is spaced a distance from the first surface 301 of the wafer 30. In other embodiments, the third adhesion layer 352 contacts the first surface 301 of the wafer 30. In an embodiment, the third adhesive layer 352 includes a UV release adhesive (UV release adhesive) or a thermal release adhesive (thermal release adhesive). Here, it should be noted that the pyrolysis temperature of the third adhesive layer 352 is about 140 ℃ to 160 ℃, such as 142 ℃, 145 ℃, 147 ℃, 150 ℃, 152 ℃, 155 ℃ or 157 ℃. In an embodiment, the third adhesion layer 352 may be formed by spin coating (spin coating), but is not limited thereto. The third carrier 354 may provide a carrier for forming a second insulating layer later. In an embodiment, the third carrier plate 354 may be a hard insulating substrate, such as a glass substrate, a ceramic substrate, a sapphire substrate, or a quartz substrate, but is not limited thereto. In addition, after the step S108 is performed, the structure shown in fig. 10 may be turned upside down, so that the third carrier 354 is located below the second carrier 334, thereby facilitating the subsequent processes.
In step S109, the second carrier 334 and the second adhesive layer 332 are removed by heating at a second temperature T2, as shown in fig. 11. In embodiments, the second temperature T2 is between 110 ℃ and 130 ℃, for example 112 ℃, 115 ℃, 117 ℃, 120 ℃, 122 ℃, 125 ℃ or 127 ℃. In more detail, since the pyrolysis temperature of the second adhesive layer 332 is about 110 ℃ to 130 ℃ and the pyrolysis temperature of the third adhesive layer 352 is about 140 ℃ to 160 ℃, when the second adhesive layer 332 is heated to the second temperature T2(110 ℃ to 130 ℃), the second carrier 334 can fall off together with the reduction of the viscosity of the second adhesive layer 332, and the third carrier 354 is still adhered to the surface of the conductive bump 303 through the third adhesive layer 352.
In step S110, a second insulating layer 360 is formed to fill the grooves 340 and cover the first surface 301, as shown in fig. 12. The second insulating layer 360 may serve as a packaging layer of the chip package for protecting the first surface 301 of the wafer 30. In some embodiments, the second insulating layer 360 also covers the sidewalls 322 of the first insulating layer 320 and the sidewalls 304 of the wafer 30. The second insulating layer 360 may serve as a packaging layer of the chip package for protecting the first surface 301 of the wafer 30. In an embodiment, the material used for the second insulating layer 360 may be polyimide (polyimide), Epoxy (Epoxy), or other suitable insulating material. In an embodiment, the second insulating layer 360 may be formed by means of underfill (underfill).
In some embodiments, after the step S110 of forming the second insulating layer 360, a Laser Mark (not shown) may be disposed on the first insulating layer 320 of each chip to Mark a product name of a subsequently formed chip package.
In step S111, heat is applied at a third temperature T3 to remove the third carrier plate 354 and the third adhesive layer 352, as shown in fig. 13. In an embodiment, the third temperature T3 is between 140 ℃ and 160 ℃, for example 142 ℃, 145 ℃, 147 ℃, 150 ℃, 152 ℃, 155 ℃ or 157 ℃. In more detail, since the pyrolysis temperature of the third adhesive layer 352 is about 140 ℃ to 160 ℃, the third carrier 354 can be peeled off together with the decrease of the viscosity of the third adhesive layer 352 when heated to the third temperature T3(140 ℃ to 160 ℃). Since the third adhesive layer 352 is adhered on the surface of the conductive bump 303, when the third carrier plate 354 and the third adhesive layer 352 are separated, the surface of the conductive bump 303 is exposed.
In step S112, the first insulating layer 320 and the second insulating layer 360 are cut along the grooves 340 to form a plurality of chip packages, as shown in fig. 14. In various embodiments, this step S112 may be achieved using knife wheel cutting, laser cutting, or water jet cutting. In the present embodiment, the first insulating layer 320 and the second insulating layer 360 are cut along the center 340C of each groove 340. In an embodiment, the cutting width CW of step S112 is 18 to 22 microns, and may be 18.5 microns, 19.0 microns, 19.5 microns, 20.0 microns, 20.5 microns, 21.0 microns, or 21.5 microns, for example. It should be noted that, since the dicing width CW is smaller than the width 304W of the groove 304, the sidewall of each chip package obtained after performing step S112, which is adjacent to the center 304C of the groove 304, still has a portion of the second insulating layer 360 to protect the wafer 30. In other words, each surface of each chip package is protected by the first insulating layer 320 and the second insulating layer 360, and only the conductive bumps 303 are exposed for external electrical connection. In other embodiments, as shown in fig. 14, before performing step S112, the structure shown in fig. 13 may be turned upside down and placed on a dicing tape 370, and then step S112 of dicing the first insulating layer 320 and the second insulating layer 360 may be performed. More specifically, the first insulating layer 320 is located between the second surface 302 of the wafer 30 and the dicing tape 370. In various embodiments, dicing tape 370 may be a blue film UV tape (blue tape).
A method of manufacturing a chip package according to another embodiment of the present invention is briefly described as follows. Fig. 2 is a flowchart illustrating a method of manufacturing a chip package according to another embodiment of the present invention. Fig. 15 to 18 are schematic cross-sectional views illustrating various process stages in a method for manufacturing a chip package according to another embodiment of the invention. As shown in fig. 2, the method 200 includes steps S101 to S107, S208, S209, S210, S211 and S212, wherein the steps S101 to S107 are already described in detail above, and will not be repeated herein.
Referring to fig. 15, after step S107, step S208 is continued to form a second insulating layer 360 to fill the recess 340 and cover the first surface 301, and the conductive bump 303 is exposed outside the second insulating layer 360. The second insulating layer 360 may serve as an encapsulation layer of the chip package for protecting the chip package, which will be described in more detail below. In some embodiments, the second insulating layer 360 also covers the sidewalls 322 of the first insulating layer 320 and the sidewalls 304 of the wafer 30. In some embodiments, the material used for the second insulating layer 360 may be polyimide (polyimide), Epoxy (Epoxy), or other suitable insulating material. In an embodiment, the second insulating layer 360 may be formed by means of underfill (underfill). Alternatively, the groove 340 may be filled by printing, coating or molding (molding) and fully covers the first surface 301 of the wafer 30, and then the conductive bump 303 is exposed outside the second insulating layer 360 by a planarization process, such as chemical mechanical polishing, mechanical brushing, planarization chemical etching, polishing process, electrolytic etching or electropolishing etching.
In step S209, a third adhesion layer 352 and a third carrier 354 are formed to cover the conductive bumps 303 and the first surface 301, as shown in fig. 16. Specifically, the third adhesive layer 352 is located between the third carrier plate 354 and the first surface 301. The detailed description of the third adhesive layer 352 and the third carrier 354 is already described above and is not repeated herein. The third carrier plate 354 may provide a carrier for forming laser marks later, so as to prevent the wafer 30 from warping.
In step S210, the substrate is heated at a second temperature T2 to remove the second carrier 334 and the second adhesive layer 332, as shown in fig. 17. In embodiments, the second temperature T2 is between 110 ℃ and 130 ℃, for example 112 ℃, 115 ℃, 117 ℃, 120 ℃, 122 ℃, 125 ℃ or 127 ℃. In more detail, since the pyrolysis temperature of the second adhesion layer 332 is about 110 ℃ to 130 ℃ and the pyrolysis temperature of the third adhesion layer 352 is about 140 ℃ to 160 ℃, when the second temperature T2(110 ℃ to 130 ℃) is reached, the second carrier 334 can fall off together with the reduction of the viscosity of the second adhesion layer 332, and the third carrier 354 is still adhered to the first surface 301 of the wafer 30 through the third adhesion layer 352.
In some embodiments, after the step S210 of removing the second carrier 334 and the second adhesive layer 332, a Laser Mark (not shown) may be disposed on the first insulating layer 320 of each chip to Mark a product name of a subsequently formed chip package.
In step S211, the third carrier plate 354 and the third adhesive layer 352 are removed by heating at a third temperature T3, as shown in fig. 18. In an embodiment, the third temperature T3 is between 140 ℃ and 160 ℃, for example 142 ℃, 145 ℃, 147 ℃, 150 ℃, 152 ℃, 155 ℃ or 157 ℃. In more detail, since the pyrolysis temperature of the third adhesive layer 352 is about 140 ℃ to 160 ℃, the third carrier 354 can be peeled off together with the decrease of the viscosity of the third adhesive layer 352 when heated to the third temperature T3(140 ℃ to 160 ℃).
In step S212, the first insulating layer 320 and the second insulating layer 360 are cut along the grooves 340 to form a plurality of chip packages, as shown in fig. 18. In various embodiments, this step S212 may be achieved using knife wheel cutting, laser cutting, or water jet cutting. In the present embodiment, the first insulating layer 320 and the second insulating layer 360 are cut along the center 340C of each groove 340. In an embodiment, the cutting width CW of step S212 is 18 to 22 microns, and may be 18.5 microns, 19.0 microns, 19.5 microns, 20.0 microns, 20.5 microns, 21.0 microns, or 21.5 microns, for example. It should be noted that, since the dicing width CW is smaller than the width 304W of the groove 304, the sidewall of each chip package obtained after performing step S212, which is adjacent to the center 304C of the groove 304, still has a portion of the second insulating layer 360 to protect the wafer 30. In other words, each surface of each chip package is protected by the first insulating layer 320 and the second insulating layer 360, and only the conductive bumps 303 are exposed for external electrical connection. In other embodiments, as shown in fig. 18, after step S211 is performed, the first insulating layer 320 under the second surface 302 of the wafer 30 is disposed on a dicing tape 370, and then step S212 of dicing the first insulating layer 320 and the second insulating layer 360 is performed. More specifically, the first insulating layer 320 is located between the second surface 302 of the wafer 30 and the dicing tape 370. In various embodiments, dicing tape 370 may be a blue film UV tape (blue tape).
In various examples, the chip package may be used to package a light sensing element or a light emitting element. However, the present invention is not limited thereto, and may be applied to various electronic components (electronic components) including integrated circuits such as discrete devices, active or passive devices, digital circuits or analog circuits, for example, opto-electronic devices (optoelectronic devices), Micro Electro Mechanical Systems (MEMS), Micro fluidic systems (Micro fluid systems), or Physical sensors (Physical sensors) that measure changes in Physical quantities such as heat, light, and pressure. In particular, a Wafer Scale Package (WSP) process may be selected to package semiconductor chips such as image sensors, light-emitting diodes (LEDs), non-light-emitting diodes (LEDs), solar cells (solar cells), radio frequency devices (RF circuits), accelerometers (accelerometers), gyroscopes (gyroscopes), micro actuators (micro actuators), surface acoustic wave devices (surface acoustic wave devices), pressure sensors (process sensors), or inkjet heads (ink printer heads).
In summary, the method for manufacturing the chip package of the present invention can not only reduce the manufacturing time and cost, but also avoid the problem of misalignment.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A method of manufacturing a chip package, comprising:
providing a wafer, wherein the wafer is provided with a first surface and a second surface opposite to the first surface, and the wafer comprises a plurality of conductive bumps positioned on the first surface;
forming a first adhesive layer and a first carrier plate to cover the conductive bumps and the first surface, wherein the first adhesive layer is located between the first carrier plate and the first surface;
thinning the wafer from the second surface toward the first surface;
forming a first insulating layer to cover the second surface;
forming a second adhesive layer and a second carrier plate to cover the first insulating layer, wherein the second adhesive layer is positioned between the second carrier plate and the first insulating layer;
heating the first adhesive layer to a first temperature to remove the first carrier and the first adhesive layer;
forming a plurality of grooves to penetrate through the wafer;
forming a third adhesive layer and a third carrier plate to cover the conductive bumps, wherein the third adhesive layer is located between the third carrier plate and the conductive bumps;
heating the second adhesive layer to a second temperature to remove the second carrier and the second adhesive layer;
forming a second insulating layer to fill the groove and cover the first surface, wherein the second insulating layer extends to cover the side wall of the wafer and the side wall of the first insulating layer;
heating the third adhesive layer to a third temperature to remove the third carrier and the third adhesive layer; and
and cutting the first insulating layer and the second insulating layer along the grooves to form a plurality of chip packaging bodies.
2. The method of claim 1, wherein the first temperature is in a range of 70 ℃ to 90 ℃.
3. The method of claim 1, wherein the second temperature is in a range of 110 ℃ to 130 ℃.
4. The method of claim 1, wherein the third temperature is 140 ℃ to 160 ℃.
5. A method of manufacturing a chip package, comprising:
providing a wafer, wherein the wafer is provided with a first surface and a second surface opposite to the first surface, and the wafer comprises a plurality of conductive bumps positioned on the first surface;
forming a first adhesive layer and a first carrier plate to cover the conductive bumps and the first surface, wherein the first adhesive layer is located between the first carrier plate and the first surface;
thinning the wafer from the second surface toward the first surface;
forming a first insulating layer to cover the second surface;
forming a second adhesive layer and a second carrier plate to cover the first insulating layer, wherein the second adhesive layer is positioned between the second carrier plate and the first insulating layer;
heating the first adhesive layer to a first temperature to remove the first carrier and the first adhesive layer;
forming a plurality of grooves to penetrate through the wafer;
forming a second insulating layer to fill the groove and cover the first surface, wherein the conductive bump is exposed out of the second insulating layer;
forming a third adhesive layer and a third carrier plate to cover the conductive bumps, wherein the third adhesive layer is located between the third carrier plate and the conductive bumps;
heating the second adhesive layer to a second temperature to remove the second carrier and the second adhesive layer;
heating the third adhesive layer to a third temperature to remove the third carrier and the third adhesive layer; and
and cutting the first insulating layer and the second insulating layer along the grooves to form a plurality of chip packaging bodies.
6. The method of claim 5, wherein the second insulating layer further extends over sidewalls of the wafer during the step of forming the second insulating layer.
7. The method of claim 5, further comprising forming a laser mark on the first insulating layer after the step of heating the second adhesive layer to the second temperature and before the step of heating the third adhesive layer to the third temperature.
8. The method of claim 5, wherein the first temperature is 70-90 ℃.
9. The method of claim 5, wherein the second temperature is in a range of 110 ℃ to 130 ℃.
10. The method of claim 5, wherein the third temperature is 140 ℃ to 160 ℃.
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