CN110970362B - Method for manufacturing chip package - Google Patents

Method for manufacturing chip package Download PDF

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Publication number
CN110970362B
CN110970362B CN201811139024.XA CN201811139024A CN110970362B CN 110970362 B CN110970362 B CN 110970362B CN 201811139024 A CN201811139024 A CN 201811139024A CN 110970362 B CN110970362 B CN 110970362B
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wafer
microns
layer
photoresist layer
patterned photoresist
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CN110970362A (en
Inventor
赖建志
林泓彣
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Comchip Technology Corp
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Comchip Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02016—Backside treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Dicing (AREA)

Abstract

The invention relates to a manufacturing method of a chip packaging body. A wafer is provided, the wafer has an upper surface and a lower surface opposite to the upper surface, and includes a plurality of conductive pads located on the upper surface. The upper surface of the wafer is cut to form a plurality of grooves. A patterned photoresist layer is formed on the upper surface and in the recess. Forming a plurality of conductive bumps on the corresponding conductive pads respectively. The wafer is thinned from the lower surface to the upper surface, so that the patterned photoresist layer in the groove is exposed from the lower surface. An insulating layer is formed below the lower surface. And cutting the patterned photoresist layer and the insulating layer along the grooves to form a plurality of chip packages. The method can avoid the problem of contraposition deviation.

Description

Method for manufacturing chip package
Technical Field
The invention relates to a manufacturing method of a chip packaging body.
Background
The conventional chip packaging process is to package the semiconductor dies cut from the wafer one by one, which is time-consuming and labor-consuming. Or, the semiconductor dies cut from the wafer are arranged on the carrier one by one for packaging and then cut into the chip packages again, and the manufacturing method of the chip packages is time-consuming and labor-consuming and is easy to cause the problem of alignment deviation.
Disclosure of Invention
The present invention is directed to overcome the defects of the conventional chip package process, i.e., the problems that the semiconductor dies cut from the wafer are packaged one by one, or the semiconductor dies cut from the wafer are arranged one by one on the carrier plate for packaging and then cut into the chip packages again, and alignment offset is easily generated, and a method for manufacturing a new chip package is provided, which can complete a plurality of chip packages, and avoid the generation of alignment offset, thereby being more practical.
The purpose of the invention and the technical problem to be solved are realized by adopting the following technical scheme. The manufacturing method of the chip packaging body provided by the invention comprises the following steps: first, a wafer is provided, the wafer having an upper surface and a lower surface opposite to the upper surface, and including a plurality of conductive pads on the upper surface. The upper surface of the wafer is cut to form a plurality of grooves. A patterned photoresist layer is formed on the upper surface and in the recess. And forming a plurality of conductive bumps on the corresponding conductive pads respectively. The wafer is thinned from the lower surface to the upper surface, so that the patterned photoresist layer in the groove is exposed from the lower surface. An insulating layer is formed below the lower surface. And cutting the patterned photoresist layer and the insulating layer along the grooves to form a plurality of chip packages.
The object of the present invention and the technical problems solved thereby can be further achieved by the following technical measures.
The method for manufacturing a chip package further includes, after the step of forming the conductive bump: forming a surface treatment layer on the conductive bump.
The method for manufacturing a chip package further includes, after the step of forming the conductive bump and before the step of thinning the wafer: forming an adhesion layer to cover the patterned photoresist layer and the conductive bump; and forming a carrier plate on the adhesion layer.
The method for manufacturing a chip package further includes, after the step of forming the insulating layer and before the step of cutting the patterned photoresist layer and the insulating layer along the grooves: removing the carrier and the adhesive layer.
In the method for manufacturing the chip package, after the step of thinning the wafer, the thickness of the wafer is 100 to 150 μm.
In the manufacturing method of the chip package, after the step of forming the insulating layer, the total thickness of the wafer, the conductive bump and the insulating layer is 120 to 210 micrometers.
In the method for manufacturing the chip package, the cutting width of the patterned photoresist layer and the insulating layer along each groove is 15 to 22 micrometers.
In the manufacturing method of the chip package, each of the conductive bumps has a height of 20 to 45 μm.
In the manufacturing method of the chip package, each of the grooves has a width of 50 to 60 micrometers and a depth of 150 to 200 micrometers.
In the method for manufacturing the chip package, after the step of providing the wafer, the wafer has a thickness of 525 to 725 μm.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By the technical scheme, the manufacturing method of the chip packaging body can achieve considerable technical progress and practicability, has wide industrial utilization value and at least has the following advantages:
a plurality of chip packages can be completed without packaging semiconductor dies cut from a wafer one by one, reducing manufacturing time and cost.
The problem that alignment deviation is easily caused by arranging the semiconductor crystal grains cut from the wafer on the carrier plate one by one for packaging and then cutting the semiconductor crystal grains into chip packages is solved. And reduces manufacturing time and costs.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a chip package according to the present invention.
Fig. 2 to 12 are schematic cross-sectional views of the manufacturing method of the chip package at various stages according to the present invention.
[ notation ] to show
100: the method 20 comprises the following steps: wafer
20T1: thickness of 20T2: thickness of
210: upper surface 220: lower surface of
230: conductive pad 240: groove
240C: center 240D: depth of
240W: width 250: the photoresist layer
250 a: first portion 250 b: the second part
250P: patterning the photoresist layer 250R: concave part
260: conductive bump 260H: height
270: insulating layer 310: surface treatment layer
320: adhesive layer 330: support plate
340: laser marking CW: width of cut
Tf: total thickness of
S110, S120, S130, S140, S150, S160, S170: step (ii) of
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of the manufacturing method of the chip package, its structure, method, steps, features and effects will be made with reference to the accompanying drawings and preferred embodiments.
The foregoing and other technical and scientific aspects, features and advantages of the present invention will be apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings. While the present invention has been described in connection with the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications, equivalent arrangements, and specific embodiments thereof. For convenience of description, in the following embodiments, the same elements are denoted by the same reference numerals.
Fig. 1 is a flow chart of a method for manufacturing a chip package according to the present invention. Fig. 2 to 12 are schematic cross-sectional views of the manufacturing method of the chip package at various stages of the manufacturing process. As shown in fig. 1, the method 100 includes step S110, step S120, step S130, step S140, step S150, step S160, and step S170.
In step S110, a wafer 20 is provided, as shown in fig. 2. Specifically, the wafer 20 has an upper surface 210 and an opposite lower surface 220, and the wafer 20 includes a plurality of conductive pads 230 located on the upper surface 210. In an embodiment, the wafer 20 may include silicon (silicon), Germanium (Germanium), or a group III-V element, but not limited thereto. In various embodiments, the conductive pad 230 includes copper (copper), nickel (nickel), tin (tin), or other suitable conductive material. In some embodiments, wafer 20 has a thickness of 20T1From 525 to 725 microns, and may be, for example, 550 microns, 575 microns, 600 microns, 625 microns, 650 microns, 675 microns, or 700 microns.
In step S120, the upper surface 210 of the wafer 20 is diced to form a plurality of grooves 240, as shown in fig. 3. In various embodiments, this step S120 may be achieved using knife wheel cutting, laser cutting, or water jet cutting. In an embodiment, each groove 240 has a width 240W of 50 to 60 microns and a depth 240D of 120 to 200 microns. For example, width 240W may be 51 microns, 52 microns, 53 microns, 54 microns, 55 microns, 56 microns, 57 microns, 58 microns, or 59 microns, and depth 240D may be 125 microns, 130 microns, 135 microns, 140 microns, 145 microns, 150 microns, 155 microns, 160 microns, 165 microns, 170 microns, 175 microns, 180 microns, 185 microns, 190 microns, or 195 microns, but is not limited thereto.
In step S130, a patterned photoresist layer is formed on the upper surface and in the recess. Fig. 4 to 5 are schematic cross-sectional views for implementing step S130 according to an embodiment of the present invention. As shown in fig. 4, a photoresist layer 250 is formed to fill the recess 240 and completely cover the upper surface 210 of the wafer 20. In one embodiment, the photoresist layer 250 has a specific thickness on the upper surface 210 of the wafer 20. In various embodiments, the photoresist layer 250 may be a positive type photoresist layer or a negative type photoresist layer. In an embodiment, the photoresist layer 250 may be formed by spraying (spraying), printing (printing), coating (coating), or Electro-deposited photoresist (Electro-deposited photoresist).
Next, as shown in FIG. 5, in an embodiment, an exposure and development process may be performed to form a patterned photoresist layer 250P on the photoresist layer 250. The patterned photoresist layer 250P includes a first portion 250a and a second portion 250b, wherein the first portion 250a fills the recess 240, and the second portion 250b is located between any two adjacent conductive pads 230 on the upper surface 210. In detail, the photoresist layer 250 may be exposed by, for example, using a mask (not shown) with a specific pattern and ultraviolet light (not shown) with an appropriate wavelength to expose the photoresist layer 250. It is noted that when the photoresist layer 250 is a positive type photoresist layer, the exposed portion of the photoresist layer is converted into an exposed photoresist layer, and the exposed photoresist layer is washed away in the subsequent developing step, leaving another portion of the photoresist layer unexposed. In other words, as shown in FIG. 5, the patterned photoresist layer 250P forms a plurality of recesses 250R, and the conductive pad 230 is exposed through the recesses 250R. That is, the portion of the specific pattern of the mask that shields the ultraviolet light is the other portion of the photoresist layer that remains unexposed. It is noted that in the step of exposing and developing the photoresist layer 250, the photoresist layer 250 in the recess 250R is exposed and developed to be washed away, so that the conductive pads 230 on the upper surface 210 of the wafer 20 are exposed. On the contrary, when the photoresist layer 250 is a negative photoresist layer, the photoresist layer 250 in the recess 250R needs to be masked by a mask so as not to be exposed to light, and can be washed away in the subsequent development.
In step S140, a plurality of conductive bumps 260 are formed on the corresponding conductive pads 230, as shown in fig. 6. In an embodiment, the conductive bumps 260 have a height 260H of 20 to 45 microns, such as may be 22 microns, 24 microns, 26 microns, 28 microns, 30 microns, 32 microns, 34 microns, 36 microns, 38 microns, 40 microns, 42 microns, or 44 microns. In various embodiments, the top surface of the conductive bump 260 may be slightly higher, flush, or slightly lower than the top surface of the patterned photoresist layer 250P. In some embodiments, the conductive bump 260 includes gold (gold), tin (tin), copper (copper), nickel (nickel), or other suitable metal material. In some embodiments, the conductive bump 260 may be formed by plating (plating), sputtering (sputtering), evaporation (evaporation) or other suitable process. It should be noted that the second portion 250b of the patterned photoresist layer 250P can be directly used as a mask for forming the conductive bump 260, thereby reducing a photolithography process for etching the metal material layer. In addition, the second portion 250b of the patterned photoresist layer 250P may also be used as a packaging layer for forming a chip package later, so as to protect the upper surface 210 of the wafer 20.
Next, referring to fig. 7, in various embodiments, after the step S140 of forming the conductive bump 260, a surface treatment layer 310 may be formed on the conductive bump 260. In some embodiments, the surface treatment layer 310 may be a single layer structure such as a nickel layer or a tin layer, or a multi-layer structure composed of sub-layers of different materials such as a nickel layer or a tin layer, but is not limited thereto. The surface treatment layer 310 may be formed by a physical method such as Nickel-Gold electroplating and tin spraying, or a chemical method such as Nickel Immersion Gold (ENIG). The surface treatment layer 310 may prevent the conductive bump 260 from being oxidized by contacting air.
Referring to fig. 8, after step S140, an adhesive layer 320 is formed to cover the patterned photoresist layer 250P and the conductive bumps 260, and then a carrier 330 is formed on the adhesive layer 320. The adhesion layer 320 can reduce stress generated during the subsequent thinning process, thereby reducing the risk of wafer cracking. In an embodiment, the adhesive layer 320 includes a UV release adhesive (UV release adhesive) or a thermal release adhesive (thermal release adhesive). In an embodiment, the adhesive layer 320 may be formed by spin coating (spin coating), but is not limited thereto. The carrier 330 can provide better protection for the wafer 20, and therefore, the carrier 330 can be a hard insulating substrate, such as a glass substrate, a ceramic substrate, a sapphire substrate, or a quartz substrate, but is not limited thereto.
In other embodiments, after the step of forming the surface treatment layer 310 on the conductive bump 260, the adhesion layer 320 is formed to cover the patterned photoresist layer 250P and the surface treatment layer 310, and then the carrier 330 is formed on the adhesion layer 320.
In step S150, the wafer 20 is thinned from the bottom surface 220 toward the top surface 210, so that the patterned photoresist layer 250P in the groove 240 is exposed from the bottom surface 220, as shown in fig. 9. The wafer 20 may be thinned by using a chemical-mechanical polishing (cmp) method, a dry etching method, or other suitable processing methods, so that the chip package formed finally has a smaller size. In some embodiments, after step S150 of thinning the wafer 20, the thickness 20T of the wafer 202From 100 to 150 microns, for example 110 microns, 115 microns, 120 microns, 125 microns, 130 microns, 135 microns, 140 microns or 145 microns. After completing the step S150, the wafer 20 is divided into a plurality of chips, and the chips pass through the grooves 240The patterned photoresist layer 250P maintains the relative position between the chips. Therefore, the problem of alignment offset in the prior art can be solved.
In step S160, an insulating layer 270 is formed under the lower surface 220, as shown in fig. 10. The insulating layer 270 may serve as a package layer of the chip package for protecting the lower surface 220 of the wafer 20. In various embodiments, the material used for the insulating layer 270 may be polyimide (polyimide), Epoxy (Epoxy), or other suitable insulating material. In some embodiments, the insulating layer 270 may be formed by printing (printing), coating (coating), or molding (molding). In the present embodiment, after the step S160 of forming the insulating layer 270, the wafer 20, the insulating layer 270 and the conductive bump 260 have a total thickness TfFrom 120 to 210 microns, for example, 125 microns, 130 microns, 135 microns, 140 microns, 145 microns, 150 microns, 155 microns, 160 microns, 165 microns, 170 microns, 175 microns, 180 microns, 185 microns, 190 microns, 195 microns, 200 microns, or 205 microns.
Then, referring to fig. 11, after the step S160 of forming the insulating layer 270, the carrier 330 and the adhesive layer 320 are removed. In detail, the carrier 330 can be peeled off along with the decrease of the viscosity of the adhesive layer 320 by irradiating or heating the adhesive layer 320 with ultraviolet light.
As shown in fig. 11, in some embodiments, a Laser Mark (Laser Mark)340 code may be disposed on the insulating layer 270 of each corresponding chip after the step S160 of forming the insulating layer 270.
In step S170, the patterned photoresist layer 250P and the insulating layer 270 are cut along each groove 240 to form a plurality of chip packages, as shown in fig. 12. In an embodiment, the patterned photoresist layer 250P and the insulating layer 270 may be cut along the center 240C of each groove 240, for example, to form a plurality of chip packages. In various embodiments, this step S170 may be achieved using a knife wheel cut, a laser cut, or a water knife cut. In the present embodiment, the cutting width CW of cutting the patterned photoresist layer 250P and the insulating layer 270 along each groove 240 is 15 to 22 micrometers, and may be, for example, 15.5 micrometers, 16.0 micrometers, 16.5 micrometers, 17.0 micrometers, 17.5 micrometers, 18.0 micrometers, 18.5 micrometers, 19.0 micrometers, 19.5 micrometers, 20.0 micrometers, 20.5 micrometers, 21.0 micrometers or 21.5 micrometers. It should be noted that, since the dicing width CW is smaller than the width 240W of the groove 240, the sidewall of each chip package obtained after performing step S170, which is adjacent to the center 240C of the groove 240, still has a portion of the patterned photoresist layer 250P to protect the wafer 20. In other words, each surface of each chip package is protected by the patterned photoresist layer 250P and the insulating layer 270, and only the surface treatment layer 310 is exposed for external electrical connection.
In various examples, the chip package may be used to package a light sensing element or a light emitting element. However, the application is not limited thereto, and for example, the present invention may be applied to various electronic components (electronic components) including integrated circuits such as discrete devices, active or passive devices (active or passive devices), digital circuits or analog circuits (digital or analog circuits), for example, optoelectronic devices (opto-electronic devices), Micro-Electro-Mechanical systems (MEMS), Micro-fluidic systems (Micro fluidic systems), or Physical sensors (Physical sensors) which measure changes in Physical quantities such as heat, light, and pressure. In particular, a Wafer Scale Package (WSP) process may be used to package semiconductor chips such as image sensors, light-emitting diodes (LEDs), diodes (diodes), solar cells (solar cells), radio frequency devices (RF circuits), accelerometers (accelerometers), gyroscopes (gyroscopes), micro actuators (micro actuators), surface acoustic wave devices (surface acoustic wave devices), pressure sensors (process sensors), or inkjet heads (ink printer heads).
In summary, the manufacturing method of the chip package of the present invention can not only reduce the manufacturing time and cost, but also avoid the problem of misalignment. Other operable embodiments of the present invention may be modified within the skill of the art to which the invention pertains so long as the basic knowledge is available. In the present invention, a patent is claimed for the essential technical solution, and the protection scope of the patent should include all the changes with the technical characteristics.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (8)

1. A method of manufacturing a chip package, comprising:
providing a wafer, wherein the wafer is provided with an upper surface and a lower surface opposite to the upper surface, and the wafer comprises a plurality of conductive pads positioned on the upper surface;
cutting the upper surface of the wafer to form a plurality of grooves;
forming a patterned photoresist layer on the upper surface and in the plurality of grooves;
forming a plurality of conductive bumps on the corresponding conductive pads respectively;
forming an adhesion layer to cover the patterned photoresist layer and the conductive bumps;
forming a carrier plate on the adhesion layer;
after the conductive bumps, the adhesive layer and the carrier are formed, the wafer is thinned from the lower surface to the upper surface, so that the patterned photoresist layer in the grooves is exposed from the lower surface;
forming an insulating layer below the lower surface, the insulating layer directly contacting the patterned photoresist layer;
removing the carrier and the adhesive layer to expose the patterned photoresist layer; and
and cutting the patterned photoresist layer and the insulating layer along each groove to form a plurality of chip packages.
2. The method of manufacturing a chip package according to claim 1, wherein after the step of forming the conductive bump, further comprising:
forming a surface treatment layer on the conductive bump.
3. The method of manufacturing a chip package according to claim 1, wherein the wafer has a thickness of 100 to 150 μm after the step of thinning the wafer.
4. The method of claim 1, wherein the wafer, the conductive bump and the insulating layer have a total thickness of 120 to 210 μm after the step of forming the insulating layer.
5. The method of claim 1, wherein a cutting width of the patterned photoresist layer and the insulating layer along each of the grooves is 15 to 22 μm.
6. The method of claim 1, wherein the conductive bump has a height of 20 to 45 μm.
7. The method of claim 1, wherein each of the grooves has a width of 50 to 60 microns and a depth of 150 to 200 microns.
8. The method of claim 1, wherein the wafer has a thickness of 525 to 725 microns after the step of providing the wafer.
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Citations (1)

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Publication number Priority date Publication date Assignee Title
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US9018758B2 (en) * 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
CN106098625B (en) * 2016-08-08 2023-05-02 华天科技（昆山）电子有限公司 Chip encapsulation structure of plasma dicing and manufacturing method

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