TW456006B - Method of chip scale packaging using chip level packaging technique - Google Patents

Method of chip scale packaging using chip level packaging technique Download PDF

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Publication number
TW456006B
TW456006B TW089114882A TW89114882A TW456006B TW 456006 B TW456006 B TW 456006B TW 089114882 A TW089114882 A TW 089114882A TW 89114882 A TW89114882 A TW 89114882A TW 456006 B TW456006 B TW 456006B
Authority
TW
Taiwan
Prior art keywords
forming
chip
insulation layer
metal pad
photoresist pattern
Prior art date
Application number
TW089114882A
Inventor
Wen-Kuen Yang
Ching-Tsung Mou
Jian-Ren Dung
Original Assignee
Advanced Chip Eng Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Chip Eng Tech Inc filed Critical Advanced Chip Eng Tech Inc
Priority to TW089114882A priority Critical patent/TW456006B/en
Application granted granted Critical
Publication of TW456006B publication Critical patent/TW456006B/en

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Abstract

The present invention includes the following steps: spraying photoresist on the back of the chip; next, spraying photoresist pattern on the front surface of the chip and exposing the metal pad; forming a passivation for the metal pad on the exposed metal pad and removing the photoresist pattern; and, forming the trench in the chip; forming insulation layer covering the chip and filling the trench; forming the opening in the insulation layer and exposing the passivation layer of the metal pad; then, forming the photoresist pattern on the insulation layer for defining the wiring pattern; forming the wiring pattern in the area defined by the photoresist pattern and on the insulation layer with contact to the passivation layer of the metal pad; removing the photoresist pattern; next, forming a mask on the conductive pattern and the insulation layer; forming through-holes in the mask for defining the area formed by the conductive bumps; polishing the back surface of the chip; and, conducting the solder paste printing process to form the solder paste on the specific area and thermally flowing the solder paste to form the conductive bumps.
TW089114882A 2000-07-26 2000-07-26 Method of chip scale packaging using chip level packaging technique TW456006B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW089114882A TW456006B (en) 2000-07-26 2000-07-26 Method of chip scale packaging using chip level packaging technique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW089114882A TW456006B (en) 2000-07-26 2000-07-26 Method of chip scale packaging using chip level packaging technique

Publications (1)

Publication Number Publication Date
TW456006B true TW456006B (en) 2001-09-21

Family

ID=21660542

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089114882A TW456006B (en) 2000-07-26 2000-07-26 Method of chip scale packaging using chip level packaging technique

Country Status (1)

Country Link
TW (1) TW456006B (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7898058B2 (en) 2001-12-31 2011-03-01 Megica Corporation Integrated chip package structure using organic substrate and method of manufacturing the same
US8426982B2 (en) 2001-03-30 2013-04-23 Megica Corporation Structure and manufacturing method of chip scale package
US8492870B2 (en) 2002-01-19 2013-07-23 Megica Corporation Semiconductor package with interconnect layers
US8535976B2 (en) 2001-12-31 2013-09-17 Megica Corporation Method for fabricating chip package with die and substrate
US9030029B2 (en) 2001-12-31 2015-05-12 Qualcomm Incorporated Chip package with die and substrate

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8426982B2 (en) 2001-03-30 2013-04-23 Megica Corporation Structure and manufacturing method of chip scale package
US9018774B2 (en) 2001-03-30 2015-04-28 Qualcomm Incorporated Chip package
US8748227B2 (en) 2001-03-30 2014-06-10 Megit Acquisition Corp. Method of fabricating chip package
US8912666B2 (en) 2001-03-30 2014-12-16 Qualcomm Incorporated Structure and manufacturing method of chip scale package
US7898058B2 (en) 2001-12-31 2011-03-01 Megica Corporation Integrated chip package structure using organic substrate and method of manufacturing the same
US9030029B2 (en) 2001-12-31 2015-05-12 Qualcomm Incorporated Chip package with die and substrate
US8535976B2 (en) 2001-12-31 2013-09-17 Megica Corporation Method for fabricating chip package with die and substrate
US8835221B2 (en) 2001-12-31 2014-09-16 Qualcomm Incorporated Integrated chip package structure using ceramic substrate and method of manufacturing the same
US8471361B2 (en) 2001-12-31 2013-06-25 Megica Corporation Integrated chip package structure using organic substrate and method of manufacturing the same
US9136246B2 (en) 2001-12-31 2015-09-15 Qualcomm Incorporated Integrated chip package structure using silicon substrate and method of manufacturing the same
US8492870B2 (en) 2002-01-19 2013-07-23 Megica Corporation Semiconductor package with interconnect layers

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