TW456006B - Method of chip scale packaging using chip level packaging technique - Google Patents

Abstract

The present invention includes the following steps: spraying photoresist on the back of the chip; next, spraying photoresist pattern on the front surface of the chip and exposing the metal pad; forming a passivation for the metal pad on the exposed metal pad and removing the photoresist pattern; and, forming the trench in the chip; forming insulation layer covering the chip and filling the trench; forming the opening in the insulation layer and exposing the passivation layer of the metal pad; then, forming the photoresist pattern on the insulation layer for defining the wiring pattern; forming the wiring pattern in the area defined by the photoresist pattern and on the insulation layer with contact to the passivation layer of the metal pad; removing the photoresist pattern; next, forming a mask on the conductive pattern and the insulation layer; forming through-holes in the mask for defining the area formed by the conductive bumps; polishing the back surface of the chip; and, conducting the solder paste printing process to form the solder paste on the specific area and thermally flowing the solder paste to form the conductive bumps.

Description

456006 V. Description of the invention (1) Field of the invention: The present invention relates to a semiconductor package, and more particularly to a method for manufacturing a wafer-size package by using a wafer-shaped package process. Background of the Invention: With the reduction in the size of electronic components, many new challenges have arisen in the manufacturing process of integrated circuits. And because of the rapid development of computer and communication technology, there is a need for more and more electronic components of different types and applications. For example, computer interfaces operated by voice or other communication interfaces require many memory components and different types of semiconductor components. Therefore, the trend of integrated circuits will continue to develop towards a high degree of integration. With the rapid evolution of semiconductor technology, driven by the trend of light, thin, short, and versatile, the number of I / Os of 1C semiconductors is not only increasing, but also increasing in density. With the increasing number of I, the speed requirements are getting faster and faster. Semiconductor wafers are usually individually enclosed in packages of plastic or ceramic materials. The structure of the package must protect the chip and dissipate heat generated during the operation of the chip. Traditional packages are also used for chip function testing. The early packaging technology mainly used lead frame packaging technology, using pins as the input and output of signals. Under the requirements of high-density input and output terminals, the packaging of lead frames currently does not meet the above requirements. At present, under the above-mentioned requirements, the package is also getting smaller and smaller to meet the current

M5 60 06 V. Explanation of the invention (2) Trends, and the packaging of high-density output / input (I / 0) has also broken through with the development of ball matrix array packaging technology (ba 1 1 gridarray; hereinafter referred to as BGA packaging). Therefore, the packages carried by IC semiconductors tend to use ball matrix array packaging technology (BGA). The characteristics of the BGA structure are that the pins responsible for I / O are spherical and have a shorter distance than the slender pins of the lead frame package components and are not easily damaged. The electrical transmission distance of the package components is short and fast, which can meet the current requirements. And future digital system speed requirements. For example, in U.S. Patent U.S. Patent No. 5629835, a structure of BGA was proposed by Mahulikar et al. The invention name is " METAL BALL GRID ARRAY PACKAGE WITH IMPROVED THERMAL CONDUCTIVITY ". Another example is U.S. Patent No. 5,239, 19 8 which discloses a package form. The package includes a substrate assembled on a printed circuit board. The substrate is made of FR4. The substrate has a conductive circuit formed on one surface of the substrate. In addition, there are already many different types of semiconductor packages. Regardless of which type of package, the vast majority of packages are cut into individual bodies before being packaged and tested. The U.S. patent discloses a wafer type package. 'Please refer to US 5 3 2 3 0 51, the invention name is Semiconductor wafer level package.' This patent first encapsulates the die before cutting the die, using glass as an adhesive The material makes the component sealed in a hole. A covered perforation is used as a channel for electrical connection. Therefore, 'wafer type packaging is a trend for semiconductor packaging. In addition, known technologies form multiple dies on semiconductor wafers. On the surface, the glass is adhered to the surface of the wafer with an adhesive substance. Then, the side without the crystal grains will be

456006 V. Description of the invention (3) Grinding to reduce its thickness is usually called back grinding. Next, the wafer was engraved with silver to separate the 1C and the adhesive material from the exposed parts. The other glass is adhered to the side with grains by using an adhesive substance. The next step is to form a film layer on the first glass, and then etch the first glass and etch into the adhesive substance part, which is commonly called a notch process, so a trench is formed in the glass and the adhesive substance. It is formed on the film layer in a subsequent process. The film layer composed of the fault will be patterned on the surface of the first glass and along the surface of the trench to provide electrical connection. ^ A solder mask is then formed on the surface of the lead film layer and on the glass to expose the corresponding surface. On the surface of the film layer. The solder ball is then implanted on the surface of the lead film layer exposed by the solder paste mask using a conventional ball implantation technique. The next step is to perform a cutting process to etch the adhesive substance through the trench to penetrate the two separated grains. However, the above-mentioned manufacturing process is too complicated, which requires ^^ man-hours and a step of cutting the second glass to separate the crystal grains. In addition, 3 forms a steep trench slope, and the lead formed thereon will not be easily attached and lead to an open circuit. The quality performance of the device will be reduced accordingly. = 2 Ba round type packaging will become the trend of packaging technology. The present invention proposes a wafer type packaging with a simpler process. Purpose and summary of the invention: The purpose of the present invention is to provide a package with a chip size. Another objective of the present invention is to provide a wafer type package for k and its manufacturing process.

Exposure to the surface 456006 Five 'invention description (4) Another object of the present invention is to provide a wafer type package which can be used for wafer type test, so as to facilitate wafer type collapse test and other tests. The wafer type packaging process of the present invention includes providing a wafer having a plurality of dies formed thereon. The metal pads as input and output are located in the first surface (front surface) of the wafer, and a photoresist is applied. On the second surface (back) of the wafer. Then, a photoresist pattern is coated on the first surface of the wafer and the metal pad is exposed. A metal pad protection layer is formed on the exposed metal pad, and the photoresist pattern is removed. Next, a trench is formed in the wafer, and then an insulating layer is formed to cover the wafer and the protective layer of the metal pad and backfill the trench, and then an opening is formed in the insulating layer and the protective layer of the metal pad is exposed. Then, a photoresist pattern is formed on the insulating layer to define a pattern of the conductive lines. Next, a wire pattern is formed in the area defined by the light pattern, and it is in contact with the protective layer of the metal pad on the insulating layer. After that, the photoresist pattern is removed. The next step is to form a mask over the conductive pattern and the insulating layer, and form a perforation in the mask to define the area where the conductive bumps are formed. Grind the second surface of the wafer to the bottom of the trench. Then, a solder paste printing step is performed to form a solder paste over a predetermined area and heat the tin T to form a conductive bump. After the heat flow step is performed, the wafer is tested. After the test is performed, the wafer is cut along the trench to form separate packaged cells.

45 60 06 V. Description of the invention (5) Detailed description of the invention The present invention discloses a method of wafer type energy, which is described in detail as follows. The aggregation and fabrication of a wafer type package are used to define the invention. See FIG. The preferred embodiment of the M only illustrates a non-first surface having a front surface (or on) of a wafer 2 packaged as an input and output. Then, a photoresist 6 is formed on the wafer substrate (I / 〇Pa d) 4 open > It is better to use a positive photoresist, as shown in the back of the second place (or the second surface), to strengthen the structure of the wafer to avoid cracking [this photoresist will cut the trench resistance pattern 8 in the subsequent Use lithography technology to coat the crystal "circle 2" and then "see Fig. 3" a light case§ has a plurality of openings 9 formed in the surface ^ f, 4 photoresist knife corresponding to the above gold 1 瓴 4 . As shown in Figure 4, a conductive layer 10 followed by a metal pad ~ the opening 9 of the photoresist pattern 8 is formed by electroplating as a protective layer of the metal pad 4. (Pad people take

P r ο 1: e c t i ο η 1 a y e r), in the preferred embodiment, ten, Aoli L 叩 5 is used as the material of the above-mentioned only layer. After showing the trench filling material, refer to FIGS. 5 to 6 to complete the production of the protective layer 10 and remove the above-mentioned photoresist pattern 8 by a known technique. Then, the wafer 2 is etched or cut by the second surface. Therefore, the trench 12 is formed in the wafer. The trench 12 is beneficial to the subsequent step of package division. Then, the substance 14 is filled into the trench 12 and covered on the first surface of the wafer 2 to facilitate insulation, and it can strengthen the structure so that the individual packages are not easily separated in the rear thread. In a preferred embodiment, Ύ 1 I 裎, 4 5 60 Οβ can be made by vacuum coating. 5. Description of the invention (6) Fill epoxy resin as the filling material for this step. This vacuum coating process can prevent the formation of vapor bubbles therein, and epoxy resin (epoXy) will be filled into the trench to connect the packages. A curing step can be performed by ultraviolet irradiation or heat treatment to harden the epoxy resin (epoxy). A plurality of openings 16 are then formed in the insulating layer 14 and corresponding to a metal pad 4 on the die. Of course, the protective layer 10 on these metal pads will be exposed. It must be noted that the epoxy resin described above can use laser openings (1 a s er p a d o p e η) to form a plurality of openings 16. Reference results: Electroless plating is formed on the known photoresist pattern of the film layer 18. The plating method can be over 18 and remove less input and output. The circuit is described again. Referring to FIG. 7, a copper seed layer (18) is formed on the surface of the upper structure and formed along the surface of the opening (16). This step can be performed by electroless Cu plating. On the surface. Next, a photoresist pattern 20 is coated on the copper seed to define the pattern distribution of the wires. This step can use the photo-etching process to achieve the above-mentioned N-center, as shown in Figure 8. After that, the case 20 was used as a barrier, which became poisonous ^ β _ and a long metal wire. For example, using electricity to form a copper material 22 in the Fushe, ^ ^ ^ ν ^ The copper seed layer covered by the photoresist pattern 20 is not broken into the distribution of wires. After removing the photoresist, ^ ^ π, the photoresist pattern 20 is removed,. Although the copper layer 22 may also be thickened by S, it will not affect the entire structure of .s,,, τ. Therefore, the metal input pad 4 can be connected to the metal wire 2 through the film layer m ^ ^ ^ 1 0, see FIG. 10. The above steps can be referred to as a conductive channel layout or a new distribution commonly referred to. Removal of photoresist is a well-known technique, so don't bother here.

456006 V. Description of the invention (7) — ~ Please refer to Figure 11 to Figure 15. The next step is to define the area where the conductor bump (usually a solder ball) is formed. First, a solder masking is formed. Or the insulating layer 24 on the wire 22 is used to define the area formed by kicking or bumps, and it is used as the insulating material. Then the laser drill 'technology is used to remove the part of the solder ball curtain 24 or the insulating layer 24. An opening 26 is formed, and a specific area of the storm wire 22 is exposed. The area where the wire 22 is exposed will be used as a pre -... area for placing the conductor bumps. The next step is to grind the second surface ^ (backside) of wafer 2 to a thickness and use laser marking, as shown in FIG. The photoresist layer 6 is removed during the grinding process. In a preferred embodiment, the photoresist layer 6 is ground to the bottom of the trench. Next, a printing process is used to apply the solder paste to the above-mentioned specific area, and then the solder paste is changed into a solder ball 28 by a heat flow process. The temperature of the heat flow can be obtained by using a known process temperature. The semiconductor die will be coupled to the above-mentioned solder balls 28. The solder balls 28 can be made by using the known solder balls. The better solder balls 28 are distributed in an array arrangement, and the solder balls 28 are connected to the above-mentioned wires. 2 2 Thus an electrical channel is established. Fig. 14 is a diagram showing individual crystal packages on a wafer 'to test the entire wafer as a wafer type. Wafer 2 is transferred to the wafer type test device for wafer type test% test, such as final test (fi na 1 testi ng) 'After completing the wafer type test, then the cutting process is performed to separate individual wafers. Grain. The dicing process mainly cuts along the trench 12 of the filling material to obtain a chip size package (CSP). The manufacturing process of the present invention is simpler than the prior art. The trench 12 for filling material is convenient for connecting the various packages before testing, and after the test, the individual sub-packs can be divided along the trench.

Page 11 456006 V. Description of the invention (8) Figure 15 shows. The wafer-type crystal grains of the present invention are formed thereon. The penetrating wafer is used to separate the metal pads 4 formed thereon. The insulating layer 14 covers the trench 12 and the protective layer 10 described above. Among the wire openings 16, the material (or tin ball cover) 2 4 forms a wire, and the conductive bumps 2 8. The positional package shown in FIG. 13 includes a plurality of circles 2, and the wafer 2 has The trench 12 is formed as a single package. Each packaged cell has a metal pad protective layer 10 covering the wafer surface of the metal pad 4 and the protective layer 10 and filling the insulating layer 1 4 with a plurality of openings 16 corresponding to the upper pattern 2 2 distributed in The insulating layer 14 is overfilled and may be backfilled with copper or an alloy thereof. Another insulating layer is on the wire pattern 22 and the exposed portion is on the exposed wire pattern 22. The present invention has been described above with reference to the preferred embodiments, and those skilled in the art can make some modifications and modifications without departing from the spirit of the present invention. Equivalent field depends.

Page 12 4 5 60 06 Brief description of the drawings Brief description of the drawings: The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures: Figure 1 is a metal pad formed on it A cross-sectional view of the wafer. Figure 2 is a cross-sectional view of a semiconductor wafer coated with a photoresist on the back of the wafer according to the present invention. FIG. 3 is a cross-sectional view of a semiconductor wafer in which a photoresist pattern is formed on the front side of a wafer according to the present invention. FIG. 4 is a cross-sectional view of a semiconductor wafer for forming a metal pad protection layer according to the present invention. FIG. 5 is a cross-sectional view of a semiconductor wafer in which the photoresist pattern is removed and trenches are formed in the wafer according to the present invention. Figure 6 shows a cross-sectional view of a semiconductor wafer with an insulating layer formed and backfilled in a trench according to the present invention. Figure 7 shows a cross-sectional view of a semiconductor wafer with a copper seed layer formed by electroless plating. FIG. 8 is a cross-sectional view of a semiconductor wafer coated with a photoresist pattern. Figure 9 shows a cross-sectional view of a semiconductor wafer with a conductive pattern in the area defined by the photoresist pattern. Figure 10 is a cross-sectional view of a semiconductor wafer with the photoresist pattern removed. FIG. 11 is a cross-sectional view of a semiconductor wafer forming a solder ball mask. Figure 12 shows a cross-sectional view of a semiconductor wafer on the back of a polished wafer. FIG. 13 is a cross-sectional view of a semiconductor wafer forming a solder ball.

Page 13 456006 Brief description of drawings Figure 14 shows a cross-sectional view of a semiconductor wafer for wafer type testing. Figure 15 shows a cross-sectional view of a semiconductor wafer performing wafer-type package dicing. Component symbol comparison wafer 2 Photoresist 6 Opening hole 9 Ditch 12 Opening hole 16 Photoresist pattern 20 Tin ball mask 2 4 Conductive bump (tin ball metal pad 4 Photoresist pattern 8 Metal pad protection layer 1 0 Insulation layer 14 Copper Seed layer 18 Conductive pattern 22 Opening 2 6

Page 14

Claims (1)

456006 VI. The process of applying for a patented range of packaging. A metal pad with several grains formed on the second surface of the circle. The scope of patent application 1. A wafer type provides a photoresist with multiple input and output coatings on the wafer. The process includes: the wafer on it, the first table of the wafer The wafer has a F1 surface; a photoresist pattern is coated on the first surface of the wafer and the metal pad is exposed; a metal pad protection layer is formed on the exposed metal pad; the photoresist pattern is removed; A trench in the wafer; forming an insulating layer covering the wafer and the metal pad protection layer and backfilling the trench; forming an opening in the insulation layer and exposing the metal pad protection layer; forming A photoresist pattern is used to define a pattern of a conductive line on the insulating layer; a conductive line pattern is formed in an area defined by the photoresist pattern and is located on the insulating layer to be in contact with the protective layer of the metal pad; removing the photoresist pattern; Forming a mask on the conductive pattern and the insulating layer; forming a perforation in the mask to define the area where the conductive bump is formed; grinding the second surface of the wafer up to the bottom of the trench and removing the same The photoresist on the second surface; performing a solder paste printing step to form a solder paste over the predetermined area; and heat-flowing the solder paste to form the conductive bump. Page 15 456006 6. Scope of patent application 2. For the wafer type package manufacturing process under the scope of patent application item I, after performing the heat flow step, it further includes testing the wafer. 3. The wafer type package manufacturing process as described in the second patent application scope, wherein after performing the test, the method further includes cutting the wafer along the trench. 4. The manufacturing process of the wafer type package according to the scope of the patent application, wherein the protective layer of the metal pad includes nickel (Ni) or chromium (Cr). 5 The manufacturing process of the wafer type package according to the first patent application scope, wherein the above-mentioned insulating layer includes epoxy resin. 6. The manufacturing process of the wafer type package according to item 1 of the patent application, wherein the opening of the insulating layer is formed by laser. 7. The manufacturing process of the wafer type package according to item 1 of the patent application scope, wherein the conductive pattern mentioned above includes copper. 8. For the wafer type package manufacturing process under the scope of patent application item 7, the above copper is formed by electroplating. 9. A wafer-type package comprising: a wafer having a plurality of dies formed thereon, wherein the wafer has trenches formed in the wafer and penetrating the wafer to separate the individual packages. single Page 16 456006 6. The scope of the patent application, each packaged unit has a metal pad formed on it; a metal pad protection layer covering the metal pad; an insulating layer covering the wafer surface and the metal pad The protective layer is filled above the trench, and the above-mentioned insulating layer includes a plurality of openings corresponding to the above-mentioned protective layer of the metal pad; a wire pattern is distributed on the insulating layer; a tin ball cover is formed on the wire A conductive wire above the pattern and the exposed portion; and a conductive bump on the exposed conductive wire pattern. 10. The wafer type package according to item 9 of the patent application scope, wherein the above-mentioned insulating layer includes epoxy resin. 1 1. The wafer type package according to item 9 of the scope of patent application, wherein the above-mentioned metal pad protection layer includes zinc (Zn) / record (Ni) or chromium (Cr). 1 2 · If the wafer type package of item 9 of the patent application scope, wherein the above-mentioned wiring pattern includes copper. 1 3. The wafer type package according to item 9 of the scope of patent application, wherein the above-mentioned wire bump includes a solder ball. Page 17