TW469608B - Fabrication method for chip scale package using wafer level packaging - Google Patents

Abstract

A photo polymer such as photo polyimide film is coated to a first (front) surface of a wafer and metal pad openings are formed in the photo polymer film. A first photoresist is then coated on a second (back) surface of the wafer. A first conducting layer is formed in the openings and covers the metal pads. A seed layer is formed on the first conducting layer and the photo polymer film. A second photoresist is formed on the seed layer to define a circuit pattern. A second conducting layer is grown to materialize the circuit pattern. The second photoresist, the first photoresist and the seed layer covered by the second photoresist are removed. Trenches are formed among individual packages, and filling material fills the trenches and covers the circuit pattern. The second (back) surface of the wafer is grinded until the filling material is exposed. Holes are opened to expose part of the circuit pattern and conducting bumps are formed.

Description

469608 V. Description of the invention (1) Field of the invention: The present invention relates to a semiconductor package, and more particularly to a method for manufacturing a wafer-size package by using a wafer-shaped package process. Background of the Invention: With the reduction in the size of electronic components, many new challenges have arisen in the manufacturing process of integrated circuits. And because of the rapid development of computer and communication technology, there is a need for more and more electronic components of different types and applications. For example, computer interfaces operated by voice or other communication interfaces require many memory components and different types of semiconductor components. Because of this, the trend of integrated circuits will still start towards high integration. With the rapid evolution of semiconductor technology, driven by the trend of light, thin, short, and versatile, the number of I / Os of 1C semiconductors is not only increasing, but also increasing in density. With this, more and more speeds are required. Semiconductor wafers are usually individually enclosed in packages of plastic or ceramic materials. The structure of the package must protect the chip and dissipate heat generated during the operation of the chip. Traditional packages are also used for chip function testing. The early packaging technology mainly used lead frame packaging technology, using pins as the input and output of signals. Under the requirements of high-density input and output terminals, the packaging of lead frames currently does not meet the above requirements.

469608 Five 'invention description (2) At present, under the above requirements, the package is getting smaller and smaller to meet the current trend, and high-density I / 0 packaging is also accompanied by the ball matrix array packaging technology (ba 1 1 gridarray; The following is a breakthrough in the development of BGA packaging technology. Therefore, the packages carried by IC semiconductors tend to use the ball matrix array packaging technology (BGA). The characteristics of the BGA structure are that the pins responsible for I / O are spherical and have a shorter distance than the slender pins of the wire-frame component and are not easily deformed. The electrical transmission distance of the package components is short and fast, which can meet the current requirements. And future digital system speed requirements. For example, in U.S. Patent No. 5629835, a structure of BG A was proposed by Mahulikar et al. The invention name is " METAL BALL GRID ARRAY PACKAGE WITH IMPROVED THERMAL CONDUCTIVITY11. At present, there are many different types of semiconductor packages, such as the above-mentioned lead frame or BGA package. For example, such as US Patent Mo. 5, 239,19 8 discloses a package form, this package includes an assembly in a printed circuit The substrate on the board is made of FR4 material. The substrate has a conductive line formed on one surface of the substrate. In addition, there are currently many different types of semiconductor packages. Regardless of which type of package, the vast majority of packages are cut into individual packages before being packaged and tested. The United States patent discloses a wafer type package, please refer to US5 3 2 3 0 51, and the invention name is' ’Semiconductor wafer level Package ". This patent encloses the package before cutting the die, using glass as a bonding material to seal the component in a hole. A covered perforation is allowed as a channel for electrical connection.

Page 6 469608 V. Description of the invention (3) Therefore, wafer type packaging is a trend of semiconductor packaging. In addition, a known technique forms a plurality of dies on the surface of a semiconductor wafer, and glass is adhered to the surface of the wafer using an adhesive substance. The side without grains is then ground to reduce its thickness, and is commonly referred to as back-grinding (back g r i n d i n g). Then, the wafer is etched to separate the IC and the adhesive substance of the exposed portion. The other glass is adhered to the side with grains by using an adhesive substance. The next step is to form a film layer on the first glass, and then etch the first glass and etch into the adhesive substance part, which is commonly called a notch process, so a trench is formed in the glass and the adhesive substance. It is formed on the film layer in a subsequent process. A film composed of lead will be patterned on the surface of the first glass and along the surface of the trench to provide electrical connection. A solder mask is then formed on the surface of the lead film layer and on the glass to expose the surface corresponding to the film layer. The solder ball is then planted on the surface of the ship's film layer exposed by the solder paste mask using the traditional ball implantation technique. The next step is to perform a cutting process to etch the adhesive substance through the trench to penetrate the glass to separate the crystal grains. However, the above-mentioned process is too complicated, it requires a notch process and a step of cutting the second glass to separate the crystal grains. In addition, it includes the formation of a steep trench slope, and the lead formed thereon will not easily adhere and lead to an open circuit. The quality performance will be reduced accordingly. In view of the fact that wafer type packaging will become the trend of packaging technology, the present invention proposes a wafer type package with a simpler process. Purpose and summary of the invention:

4 69 608 V. Description of the invention (4) The object of the present invention is to provide a package having a chip size. Another object of the present invention is to provide a wafer type package and a manufacturing process thereof. Another object of the present invention is to provide a wafer type package that can be used for wafer type testing * to facilitate wafer type testing and other tests. The wafer type packaging process of the present invention includes providing a A wafer having a plurality of dies formed thereon, the wafer having metal pads as input and output is located in the first surface of the wafer. After that, a photo-polymerizable polymer such as a photo-sensitive polyimide film (PHOTO PI) is coated on the first surface, and a portion of the film layer can be removed by laser to expose the metal pad. The next step includes coating a first photoresist on the second surface of the wafer, wherein the first photoresist includes a positive photoresist. Then, a first conductive layer is formed in the openings of the photo-sensitive polyimide film (PHOTO PI) and covers the metal pad, wherein the first conductive layer includes an alloy and the composition includes zinc / nickel / copper. The next step is to form a copper seed layer on the first conductive layer and the photopolymerizable polymer, and then form a second photoresist on the seed layer to define the circuit distribution pattern, and then grow the second conductive layer as The above-mentioned circuit distribution pattern is located in a region defined by a second photoresist, wherein the above-mentioned second conductive layer comprises copper. Then, the second photoresist and the first photoresist are removed, and the seed layer covered by the second photoresist is removed to form a trench between the packages.

469608 " — V. Description of the invention (5)

Then, the filling material is filled in the trench and covered on the circuit distribution pattern 'wherein the above-mentioned filling material includes epoxy resin (epoxy) D', and then the polishing process is performed to polish the second surface of the wafer until the filling material is exposed, An opening step is performed to expose a portion of the circuit distribution pattern to define a predetermined area formed by the conductive bumps. A solder paste printing step is performed to form a solder paste on the predetermined area, and finally the solder paste is hot-flowed to form a conductive bump. Detailed description of the invention: The present invention discloses a wafer type package and a method for manufacturing the wafer type package. The detailed description is as follows: 'The preferred embodiment described is only for explanation and is not intended to limit the present invention.' See FIG. 1 and FIG. Second, the surface (or the first surface) of a wafer 2 has a metal pad (丨 / 〇pad) as the input and output 4 °, and a window for laser repair can be formed in the wafer 2 6 °. A polymer film 8 is formed on the first surface of the wafer 2. It is best to use a photosensitive polyimide film layer (PHOTO PI) or epoxy resin. A curing step can use ultraviolet irradiation or heat treatment to harden the above-mentioned epoxy resin (the step after epoxy h) includes forming a plurality of openings 9 in the insulating layer 8 and corresponding to metal pads (Pad) on the grains 4. Of course, these metal pads 4 will be exposed, it must be noted that the above-mentioned Photo PI or epoxy seal laser is 矸 translucent material ', so the alignment mark on the cutting track will not be Covered by the insulating layer 8. In other words, the alignment mark

Page 9 4 69 60 8 V. Description of the invention ¢ 6) The note is visible to the alignment device. In addition, the opening 9 may be formed to expose the metal pad 4 in the following manner. A photopolymerizable polymer 8 is deposited on the wafer 2 and a photomask (not shown) with a specific pattern is used to transfer the pattern to the photoresist. Then, the photopolymerization type on the metal pad 4 is etched using an etching technique. The polymer 8 is removed, and an opening 9 is formed to expose the metal pad 4. Referring to FIG. 3, a photoresist 10 is coated on the second surface of the wafer 2, and then a we 11 ing layer 12 as an input / output metal pad is filled in the opening 9. Generally, an electrical clock can be used. The wetting layer 12 of the metal pad is formed in the above manner. Its composition may generally be an alloy or a metal. For example, it may be a zinc / record / copper composition, as shown in FIG. The above-mentioned composition or material is only described for the purpose of not limiting the present invention. Next, referring to FIG. 5, a copper seed layer 14 is formed on the above-mentioned structure surface. The copper seed layer 14 can be formed on the film layer 8 and the metal pad by means of electroless Cu plating. Of we 11 i ng layer 1 2 above. Next, the photoresist pattern 16 is applied on the copper seed layer 14 using a lithography technique to define a pattern of a metal wire, as shown in FIG. 6. Using the photoresist pattern 16 as a barrier, a conductive pattern (copper layer) 18 is formed on the copper seed layer 14 not covered by the photoresist pattern 16. The copper layer 18 can be made by electroplating or other methods to form a pattern of metal wires on the surface of the wafer 2, as shown in FIG. Of

Page 10 469608 5. After the description of the invention (7), the photoresist pattern 16 is removed, and the copper seed layer 14 located thereunder is also removed. Although the copper layer 18 may be removed to a small thickness, it will not affect the entire structure. Therefore, the input / output metal pad 4 can be connected to the wire pattern 18 through the film layer 12 as shown in FIG. The above steps can be called conductive channel layout or circuit redistribution. Referring to FIG. 9, the wafer 2 is then etched or cut from the first surface of the wafer 2, so that a trench 20 is formed in the wafer, and the trench 20 facilitates subsequent singulation steps. A filling material 22 is further filled in the trench 20 and covered with the wiring pattern 18 to facilitate insulation, and the individual packages cannot be easily separated in subsequent steps. It is best to use a vacuum coating process. The filling material 2 2 can be an epoxy resin (e ρ ο X y) as a protective layer on the wafer surface. This vacuum coating process can prevent bubbles from being formed therein, and epoxy resin (e ρ ο X y) will be filled into the trench to connect the packages. A curing step may be performed by ultraviolet irradiation or heat treatment to harden the epoxy resin described above. A wafer back grinding process is then used to grind the second surface of the wafer (the side without the circuit) to the bottom of the trench 20, which is to expose the filling material (epoxy resin) 2 2 as shown in the figure. Ten. Please refer to Figure 11. The next step is to define the area formed by the conductor bump (usually a solder ball). As a filling material for insulation 22, a part of the area will be removed and the specific area of the wire pattern 18 will be exposed. 18 The exposed area is the area where the conductor bumps are intended to be placed. The printing process can be used to apply the solder paste to the above specific areas. Then the heat flow process is used to remove tin

4 6 9 6 0 8 V. Description of the invention (8) The paste is converted into a solder ball 24. The temperature of this heat flow can be obtained by using a known process temperature. The semiconductor die will be coupled to the above-mentioned solder balls 24. The solder balls 24 can be fabricated by known BGA technology. The preferred solder balls 24 are arranged in an array, and the solder balls 24 are connected to the above-mentioned circuit or wire pattern 1. 8 Thus an electrical channel is established. Figure 12 is a schematic diagram of individual die packages located on a wafer, and the whole wafer being tested for wafer type. The wafer 2 is transferred to a wafer type testing device for wafer type testing, such as a final test (f i na 1 t e s t i n g). After the wafer type test is completed, a dicing process is performed to separate individual dies. The cutting process mainly cuts along the trench 20 filled with epoxy resin 22 to obtain a chip size package (c h i p s i z e p a c k a g e; CSP). The manufacturing process of the present invention is simpler than the prior art. The trench 20 on the backside of the photoresist and the filling material is convenient for connecting various packages before testing, and after testing, the individual sub-packages can be divided along the trench, as shown in Figure 10. Three shown. As shown in FIG. 11, the wafer type package of the present invention includes a wafer 2 having a plurality of dies formed thereon, wherein the wafer 2 has a trench 20 formed therein and penetrating the wafer. Fill material 2 2 is filled in the trench. A metal pad 4 is formed on the surface of the wafer 2, and a photosensitive polymer such as a photosensitive polyurethane film 8 is formed on the surface of the wafer 2, and the metal pad 4, the first conductive layer 12, and the insulating material 8 are exposed. Among them, the conductive channel 18 is located on the insulating material 2 2 and the first conductive layer 12. The protective layer covers the conductive channel and the insulating material, and the exposed conductive channel and the conductive bump 24 are located on the exposed wire pattern 18.

Page 12 469608 V. Description of the invention (9) The present invention has been described above with reference to the preferred embodiments. Those skilled in the art can make some modifications and modifications without departing from the spirit of the present invention. It depends on the scope of the attached patent application and its equivalent fields.

Page 13 469608 Simple description of the pattern Simple illustration of the pattern: The figure IWV below is supplemented by the Chinese character text, and then the example will be implemented: the detailed and detailed description of the better explanation will be used as a truncated circular crystal guide. The surface of the half figure is a step with a round hole. The pad is made of gold. It is formed into a shape. The hair is made of metal. The figure is shown. Mingfa was showing it. . The figure is shown in the following three sections:

Layers of W-shaped truncated crystal guides. Layers of truncated circular crystal seeded copper are electroformed without electroplating. Figure 5. The plan view of the body chart is shown in the figure. The figure shows the six-circle figure crystals. The cross-section of the cross-section of the wafer is a semi-conductor of the semi-conductor wafer. The copper material is formed by photoresist plating and the photoresist is divided by the display. The protective cover and the middle channel trench are filled with the material. To. The canal map The trough surface is cut into a circle, which is a layer map of the crystal display display guide. The figure shows the rounded wafer crystal conductor semiconducting semi-ground grinding of the spherical surface of the tin back into a round crystal as shown in the figure. Figure 10 The test cutting and cutting state of the round shape crystal is shown in the figure

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Claims (1)

4 6 9 60 8 • .------ * " ··-丨 VI. Patent Application Scope 1. A method for making a wafer size package using wafer type packaging technology includes: providing a chip with a plurality of crystals formed on A wafer thereon, the wafer having metal ions as input and output located in the first surface of the wafer; coating a photopolymerizable polymer on the first surface; removing a portion of the photopolymerizable polymer For exposing the metal pad; coating a photoresist on the second surface of the wafer; forming a first conductive layer in the photopolymerizable polymer and covering the metal pad; forming a conductive seed layer on the conductive layer and the Photoelectric polymer-type electricity., The case description on the map is divided into the definition of the road area electrical area meaning to determine the use of the layer on the case of the photoresistor layer should be in the layer case of the electric resistance of the second photodiode; The formation of the upper and lower cases is to block the light and remove the cover and block the light and the case; a ^ j case to block the light and the cloth should be separated from the way to seal the body. Yi Dingyi, use case, The road of the distribution part is filled with electricity. The cloth is covered by the dew cover. The storm road is covered with electricity and straight to the middle surface of the surface canal. The second trench is the one filled with the round crystals. The step area of the step hole 89 should be set to the guest pair; the tin block field is set to form a convex area, so as to guide the step into a brush shape, and the tin block is tinned to form a piece of electricity. Conductive heat conduction and page 16 4 69 60 A_ VI. Application for patent scope 2. For the method of making wafer size package using wafer type packaging technology in the first scope of patent application, after performing the heat flow step It also includes testing the wafer. 3. The method of manufacturing a wafer-size package using wafer type packaging technology as described in item 2 of the patent application scope, wherein after performing the test, the method further includes cutting the wafer along the trench. 4. For example, the method for manufacturing a wafer-size package by using wafer type packaging technology in the first scope of the patent application, wherein the above-mentioned photosensitive polymer type polymer includes a photosensitive polyimide film layer. 5. For example, the method for manufacturing a wafer-size package using wafer type packaging technology in item 1 of the scope of patent application, wherein the aforementioned photopolymerizable polymer includes an epoxy resin. 6. For example, the method for manufacturing a wafer size package using wafer type packaging technology in the first patent application scope, wherein the above-mentioned opening of the metal pad is formed by laser. 7. The method for manufacturing a wafer-size package by using the wafer type packaging technology according to the first patent application scope, wherein the first conductive layer mentioned above contains an alloy and the composition contains zinc / nickel / copper. Page 17 469608 6. Scope of patent application 8. For the method of making wafer size package using wafer type packaging technology as described in item 1 of patent application scope, the seed layer mentioned above includes copper formed by electroless plating. 9. The method for manufacturing a wafer-size package by using the wafer type packaging technology as described in the first patent application scope, wherein the second conductive layer includes copper. B. 10. The method for making a chip-size package using wafer type packaging technology as described in item 9 of the scope of patent application, wherein the above-mentioned copper is formed by electroplating. A method for manufacturing a chip-size package using a state-of-the-art packaging technology, wherein the above-mentioned filling material includes epoxy 〇1 2. The method for manufacturing a chip-size package using a wafer type packaging technology as described in item 11 of the patent application scope, wherein The method includes performing a curing step to cure the epoxy resin. 13. Contains: a wafer size package made using wafer type packaging technology, the package has a plurality of wafers formed on the wafer, wherein the wafer has trenches formed in the wafer and penetrates the wafer A filling material is filled in the trench; a metal plutonium is formed on the surface of the wafer; Page 18 4 69 60 8 VI. Patent application scope Photopolymerizable polymer material is formed on the surface of the wafer and exposes the metal pad; the first conductive layer is interposed between the photopolymerizable polymer material; A wire pattern on the photopolymerizable polymer material and the first conductive layer; a protective layer covering the wire pattern and the photopolymerizable polymer material on the exposed portion of the wire pattern; and a conductive bump Above the exposed wire pattern. 1 4. The wafer size package produced by the wafer type packaging technology according to item 13 of the patent application scope, wherein the above photopolymerizable polymer includes a photosensitive polyimide film layer. 15. The wafer-size package manufactured by using the wafer type packaging technology according to item 13 of the patent application scope, wherein the above-mentioned photopolymerizable polymer includes an epoxy resin. 1 6. The wafer size package produced by the wafer type packaging technology according to item 13 of the patent application scope, wherein the above-mentioned filling material includes epoxy resin. 1 7. The wafer size package manufactured by using the wafer type packaging technology according to item 13 of the patent application scope, wherein the above protective layer includes epoxy resin. 1 8. Manufactured using wafer type packaging technology as described in item 13 of the scope of patent application Page 19: 69608 Page 20