200921810 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種晶粒重新配置之封裝方法，特別是有關於一種在 晶粒重新配置之封裝結構中使用金屬凸塊之製造方法。 【先前技術】 半導體的技術已經發展的相當的迅速，因此微型化的半導體晶粒(Dice) 必須具有多樣化的功能的需求，使得半導體晶粒必須要在很小的區域中配 置更多的輸入/輸出墊(I/O pads)，因而使得金屬接腳(pins)的密度也快速的 提高了。因此，早期的導線架封裝技術已經不適合高密度之金屬接腳；故 發展出一種球陣列(Ball Grid Array: BGA)的封裝技術，球陣列封裝除了有比 導線架封裝更高密度之優點外，其錫球也比較不容易損害與變形。 隨著3C產品的流行’例如：行動電話(cell Ph〇ne )、個人數位助理(pDA ) 或是iPod等，都必須要將許多複雜的系統晶片放入一個非常小的空間中， 因此為解決此一問題，一種稱為「晶圓級封裝（Waferlevdpaekage;wij))」 之封裝技術已經發展出來，其可以在切割晶圓成為一顆顆的晶粒之前，就 先對晶圓進行封裝。美國第5,323,051號專利即揭露了這種「晶圓級封裝」 技術。然而，這種「晶圓級封裝」技術隨著晶粒主動面上的焊墊數目 的增加，使得焊塾(pads)之間距過小，除了會導致喊轉合或訊號干擾的問 題外，也會因為焊墊間距過小而造成封裝之可靠度降低等問題。因此，當 晶粒再更進一步的縮小後，使得前述的封裝技術都無法滿足。 為解決此-問題，美國公開專利第7，196,4G8號已揭露了—種將完成半 導體製程之晶圓，經過測試及切割後，將測試結果為良好的晶粒此) 重新放置於另-個基板之上’然後再進行封裝製程，如此，使得這些被重 新放置的晶Μ具有較寬關距，故可以將晶粒上的焊墊適當的分配，例 如使用橫向延伸（fan〇ut)技術，因此可以有效解決因間距過小，除了會導 5 200921810 致sil號麵合或訊號干擾的問題。 ▲然而’缺半導體晶片能財較小及較薄的封裝結構，在進行晶圓切 割前’會先對晶圓進行薄化處理，例如以背磨（backside lapping)方式將晶 圓薄化至2〜2GmH，然後再切誠一顆顆的晶粒。此—經過薄化處理之晶 粒，經過重新配置在另—基板上，再以注模方式將複數個晶_成一封膠 體；由於晶粒很薄，使得封膠體也是非常的薄，故當封膠體脫離基板之後， 封膠體本身的應力會使得封膠體產生減，增加後續進行_製程的困難。 另外在曰曰圓七刀割之後，重新配置在另一個基板日夺，由於新的基板的 尺寸=原來的尺寸為大’因此在後續植球製程中，會無法對準其封裝結 構可靠度降低。為此，本發明提供—種在進行晶圓切割之前，在晶圓背面 形成對準標諸(alignment _幻其可以有效地解決植球時無法對準以及封膠 體產生翹曲的問題。 此外，在整個封裝的過程中，還會產生植球時，製造設備會對晶粒產 生局部過大的壓力’而可能損傷晶粒的問題；同時，也可能因為植球的材 料造成與晶粒上的焊墊間之電阻值社，而影響晶粒之性能等問題。 【發明内容】 有馨於發㈣景巾所叙損傷晶粒及f彡響晶粒之性鮮問題。本發明 之主要目的在提供一種在晶粒重新配置之封裝方法，係在植球前，先在晶 粒上的焊墊上’絲成_化之金屬線段，紐形成導電柱以作為一緩衝， 藉由導電柱以電性連接導電元件及金屬線段，且可藉由導電柱降低植球對 晶粒的損傷，故可有效提高製造之良率及可靠度。 本發明之另一主要目的在提供一種在晶粒重新配置之封裝方法，係在 植球則’選擇適當的導電材料卿成導電柱，因此可降低植_材料焊塾 間之電阻值，故可有效提晶粒之性能。 200921810 此外，本發明還有—主要目的在提供一種晶粒重新配置之封裝方法， 其可以將12 4晶騎蝴丨來的晶粒重新配置於8)^晶圓之基板上，如此 可以有效運用8对晶圓之即有之封裝設備，而無需重新設立12对晶圓 裝設備，可以降低12吋晶圓之封裝成本。 本發明之再-主要目的在提供—種晶粒重新配置之封裝方法，使得進 行封裝的晶片都是”已知是功能正常之晶片，，（Kn_ gQQd㈣，可以節省 封裝材料，故也可以降低製程之成本 根據以上所述，本發明揭露_種晶粒重新配置之封裝方法，包括:提供 了基板’具有-上表面及—下表面，於上表面配置—黏著層；提供複數個 晶粒，具有-絲面及-背面，於主動面上配置有複油焊墊；取放複數 個晶粒，係將每-晶粒之主動面以覆晶方式置放在基板之黏著層上；形成 -高分子材料層在基板及部份晶粒之下表面上；提供—模具裝置，用以平 坦化高分子材㈣，使得高分子材料層填滿在複數個晶粒之間；脫離模具 裝置以纟傅體並包覆每—晶粒；剝離基板，以裸露丨複數個晶粒 之主動面上之複數個焊塾；形成—金屬層以覆蓋複數個晶粒之主動面上之 複Ml焊墊；形成―第—圖案化之保護層在金屬層上並曝露出部份金屬層 之一表面；形成複數個導電柱’係將導電材料形於已曝露之部份金屬層上； 移除第-®案化之賴層轉露出複數個導電柱及部份金屬層；形成第二 圖案化=保護層在複數縛及部份金屬層之上並曝露出部份金屬層； 移=曝露之金屬層，以形成複數個圖案化之金屬線段，其中圖案化之金屬 線段之-端與每-晶粒之主動面之複數個焊墊電性連接，而另—端則與複 數個導電_成電性連接；形成__化之保蘭，哺蓋複數侧案化 =屬線段，且曝露出複數轉電柱之―表面以作為導電端點；形成複數 導電讀，係鱗列排财式戰在已《之複數鱗電柱之表面上以 形成電性連接；及切卿雜，以軸複數個各自社完裝之晶粒。 根據以上之晶粒重新配置之封裝方法，本發明揭露—種晶粒重新配置 200921810 之封裝結構’包括:一晶粒’其一主動面上配置有複數個焊墊；複數個圖案 化之金屬線段，其複數個圖案化之金屬線段之一端與晶粒之主動面之複數 個焊墊電性連接；複數個導電柱，係形成在複數個圖案化之金屬線段上； 一封膠體，係包覆晶粒之五個面且曝露出複數個圖案化之金屬線段；複數 個導電柱，形成在複數個圖案化之金屬線段之另一端上；一圖案化之保護 層’係包I：複數個圖案化之金屬線段且曝露出複數個導電柱之—表面以作 為導電端點；及複數個導電元件，係鱗卿财式躲連接於已曝露之 複數個導電柱之表面上。 有關本發明的特徵與實作’茲配合圖示作最佳實施例詳細說明如下。 (為使對本發明的目的、構造、雛、及其魏有進-㈣瞭解，兹配合 實施例詳細說明如下。） 【實施方式】 本發明在此所探討的方向為—種晶粒飾配置之封裝方法，將複數顆 晶粒重新配置於另-基板上’織進行職的方法。為了驗紐瞭解本 發明，將在下列的描述令提出詳盡的步驟及其組成。顯然地，本發明的施 行並未限定晶片堆疊的方式之技藝者所熟習的特殊細節。另—方面，眾所 周知的晶片職方式以及晶㈣化额段製程之詳細步驟並未描述於細節 中’以避免造成本發明不必要之限制。然而，對於本發明的較佳實施例， 則會詳細描述如下，然崎了這些詳細描述之外，本發㈣可簡泛地施 行在其他的實施财，且本發_範圍不受限定，纽之後的專利範圍為 準。 在現代的半導體封裝製封，均是將一個已經完成前段製程（Fr〇mEnd Process)之晶圓（wafer)先進行薄化處理（ThinningPr〇cess)，例如將晶片 的厚度研磨至2〜20 miI之間；然後，進行晶圓的切割（讀㈣帅咖)日曰以 形成-顆顆的晶粒；然後，使用取放裝置（pkkajidplaee)將—顆顆的晶粒 200921810 逐一放置於另一個基板100上’如第1圖所示。很明顯地，基板上的晶粒 間隔區域比晶粒110大，因此，可以使得這些被重新放置的晶粒110間具有 較寬的間距，故可以將晶粒110上的焊墊適當的分配。此外，本實施例所使 用的封裝方法，可以將12吋晶圓所切割出來的晶粒110重新配置於8吋晶 圓之基板100上，如此可以有效運用8时晶圓之即有之封裝設備，而無需 重新設立12吋晶圓之封裝設備，可以降低12吋晶圓之封裝成本。然後要 強調的是，本發明之實施例並未限定使用8对晶圓大小之基板，其只要能 提供承載的功能者，例如：玻璃、石英、陶瓷、電路板或金屬薄板（metal f〇il) 等’均可作為本實施例之基板，因此基板的形狀也未加以限制。 接著，請參考第2A圖及第2B圖，係表示具有對準標誌之晶圓之俯視 圖。如第2A圖所示，係表示在晶圓40的上表面上具有複數個晶粒41〇，且 在晶圓40之背面的x-y方向上，設置有複數個對準標誌(alignment mark)402，如第2B圖所示。如前所述，當晶圓40經過切割之後形成複數 個晶粒410，再重新將這些晶粒41〇逐一配置在基板時，由於新的基板之間 的晶粒間隔區域比重新配置的晶粒41〇大，在後續封裝製程的植球步驟(ball mount)會無法對準，而造成封裝結構的可靠度降低。在此，形成對準標誌 4〇2的方式可以利用光蝕刻(ph〇t〇_etching)製程，其係在晶圓4〇的背面且在 x-y方向上形成複數個對準標誌402，且其形狀為十字之標誌。另外，形成 對準標諸402的方式還包括利用雷射標籤(iasermark)製程。 緊接著，再進行晶圓40的切割步驟，係將晶圓40切割以形成複數個 曰曰粒410 ’然後再使用取放裝置（pick and place apparatus )將複數個晶粒410 重新配置在新的基板2〇上，如第3圖所示；其中，每一顆晶粒41〇具有主 動面及下表面，且在主動面上配置有複數個焊墊412。在此，晶粒重新配置 的方式係將每一顆晶粒41〇以覆晶方式(flip chip)置放在基板2〇上配置有一 黏著層30之上表面。 接著，請參考第4圖，於基板20及部份晶粒410上形成一高分子材料 200921810 ^ ’並且使用-模具裝4駕以平坦化高分子材料層⑼，其中，模且裝 置500是與每一顆晶粒41〇之背 八 籍魏“， 超如第5圖所示，使得高分 子材枓層60械-平坦化的表面並且填滿於每—顆晶粒· =膠體，此高分子材料層60可以是轉、環氧樹脂、丙稀酸 及本％丁烯（BCB)等材料。 一接著’可以選擇性地對平坦化的高分子材料層6〇進行一輯程序，使 =侧4層㈣化。再接著，進行脫模程序，將模具裝置與固化後 的^刀子材繼6G分離’啸露出部解坦之高分子材顯⑼之表面以 及複數個晶粒彻之背面，如第6圖所示。此時，可以選擇性地使用一種 Z刀(未在财表示），在高分子材料層⑼的表面上形成複數條切割道 由其中每一條切割道602的深度為〇.5〜1密爾㈣），而_道602的寬 又則為5至25微米。在一較佳實施例中，切割道6〇2可以是相互垂直交錯， 並且可以作為實際切割晶粒時的參考線。 緊接著，將基板20與高分子機層⑼分離，例如將基板μ與高分子 ;斗層6〇起放人去離子水的槽巾(未在圖巾表示），使基板2G與高分子材 料層60分離，以形成—個封膠體。此封賴包覆每一顆晶粒彻的五個面， 並且曝露出每-顆晶粒的主動面上複數個焊塾412。在本實施例中，由 於封膠體之相對於晶粒210之主動面的表面上有複數條切割道6〇2,因此， 當高分子材料層60 板2{)剝離後，封膠體上的應力會被這些切割道6〇2 所形成的區域峨消’故可有效鱗決娜馳曲的問題。 緊接著’參考第7圖至第u目，係緣示在複數個晶粒之主動面之複數 個焊墊上形成複數鋼案化之金屬線段及複數個導電柱之各步驟示意圖。 如第7圖所示，係在娜體之上表面及複數個晶粒之絲面上形成一 金屬層7〇 ;在此要強調，此金屬層％可以是金屬層。接著，如第8 圖所示，形成第一保護層8〇在金屬層7〇上方，此第一保護層8〇的材料可 以是pdyimide ;再接著，如第9圖所示，利用半導體製程技術，例如顯影 200921810 及蝕刻，以移除部份第一保護層80,且形成一圖案化之第一保護層8〇並曝 露出部份金屬層之表面；接下來，將複數個導電柱90形成於已曝露之部份 的金屬層70之表面上；然後，再利用半導體製程技術，將第一保護層8〇 移除’以曝露出複數個形成陣列式排列之導電柱9〇及部份金屬層，如第1〇 圖所不。接著，再以另一圖案化之保護層（未顯示於圖中）形成在導電柱 90及金屬層上，然後以蝕刻方式移除部份金屬層，以形成複數個圖案化之 金屬線段70，且每一金屬線段7〇之一端與每一晶粒41〇之主動面上之複數 個焊墊412電性連接，如第u圖所示。 此外，在本發明之另一實施例中，其形成複數個導電柱9〇的方式還可 以選擇在移除部份第-保護層8〇，且曝露出部份金屬層之表面之步驟後， 以電鍍(plating)的方式在曝露之金屬層的表面上形成導電柱9〇，其步驟包括： 先在部份第-保護層8〇及曝露之金制的表面上形成—晶種層㈣ layer)(未在®中表示然後再以電鍍的方式在曰3曰種層上形成導電材料層， 然後再利辭導難程技術’移畴料電材料層及晶種層；接著，剝除 第一保護層80以形成複數個導電柱％在已曝露之金屬線段7〇之表 面。在本發日种，導電柱9G之材料可以為金（Au)、銅（cu)或是銅合金 等。200921810 IX. Description of the Invention: [Technical Field] The present invention relates to a method of packaging a die re-arrangement, and more particularly to a method of fabricating a metal bump in a package structure for die re-arrangement. [Prior Art] The technology of semiconductors has been developed quite rapidly, so the miniaturized semiconductor die (Dice) must have a variety of functional requirements, so that the semiconductor die must be configured with more inputs in a small area. / Output pads (I/O pads), thus increasing the density of metal pins. Therefore, the early lead frame packaging technology is not suitable for high-density metal pins; therefore, a ball grid array (BGA) packaging technology has been developed. In addition to the higher density than the lead frame package, the ball array package has the advantages of higher density than the lead frame package. Its tin ball is also less susceptible to damage and deformation. With the popularity of 3C products such as cell phon, personal digital assistant (pDA) or iPod, many complex system chips must be placed in a very small space, so For this problem, a packaging technology called "wafer-level package (Waferlevdpaekage; Wij)" has been developed, which can package a wafer before cutting the wafer into individual dies. This "wafer level packaging" technology is disclosed in U.S. Patent No. 5,323,051. However, this "wafer-level packaging" technology increases the number of pads between the pads on the active side of the die, in addition to causing problems such as shouting or signal interference. Because the pitch of the pad is too small, the reliability of the package is lowered. Therefore, when the die is further reduced, the aforementioned packaging technology cannot be satisfied. In order to solve this problem, U.S. Patent No. 7,196,4G8 has disclosed a wafer which will be completed in a semiconductor process, and after testing and cutting, the test result is a good grain. On top of the substrate' and then encapsulation process, so that these repositioned wafers have a wider separation, so the pads on the die can be properly distributed, for example using the horizontal extension (fan) technology Therefore, it can effectively solve the problem that the spacing is too small, in addition to the conduction or signal interference caused by the 5 200921810. ▲However, the lack of semiconductor wafers can make the wafers thinner and thinner before the wafer is cut. For example, the wafers are thinned to 2 by backside lapping. ~2GmH, and then cut a die of crystal. This—the thinned crystal grains are reconfigured on another substrate, and then a plurality of crystals are formed into a colloid by injection molding; since the crystal grains are thin, the sealing body is also very thin, so when sealing After the colloid is separated from the substrate, the stress of the sealant itself causes the sealant to be reduced, which increases the difficulty of subsequent processing. In addition, after the rounding of the seven-knife cut, the re-disposal on the other substrate is taken, because the size of the new substrate = the original size is large, so in the subsequent ball-making process, the reliability of the package structure cannot be aligned. . To this end, the present invention provides a problem of forming an alignment mark on the back surface of the wafer before wafer dicing (alignment), which can effectively solve the problem of misalignment and warpage of the sealant when the ball is implanted. During the entire packaging process, when the ball is implanted, the manufacturing equipment will locally generate excessive pressure on the crystal grains, which may damage the crystal grains. At the same time, it may also be caused by the material of the ball. The resistance value between the mats affects the performance of the crystal grains, etc. [Summary of the Invention] The main purpose of the present invention is to provide the problem of the damage of the crystal grains and the cracking of the crystal grains. A packaging method for reconfiguring a die is to form a wire segment on a pad on a die before forming a ball, and forming a conductive post as a buffer, electrically connected by a conductive pillar The conductive component and the metal wire segment can reduce the damage of the ball to the die by the conductive pillar, so that the manufacturing yield and reliability can be effectively improved. Another main object of the present invention is to provide a package in the die reconfiguration. The method is to select the appropriate conductive material into the conductive column in the ball-planting process, so that the resistance value between the material and the material-welding can be reduced, so that the performance of the grain can be effectively improved. 200921810 In addition, the present invention has the main purpose. Providing a method for encapsulating a die re-arrangement, which can reconfigure the die of the 12-crystal wafer on the substrate of the 8) wafer, so that the package device of the 8-pair wafer can be effectively utilized. Without the need to re-establish 12 pairs of wafer equipment, the packaging cost of 12-inch wafers can be reduced. A further object of the present invention is to provide a package method for re-disposing a crystal grain so that the wafer to be packaged is a "known as a functioning wafer, (Kn_gQQd (4), which can save packaging materials, and thus can also reduce the process. According to the above, the present invention discloses a method for packaging a crystal grain re-arrangement, comprising: providing a substrate having an upper surface and a lower surface, and an adhesive layer disposed on the upper surface; providing a plurality of crystal grains having - a silk surface and a back surface, a reflow soldering pad is disposed on the active surface; and a plurality of crystal grains are taken and placed, and the active surface of each of the crystal grains is placed on the adhesive layer of the substrate in a flip chip manner; The molecular material layer is on the surface of the substrate and a part of the crystal grain; a mold device is provided for flattening the polymer material (4), so that the polymer material layer is filled between the plurality of crystal grains; And coating each of the grains; stripping the substrate to expose a plurality of solder bumps on the active surface of the plurality of crystal grains; forming a metal layer to cover the plurality of M1 pads on the active surface of the plurality of crystal grains; forming ―第— The protective layer is formed on the metal layer and exposes a surface of a portion of the metal layer; forming a plurality of conductive pillars is formed by exposing the conductive material to the exposed portion of the metal layer; The layer exposes a plurality of conductive pillars and a portion of the metal layer; forming a second patterning = protective layer over the plurality of metal layers and exposing a portion of the metal layer; shifting the exposed metal layer to form a plurality of layers The patterned metal line segment, wherein the end of the patterned metal line segment is electrically connected to the plurality of pads of each active surface of the die, and the other end is electrically connected with the plurality of conductive wires; forming __ Hua Baolan, feeding the complex side case = the line segment, and exposing the "surface" of the complex number of electric poles as the conductive end point; forming a complex conductive reading, the system of scales and rowing in the financial system Forming an electrical connection on the surface; and cutting the crystal to complete the die of the respective components. According to the above packaging method of die reconfiguration, the present invention discloses a package structure of the die reconfiguration 200921810. Including: a die 'an active surface Configuring a plurality of pads; a plurality of patterned metal segments, one end of the plurality of patterned metal segments being electrically connected to a plurality of pads of the active faces of the die; the plurality of conductive pillars being formed in the plurality of conductive pillars a patterned metal line segment; a colloid covering the five sides of the die and exposing a plurality of patterned metal segments; a plurality of conductive posts formed on the other end of the plurality of patterned metal segments; a patterned protective layer 'package I: a plurality of patterned metal segments and exposing a plurality of conductive pillars - the surface serves as a conductive end point; and a plurality of conductive elements, the scaly The features of the present invention are described in detail below with reference to the preferred embodiments of the present invention. (For the purpose of the present invention, the structure, the chick, and its Wei-jin--(4), The details of the embodiment are as follows. [Embodiment] The present invention is directed to a method of encapsulating a crystal grain arrangement, and a method of rearranging a plurality of crystal grains on another substrate. In order to understand the present invention, detailed steps and compositions thereof will be presented in the following description. Obviously, the implementation of the present invention does not define the specific details familiar to those skilled in the art of wafer stacking. In addition, the well-known steps of the wafer mode and the detailed steps of the wafer process are not described in detail to avoid unnecessarily limiting the invention. However, for the preferred embodiment of the present invention, it will be described in detail below. In addition to these detailed descriptions, the present invention (4) can be implemented in other implementations in a simplified manner, and the scope of the present invention is not limited. The scope of the patents that follow will prevail. In modern semiconductor package sealing, a wafer that has completed the front-end process (Fr〇mEnd Process) is first thinned (ThinningPr〇cess), for example, the thickness of the wafer is polished to 2~20 miI. Then, the wafer is cut (read (four) handsome coffee) to form a grain of the grain; then, using the pick and place device (pkkajidplaee) - the grain of the film 200921810 is placed one by one on the other substrate 100 on 'as shown in Figure 1. It is apparent that the intergranular spacer regions on the substrate are larger than the crystal grains 110, and therefore, a wider pitch between the repositioned crystal grains 110 can be made, so that the pads on the crystal grains 110 can be appropriately distributed. In addition, the packaging method used in the embodiment can reconfigure the die 110 cut by the 12-inch wafer on the substrate 100 of the 8-inch wafer, so that the package device of the 8-hour wafer can be effectively utilized. Without the need to re-set up 12-inch wafer packaging equipment, the packaging cost of 12-inch wafers can be reduced. It is then emphasized that embodiments of the present invention do not limit the use of 8-pair wafer sized substrates, as long as they provide a load bearing function, such as glass, quartz, ceramic, circuit board or metal foil (metal f〇il The same can be used as the substrate of the present embodiment, and therefore the shape of the substrate is not limited. Next, please refer to FIGS. 2A and 2B for a plan view of a wafer having an alignment mark. As shown in FIG. 2A, a plurality of crystal grains 41A are formed on the upper surface of the wafer 40, and a plurality of alignment marks 402 are disposed in the xy direction of the back surface of the wafer 40. As shown in Figure 2B. As described above, when the wafer 40 is diced to form a plurality of dies 410, and the dies 41 are again disposed on the substrate one by one, since the die spacing regions between the new substrates are more than the reconfigured dies At 41 inches, the ball mount in the subsequent packaging process will not be aligned, resulting in reduced reliability of the package structure. Here, the manner of forming the alignment mark 4〇2 may be performed by a photolithography process, which is formed on the back surface of the wafer 4〇 and forms a plurality of alignment marks 402 in the xy direction, and The shape is a sign of the cross. Additionally, the manner in which alignment marks 402 are formed also includes the use of an iasermark process. Next, the dicing step of the wafer 40 is performed by cutting the wafer 40 to form a plurality of granules 410' and then reconfiguring the plurality of dies 410 in the new one using a pick and place apparatus. The substrate 2 is as shown in FIG. 3; wherein each of the crystal grains 41 has an active surface and a lower surface, and a plurality of pads 412 are disposed on the active surface. Here, the die re-disposing method is such that each of the crystal grains 41 is placed on the substrate 2 with a flip chip disposed on the upper surface of the adhesive layer 30. Next, referring to FIG. 4, a polymer material 200921810 ^ ' is formed on the substrate 20 and a portion of the die 410 and the flat polymer layer (9) is driven using the mold package 4, wherein the mold and the device 500 are Each of the crystal grains is 41 〇 back to the eight-country Wei, as shown in Figure 5, so that the polymer material layer 60 mechanical-flattened surface and filled with each grain = colloid, this high The molecular material layer 60 may be a material such as a transfer, an epoxy resin, an acrylic acid or a present butylene (BCB). Then, a process can be selectively performed on the planarized polymer material layer 6 , to make = 4 layers (four). Then, the demoulding process is carried out, and the mold device and the cured ^ knife material are separated from the 6G, and the surface of the polymer material (9) and the back surface of the plurality of crystal grains are completely removed. As shown in Fig. 6, at this time, a Z-knife (not shown) can be selectively used to form a plurality of dicing streets on the surface of the polymer material layer (9) from the depth of each of the dicing streets 602. .5~1 mil (4)), while the width of _ 602 is 5 to 25 microns. In the example, the dicing streets 6〇2 may be vertically interlaced and may serve as reference lines for actually cutting the dies. Next, the substrate 20 is separated from the polymer layer (9), for example, the substrate μ and the polymer; 6 pick up the tarpaulin (not shown in the towel), and separate the substrate 2G from the polymer material layer 60 to form a sealant. a plurality of dies 412 on the active surface of each of the dies. In this embodiment, a plurality of dicing streets 6 〇 2 are formed on the surface of the active surface of the encapsulant relative to the die 210. Therefore, when the layer of the polymer material layer 60{) is peeled off, the stress on the sealant body is removed by the area formed by the dicing streets 6〇2, so that the problem of the scale can be effectively reduced. Referring to Figures 7 through u, the steps of the steps of forming a plurality of steel segments and a plurality of conductive columns on a plurality of pads of the active faces of the plurality of grains are shown in Figure 7. Forming a metal layer 7〇 on the surface of the upper surface of the body and the surface of the plurality of crystal grains; It should be emphasized that the metal layer % may be a metal layer. Then, as shown in Fig. 8, the first protective layer 8 is formed over the metal layer 7〇, and the material of the first protective layer 8〇 may be pdyimide; Next, as shown in FIG. 9, a semiconductor process technology, such as development 200921810 and etching, is used to remove a portion of the first protective layer 80, and a patterned first protective layer 8 is formed and a portion of the metal layer is exposed. a surface; next, a plurality of conductive pillars 90 are formed on the surface of the exposed portion of the metal layer 70; then, the first protective layer 8 is removed by semiconductor processing technology to expose a plurality of Forming an array of conductive pillars 9 部份 and a portion of the metal layer, as shown in Figure 1. Then, another patterned protective layer (not shown) is formed on the conductive pillars 90 and the metal layer. Then, part of the metal layer is removed by etching to form a plurality of patterned metal line segments 70, and one end of each metal line segment 7 is electrically connected to a plurality of pads 412 on the active surface of each of the crystal grains 41〇. Sexual connection, as shown in Figure u. In addition, in another embodiment of the present invention, the manner of forming the plurality of conductive pillars 9〇 may also be selected after removing the partial first protective layer 8〇 and exposing the surface of the partial metal layer. Forming a conductive pillar 9 on the surface of the exposed metal layer by plating, the steps comprising: first forming a seed layer on the surface of the portion of the first protective layer 8 and the exposed gold layer (4) (not formed in the ® and then electroplated to form a layer of conductive material on the layer of 曰3, and then the refractory technology 'transfer material layer and seed layer; then, stripping A protective layer 80 is formed to form a plurality of conductive pillars on the surface of the exposed metal wire segment 7. In the present invention, the material of the conductive pillar 9G may be gold (Au), copper (cu) or copper alloy.
緊接著，如第丨2 _示，_成第二保護層82以覆蓋在複數個圖案 化之金屬線段7〇及複數個導電柱9〇上；接著移除部份第二保護層82以曝 露出複數個導電柱90之-表面，以作為導電端點，其中導電柱％與第二 保護層82具有相同高度，在此’移除部份第二保護層Μ鱗露出複數個 導電柱9〇之方法包括:利祕刻或是研磨，將部份的第二保護層82移除， 以曝露出複數個導電柱90之一表面。 接^，如第13圖所示，在曝露之複數個導電柱9〇之表面之上以陣列 =方=成複數，件"，例如金屬凸塊㈣—腿球 (备ball)，即可進行最後的晶粒切割以完柄裝製程 200921810 92與導電柱9〇連接時，導電柱％可以作為一緩衝，以避免製程設備直接 將作用力加在晶粒41〇之焊墊412上，因此可降低對晶粒的損傷，故 可有效提高f造之良率及可靠度。同時，也可以在猜導電元㈣之前， 選擇適當的導電材料以形成導電柱％，因此可降低導電元件％與焊塾化 間之電阻值，故可有效提晶粒410之性能。 另外’第14 ®至第15圖係表示本發明另一具體實施例，其與第圖 及第13圖之差異在於：形成第二保護層82以覆蓋複數個圖案化之金屬線段 7〇及複數個導電柱90之後’同樣利用姓刻或是研磨，以移除部份第二保護 層82以凸出第二保護層82之一表面以作為導電端點，其中第二保護層於 與導電柱92具有;同高度，如第獅。因此，可以藉由此凸出之導電 柱9〇作為複數個導電元件92之電性連接之導電端點。接著，在曝露之複數 個導電柱9〇上’以陣列排列方式形成複數個導電元件％，如第B圖所示。 由於，本實補的其他製造過程與歧之實财式_，故不娜述其過程。 在此’複數個晶粒410之主動面之複數個焊墊仍上形成複數個圖案化 之金屬線段70及複數個導電柱9〇之另一實施例係先形成複數個圖案化之金 屬線段70於該每-晶粒之主動面之複數個焊塾412上，且複數個圖案 化之金屬線段7〇之-端與每一晶粒彻之主動面之複數個焊塾化電性連 接；其中’形成複數個圖案化之金屬線段7G的方式包含:形成—金屬層在複 數個晶粒410之主動面之複數個焊墊412上；利用半導體製程，例如顯影及 _，形成-Μ化之光阻層(未在财表示)在金屬層上；侧以移除部份 金屬層’以形成複數侧案化之金屬線段7〇，且複數個圖案化之金屬線段 70之一端與每一晶粒410之主動面上的複數個焊墊412形成電性連接。形 成複數個導電柱9G ’係先形成—圖案化之保護層(未在圖中表示)在複數個圖 案化之金屬線段70上;形成一導電材料層(未在圖中表示)在_化之保護層 之上；蝕刻以移除部份導電材料層；移除圖案化之保護層，以形成複數個導 電柱90在複數個圖案化之金屬線段7〇之另一端之一表面上。之後，形成圖 12 200921810 ’、 …層 曝露出複數個導電柱9〇之—表面以做為 使複數個導電柱9〇凸出 表面以做為導電端點；或是 霜。 _統之減層82之步_與前述_在此不再番 雖然本發㈣前述之較佳實關揭露如上， 明，任何熟習相傻枯—然其並非用以限定本發 ==此本發明之專利保護範圍須視本說：附 之f触、者，在减離本發明之精神和範圍内， 之更動與潤飾，因 範圍所界定者為準 【圖式簡單說明】 第1圖係表示先前技術之示意圖； 第2Α圖，係表示於晶圓之背面配置有複數個對準標諸之俯視圖； 第2Β圖係表示根據晶圓之背面上具有複數個對準標諸之示意圖； 之^^至第13 _輯本發賊揭露之技術，♦示形成重新配置 之封裝結構之各步驟流程示意圖； 堪夕2圖係根縣翻_露之技術’表示形成晶®重新配置之封裝結 '驟錄巾移除部份保護層以使複數個導與保護層具有不相同 鬲度之示意圖；及 目彳錄據本翻所揭露之細1，係在f 14目巾所凸丨之複數個 導電柱上形成複數辦電元件之示意圖。 【主要元件符號說明】 20 基板 3〇黏著層 40 晶圓 402對準標誌 410 晶粒 412焊墊 60 高分子材料層 6〇2切割道 13 200921810 70 UBM金屬線段 80 82保護層 90 導電柱 92 100基板 110 200黏著層 保護層 導電元件 晶粒 14Next, as shown in FIG. 2, the second protective layer 82 is overlaid on the plurality of patterned metal segments 7〇 and the plurality of conductive pillars 9〇; then a portion of the second protective layer 82 is removed for exposure. The surface of the plurality of conductive pillars 90 is formed as a conductive end point, wherein the conductive pillar % has the same height as the second protective layer 82, where the portion of the second protective layer is removed to expose a plurality of conductive pillars. The method includes: removing or polishing a portion of the second protective layer 82 to expose a surface of the plurality of conductive pillars 90. Connected, as shown in Fig. 13, above the surface of the exposed plurality of conductive columns 9〇, the array = square = complex number, piece ", for example, metal bump (four) - leg ball (ball) When the final die cutting is performed to connect the handle mounting process 200921810 92 to the conductive post 9〇, the conductive pillar % can be used as a buffer to prevent the process device from directly applying the force to the pad 41 of the die 41〇, thus It can reduce damage to the crystal grains, so it can effectively improve the yield and reliability of f. At the same time, it is also possible to select a suitable conductive material to form a conductive pillar % before guessing the conductive element (4), thereby reducing the resistance value between the conductive component % and the solder bump, so that the performance of the die 410 can be effectively improved. In addition, the '14th through 15th drawings show another embodiment of the present invention, which differs from the first and the third figures in that a second protective layer 82 is formed to cover a plurality of patterned metal line segments 7 and plural. After the conductive pillars 90, the same name or engraving is used to remove a portion of the second protective layer 82 to protrude from the surface of the second protective layer 82 as a conductive end point, wherein the second protective layer is adjacent to the conductive pillar 92 has; the same height, such as the lion. Therefore, the conductive pillars 9 embossed thereby can be used as the conductive terminals of the electrical connection of the plurality of conductive members 92. Next, a plurality of conductive elements % are formed in an array arrangement on the plurality of exposed conductive pillars 9A as shown in FIG. Because the other manufacturing processes of this implementation are inconsistent with the real financial formula, the process is not mentioned. Another embodiment in which a plurality of pads of the active faces of the plurality of die 410 are still formed with a plurality of patterned metal segments 70 and a plurality of conductive pillars 9 is formed by forming a plurality of patterned metal segments 70 first. And a plurality of solder bumps 412 on each of the active faces of the die, and a plurality of soldered wires of the plurality of patterned metal segments are electrically connected to a plurality of solder bumps of each of the active faces of the die; The manner of forming a plurality of patterned metal line segments 7G includes: forming a metal layer on a plurality of pads 412 of the active faces of the plurality of die 410; using a semiconductor process, such as developing and forming, to form a deuterated light a resist layer (not shown) on the metal layer; a side to remove a portion of the metal layer 'to form a plurality of side-formed metal segments 7〇, and one of the plurality of patterned metal segments 70 and each die A plurality of pads 412 on the active surface of 410 form an electrical connection. Forming a plurality of conductive pillars 9G' is formed first-patterned protective layer (not shown) on a plurality of patterned metal line segments 70; forming a conductive material layer (not shown in the figure) Above the protective layer; etching to remove a portion of the conductive material layer; removing the patterned protective layer to form a plurality of conductive pillars 90 on one of the other ends of the plurality of patterned metal segments 7〇. Thereafter, the surface of Fig. 12 200921810' is formed, and the surface of the plurality of conductive pillars 9 is exposed as a surface of the plurality of conductive pillars 9 〇 as a conductive end; or frost. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The scope of patent protection of the invention shall be deemed to be in addition to the scope and scope of the invention, and the modifications and refinements shall be subject to the scope defined by the scope of the invention. A schematic diagram showing a prior art; a second diagram showing a top view of a plurality of alignment marks disposed on the back side of the wafer; and a second diagram showing a schematic diagram having a plurality of alignment marks on the back surface of the wafer; From ^^ to the 13th _ series of the thief revealed the technology, ♦ shows the process flow of each step of forming a reconfigured package structure; Kanxi 2 map of the root county _ _ technology of the 'represents the formation of the crystal reconfigure package junction 'Scratch towel removes part of the protective layer so that the plurality of guides and the protective layer have different degrees of twist; and the details of the item disclosed in the book are based on the number of the f 14 A schematic diagram of forming a plurality of electrical components on a conductive column. [Main component symbol description] 20 substrate 3 〇 adhesive layer 40 wafer 402 alignment mark 410 die 412 pad 60 polymer material layer 6 〇 2 dicing road 13 200921810 70 UBM metal wire segment 80 82 protective layer 90 conductive column 92 100 Substrate 110 200 adhesive layer protective layer conductive element die 14