CN216145587U - Patch packaging test structure - Google Patents

Abstract

The utility model provides a chip packaging test structure. The chip packaging test structure comprises a substrate wafer, a protective layer positioned on the surface of the substrate wafer and a conductive bump positioned on the protective layer. According to the utility model, before the conductive bump is formed on the surface of the substrate wafer, the protective layer is formed on the surface of the wafer, so that the adhesion between the conductive bump and the wafer can be enhanced, the conductive bump is prevented from falling off in subsequent cleaning and other processes, the stability of a test structure is effectively improved, and the test cost is reduced.

Description

Patch packaging test structure

Technical Field

The utility model relates to the technical field of semiconductor packaging, in particular to a chip packaging test structure.

Background

With the rapid development of semiconductor technology, the integration degree of devices is increasing, the density of interconnection structures used in the packaging process is increasing and the packaging thickness is being compressed, and some advanced packaging technologies, such as WLP (wafer level package), TSV (through silicon via), 2.5D silicon interposer package, 3D package, fan out (fan out package), and the like, are emerging in succession.

To ensure the performance of the packaged chip, electrical tests are usually performed after the die bond is completed. During the chip mounting test, a large number of conductive bumps (bump) are usually formed on the surface of the silicon substrate wafer for testing, and then the chips are soldered to the conductive bumps by using the flux and then cleaned, so as to remove the residual flux. The base wafer is typically a bare wafer without any structures prepared on the surface, i.e., a smooth monocrystalline or polycrystalline silicon layer on the surface. Due to poor adhesion between the conductive bumps and the surface of the silicon substrate wafer, the conductive bumps tend to fall off during the subsequent cleaning or stripping process of the flux, thereby causing damage to the test structure.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a chip package test structure, which is used to solve the problems that in the chip package test in the prior art, a conductive bump is directly formed on a bare wafer and a chip is flipped over on the conductive bump, and in the subsequent cleaning or peeling process, the conductive bump is easy to fall off, which causes damage to the test structure.

In order to achieve the above and other related objects, the present invention provides a test structure for a chip package, which comprises:

providing a substrate wafer, and forming a protective layer on the surface of the substrate wafer;

and forming a conductive bump on the protective layer.

Optionally, the forming method of the protective layer includes one or a combination of an oxidation method and a vapor deposition method.

Optionally, the protective layer includes one or a stack of a plurality of silicon nitride layers, silicon oxide layers, and silicon oxynitride layers.

Optionally, the protective layer has a thickness of 500nm to 5000 nm.

The utility model provides a chip packaging test structure which comprises a substrate wafer, a protective layer positioned on the surface of the substrate wafer and a conductive bump positioned on the protective layer.

Optionally, the protective layer includes one or a stack of a plurality of silicon nitride layers, silicon oxide layers, and silicon oxynitride layers.

Optionally, the protective layer has a thickness of 500nm to 5000 nm.

Optionally, the conductive bump comprises a copper pillar.

Optionally, the base wafer includes any one of a silicon wafer, a germanium wafer, and a germanium-silicon wafer.

Optionally, the number of the conductive bumps is multiple, and the multiple conductive bumps are arranged on the protective layer in an array.

Optionally, a pad is formed on the surface of the conductive bump.

Optionally, the bonding pad includes any one or more of a silver pad, an aluminum pad, and a tin pad.

Optionally, the chip package test structure further includes a chip, and the chip is flip-mounted on the conductive bump.

Optionally, the chip is flip-chip mounted on the conductive bump by a flux.

As described above, the patch package test structure of the present invention has the following beneficial effects: according to the utility model, before the conductive bump is formed on the surface of the substrate wafer, the protective layer is formed on the surface of the wafer, so that the adhesion between the conductive bump and the wafer can be enhanced, the conductive bump is prevented from falling off in subsequent cleaning and other processes, the stability of a test structure is effectively improved, and the test cost is reduced.

Drawings

Fig. 1-5 show schematic diagrams of a prior art chip package testing process.

Fig. 6-11 are schematic cross-sectional views of the test structure of the chip package according to the present invention in various steps during the manufacturing process.

Description of the element reference numerals

11, 21 substrate wafer

12 protective layer

13, 23 conductive bump

14, 24 chips

141 conductive pin

15, 25 flux

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The utility model is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated. In order to keep the drawings as concise as possible, not all features of a single figure may be labeled in their entirety.

To ensure the performance of the packaged chip, a chip package test is generally performed after the chip is soldered to a package substrate to test the electrical performance of the chip. A conventional process of a chip package test is shown in fig. 1-5, and includes providing a substrate wafer 21 (see fig. 1), preparing a plurality of conductive bumps 23 (see fig. 2) on the test wafer 21, dispensing a flux 25 (see fig. 3) on the surfaces of pins of a chip 24 to be tested, soldering the chip 24 onto the conductive bumps 23 in a manner that the pins face the conductive bumps 23 (i.e., flip chip bonding), obtaining a structure shown in fig. 4, and cleaning (flux clean) after soldering to avoid the chip performance being affected by chip contamination caused by residual flux, for example, avoiding the problems of electrical insulation performance degradation and short circuit of the chip caused by the flux, and performing an electrical performance test of the chip after cleaning. Since the test wafer used in the prior art is usually a bare silicon wafer without any device structure (including any film layer) prepared on the surface, the formed conductive bump has poor adhesion on the surface of the bare silicon wafer, and is easy to fall off in the cleaning process (refer to the area a marked by the dashed circle in fig. 5), so that the die attach test structure is damaged and the performance of the chip cannot be normally tested. Therefore, the utility model provides an improvement scheme through long-term research.

Specifically, the utility model provides a chip packaging test structure, and a preparation method thereof, wherein the preparation method comprises the following steps:

providing a substrate wafer 11, and forming a protective layer 12 on the surface of the substrate wafer 11, wherein the protective layer 12 can reduce the stress between the subsequently prepared conductive bump 13 and the substrate wafer 11, improve the adhesive force of the conductive bump 13 on the surface of the substrate wafer 11, and prevent the conductive bump 13 from falling off in the subsequent cleaning process, thereby improving the stability of the chip package test structure; the substrate wafer 11 is preferably a bare wafer without any device structure on the surface, and particularly, a dummy wafer (dummy wafer) for testing, which is commonly used in a semiconductor factory, is used, and the material of the bare wafer may be silicon, germanium or germanium-silicon, preferably, a silicon wafer, and the structure of the bare wafer may be as shown in fig. 6; the protective layer 12 is preferably an insulating layer to reduce the influence on the subsequent electrical test, such as the protective layer 12 including but not limited to one or a stack of multiple silicon nitride, silicon oxide and silicon oxynitride layers, and formed by one or a combination of but not limited to oxidation and vapor deposition; more specifically, in an example, the base wafer 11 is a bare silicon wafer, and a silicon oxide layer may be formed on a surface of the bare silicon wafer as the protection layer 12 by a thermal oxidation method and/or a vapor deposition method; in another example, a thermal oxidation method may be used to form a silicon oxide layer on the surface of the bare silicon wafer, and then a vapor deposition method is used to form a silicon nitride or silicon oxynitride layer on the surface of the silicon oxide layer to obtain a composite film layer, which is helpful to avoid damage to the substrate wafer 11 during the test process, thereby realizing cyclic utilization of the substrate wafer 11; the thickness of the protective layer 12 is preferably 500nm to 5000nm (inclusive, unless otherwise specified, inclusive when describing numerical ranges in this specification), such as 500nm, 1000nm, 1500nm, 2000nm, etc., and the structure after forming the protective layer 12 is shown in fig. 7; after the protective layer 12 is formed, high temperature annealing may be performed to reduce lattice mismatch between the protective layer 12 and the base wafer 11;

forming a conductive bump 13 on the protection layer 12; specifically, the method for forming the conductive bump 13 is preferably a sputtering method, the formed conductive bump 13 may be a copper pillar, an aluminum pillar, a silver pillar or a combination of various metal pillars, and the conductive bump 13 is preferably a cylindrical bump, and the conductive bumps 13 are usually multiple, and the multiple conductive bumps 13 are usually arranged in an array to correspond to the multiple chips 14, and the structure obtained after this step is as shown in fig. 8. Of course, in other examples, the conductive bump 13 may be formed by transferring and fixing a prepared conductive pillar onto the protective layer 12, but preferably, the conductive bump 13 is formed by a sputtering method, so that a desired structure can be flexibly formed according to test requirements, and the adhesion between the conductive bump 13 and the substrate can be further improved.

To facilitate the soldering of the chip 14, by way of example, a bonding pad (not shown) may be formed on the conductive bump 13, and the bonding pad includes, but is not limited to, a silver pad, an aluminum pad, a tin pad, or a combination of multiple bonding pads, or a groove (not shown) may be formed on the surface of the conductive bump 13 by etching back the conductive bump 13 after the conductive bump 13 is formed, and the bonding pad may be formed on the inner surface of the groove, which may help to improve the stability of the subsequent test structure. The height of the conductive bump 13 may not be too high or too small, preferably 3000nm to 8000 nm.

According to the utility model, before the conductive bump 13 is formed on the surface of the substrate wafer 11, the protective layer 12 is formed on the surface of the wafer, so that the adhesion between the conductive bump 13 and the wafer can be enhanced, the conductive bump 13 is prevented from falling off in subsequent cleaning and other processes, the stability of the test structure is effectively improved, the cyclic utilization of the test structure can be realized, and the test cost is reduced.

As shown in fig. 8, the chip package test structure provided by the present invention includes a substrate wafer 11, a protection layer 12 located on the surface of the substrate wafer 11, and a conductive bump 13 located on the protection layer 12. The base wafer 11 is preferably a bare wafer without any structures fabricated on the surface, including but not limited to silicon wafers, germanium-silicon wafers, SOI substrates, and the like. The protective layer 12 includes, but is not limited to, a stack of one or more of silicon oxide layers and silicon nitride layers, and preferably has a thickness of 500nm to 5000 nm. The conductive bumps 13 are usually multiple, and the multiple conductive bumps 13 may be arranged in an array, so that the chip packaging test can be performed simultaneously in combination with the chip packaging test of the multiple chips 14. The conductive bump 13 includes, but is not limited to, any one or more of a copper pillar, a silver pillar, an aluminum pillar, or other metal pillar, the surface of the conductive bump 13 may be formed with a bonding pad including, but not limited to, a combination of one or more of a silver pad, an aluminum pad, and a tin pad, and the surface of the conductive bump 13 may also be formed with a groove to facilitate bonding between subsequent chips 14 to be tested, such as avoiding flux 15 flowing out to the surface of the conductive bump 13 and/or the chip 14 during subsequent die bonding (die bond). The chip packaging test structure can further comprise a plurality of chips which are arranged on the conductive bumps 13 in an inverted mode and electrically connected with the conductive bumps 13 so as to test the chips, the chips are spaced from one another, and the chips can be arranged on the conductive bumps 13 in an inverted mode through soldering flux.

As an example, the method for testing the chip package according to the chip package testing structure of the present invention includes the steps of:

providing a substrate wafer 11, forming a protective layer 12 on the surface of the substrate wafer 11, wherein the protective layer 12 can reduce stress between a subsequently prepared conductive bump 13 and the substrate wafer 11, improve the adhesive force of the conductive bump 13 on the surface of the substrate wafer 11, and prevent the conductive bump 13 from falling off in the subsequent cleaning process, so as to improve the stability of the chip package test structure; the substrate wafer 11 is preferably a bare wafer without any device structure on the surface, and particularly, a dummy wafer (dummy wafer) for testing, which is commonly used in a semiconductor factory, is used, and the material of the bare wafer may be silicon, germanium or germanium-silicon, preferably, a silicon wafer, and the structure of the bare wafer may be as shown in fig. 6; the protective layer 12 is preferably an insulating layer to reduce the influence on the subsequent electrical test, such as the protective layer 12 including but not limited to one or a stack of multiple silicon nitride, silicon oxide and silicon oxynitride layers, and formed by one or a combination of but not limited to oxidation and vapor deposition; more specifically, in an example, the base wafer 11 is a bare silicon wafer, and a silicon oxide layer may be formed on a surface of the bare silicon wafer as the protective layer 12 by using a thermal oxidation method and/or a vapor deposition method, or in other examples, a silicon oxide layer may be formed on a surface of the bare silicon wafer by using a thermal oxidation method first, and then a silicon nitride layer or a silicon oxynitride layer is formed on a surface of the silicon oxide layer by using a vapor deposition method to obtain a composite film layer, which is helpful for avoiding damage to the base wafer 11 during a test process and realizing cyclic utilization of the base wafer 11; the thickness of the protective layer 12 is preferably 500nm to 5000nm (inclusive, unless otherwise specified, inclusive when describing numerical ranges in this specification), such as 500nm, 1000nm, 1500nm, 2000nm, etc., and the structure after forming the protective layer 12 is shown in fig. 7; after the protective layer 12 is formed, high-temperature annealing can be carried out to eliminate the stress between the protective layer 12 and the substrate wafer 11;

forming a conductive bump 13 on the surface of the protection layer 12; specifically, the method for forming the conductive bump 13 is preferably a sputtering method, the formed conductive bump 13 may be a copper pillar, an aluminum pillar, a silver pillar or a combination of multiple metal pillars, and the conductive bump 13 is preferably a cylindrical bump, and the conductive bumps 13 are usually multiple, the multiple conductive bumps 13 are usually arranged in an array to correspond to the multiple chips 14, and the structure obtained after this step is as shown in fig. 8;

inversely installing a single chip or a plurality of chips 14 to be tested on the surface of the conductive bump 13 through a flux 15(flux) to obtain a test structure; specifically, the flux 15 may be an organic or inorganic material having a melting point lower than that of the conductive bumps 13, such as a rosin resin-based flux 15 composed of rosin, a resin, an active agent containing halide, an additive and an organic solvent, the flux 15 may be applied to the surfaces of the conductive pins 141 of the chip 14 by a dispensing process (e.g., die dispensing), the flux 15 may be dispensed on the surfaces of the conductive bumps 13, or the flux 15 may be simultaneously dispensed on the surfaces of the conductive bumps 13 and the conductive pins 141 of the chip 14, and then the chip 14 is soldered to the substrate wafer 11 by way of the conductive pins 141 (i.e., flip chip) in a manner as shown in fig. 9, and the structure obtained after flip chip soldering is shown in fig. 10;

in the flip-chip bonding process, the flux 15 easily flows to the surfaces of the conductive bumps 13 and/or the chips 14, so that the chips 14 are contaminated and/or the different conductive pins 141 are adhered to cause problems of reduction in electrical insulation performance and short circuit of the chips 14, and the like, therefore, after the flip-chip bonding process, the test structure is usually cleaned, for example, by using a stripping liquid to remove the residual flux 15, the obtained structure is shown in fig. 11, and then the cleaned package structure is dried to be tested, and after the test is completed, the chips can be stripped. Since the passivation layer 12 is formed on the surface of the substrate wafer 11 in advance, the conductive bumps 13 can be more firmly attached to the surface of the substrate wafer 11, so that the conductive bumps 13 will not fall off from the surface of the substrate wafer 11 in the step of cleaning the flux 15, and the subsequent test can be successfully completed.

In summary, the present invention provides a test structure for chip package. The chip packaging test structure comprises a substrate wafer, a protective layer positioned on the surface of the substrate wafer and a conductive bump positioned on the protective layer. According to the utility model, before the conductive bump is formed on the surface of the substrate wafer, the protective layer is formed on the surface of the wafer, so that the adhesion between the conductive bump and the wafer can be enhanced, the conductive bump is prevented from falling off in subsequent cleaning and other processes, the stability of a test structure is effectively improved, and the test cost is reduced. Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the utility model. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A chip packaging test structure is characterized by comprising a substrate wafer, a protective layer and a conductive bump, wherein the protective layer is located on the surface of the substrate wafer, the conductive bump is located on the protective layer, the protective layer is an insulating layer, and a groove is formed in the conductive bump.

2. The chip package test structure according to claim 1, wherein the protective layer comprises one or more of a silicon nitride layer, a silicon oxide layer and a silicon oxynitride layer stacked on top of each other.

3. The chip package test structure according to claim 1, wherein the protective layer has a thickness of 500nm to 5000 nm.

4. The chip package test structure according to claim 1, wherein the conductive bumps comprise copper pillars.

5. The chip package test structure according to claim 1, wherein the base wafer comprises any one of a silicon wafer, a germanium-silicon wafer, and an SOI wafer.

6. The chip package test structure according to claim 1, wherein the conductive bumps are a plurality of bumps, and the plurality of bumps are arranged on the protection layer in an array.

7. The chip package test structure as recited in claim 1, wherein the conductive bumps have pads formed on a surface thereof.

8. The chip package test structure according to claim 7, wherein the bonding pad comprises any one or more of a silver pad, an aluminum pad and a tin pad.

9. A chip package test structure according to any one of claims 1 to 8, further comprising a chip, wherein the chip is flip-chip mounted on the conductive bump.

10. The chip package test structure of claim 9, wherein the chip is flip-chip mounted on the conductive bump by a flux.

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