1352411 2011年6月30日修正替換頁 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體之封裝方法，特別是有關於一種研磨 式之晶粒重新配置之封裝方法。 【先前技術】 半導體的技術已經發展的相當的迅速，因此微型化的半導體晶粒 (Dice)必須具有多樣化的功能的需求，使得半導體晶粒必須要在很小的 區域中配置更多的輸入/輸出墊(I/0 pads)，因而使得金屬接腳②^^的 密度也快速的提高了。因此，早期的導線架封裝技術已經不適合高密 度之金屬接腳；故發展出一種球陣列(Ball Grid Array: BGA)的封裝技 術，球陣列封裝除了有比導線架封裝更高密度之優點外，其錫球也比 較不容易損害與變形。 隨著3C產品的流行，例如q于動電話（Cdl ph〇ne)、個人數位助 理（PDA)妓iPod f ’都必須要將許多複雜的系統晶片放入一個非 ¥小的空射’因此為解決此—問題，一種稱為「晶圓級封裝（w晚r level package ; WLP)」之封裝技術已經發展出來，其可以在切割晶圓 成為一顆顆的晶粒之前，就先對晶圓進行封裝。美國專利公告第 5,323,051號專利即揭露了這種「晶圓級封裝」技術。然而，這種「晶 圓級封裝」技術隨著晶粒主動面上的焊塾(pads)數目的增加，使得焊塾 (pads)之間距過小，除了會導致織齡或訊號干擾的問題外也會因 為焊塾間距過小而造朗裝之可靠度降低等問題，此當晶粒再更 進一步的縮小後，使得前述的封裝技術都無法滿足。 為解決此-問題，美國專利公告第7,i%，4〇8號已揭露了一種將完 成半導體製程之晶圓’經·試及切織，制試結果為良好的晶= (good㈣重新放置於另一個基板之上，然後再進行封裝製程，如此， 1352411 2011年6月3〇日修正替換頁 使得這些被重新放置的晶粒間具有較寬的間距，故可以將晶粒上的焊 墊適當的分配，例如使用向外延伸（fan〇m)技術，因此可以有效解決 因間距過小，除了會導致訊號耦合或訊號干擾的問題。 然而，為使半導體晶片能夠有較小及較薄的封裝結構，在進行晶 圓切割前’會先對晶圓進行薄化處理，例如以背磨（backsideia_g) 方式將晶®薄化至2〜2_ ’織再_成—願的晶粒。此—經過薄 化處理之晶粒’經過重新配置在另—基板上，再以注模方式將複數個 晶粒形成-封裝體；由於晶粒㈣’使得封裝體也是非常的薄，故當 封裝體脫離基板之後，封裝體本身的應力會使得封裝體產生勉曲，增 加後續進行切割製程的困難。 另外’在晶圓切割之後，重新配置在另一個基板時，由於新的基 板的尺寸較原來的尺寸為大’因此在後續植球製程t，會無法對準， 其封裝結構可靠度降低4此，本發明提供—種在進行晶圓切割之前， 在B曰圓背©域解標獅ig_t _)其可以有效轉決植球時益 法對準以及封裝财生祕關& '··、 此外，在整個封裝的過程中，還會產生植 粒產生局部過大_力，而可能損傷晶粒的問題；同時 ㈣造额的焊㈣之電大，时池$粒之性^ 【發明内容】 明提中所述之植球對準以及封裝體勉曲的問題，本發 服供種利用晶圓對準標誌之晶粒 =數物㈣細㈣法。目 行晶粒二：園切割之前先形成對準標訪，然後藉由對準觀進 ， 置之封裝方法，使得在植球之製針可以對準之外，封 萝驴太鱼-r、，士 2011年6月30曰修正替換頁 : ”克職力而會使得封裝H在麟絲後，轉平整，可 有效提高製造之良率及可靠度。 t發明之另—主要目的在提供—種在晶粒重新配置之封裝方法， 糸將藉由研磨的方式薄化晶粒之封裝體厚度之晶粒重新 上之封裝妓。 ^卜’本發嗎有—主要目的在提供—種晶粒重新配置之封裝方 、、’、可以將12忖晶圓所切割出來的晶粒重新配置於8忖晶圓之基板 如此可以有效運用8对晶圓之即有之封裝設備而無需重新設立 12时晶圓之封裝設備，可崎低12咐圓之封裝成本。 …本發月之再—主要目的在提供—種晶粒重新配置之封裝方法，使 付進=封裂的晶片都是”已知是功能正常之晶片，，㈤麵⑽出e)， 可以即省封裝材料，故也可崎低製程之成本 π本發Θ之再-主要目的在提供—種晶粒重新配置之封裝方法，使 得進二封裝的晶片都是，，已知是功能正常之晶片，，㈤麵㈣d⑹， 可以節省封裝材料’故也可以降低f程之成本。 曰根據以上所述’本剌揭露一種晶粒重新配置之封裝方法，包括: 提，日日圓’具有一上表面及一背面，且晶圓上配置有複數個晶粒及 於Γ圓之上表面配置有—第—高分子材料層；蝴晶圓，以形成複數 個曰a粒且於每-晶粒之—主動面上覆蓋第__高分子材料層；取放複數 個曰曰粒至金屬基板上，係將複數個晶粒之一背面與一配置於金屬基 板上的黏著層連接；形成—第二高分子材料層於金屬基板及複數個晶 粒之主動面之第—高分子材料層上；覆蓋-模具裝置至第二高分子材 料層上，以平坦化該第=高分子材料層，使第二高分子材料層充滿於 複數個aa粒之間並環覆每一晶粒以形成一封裝體；脫離模具裝置，以 曝露出封裝體之—表面；薄化封裝體，以使每—晶粒之主動面上之第 1352411 2〇11年6月3〇曰修正替換頁 一高分子材料層曝露；形成—圖案化之第—高分子材料層以曝露出每 -晶粒之主動面上之複數個焊塾；形成圖案化之第三高分子材料層在 每-晶粒及部份封裝體之__表面上，且曝露出每—晶粒之該主動面上 之複數個焊塾；形成複數個圖案化之金屬線段，每—圖案化之金屬線 段之-端與每-晶粒之絲面上之複數個焊塾電性連接，每—圖案化 ，金屬線段具有向每-晶粒之主動面賴延伸之—扇出結構覆蓋部份 第三高分子材料層上；形成—圖案化之保護層，以覆蓋複數個圖案化 之金屬線段’麟露出槪侧案化之金麟段之向H粒之主動 面之外側延伸之扇出結構之部份表面；形成複數個導電元件，係將複 數個導電it件電性連接至複數個圖案化之金屬線段之已曝露之扇出結 構之部份表面：及切贿裝體以形成複數個具有金屬基板且各自獨立 之完成封裝之晶粒。 本發明還揭露-種晶粒重新配置之封裝結構，包括:―晶粒，其一 主動面上配置有複數個焊墊及—高分子材料層且曝露出複數個焊塾， 且於日曰粒之彳面具有一金屬基板；一封裝體，係環覆於晶粒之四個 面以曝路出晶粒之主動面及—下表面；複數個醜化之金屬線段，其 -端與晶粒之主動面上的複數個焊魏性連接，其另—端則以扇出的 方式延伸並覆胁高分幾4層上；—_化之髓層，係覆蓋於複 ^個圖案化之金屬線段且曝露域數侧案化之金屬線段之向複數個 曰曰粒之主動面外側延伸之_扇出結構之部份表面；及複數個導電元 件’係電性連接至複數侧案化之金屬線段之已曝露之U結構之部 份表面上。 有關本發_概與實作，_合_作最佳實施觸細說明如 I。（級對本發明的目的、構造、特徵、及其功能有進-步的瞭解， 兹配合貫施例詳細說明如下。） 8 1352411 r _ 201丨年6月30曰修正替換頁 【實施方式】 本發明在此所探討的方向為—㈣粒重新配置之封裝方法，將複 數個晶粒重新配置於另-基板上’紐利用薄化封裝體之厚度以縮小 封裝結構之封裝的方法。為了驗底地瞭解本發明，將在下列的描述 中提出詳盡的步驟及其組^顯,魏，本發_施行並未蚊晶片堆 疊的方式之技藝者所熟習的特殊細節n面，眾所周知的晶片形 成方式以及晶片薄化等後段製程之^細步驟並未描述於細節中，以避 免造成本發明不必要之聞細，對於本發明的較佳實施例，則會 詳細描述如下’然而除了這些詳細描述之外，本發明射以廣泛地施 行在其他的實施财，且本發_範圍不受限定，其以之後的專利範 圍為準。 在現代的半導體封裝製程中，均是將一個已經完成前段製程（F_ End Process)之晶圓（wafer)先進行薄化處理（ThinningPr〇cess)，例 如將晶片的厚度研磨至2〜20 mil之間；然後，進行晶圓的切割（sawing process )以形成一顆顆的晶粒丨丨〇;然後，使用取放裝置（扭伙咖咖ce ) 將一顆顆的晶粒逐一放置於另一個基板100上，如第丨圖所示。很明 顯地，基板100上的晶粒間隔區域比晶粒11〇大，因此，可以使得這些 被重新放置的晶粒110間具有較寬的間距，故可以將晶粒11〇上的焊墊 適當的分配。此外，本實施例所使用的封裝方法，可以將12吋晶圓所 切割出來的晶粒110重新配置於8吋晶圓之基板上，如此可以有效運用 8吋晶圓之即有之封裝設備，而無需重新設立12吋晶圓之封裝設備， 可以降低12吋晶圓之封裝成本。然後要強調的是，本發明之實施例並 未限定使用8吋晶圓大小之基板，其只要能提供承載的功能者，例如： 玻璃、石英 '陶竟、電路板或金層薄板（metal foil)等，均可作為本實 施例之基板，因此基板的形狀也未加以限制。 首先，第2圖，係表示在晶圓之上表面具有一高分子材料層之截 1352411 2011年6月30日修正替換頁 面示意圖。如第2圖所示，係表示在晶圓20的上表面配置有複數個晶 粒210，且在晶圓20的每一個晶粒210的主動面上形成高分子材料層 310,例如光阻層；接著，使用取放裝置（未於圖中顯示）將每一顆晶 粒210吸起並將晶粒210之主動面朝上放置在配置有黏著層之另一基 板40上。 接下來，參考第3圖，於基板40及複數個晶粒21〇之第一高分子 材料層310上塗佈第二高分子材料層6〇，例如聚亞醯胺， 並且使用一模具裝置500將第二高分子材料層6〇壓平，使得第二高分 子材料層60形成-平坦化的表面，並幻吏得第二高分子材料層6〇填 滿於晶粒210之間並且每一顆晶粒21〇的五個面均由第二高分子材料 層60所包覆。 然後’可以選擇性地對平坦化的第二高分子材料層6〇進行一洪烤 程序，以使第三高分子材料層60固化。再接著，進行脫模程序，將模 具裝置5GG與後的第二高分子材· 6G分離，輯露出平坦化的 第二高分子材料層60的表面，如第4圖所示。 接著’如第5圖所示，係薄化第二高分子材料層6〇，以曝露出每 =晶粒210之主動面上的第—高分子材料層31()的表面：在此，薄化 第二高分子材料層6G的方式包括：以配置在每_晶粒加之主動面上 之第-高分子材料層310為終止層，研磨第二高分子材料層⑻直至曝 露出第-高分子材料層31〇的表面。藉由薄化第二高分子材料層的之 厚度可以縮小之後形成的封裝結構的厚度。 接著’同樣參考第5圓，將第二高分子材料層6〇與黏著層5〇分離， 其方法例如將$二高分子材觸6〇錄板4G _域人具有去離子水 的槽中’使得第二高分子材料層60與黏著層5〇分離以形成一 裝體U匕封裝體包覆每—顆晶粒21_四個面，且曝露出每一晶粒2⑴ 之主動面上的第-高分子材料層31〇之表面。然後，使用切割刀（未 10 13.52411 , x 201丨年6月30日修正替換頁 顯不於圖中）在相對於每-晶粒21〇之主動面之背面的第二高分子材 料層6二的表面上’械複數條蝴道_ ;每—蝴道⑽的深度為 〇·5〜1密爾（mil)，而切割道⑽之寬度則為5至25微米。在—較佳的 實施例中，此切割道⑽可以是相互垂直交錯’並且可以作為實際切 割晶粒時的參考線。由於封裝體之相對於晶粒2⑴之主動面之背面上 有複數條_道因此，t第二高分子娜f 6()絲板*剝離後， 封裝體上的應力會被這些_道⑽所形成的區域所減故可有效 地解決封裝體趣曲的問題。 曰接著’參考第6目，係表示形成圖案化之第一高分子材層在每一 曰曰粒之主動面上’歸露出每—晶粒之主動面上之複數個焊塾之示意 圖。在此’係利用半導體製程，例如顯影及蝕刻，首先，在第一高分 ^材料層310上形成一圖案化之光阻層(未在圖中表示）；钮刻以移除部 ^第一高分子材料層310，以曝露出每一晶粒210之主動面上之複數個 焊墊212 ;及移除圖案化之光阻層以曝露出每一晶粒210之主動面上之 複數個焊墊212。 接著，參考第7冑’表示在每一晶粒及部份封裝體之表面上形成 圖案化之第分子材料層，並曝露出每—晶粒之焊墊之示意圖。在 此，係先在每一晶粒210及部份封裝體之表面形成一層第三高分子材 料層320 ’例如，聚亞醯胺（p〇lyimide);接著，利用半導體製程，例 如顯影及侧，在第三高分子材料層挪上形成—圖案化之光阻層(未 在圖中表示），钱刻以移除部份第三高分子材料層以形成多數個孔洞 322且曝硌出母一晶粒21〇之主動面上之複數個焊塾212 ;移除圖案 化之光阻層。 接著，參考第8圖，表示形成複數個圖案化之金屬線段7〇在每一 晶粒210之主動面上之複數個焊墊212上。每一條金屬線段7〇之向外 11 1352411 2011年6月30日修正替換頁 延伸之扇出結構之一端係電性連接每一晶粒21〇上之焊墊212 ;其中， 形成複數個隨化之金屬線段之步驟包含:首先，係先利用餅 (sputtering)形成一晶種層(seed layer)(未在圖_表示)在部份第三高分^ 材料層320及複數個孔洞322之表面以覆蓋每一晶粒21〇之主動面之 複數個焊墊212 ;利用電鍵的方式形成一金屬層(未在圖中表示)於晶種 層上；接下來，利用半導體製程技術，利如顯影及_，首先，形成 -圖案化之光峨未在圖巾表示)在金屬層之上；侧以移除部份金屬 層，以形成複數個圖案化之金屬線段7〇 ;以及剝除圖案化之光阻層。 其中每- Μ化之金屬線段7G之—端係電性連接至每—晶粒2ι〇上之 複數個 212 ’如第9圖所示4金屬線段7G可岐刪金屬層， 其材料可以是Ti/Cu或是TiW/Cu。 接者，如第10圖所示，形成一圖案化之保護層8〇以覆蓋複數個 圖案化之金屬線段7〇，鱗露出複數個_化之金屬線段％之向晶粒 21〇之主動面之外側延伸之—端之部份表面；其中，形成圖案化之保護 』的步驟包括:形成一保護層(未在圖中表示)在複數個圖案化之金屬 線&7〇上，侧半導鮮程’例域影及侧，先形成—圖案化之光 7層(未在圖中表示)在保護層上；接著，働對於複數個醉 1金屬線段7〇之向晶粒⑽之主動面之外側延伸之—端上之部份保 遵層，以曝露出數個圖案化之金屬線段7〇之向晶粒21〇之主動面之外 側延伸之-端之部絲面上；及剝_案化之光阻層。 ^著’如第U圖所示，形成複數個導電元件9〇，係電性連如 二路之每—圖案化之金屬線段7〇之向晶粒训之主動面之外側㈣ =之部份表面上；以及切割封裝體，以形成複數個各自獨立之$ 粒，如第12_示。其中輪件9g可以是錫球_㈣ 或疋金屬凸塊(metal bump)e 12 1352411 .—L 2011年6月30日修正替換苜 之辟方I關巾其基板4G可叹金屬紐，目此在晶粒重新配置 金=0=中，可以不用脫離基板40，在整個封裝製程中保留 土 金屬基板40可以做為散熱基板，用以增加完成封果 之晶粒210的散熱效率，如第 兀賊裝 黏著層5〇可以是導電夥；此外=不，且配置於金屬基板40上之 步成封BS a重新配置於新的基板4G上以及 I成封裝辭各錢麵均鱗述蝴，在料再資述。 另外，如第14圖所示，係可以在每一個獨立 的背面形成-散熱裝置94，例如鍵 成封裝之阳粒210 94之Η爭勺人“ "片（fη) ’且在日日粒21〇與散熱裝置 面更包3一導電勝92 ’用以將散熱裝置94固定在晶粒210的背 雖然本發_前述之健實齡鴻露如上， 作些許之更動與潤飾，因此本發 姻内田了 之申請專利所界定者為[本·書所附 【圖式簡單說明】 第1圖係表示先前技術之示意圖； 第2 _娜本㈣所财之猶，縣轉 -高分子難層之截面示意圖； 1«之上表面具有 第3圖至第U _根據本發明所揭露之技 =準標⑽重新-之封裝方法所形成之:= 意圖第广根據本發明所揭露之技術，係表示完成封裝之晶粒之示 13 1352411 第13圖係根據本發明所揭露之技術， 面具有金屬基板之示意圖；及 第14圖係根據本發明所揭露之技術， 面具有散熱裝置之示意圖。 【主要元件符號說明】 100基板 110晶粒 20晶圓 210晶粒 212焊墊 31〇第一高分子材料層 320第三高分子材料層 322孔洞 4〇基板 50黏著層 60第二高分子材料層 610切割道 7〇金屬線段 80保護層 90導電元件 92導電膠 94散熱裝置 500模具裝置 2〇11 ^ fa 係声；八 Θ30曰修正替換頁 表不完成封装之晶粒之背 係表示完成封裝之晶粒之背1352411 Corrective Replacement Page, June 30, 2011 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor packaging method, and more particularly to a method of encapsulating a polished crystal grain reconfiguration. [Prior Art] The technology of semiconductors has been developed quite rapidly, so the miniaturized semiconductor die (Dice) must have a variety of functional requirements, so that the semiconductor die must be configured with more inputs in a small area. / Output pad (I / 0 pads), thus making the density of the metal pin 2 ^ ^ also quickly increased. Therefore, the early lead frame packaging technology is not suitable for high-density metal pins; therefore, a ball grid array (BGA) packaging technology has been developed. In addition to the higher density than the lead frame package, the ball array package has the advantages of higher density than the lead frame package. Its tin ball is also less susceptible to damage and deformation. With the popularity of 3C products, such as q mobile phone (Cdl ph〇ne), personal digital assistant (PDA) 妓 iPod f ' must put many complex system chips into a non-¥ small air jet' To solve this problem, a packaging technology called "W-level package (WLP)" has been developed, which can be used to wafer before cutting the wafer into individual grains. Package. This "wafer level packaging" technique is disclosed in U.S. Patent No. 5,323,051. However, this "wafer-level packaging" technology increases the number of pads between the pads on the active side of the die, in addition to the problem of woven age or signal interference. Because the soldering pitch is too small, the reliability of the lang-language is reduced, and the chip is further reduced, so that the aforementioned packaging technology cannot be satisfied. In order to solve this problem, U.S. Patent Publication No. 7, i%, No. 4, No. 8 has disclosed a wafer that will be completed and tested by a semiconductor process, and the test results are good crystal = (good) reposition On the other substrate, and then the packaging process, so, 1352411 June 3, 2011 revised replacement page makes these relocated crystals have a wider spacing, so the pads on the die can be Proper distribution, such as the use of outward extension (fan〇m) technology, can effectively solve the problem that the spacing is too small, in addition to causing signal coupling or signal interference. However, in order to enable semiconductor wafers to have smaller and thinner packages The structure, before wafer dicing, will first thin the wafer, for example, by back grinding (backsideia_g), the crystal is thinned to 2~2_' woven and then _ into the desired grain. The thinned film 'is reconfigured on the other substrate, and then a plurality of crystal grains are formed into a package by injection molding; since the die (4) makes the package very thin, when the package is separated from the substrate After that, seal The stress of the package itself causes the package to be distorted, which increases the difficulty of subsequent cutting processes. In addition, 'after the wafer is cut, when re-arranging on another substrate, the size of the new substrate is larger than the original size' Therefore, in the subsequent ball processing process t, it will be impossible to align, and the reliability of the package structure is reduced by 4, and the present invention provides that the lion ig_t _) can be effectively used in the B 曰 round back © domain before performing wafer dicing. In the process of transferring the ball, the method of aligning and encapsulating the financial secrets & '··, in addition, during the whole process of encapsulation, the problem of local excessive _ force of the granules may occur, and the grain may be damaged; (4) The welding of the amount of money (4) The electricity of the battery, the time of the pool of particles. [Inventive content] The problem of the ball alignment and the distortion of the package described in the description, the hair supply uses the wafer alignment mark The grain = number of objects (four) fine (four) method.目目二二: Before the cutting, the alignment is first formed, and then by the alignment, the encapsulation method is adopted, so that the needle can be aligned in the ball, the squid -太鱼-r, On June 30, 2011, the revised replacement page: "The gram strength will make the package H after the lining, turn flat, can effectively improve the manufacturing yield and reliability. t Another part of the invention - the main purpose is to provide - In the encapsulation method of grain re-arrangement, the grain of the package thickness of the die is thinned by grinding to re-package the ruthenium. [Bu] The main purpose is to provide the grain Reconfigured package, ', can re-distribute the die cut from the 12-inch wafer to the substrate of 8忖 wafer, so that it can effectively use the packaged equipment of 8 pairs of wafers without re-establishing 12 hours The packaging equipment of the wafer can reduce the packaging cost of 12 rounds. ... The main purpose of this month is to provide a kind of packaging method for grain reconfiguration, so that the wafers that are paid in = cracked are all known. Is a functioning chip, (5) face (10) out e), can be sealed Material, so it can also reduce the cost of the process π. The main purpose is to provide a package method for grain reconfiguration, so that the chips into the second package are, and are known to be functional wafers, (5) Face (4) d (6), which can save packaging materials', so it can also reduce the cost of f-process. According to the above description, the present invention discloses a method for packaging a crystal re-arrangement, comprising: providing that the Japanese yen has an upper surface and a back surface, and the wafer is provided with a plurality of crystal grains and a surface above the dome The first layer of the polymer material is disposed; the wafer is formed to form a plurality of 曰a grains and the __ polymer material layer is covered on the active surface of each of the grains; and the plurality of bismuth particles are taken to the metal On the substrate, a back surface of one of the plurality of crystal grains is connected to an adhesive layer disposed on the metal substrate; and a second polymer material layer is formed on the metal substrate and the first polymer layer of the active surface of the plurality of crystal grains And covering the mold device to the second polymer material layer to planarize the first polymer material layer, so that the second polymer material layer is filled between the plurality of aa particles and annularly covering each of the crystal grains to form a package; the mold is removed from the mold to expose the surface of the package; the package is thinned so that the first surface of each of the active faces of the die is corrected to replace the first page of the polymer. Material layer exposure; formation - patterning - high a sub-material layer to expose a plurality of solder bumps on each active surface of the die; forming a patterned third polymer material layer on each surface of the die and the partial package, and exposing each a plurality of solder bumps on the active surface of the die; forming a plurality of patterned metal segments, each end of the patterned metal segment being electrically connected to a plurality of solder bumps on each of the die faces Each patterning, the metal line segment has an extension to the active surface of each of the grains - the fan-out structure covers a portion of the third polymer material layer; and a patterned protective layer is formed to cover the plurality of patterned layers The wire segment is exposed to a part of the surface of the fan-out structure extending from the outer side of the active surface of the H-grain. The plurality of conductive elements are electrically connected to the plurality of conductive members. A portion of the surface of the exposed fan-out structure of the patterned metal segment: and the briquetting body is formed to form a plurality of dies having metal substrates and each of which is independently packaged. The invention also discloses a package structure for re-disposing a crystal grain, comprising: a “grain”, wherein an active surface is provided with a plurality of solder pads and a polymer material layer and exposing a plurality of solder bumps, and The mask has a metal substrate; a package is attached to the four faces of the die to expose the active surface of the die and the lower surface; a plurality of smeared metal segments, the ends of the die and the die A plurality of welded Wei-shaped joints on the active surface, the other end of which extends in a fan-out manner and covers a plurality of high-altitude layers; the _--------------------------------------------------------------- And exposing the number of sides of the metal segment to a part of the surface of the fan-out structure extending outside the active surface of the plurality of particles; and the plurality of conductive elements are electrically connected to the metal segments of the plurality of sides Part of the surface of the exposed U structure. For the present issue _ general and implementation, _ _ _ for the best implementation touch instructions such as I. (The level has a step-by-step understanding of the purpose, structure, features, and functions of the present invention, and is described in detail below with reference to the example.) 8 1352411 r _ 201 June 30曰 Correction Replacement Page [Embodiment] The invention discussed herein is a method of packaging a (four) grain reconfiguring method, and reconfiguring a plurality of crystal grains on another substrate to reduce the thickness of the thinned package to reduce the package of the package structure. In order to thoroughly understand the present invention, detailed steps and combinations thereof will be set forth in the following description. Wei, the present invention is a special detail that is familiar to those skilled in the art of stacking mosquito wafers. The steps of the wafer forming method and the wafer thinning process are not described in detail to avoid causing the invention to be unnecessarily detailed. For the preferred embodiment of the present invention, the following description will be described in detail. In addition to the detailed description, the present invention is widely practiced in other implementations, and the scope of the present invention is not limited, and the scope of the following patents will prevail. In modern semiconductor packaging processes, a wafer that has completed the F_End Process is first thinned, such as grinding the thickness of the wafer to 2 to 20 mils. Then, the wafer is subjected to a sawing process to form a single grain enthalpy; then, the pick and place device (twisting café) is used to place the individual dies one by one. On the substrate 100, as shown in the figure. Obviously, the area of the die on the substrate 100 is larger than that of the die 11 and, therefore, the width of the repositioned die 110 can be made wider, so that the pads on the die 11 can be properly Distribution. In addition, the packaging method used in the embodiment can reconfigure the die 110 cut by the 12-inch wafer on the substrate of the 8-inch wafer, so that the package device of the 8-inch wafer can be effectively used. Without the need to re-set up 12-inch wafer packaging equipment, the packaging cost of 12-inch wafers can be reduced. It is then emphasized that embodiments of the present invention do not limit the use of a substrate having a size of 8 Å, as long as it provides a load bearing function, such as: glass, quartz, ceramic board, or metal foil. The substrate can be used as the substrate of the present embodiment, and therefore the shape of the substrate is not limited. First, Fig. 2 shows a cross-sectional view of a modified replacement page on the upper surface of the wafer with a layer of polymer material. 1352411 June 30, 2011. As shown in FIG. 2, a plurality of crystal grains 210 are disposed on the upper surface of the wafer 20, and a polymer material layer 310, such as a photoresist layer, is formed on the active surface of each of the crystal grains 210 of the wafer 20. Next, each of the crystal grains 210 is sucked up using a pick-and-place device (not shown) and the active side of the die 210 is placed on the other substrate 40 on which the adhesive layer is disposed. Next, referring to FIG. 3, a second polymer material layer 6 , such as polyamine, is coated on the substrate 40 and the first polymer material layer 310 of the plurality of crystal grains 21 , and a mold device 500 is used. The second polymer material layer 6 is flattened so that the second polymer material layer 60 forms a flattened surface, and the second polymer material layer 6 吏 is filled between the crystal grains 210 and each The five faces of the 21 Å grains are all covered by the second polymer material layer 60. Then, the planarized second polymer material layer 6 can be selectively subjected to a buffing process to cure the third polymer material layer 60. Then, the mold release process is performed to separate the mold device 5GG from the second polymer material 6G, and the surface of the planarized second polymer material layer 60 is exposed, as shown in Fig. 4. Then, as shown in FIG. 5, the second polymer material layer 6 is thinned to expose the surface of the first polymer material layer 31 () on the active surface of each of the crystal grains 210: here, thin The method for forming the second polymer material layer 6G comprises: polishing the second polymer material layer (8) with the first polymer material layer 310 disposed on the active surface of each of the crystal grains to expose the first polymer The surface of the material layer 31〇. The thickness of the package structure formed later can be reduced by thinning the thickness of the second polymer material layer. Then, the second polymer material layer 6〇 is separated from the adhesive layer 5〇 by the same reference to the fifth circle. For example, the method of touching the two polymer materials into the 4G recording plate 4G _ domain people in the tank with deionized water The second polymer material layer 60 is separated from the adhesive layer 5〇 to form a package U匕 package covering each of the four faces of the die 21__, and exposing the first surface of each die 2(1) - The surface of the polymer material layer 31. Then, using a dicing blade (not 10 13.52411, x 201, June 30, revised replacement page is not shown in the figure) in the second polymer material layer 6 on the back side of the active face relative to each die 21 二The surface of the surface is 械·5~1 mil, and the width of the scribe line (10) is 5 to 25 microns. In a preferred embodiment, the scribe lines (10) may be vertically staggered with each other and may serve as a reference line when the dies are actually cut. Since there are a plurality of strips on the back surface of the active surface of the package 2 relative to the die 2(1), the stress on the package is removed by the second layer after the second polymer nano-f6() silk plate* is peeled off. The reduction of the formed area can effectively solve the problem of the package interesting. Next, reference is made to the sixth item, which is a schematic view showing the formation of a patterned first polymer layer on the active surface of each of the grains to reveal a plurality of solder fillets on the active surface of each of the grains. Here, by using a semiconductor process, such as development and etching, first, a patterned photoresist layer (not shown) is formed on the first high-division material layer 310; the button is engraved to remove the portion ^ first a polymer material layer 310 for exposing a plurality of pads 212 on the active surface of each die 210; and removing the patterned photoresist layer to expose a plurality of solders on the active surface of each die 210 Pad 212. Next, referring to Fig. 7', a patterned layer of the first molecular material is formed on the surface of each of the crystal grains and the partial package, and a schematic view of each of the pads of the crystal grains is exposed. Here, a third polymer material layer 320' is formed on the surface of each of the crystal grains 210 and a part of the package, for example, polyplyimide; then, using a semiconductor process, such as development and side Forming a patterned photoresist layer (not shown in the figure) on the third polymer material layer, and removing a portion of the third polymer material layer to form a plurality of holes 322 and exposing the mother A plurality of solder pads 212 on the active surface of a 21 Å die; the patterned photoresist layer is removed. Next, referring to Fig. 8, it is shown that a plurality of patterned metal line segments 7 are formed on a plurality of pads 212 on the active surface of each of the crystal grains 210. Each of the metal segments 7 is outwardly 11 1352411. One end of the fan-out structure extending from the replacement page on June 30, 2011 is electrically connected to the pad 212 on each of the die 21; wherein, a plurality of ions are formed The step of the metal line segment comprises: firstly, using a sputtering to form a seed layer (not shown in FIG. _) on the surface of the portion of the third high-division material layer 320 and the plurality of holes 322 a plurality of pads 212 covering the active surface of each of the dies 21; a metal layer (not shown) is formed on the seed layer by means of an electric bond; and then, using a semiconductor process technology, And _, firstly, the formed-patterned pupil is not shown on the metal layer; the side is removed to remove a portion of the metal layer to form a plurality of patterned metal segments 7; and the stripping is patterned The photoresist layer. The end of each of the metal strip segments 7G is electrically connected to a plurality of 212's on each of the grains 2 〇. As shown in FIG. 9, the 4 metal strip segments 7G can be etched metal layers, and the material thereof can be Ti. /Cu or TiW/Cu. As shown in FIG. 10, a patterned protective layer 8 is formed to cover a plurality of patterned metal segments 7〇, which exposes a plurality of active metal segments to the active surface of the die 21〇. The step of extending the outer side of the end portion; wherein the step of forming the patterning protection comprises: forming a protective layer (not shown) on the plurality of patterned metal lines & In the case of the fresh-keeping process, the image is formed on the side of the pattern, and the layer 7 of the patterned light (not shown in the figure) is placed on the protective layer; then, the active layer of the grain (10) for the plurality of drunk 1 metal segments is 7 a portion of the surface extending from the outer side of the surface to expose a portion of the surface of the patterned metal segment 7 向 extending toward the outer side of the active surface of the die 21 ;; and stripping _ Case of the photoresist layer. ^ As shown in Figure U, a plurality of conductive elements 9 形成 are formed, which are electrically connected as each of the two paths - the patterned metal line segment 7 之外 is outside the active side of the grain training (4) = part Surface; and cutting the package to form a plurality of separate $ particles, as shown in the 12th. The wheel member 9g may be a solder ball _ (four) or a metal bump (metal bump) e 12 1352411 .-L June 30, 2011, the replacement of the 苜 苜 I I 关 其 其 其 其 其 其 其 其 其 其 其 其 其 其In the die reconfiguration gold=0=, the substrate metal substrate 40 can be used as a heat dissipation substrate in the whole packaging process without using the substrate 40, so as to increase the heat dissipation efficiency of the die 210. The thief-mounted adhesive layer 5 can be a conductive partner; in addition, if not, and the step on the metal substrate 40 is re-arranged on the new substrate 4G, and the I-package words are all scaled, Re-reported. In addition, as shown in Fig. 14, it is possible to form a heat dissipating device 94 on each of the independent back surfaces, for example, a key piece of the packaged granules 210 94, and a "f") 21〇 and the heat sink surface are more than 3 conductive wins 92' to fix the heat sink 94 on the back of the die 210. Although the hair of the above-mentioned health-aged Honglu is as above, make some changes and retouching, so this hair The application for patents by Marunouchi is [this book is attached [simplified description of the schema]. The first diagram shows the schematic diagram of the prior art; the second _ Naben (four) is the wealth of the state, the county turn - the polymer difficult layer Schematic cross-sectional view; 1«The upper surface has the 3rd to the uth_ according to the technique of the invention disclosed in the invention, the standard method of the re-marking (10) re--: the intention is broadly according to the technology disclosed in the present invention. 13 1352411 FIG. 13 is a schematic view showing a metal substrate according to the technology disclosed in the present invention; and FIG. 14 is a schematic view showing a heat dissipating device according to the technology disclosed in the present invention. Main component symbol description] 100 substrate 110 crystal 20 wafer 210 die 212 pad 31 〇 first polymer material layer 320 third polymer material layer 322 hole 4 〇 substrate 50 adhesive layer 60 second polymer material layer 610 cutting road 7 〇 metal line segment 80 protective layer 90 Conductive element 92 conductive paste 94 heat sink 500 mold device 2〇11 ^ fa system sound; gossip 30曰 correction replacement page table does not complete the packaged die back system indicates the back of the finished die