CN104752189A - WLCSP wafer back thinning process - Google Patents
WLCSP wafer back thinning process Download PDFInfo
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- CN104752189A CN104752189A CN201310747513.4A CN201310747513A CN104752189A CN 104752189 A CN104752189 A CN 104752189A CN 201310747513 A CN201310747513 A CN 201310747513A CN 104752189 A CN104752189 A CN 104752189A
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- 238000000034 method Methods 0.000 title claims abstract description 60
- 230000008569 process Effects 0.000 title abstract description 16
- 239000011241 protective layer Substances 0.000 claims abstract description 23
- 238000010276 construction Methods 0.000 claims description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 30
- 229910052710 silicon Inorganic materials 0.000 claims description 30
- 239000010703 silicon Substances 0.000 claims description 30
- 239000010410 layer Substances 0.000 claims description 24
- 150000004767 nitrides Chemical class 0.000 claims description 23
- 238000011946 reduction process Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 10
- 239000004642 Polyimide Substances 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 238000000227 grinding Methods 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229920002577 polybenzoxazole Polymers 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 239000002313 adhesive film Substances 0.000 claims description 4
- 238000003701 mechanical milling Methods 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 abstract description 4
- 239000012790 adhesive layer Substances 0.000 abstract 2
- 238000012858 packaging process Methods 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 13
- 238000005538 encapsulation Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 6
- 238000012536 packaging technology Methods 0.000 description 6
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000008280 blood Substances 0.000 description 2
- 210000004369 blood Anatomy 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005485 electric heating Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 230000009172 bursting Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention provides a WLCSP wafer back thinning process. The WLCSP wafer back thinning process is applied to a wafer level chip size packaging process; an adhesive layer for physical supporting and as high as a lug is formed on the surface of the front face edge of a wafer to be thinned; when the wafer to be thinned is thinned, the adhesive layer is capable of supporting the edge of the wafer and also adhering to a protective layer, and the supporting structure is removed after the wafer is thinned, and therefore, the collapse of the wafer edge in the process of thinning the wafer back can be effectively avoided; in addition, the degrees of freedom of wafer thinning can be further increased, and moreover, the WLCSP packaging efficiency is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of WLCSP technique for thinning back side of silicon wafer.
Background technology
Along with the development of semiconductor technology and the driving of consumer electronics market, encapsulation technology to gentlier, the future development that thinner, volume is less, electric heating property is more excellent.Chip package process is changed to wafer level packaging by chip package one by one, and crystal wafer chip dimension encapsulation (WaferLevel Chip Scale Package, be called for short WLCSP) just in time meet the requirement of packaging technology because having the advantages such as high density, volume is little, reliability is high, and electric heating property is excellent and to become most advanced at present gradually be also one of most important packing forms.At present, crystal wafer chip dimension encapsulation is widely used in the encapsulation of consumer chip product, and the application of projection has become the main flow of high-density packages in crystal wafer chip dimension encapsulation technology, adopt projection as the interconnection of chip and substrate, although simplify the flow process of packaging technology, but because in new technological process, the edge of WLCSP wafer does not have supporter supports, thus result in WLCSP wafer rear is carried out grinding technics with technique during thinning WLCSP wafer be restricted (as wafer thickness can not too thin and crystal round fringes easily cracked etc.), and the demand of WLCSP packaging technology cannot be met, thus reduce the packaging efficiency of wafer.
Therefore how to optimize WLCSP technique for thinning back side of silicon wafer and become with the packaging efficiency improving WLCSP wafer the direction that those skilled in the art endeavour research.
Summary of the invention
For above-mentioned Problems existing, the present invention discloses a kind of WLCSP technique for thinning back side of silicon wafer, because crystal round fringes causes wafer reduction process to be subject to process technology limit without supporter supports during to overcome the reduction process carrying out WLCSP wafer rear in prior art, the thickness of process requirements and the problem easily cracked when thinning of crystal round fringes cannot be thinned to.
To achieve these goals, the present invention adopts following technical scheme:
A kind of WLCSP technique for thinning back side of silicon wafer, comprises the steps:
What provide one to have several bulge-structures treats thinned wafer;
Supporting construction is formed on described surface for the treatment of the front edge place of thinned wafer;
Continue at this and treat that the upper front of thinned wafer covers a protective layer;
Utilize described in the support of described supporting construction and treat to this, the edge of thinned wafer treats that reduction process is carried out at the back side of thinned wafer;
Remove described protective layer and described supporting construction;
Wherein, described supporting construction be arranged in described in treat the non-device region of thinned wafer.
Above-mentioned WLCSP technique for thinning back side of silicon wafer, wherein, the absolute value of the difference in height of described supporting construction and described bulge-structure is less than 10 of the height of described bulge-structure.
Above-mentioned WLCSP technique for thinning back side of silicon wafer, wherein, the material of described bulge-structure is metal.
Above-mentioned WLCSP technique for thinning back side of silicon wafer, wherein, described in treat thinned wafer front on be also provided with some chips, the weld pad on this some chip and described bulge-structure are electrically connected;
Wherein, the material of described bulge-structure is solder.
Above-mentioned WLCSP technique for thinning back side of silicon wafer, wherein, described supporting construction is for binding nitride layer.
Above-mentioned WLCSP technique for thinning back side of silicon wafer, wherein, adopts coating technique to treat that nitride layer is binded in the surface coating at the front edge place of thinned wafer in described.
Above-mentioned WLCSP technique for thinning back side of silicon wafer, wherein, the material of described bonding nitride layer is polybenzoxazole or polyimides.
Above-mentioned WLCSP technique for thinning back side of silicon wafer, wherein, adopts developing technique to remove described bonding nitride layer.
Above-mentioned WLCSP technique for thinning back side of silicon wafer, wherein, described protective layer is adhesive film.
Above-mentioned WLCSP technique for thinning back side of silicon wafer, wherein, adopt back side mechanical milling tech to treat that the back side of thinned wafer is carried out thinning to described, wherein grinding rotating speed is 1000-3500r/min.
Above-mentioned WLCSP technique for thinning back side of silicon wafer, wherein, treat that the back side of thinned wafer is carried out reduction process and described wafer is thinned to predetermined dimensional thickness stopping to described, described predetermined dimensional thickness scope is 75-200 μm.
Foregoing invention tool has the following advantages or beneficial effect:
In sum, owing to present invention employs technique scheme, by formed in the surface for the treatment of the front edge place of thinned wafer in crystal wafer chip dimension encapsulation technique suitable with metal coupling height the bonding nitride layer of physical support effect (its material can be PBO, PI etc.), when carrying out thinning to this until thinned wafer, bind the effect that nitride layer can play supporting wafer edge, this bonding nitride layer also can protective layer of adhesion simultaneously, and this wafer is being carried out to thinning this supporting construction of rear removal, thus effectively prevent the phenomenon that crystal round fringes bursts apart when carrying out reduction process to wafer rear, and further increase the thinning degree of freedom of wafer, and then improve the efficiency of WLCSP encapsulation.
Concrete accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the present invention and feature, profile and advantage will become more apparent.Mark identical in whole accompanying drawing indicates identical part.Proportionally can not draw accompanying drawing, focus on purport of the present invention is shown.
Fig. 1 ~ 6 are flowage structure schematic diagrames of WLCSP technique for thinning back side of silicon wafer in the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the present invention is further illustrated, but not as limiting to the invention.
Fig. 1 ~ 6 are flowage structure schematic diagrames of WLCSP technique for thinning back side of silicon wafer in the embodiment of the present invention.As shown in figs. 1 to 6:
The present embodiment relates to a kind of WLCSP technique for thinning back side of silicon wafer, is applied in crystal wafer chip dimension encapsulation technique, comprises the steps:
Step S1, what provide one to include some chips treats thinned wafer 1, this treats that the front of thinned wafer 1 has several and protrudes from the bulge-structure 2 treating thinned wafer 1 front face surface, and this bulge-structure 2 is electrically connected with the weld pad on chip, structure as shown in Figure 1.
In an embodiment of the present invention, shape, the size of several bulge-structures 2 above-mentioned are all identical, and treat on thinned wafer 1 evenly distributed, form array, several bulge-structures 2 are all positioned at the device area treating thinned wafer 1, and several bulge-structures 2 play the effect of the interconnection as chip and substrate in follow-up packaging technology, simplify the flow process of WLCSP packaging technology.
In an embodiment of the present invention, these several bulge-structures 2 are metal coupling, preferred solder projection, in treating that technique thinned wafer 1 being formed this metal coupling adopts prior art institute conventional techniques means, therefore do not repeat them here.
Step S2, the supporting construction 3 of physical support effect in the surface at front edge place for the treatment of thinned wafer 1 is formed, and supporting construction 3 is positioned at and treats that thinned wafer 1 edge does not comprise the region of bulge-structure 2, namely in non-device region, contactless between this supporting construction 3 and bulge-structure 2; This supporting construction 3 can be the stratiform supporting construction of the one-tenth annular being positioned at the non-device region for the treatment of thinned wafer 1 front edge place, also can be positioned at several supporting constructions treating that the non-device region at thinned wafer 1 front edge place is evenly distributed, structure as shown in Figure 3.
In an embodiment of the present invention, the absolute value of the height of this supporting construction 3 and the difference in height of bulge-structure 2 is less than 10 of the height of bulge-structure 2, that is, when supporting construction 3 is higher than bulge-structure 2, supporting construction 3 is less than 10 of the height of bulge-structure 2 with the difference in height of bulge-structure 2; When supporting construction 3 is lower than bulge-structure 2, bulge-structure 2 is less than 10 of the height of bulge-structure 2 with the difference in height of supporting construction 3.
Preferred further, the height of this supporting construction 3 is identical with the height of bulge-structure 2, and now, supporting construction 3 reaches best support effect follow-up treating when thinned wafer 1 carries out reduction process.
Wherein, this supporting construction 3 can be any passive and meet the supporter of process requirements, preferably, this supporting construction 3 is for binding nitride layer, preferred further, the material of this bonding nitride layer is polybenzoxazole (PBO) or polyimides (PI), in an embodiment of the present invention, adopts coating technique to form this bonding nitride layer in the surface coating of the edge treating thinned wafer 1 front.
Step S3, continues at and treats that the upper front of thinned wafer 1 covers a protective layer 4, and this protective layer 4 plays the effect protecting this to treat the device architecture in thinned wafer 1 front in follow-up reduction process, structure as shown in Figure 3.
Preferably, the top in the front of thinned wafer 1 is treated in this protective layer 4 all standing, and after covering in protective layer 4, treat the surface in the front of thinned wafer 1, the surface of bulge-structure 2, the surface of supporting construction 3 is all protected; Wherein protective layer 4 can be the diaphragm that adhesive film or ABC base material class versatility backside mask diaphragm etc. meet process requirements; if above-mentioned supporting construction 3 is for binding nitride layer; because binding nitride layer itself, there is stickiness; follow-up reduction process is carried out to wafer rear time protective layer tightly can be pasted front at wafer; thus avoid protective layer due to stressed loosening the phenomenon that comes off; now protective layer 4 can be non-stickiness diaphragm, can the cost of saving and protection layer.
Step S4, reduction process is carried out at the back side of continuing to treat thinned wafer 1, adopt grinding technics by treat thinned wafer 1 be thinned to predetermined dimensional thickness after stop thinning, formed wafer 1 '; When carrying out reduction process, supporting construction 3 supports edge until thinned wafer 1 to make until thinned wafer 1 stress equalization everywhere when thinning, namely treat the edge of thinned wafer 1 and treat that region that thinned wafer 1 has a bulge-structure 2 is owing to all having support body supports and stress equalization, easier can will treat that thinned wafer 1 is thinned to the thickness meeting process requirements, structure as shown in Figure 4.
In an embodiment of the present invention, the grinding technics that this reduction process adopts is back side mechanical milling tech, its grinding rotating speed is that 1000-3500r/min(is as 1000r/min, 1500r/min, 3500r/min or 2500r/min etc.), the span of predetermined dimensional thickness is 75-200 μm (as 75 μm, 100 μm, 150 μm or 200 μm etc.), also can meet the thickness of process requirements for other.
Step S5, removes the protective layer 4 of the upper front covering wafer 1 ', if when protective layer 4 is the diaphragm of adhesive film or other direct stickups, can directly remove, structure as shown in Figure 5.
Step S6, removes supporting construction 4, if supporting construction 4 is for binding nitride layer, then developing technique can be adopted to remove, structure as shown in Figure 6.
The present invention is by above-mentioned technique; the edge-coating treating thinned wafer in advance prior to having metal coupling binds nitride layer; the effect that nitride layer not only can play supporting wafer edge is binded when wafer rear carries out reduction process; and due to this bonding nitride layer, there is stickiness; the protective layer of wafer frontside can tightly be pasted the front at wafer and can not come off; reduce the requirement to the protective layer that wafer frontside covers; when preventing wafer rear from carrying out reduction process crystal round fringes chipping while; improve the degree of freedom of thinning back side of silicon wafer, save production cost.
In sum, owing to present invention employs technique scheme, by in crystal wafer chip dimension encapsulation technique treat the edge preparation of thinned wafer suitable with bulge-structure height the bonding nitride layer of physical support effect (its material can be PBO, the binders such as PI), so that in WLCSP packaging technology carry out reduction process until the thinned wafer back side time, bind nitride layer and can play physical support crystal round fringes to make the effect of whole wafer uniform force, this bonding nitride layer also can protective layer of adhesion simultaneously, then a protective layer is covered in wafer frontside, this protective layer follow-up reduction process carries out to wafer time protection wafer frontside device architecture, and this wafer is being carried out to thinning this supporting construction of rear removal, thus the phenomenon of bursting apart effectively avoiding crystal round fringes when carrying out reduction process to wafer rear owing to not having support and generation, and further increase the thinning degree of freedom of wafer, improve the efficiency of WLCSP encapsulation, and design science of the present invention is reasonable, compatible strong with traditional process equipment, simple for process, workable.
It should be appreciated by those skilled in the art that those skilled in the art are realizing described change case in conjunction with prior art and above-described embodiment, do not repeat at this.Such change case does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (11)
1. a WLCSP technique for thinning back side of silicon wafer, is characterized in that, comprises the steps:
What provide one to have several bulge-structures treats thinned wafer;
Supporting construction is formed on described surface for the treatment of the front edge place of thinned wafer;
Continue at this and treat that the upper front of thinned wafer covers a protective layer;
Utilize described in the support of described supporting construction and treat to this, the edge of thinned wafer treats that reduction process is carried out at the back side of thinned wafer;
Remove described protective layer and described supporting construction;
Wherein, described supporting construction be arranged in described in treat the non-device region of thinned wafer.
2. WLCSP technique for thinning back side of silicon wafer as claimed in claim 1, it is characterized in that, the absolute value of the difference in height of described supporting construction and described bulge-structure is less than 10 of the height of described bulge-structure.
3. WLCSP technique for thinning back side of silicon wafer as claimed in claim 1, it is characterized in that, the material of described bulge-structure is metal.
4. WLCSP technique for thinning back side of silicon wafer as claimed in claim 1, is characterized in that, described in treat thinned wafer front on be also provided with some chips, the weld pad on this some chip and described bulge-structure are electrically connected;
Wherein, the material of described bulge-structure is solder.
5. WLCSP technique for thinning back side of silicon wafer as claimed in claim 1, is characterized in that, described supporting construction is for binding nitride layer.
6. WLCSP technique for thinning back side of silicon wafer as claimed in claim 5, is characterized in that, adopts coating technique to treat that the surface at the front edge place of thinned wafer forms bonding nitride layer in described.
7. WLCSP technique for thinning back side of silicon wafer as claimed in claim 5, it is characterized in that, the material of described bonding nitride layer is polybenzoxazole or polyimides.
8. WLCSP technique for thinning back side of silicon wafer as claimed in claim 5, is characterized in that, adopts developing technique to remove described bonding nitride layer.
9. WLCSP technique for thinning back side of silicon wafer as claimed in claim 1, it is characterized in that, described protective layer is adhesive film.
10. WLCSP technique for thinning back side of silicon wafer as claimed in claim 1, is characterized in that, adopt back side mechanical milling tech to treat that the back side of thinned wafer is carried out thinning to described, wherein, grinding rotating speed is 1000-3500r/min.
11. WLCSP technique for thinning back side of silicon wafer as claimed in claim 1, it is characterized in that, treat that the back side of thinned wafer is carried out reduction process and treated that thinned wafer is thinned to predetermined dimensional thickness and stops by described to described, the span of described predetermined dimensional thickness is 75-200 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310747513.4A CN104752189A (en) | 2013-12-30 | 2013-12-30 | WLCSP wafer back thinning process |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310747513.4A CN104752189A (en) | 2013-12-30 | 2013-12-30 | WLCSP wafer back thinning process |
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| CN104752189A true CN104752189A (en) | 2015-07-01 |
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| CN201310747513.4A Pending CN104752189A (en) | 2013-12-30 | 2013-12-30 | WLCSP wafer back thinning process |
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Cited By (5)
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| CN107706102A (en) * | 2017-09-19 | 2018-02-16 | 上海华虹宏力半导体制造有限公司 | Technique for thinning back side of silicon wafer method |
| CN107836040A (en) * | 2015-08-26 | 2018-03-23 | 株式会社爱发科 | The manufacture method and processing system of electronic unit |
| CN108436604A (en) * | 2018-04-23 | 2018-08-24 | 宜特(上海)检测技术有限公司 | Resist delamination grinding method applied to low dielectric material crystal covered chip |
| CN110335825A (en) * | 2019-05-29 | 2019-10-15 | 宁波芯健半导体有限公司 | A kind of wafer stage chip encapsulation method |
| CN111592832A (en) * | 2020-05-29 | 2020-08-28 | 南通通富微电子有限公司 | DAF film, preparation method thereof and chip packaging structure |
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Application publication date: 20150701 |