CN207250484U - Wafer stage chip encapsulating structure - Google Patents
Wafer stage chip encapsulating structure Download PDFInfo
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- CN207250484U CN207250484U CN201721320009.6U CN201721320009U CN207250484U CN 207250484 U CN207250484 U CN 207250484U CN 201721320009 U CN201721320009 U CN 201721320009U CN 207250484 U CN207250484 U CN 207250484U
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- dielectric layer
- package structure
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- 239000004065 semiconductor Substances 0.000 claims abstract description 134
- 229910000679 solder Inorganic materials 0.000 claims abstract description 66
- 239000000463 material Substances 0.000 claims abstract description 52
- 229910052751 metal Inorganic materials 0.000 claims description 63
- 239000002184 metal Substances 0.000 claims description 63
- 230000001681 protective effect Effects 0.000 claims description 37
- 239000002313 adhesive film Substances 0.000 claims description 24
- 229920000642 polymer Polymers 0.000 claims description 4
- 239000004593 Epoxy Substances 0.000 claims 1
- 238000004806 packaging method and process Methods 0.000 abstract description 18
- 239000004033 plastic Substances 0.000 abstract description 14
- 230000000694 effects Effects 0.000 abstract description 6
- 238000002360 preparation method Methods 0.000 abstract description 6
- 230000000149 penetrating effect Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 244
- 238000000034 method Methods 0.000 description 31
- 238000005520 cutting process Methods 0.000 description 27
- 239000000853 adhesive Substances 0.000 description 15
- 230000001070 adhesive effect Effects 0.000 description 15
- 239000012790 adhesive layer Substances 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000005336 cracking Methods 0.000 description 4
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical group [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 3
- 229910003460 diamond Inorganic materials 0.000 description 3
- 239000010432 diamond Substances 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000005272 metallurgy Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000012466 permeate Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model provides a kind of wafer stage chip encapsulating structure, including：Semiconductor chip；Re-wiring layer, positioned at the front of semiconductor chip；Solder projection, positioned at surface of the re-wiring layer away from semiconductor chip；Bonding die film, positioned at the back side of semiconductor chip；The protected material bed of material, for plastic packaging in the periphery of semiconductor chip, re-wiring layer, solder projection and bonding die film, the upper surface of the protected material bed of material is not higher than the upper surface of solder projection, and the lower surface flush of the lower surface of the protected material bed of material and bonding die film.The utility model at the back side of semiconductor chip by setting bonding die film, it can be ensured that semiconductor chip will not shake in the preparation process such as follow-up plastic packaging；It can prevent the back side of semiconductor chip from rupturing；The protected material bed of material is by semiconductor chip and the side wall plastic packaging of dielectric layer, you can effectively to avoid the steam of outside from penetrating into dielectric layer so that dielectric layer is not allowed easily rupturable, and can prevent effect of the external force to the medium damage layer.
Description
Technical Field
The utility model relates to a semiconductor package technical field especially relates to a wafer level chip package structure.
Background
In order to meet the demand for small-scale development in the conventional wafer level chip package structure (WLCSP), a low-k dielectric layer (e.g., a rewiring layer) is used in the wafer level chip package structure, and laser dicing (laseraw) or blade dicing (blade saw) is performed subsequently; however, since the low-k dielectric layer is brittle, particularly after the low-k dielectric layer is exposed to the atmospheric environment, moisture in the atmosphere enters the low-k dielectric layer, so that the low-k dielectric layer is prone to generating cracks (crack) in the subsequent cutting process, and the performance of the packaged chip is seriously affected by the existence of the cracks in the low-k dielectric layer. Meanwhile, in the cutting process, the back surface of the semiconductor chip is directly exposed, so that the problems of cracking (chipping) and the like of the semiconductor chip from the back surface are easily caused; in addition, the conventional packaging structure is generally prepared by sticking a semiconductor chip on a semiconductor substrate through a stripping layer, and then performing plastic packaging; because the adhesive force between the semiconductor chip and the stripping layer is poor, the semiconductor chip is easy to shake in the packaging process and after packaging, so that the contact between the semiconductor chip and the rewiring layer is poor, and the performance of the packaging structure is affected.
SUMMERY OF THE UTILITY MODEL
In view of the above, an object of the present invention is to provide a wafer level chip package structure, which is used to solve the problem that the low-k dielectric layer is cracked in the cutting process in the prior art, and further the performance of the packaged chip is affected, which easily causes the cracking of the back of the semiconductor chip and the shaking of the semiconductor chip in the packaging process and after the packaging because the adhesive force between the semiconductor chip and the peeling layer is poor, thereby causing the bad contact between the semiconductor chip and the rewiring layer, and further affecting the performance of the package structure.
To achieve the above and other related objects, the present invention provides a wafer level chip package structure, which comprises:
a semiconductor chip;
the rewiring layer is positioned on the front surface of the semiconductor chip and is electrically connected with the semiconductor chip;
a solder bump located on a surface of the rewiring layer away from the semiconductor chip and electrically connected to the rewiring layer;
a sheet adhesive film on the back surface of the semiconductor chip;
and the protective material layer is plastically packaged at the peripheries of the semiconductor chip, the rewiring layer, the solder bump and the bonding film, the upper surface of the protective material layer is not higher than the upper surface of the solder bump, and the lower surface of the protective material layer is flush with the lower surface of the bonding film.
Preferably, the re-routing layer includes:
the dielectric layer is positioned on the front side of the semiconductor chip;
and the metal wire layer is positioned in the medium layer and on the surface of the medium layer and is electrically connected with the semiconductor chip and the solder bump.
Preferably, the re-routing layer includes:
the first dielectric layer is positioned on the front side of the semiconductor chip;
at least one metal wire layer which is positioned in the first medium layer and is electrically connected with the semiconductor chip;
the second dielectric layer covers the upper surfaces of the first dielectric layer and the metal wire layer;
and the under bump metal layer is positioned in the second medium layer and on the surface of the second medium layer and is electrically connected with the metal wire layer and the solder bump.
Preferably, the protective material layer is a polymer waterproof material layer.
Preferably, the protective material layer is an epoxy resin layer.
Preferably, the adhesive sheet film is a DAF film or a BSL film.
Preferably, the solder bump includes:
a metal pillar located on a second surface of the rewiring layer and electrically connected to the rewiring layer;
and the solder balls are positioned on the surfaces of the metal columns far away from the semiconductor chip.
Preferably, the solder bumps are solder balls.
Preferably, the number of the semiconductor chips in the wafer level chip packaging structure is one.
Preferably, the number of the semiconductor chips in the wafer-level chip packaging structure is at least two, and a space is formed between every two adjacent semiconductor chips.
The utility model also provides a preparation method of wafer level chip package structure, preparation method of wafer level chip package structure includes following step:
1) providing a wafer, wherein a plurality of semiconductor chips are formed in the wafer;
2) forming a rewiring layer on the upper surface of the wafer, wherein the rewiring layer is electrically connected with the semiconductor chip; the rewiring layer comprises a dielectric layer and a metal connecting layer positioned in the dielectric layer and on the upper surface of the dielectric layer;
3) forming a solder bump on the upper surface of the rewiring layer, wherein the solder bump is electrically connected with the metal connecting line layer;
4) forming a first groove penetrating through the dielectric layer from top to bottom in the dielectric layer, wherein the first groove is positioned between the semiconductor chips and surrounds the semiconductor chips;
5) attaching the wafer with the rewiring layer and the solder bumps formed on the upper surface to a cutting blue film by using a bonding film, wherein the lower surface of the wafer is in contact with the bonding film;
6) forming a second groove under the first groove, wherein the second groove vertically penetrates through the wafer and the adhesive film and extends into the cutting blue film to obtain mutually separated semiconductor chips with a rewiring layer and a solder bump formed on the front surface and an adhesive film formed on the back surface;
7) providing a carrier, taking down each semiconductor chip obtained in the step 6) from the cutting blue film and attaching the semiconductor chips to the surface of the carrier, wherein the adhesive film is in contact with the surface of the carrier, and a space is reserved between the adjacent semiconductor chips;
8) forming a protective material layer on the upper surface of the carrier, wherein the protective material layer fills gaps among the semiconductor chip, the rewiring layer, the solder bumps and the die bonding film and plastically packages the semiconductor chip, the rewiring layer, the solder bumps and the die bonding film;
9) removing the carrier;
10) cutting the structure obtained in the step 9) to obtain the wafer-level chip packaging structure.
Preferably, in step 7), before each of the semiconductor chips obtained in step 6) is attached to the surface of the carrier, a step of forming a peeling layer on the surface of the carrier is further included.
As described above, the utility model discloses a wafer level chip package structure has following beneficial effect: the wafer-level chip packaging structure of the utility model has the advantages that the adhesive film is arranged on the back surface of the semiconductor chip, so that the adhesive force between the semiconductor chip and the carrier is greatly increased, the semiconductor chip can be firmly attached to the upper surface of the cutting blue film or the carrier, and the semiconductor chip can be ensured not to shake in the subsequent preparation processes of plastic package and the like, thereby ensuring the performance of the wafer-level chip packaging structure; the adhesive film is used as a back protection layer of the semiconductor chip, and can prevent the back of the semiconductor chip from cracking; six-side plastic package of the semiconductor chip can be realized by the adhesive film and the protective material layer, the whole plastic package process is simple in process and low in cost; the lateral wall plastic envelope of protective material layer with semiconductor chip and dielectric layer can be in order effectively to avoid outside steam to permeate into the dielectric layer for the dielectric layer is difficult to break, can play firmly again the dielectric layer prevents that external force is right the effect that the dielectric layer destroyed, thereby makes the utility model provides a crack can not appear at the cutting in-process in the dielectric layer, and then has ensured the performance of encapsulation chip.
Drawings
Fig. 1 is a flowchart illustrating a method for manufacturing a wafer level chip package structure according to a first embodiment of the present invention.
Fig. 2 to fig. 14 are schematic structural diagrams of steps of a manufacturing method of a wafer level chip package structure provided in an embodiment of the present invention, wherein fig. 14 is a schematic structural diagram of the wafer level chip package structure of the present invention.
Description of the element reference numerals
10 wafer
11 semiconductor chip
111 connection pad
12 rewiring layer
121 dielectric layer
1211 first dielectric layer
1212 second dielectric layer
122 metal connection layer
1221 Metal wire layer
1222 under bump metallurgy
13 solder bump
14 first trench
141 laser
15 cutting blue film
16 iron ring
17 adhesive sheet film
18 second trench
19 vector
20 protective Material layer
21 peeling layer
22 diamond synthetic knife
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
Please refer to fig. 1 to 14. It should be noted that the drawings provided in the present embodiment are only schematic and illustrative of the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.
Example one
Referring to fig. 1, the present embodiment provides a method for manufacturing a wafer level chip package structure, which includes the following steps:
1) providing a wafer, wherein a plurality of semiconductor chips are formed in the wafer;
2) forming a rewiring layer on the upper surface of the wafer, wherein the rewiring layer is electrically connected with the semiconductor chip; the rewiring layer comprises a dielectric layer and a metal connecting layer positioned in the dielectric layer and on the upper surface of the dielectric layer;
3) forming a solder bump on the upper surface of the rewiring layer, wherein the solder bump is electrically connected with the metal connecting line layer;
4) forming a first groove penetrating through the dielectric layer from top to bottom in the dielectric layer, wherein the first groove is positioned between the semiconductor chips and surrounds the semiconductor chips;
5) attaching the wafer with the rewiring layer and the solder bumps formed on the upper surface to a cutting blue film by using a bonding film, wherein the lower surface of the wafer is in contact with the bonding film;
6) forming a second groove under the first groove, wherein the second groove vertically penetrates through the wafer and the adhesive film and extends into the cutting blue film to obtain mutually separated semiconductor chips with a rewiring layer and a solder bump formed on the front surface and an adhesive film formed on the back surface;
7) providing a carrier, taking down each semiconductor chip obtained in the step 6) from the cutting blue film and attaching the semiconductor chips to the surface of the carrier, wherein the adhesive film is in contact with the surface of the carrier, and a space is reserved between the adjacent semiconductor chips;
8) forming a protective material layer on the upper surface of the carrier, wherein the protective material layer fills gaps among the semiconductor chip, the rewiring layer, the solder bumps and the die bonding film and plastically packages the semiconductor chip, the rewiring layer, the solder bumps and the die bonding film;
9) removing the carrier;
10) cutting the structure obtained in the step 9) to obtain the wafer-level chip packaging structure.
In step 1), referring to step S1 in fig. 1 and fig. 2, a wafer 10 is provided, and a plurality of semiconductor chips 11 are formed in the wafer 10.
As an example, the wafer 10 may be a silicon wafer, a sapphire wafer, a gallium nitride wafer, or the like; preferably, in this embodiment, the wafer 10 is a silicon wafer.
As an example, the semiconductor chip 11 may be any semiconductor functional chip, the front surface of the semiconductor chip 11 is formed with a connection pad 111 for electrically leading out a functional device therein, and an upper surface of the connection pad 111 is exposed on the upper surface of the semiconductor chip 11, that is, an upper surface of the connection pad 111 is flush with the upper surface of the semiconductor chip 11.
In step 2), please refer to step S2 in fig. 1 and fig. 3, a redistribution layer 12 is formed on the upper surface of the wafer 10, and the redistribution layer 12 is electrically connected to the semiconductor chip 11; the redistribution layer 12 includes a dielectric layer 121 and a metal interconnection layer 122 located in the dielectric layer 121 and on the upper surface of the dielectric layer 121.
In one example, as shown in fig. 3, the step of forming the redistribution layer 12 on the top surface of the wafer 10 includes the following steps:
2-1) forming a first dielectric layer 1211 on the upper surface of the wafer 10;
2-2) forming a first opening (not shown) in the first dielectric layer 1211, wherein the first opening exposes the connection pad 111;
2-3) forming a metal wire layer 1221 on the upper surface of the first dielectric layer 1211 in the first opening and at the periphery of the first opening, wherein the metal wire layer 1221 is in contact connection with the connection pad 111;
2-4) forming a second dielectric layer 1212 on the metal line layer 1221 and the upper surface of the first dielectric layer 1211;
2-5) forming a second opening (not shown) in the second dielectric layer 1212, wherein the second opening exposes the metal line layer 1221;
2-6) forming an under bump metal layer 1222 on the upper surface of the second dielectric layer 1212 in the second opening and at the periphery of the second opening, wherein the under bump metal layer 1222 is in contact connection with the metal wire layer 1221.
Of course, in other examples, any re-wiring layer preparation process that is available in the prior art may be used to prepare the re-wiring layer 12 including the dielectric layer 121, the metal line layer 1221 and the under bump metal layer 1222.
The first dielectric layer 1211 and the second dielectric layer 1212 may be made of the same material.
It should be further noted that, in the above example, the first dielectric layer 1211 and the second dielectric layer 1212 together form the dielectric layer 121 of the redistribution layer 12, and the metal line layer 1221 and the under-bump metal layer 1222 together form the metal connection layer 122 of the redistribution layer 12.
In another example, the redistribution layer 12 includes a dielectric layer 121 and a metal line layer 1221, and the step of forming the redistribution layer 12 on the upper surface of the wafer 10 includes:
2-1) forming the dielectric layer 121 on the upper surface of the wafer 10;
2-2) forming an opening (not shown) in the dielectric layer 121, the opening exposing the connection pad 111;
2-3) forming a metal wire layer 1221 on the upper surface of the dielectric layer 121 in and around the opening, wherein the metal wire layer 1221 is in contact connection with the connection pad 111.
In step 3), please refer to step S3 in fig. 1 and fig. 4, a solder bump 13 is formed on the upper surface of the redistribution layer 12, and the solder bump 13 is electrically connected to the metal interconnection layer 122.
In one example, forming the solder bump 13 on the upper surface of the redistribution layer 12 includes the following steps:
3-1) forming a metal pillar on the upper surface of the redistribution layer 12;
3-2) forming a solder ball on the upper surface of the metal column.
As an example, the material of the metal pillar may be one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium, and the metal pillar may be formed by any one of a physical vapor deposition Process (PVD), a chemical vapor deposition process (CVD), sputtering, electroplating, and electroless plating. The material of the solder ball can be one or a combination of two or more of copper, aluminum, nickel, gold, silver and titanium, and the solder ball can be formed through a ball-planting reflow process.
In another example, as shown in fig. 4, the solder bump 13 is a solder ball, and the solder ball can be directly formed as the solder bump 13 through a ball-mounting reflow process.
Specifically, when the metal connection layer 122 in the redistribution layer 12 includes a metal line layer 1221 and the under bump metal layer 1222, the solder bump 13 is formed on the upper surface of the under bump metal layer 1222; when the metal connection layer 122 within the re-wiring layer 12 includes only the metal line layer 1221, the solder bump 13 is formed on the upper surface of the metal line layer 1221.
In step 4), referring to step S4 in fig. 1 and fig. 5, a first trench 14 penetrating through the dielectric layer 121 up and down is formed in the dielectric layer 121, and the first trench 14 is located between the semiconductor chips 11 and surrounds the semiconductor chips 11.
As an example, the first trench 14 may be formed in the dielectric layer 121 by using laser emitted by the laser 141, and in other examples, the first trench 14 may also be formed in the dielectric layer 121 by using an etching process or a mechanical cutting process.
In step 5), referring to step S5 in fig. 1 and fig. 6, the wafer 10 with the redistribution layer 12 and the solder bumps 13 formed on the upper surface thereof is attached to a dicing blue film 15 by using a tape film 17, and the lower surface of the wafer 10 (i.e., the back surface of the wafer 10) is in contact with the tape film 17.
As an example, an iron ring 16 for fixing the cut blue film 15 is formed above the cut blue film 15.
As an example, the adhesive film 17 may be a DAF (die-attach film) or a BSL (backing dry film) film, and preferably, the adhesive film 17 has a laminated structure including a first adhesive layer, a high thermal conductive resin layer, and a second adhesive layer, which are sequentially stacked. Because the adhesive film 17 is arranged between the wafer 10 and the cutting blue film 15, the adhesive force between the wafer 10 and the cutting blue film 15 can be enhanced, and the wafer 10 does not shake in the cutting process, so that the cutting accuracy can be ensured.
In step 6), referring to S6 in fig. 1 and fig. 6, a second trench 18 is formed right below the first trench 14, and the second trench 18 penetrates the wafer 10 and the adhesive film 17 up and down and extends into the dicing blue film 15, so as to obtain the semiconductor chip 11 which is separated from each other, has the redistribution layer 12 and the solder bump 13 formed on the front surface and the adhesive film 17 formed on the back surface.
As an example, the second trench 18 may be formed under the first trench 14 by using laser light emitted from the laser 141, and in other examples, the second trench 18 may be formed under the first trench 14 by using an etching process or a mechanical cutting process.
In step 7), please refer to S7) in fig. 1 and fig. 7 to 9, a carrier 19 is provided, each semiconductor chip 11 obtained in step 6) is taken off from the dicing blue film 15 and attached to the surface of the carrier 19, the adhesive sheet film 17 is in contact with the surface of the carrier 19, and a space is formed between adjacent semiconductor chips 11.
By way of example, the carrier 19 may be a glass carrier, a ceramic carrier, a wafer, or the like, and is not limited herein.
As an example, as shown in fig. 8, before each of the semiconductor chips 11 obtained in step 6) is attached to the surface of the carrier 19, a step of forming a peeling layer 21 on the surface of the carrier 19 is further included.
When the peeling layer 21 is formed on the surface of the carrier 19, the semiconductor chips 11 obtained in step 6) are attached to the surface of the peeling layer 21, and the adhesive sheet film 17 is connected to the surface of the peeling layer 21; i.e. the release layer 21 is located between the adhesive sheet film 17 and the carrier 19.
As an example, the semiconductor chip 11 may be attached to the upper surface of the carrier 19 with the adhesive sheet film 14 facing up by a bond-on-trace method (bond-on-trace). Such bond tracing methods are well known to those skilled in the art and will not be described in detail herein. Of course, in this embodiment, the semiconductor chip 11 may be attached to the upper surface of the carrier 19 by any other bonding method, as shown in fig. 9.
In step 8), please refer to step S8 in fig. 1 and fig. 10, a protective material layer 20 is formed on the upper surface of the carrier 19, the protective material layer 20 fills the gap between the semiconductor chip 11, the redistribution layer 12, the solder bump 13 and the die attach film 17, and the semiconductor chip 11, the redistribution layer 12, the solder bump 13 and the die attach film 17 are molded.
As an example, the protective material layer 20 may be formed on the upper surface of the carrier 19 using a compression molding process, a transfer molding process, a liquid seal molding process, a molding underfill process, a capillary underfill process, a vacuum lamination process, or a spin coating process, for example. Preferably, in this embodiment, a transfer molding process is used to form the protective material layer 20 on the upper surface of the carrier 19.
As an example, the protective material layer 20 is a polymer waterproof material layer; preferably, in this embodiment, the protective material layer 20 is an epoxy resin layer.
As an example, the upper surface of the protective material layer 20 is not higher than the upper surface of the solder bump 13, that is, the upper surface of the protective material layer 20 is lower than the upper surface of the solder bump 13 or the upper surface of the protective material layer 20 is flush with the upper surface of the solder bump 13. Because the back of the semiconductor chip 11 is provided with the adhesive film 17, the semiconductor chip 11 does not shake in the plastic packaging process, so that a better plastic packaging effect can be ensured.
When the peeling layer 21 is formed on the upper surface of the carrier 19, the protective material layer 20 is formed on the upper surface of the peeling layer 21.
In step 9), please refer to step S9 in fig. 1 and fig. 11, the carrier 19 is removed.
As an example, the removal of the carrier 19 and the peeling layer 21 may be performed by a grinding process, a thinning process, or the like. Preferably, in this embodiment, the peeling layer 21 is a UV tape, and the carrier 19 may be removed by tearing off the peeling layer 21.
In step 10), referring to step S10 in fig. 1 and fig. 12 to 14, the structure obtained in step 9) is diced to obtain the wafer level chip package structure.
As an example, the step of cutting the structure obtained in step 9) to obtain the wafer-level chip package structure includes the following steps:
10-1) attaching the structure obtained in step 9) to a cut blue film 15, as shown in fig. 12;
10-2) cutting from the area between the semiconductor chips 11, as shown in fig. 13, and after the cutting, taking down the cut structure from the cutting blue film 15 to obtain the wafer level chip package structure.
As an example, a laser cutting process or a diamond synthesis knife may be used to perform cutting separation between the semiconductor chips 11, so as to obtain the wafer-level chip package structure including one semiconductor chip 11, as shown in fig. 14.
In another example, a laser dicing process or a diamond synthesis knife may be used to separate the two or more semiconductor chips 11 from each other, so as to obtain the wafer-level chip package structure of the two or more semiconductor chips 11.
Example two
With reference to fig. 14, the present embodiment further provides a wafer level chip package structure, which can be prepared by the method for preparing a wafer level chip package structure described in the first embodiment, but not limited to the method for preparing a wafer level chip package structure, and the wafer level chip package structure includes: a semiconductor chip 11; a rewiring layer 12, the rewiring layer 12 being located on the front surface of the semiconductor chip 11 and electrically connected to the semiconductor chip 11; a solder bump 13, the solder bump 13 being located on a surface of the redistribution layer 12 away from the semiconductor chip 11 and electrically connected to the redistribution layer 12; a sheet adhesive film 17, the sheet adhesive film 17 being located on the back surface of the semiconductor chip 11; and the protective material layer 20 is plastically packaged on the periphery of the semiconductor chip 11, the rewiring layer 12, the solder bump 13 and the adhesive sheet film 17, the upper surface of the protective material layer 20 is not higher than the upper surface of the solder bump 13, and the lower surface of the protective material layer 20 is flush with the lower surface of the adhesive sheet film 17.
In one example, the re-routing layer 12 includes: a dielectric layer 121, wherein the dielectric layer 121 is located on the front surface of the semiconductor chip 11; and the metal wire layer 1221 is positioned in the dielectric layer 121 and on the surface of the dielectric layer 121, and is electrically connected with the semiconductor chip 11 and the solder bump 13.
In another example, the re-routing layer 12 includes: a first dielectric layer 1211, wherein the first dielectric layer 1211 is positioned on the front side of the semiconductor chip 11; at least one metal wire layer 1221, wherein the metal wire layer 1221 is located in the first dielectric layer 1211 and electrically connected to the semiconductor chip 11; a second dielectric layer 1212, wherein the second dielectric layer 1212 covers the first dielectric layer 1211 and the upper surface of the metal wire layer 121; and an under bump metal layer 1222, wherein the under bump metal layer 1222 is located in the second dielectric layer 1211 and on the surface of the second dielectric layer 1212, and is electrically connected to the metal wire layer 1221 and the solder bump 13. The first dielectric layer 1211 and the second dielectric layer 1212 together form the dielectric layer 121 of the redistribution layer 12, and the metal line layer 1221 and the under bump metallurgy 1222 together form the metal connection layer 122 of the redistribution layer 12.
As an example, the protective material layer 20 is a polymer waterproof material layer; preferably, in this embodiment, the protective material layer 20 is an epoxy resin layer.
As an example, the adhesive sheet film 17 is a DAF film or a BSL film. Preferably, in this embodiment, the adhesive sheet film 17 is a laminated structure including a first adhesive layer, a high thermal conductive resin layer, and a second adhesive layer, and the first adhesive layer, the high thermal conductive resin layer, and the second adhesive layer are sequentially stacked.
In one example, the solder bump 13 includes: a metal pillar located on a surface of the redistribution layer 12 away from the semiconductor chip 11 and electrically connected to the redistribution layer 12; and the solder balls are positioned on the surfaces of the metal columns far away from the semiconductor chip 11.
In another example, as shown in fig. 14, the solder bumps 13 are solder balls.
In one example, as shown in fig. 14, the number of the semiconductor chips 11 in the wafer level chip package structure is one.
In another example, the number of the semiconductor chips 11 in the wafer level chip package structure is at least two, and a space is provided between adjacent semiconductor chips 11.
To sum up, the utility model discloses a wafer level chip package structure, wafer level chip package structure includes: a semiconductor chip; the rewiring layer is positioned on the front surface of the semiconductor chip and is electrically connected with the semiconductor chip; a solder bump located on a surface of the rewiring layer away from the semiconductor chip and electrically connected to the rewiring layer; a sheet adhesive film on the back surface of the semiconductor chip; and the protective material layer is plastically packaged at the peripheries of the semiconductor chip, the rewiring layer, the solder bump and the bonding film, the upper surface of the protective material layer is not higher than the upper surface of the solder bump, and the lower surface of the protective material layer is flush with the lower surface of the bonding film. The wafer-level chip packaging structure of the utility model has the advantages that the adhesive film is arranged on the back surface of the semiconductor chip, so that the adhesive force between the semiconductor chip and the carrier is greatly increased, the semiconductor chip can be firmly attached to the upper surface of the cutting blue film or the carrier, and the semiconductor chip can be ensured not to shake in the subsequent preparation processes of plastic package and the like, thereby ensuring the performance of the wafer-level chip packaging structure; the adhesive film is used as a back protection layer of the semiconductor chip, and can prevent the back of the semiconductor chip from cracking; six-side plastic package of the semiconductor chip can be realized by the adhesive film and the protective material layer, the whole plastic package process is simple in process and low in cost; the lateral wall plastic envelope of protective material layer with semiconductor chip and dielectric layer can be in order effectively to avoid outside steam to permeate into the dielectric layer for the dielectric layer is difficult to break, can play firmly again the dielectric layer prevents that external force is right the effect that the dielectric layer destroyed, thereby makes the utility model provides a crack can not appear at the cutting in-process in the dielectric layer, and then has ensured the performance of encapsulation chip.
The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A wafer level chip package structure, comprising:
a semiconductor chip;
the rewiring layer is positioned on the front surface of the semiconductor chip and is electrically connected with the semiconductor chip;
a solder bump located on a surface of the rewiring layer away from the semiconductor chip and electrically connected to the rewiring layer;
a sheet adhesive film on the back surface of the semiconductor chip;
and the protective material layer is plastically packaged at the peripheries of the semiconductor chip, the rewiring layer, the solder bump and the bonding film, the upper surface of the protective material layer is not higher than the upper surface of the solder bump, and the lower surface of the protective material layer is flush with the lower surface of the bonding film.
2. The wafer level chip package structure of claim 1, wherein the re-routing layer comprises:
the dielectric layer is positioned on the front side of the semiconductor chip;
and the metal wire layer is positioned in the medium layer and on the surface of the medium layer, is electrically connected with the semiconductor chip and the solder bump, and is used as a metal connecting wire layer of the rewiring layer.
3. The wafer level chip package structure of claim 1, wherein the re-routing layer comprises:
the first dielectric layer is positioned on the front side of the semiconductor chip;
at least one metal wire layer which is positioned in the first medium layer and is electrically connected with the semiconductor chip;
the second dielectric layer covers the upper surfaces of the first dielectric layer and the metal wire layer;
the under bump metal layer is positioned in the second medium layer and on the surface of the second medium layer and is electrically connected with the metal wire layer and the solder bump; wherein,
the first dielectric layer and the second dielectric layer jointly form a dielectric layer of the rewiring layer, and the metal wire layer and the under-bump metal layer jointly form a metal connecting wire layer of the rewiring layer.
4. The wafer-level chip package structure of claim 1, wherein the protective material layer is a polymer waterproof material layer.
5. The wafer-level chip package structure according to claim 4, wherein the protective material layer is an epoxy layer.
6. The wafer-level chip package structure of claim 1, wherein the adhesive film is a DAF film or a BSL film.
7. The wafer-level chip package structure of claim 1, wherein the solder bump comprises:
the metal column is positioned on the surface of the rewiring layer, which is far away from the semiconductor chip, and is electrically connected with the rewiring layer;
and the solder balls are positioned on the surfaces of the metal columns far away from the semiconductor chip.
8. The wafer-level chip package structure of claim 1, wherein the solder bumps are solder balls.
9. The wafer-level chip package structure according to claim 1, wherein the number of the semiconductor chips in the wafer-level chip package structure is one.
10. The wafer-level chip package structure of claim 1, wherein the number of the semiconductor chips in the wafer-level chip package structure is at least two, and a space is formed between adjacent semiconductor chips.
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| CN107611097A (en) * | 2017-10-13 | 2018-01-19 | 中芯长电半导体（江阴）有限公司 | Wafer stage chip encapsulating structure and preparation method thereof |
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| CN107611097A (en) * | 2017-10-13 | 2018-01-19 | 中芯长电半导体（江阴）有限公司 | Wafer stage chip encapsulating structure and preparation method thereof |
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