CN207250484U - Wafer stage chip encapsulating structure - Google Patents
Wafer stage chip encapsulating structure Download PDFInfo
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- CN207250484U CN207250484U CN201721320009.6U CN201721320009U CN207250484U CN 207250484 U CN207250484 U CN 207250484U CN 201721320009 U CN201721320009 U CN 201721320009U CN 207250484 U CN207250484 U CN 207250484U
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- layer
- semiconductor chip
- wafer stage
- encapsulating structure
- wiring layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
The utility model provides a kind of wafer stage chip encapsulating structure, including：Semiconductor chip；Re-wiring layer, positioned at the front of semiconductor chip；Solder projection, positioned at surface of the re-wiring layer away from semiconductor chip；Bonding die film, positioned at the back side of semiconductor chip；The protected material bed of material, for plastic packaging in the periphery of semiconductor chip, re-wiring layer, solder projection and bonding die film, the upper surface of the protected material bed of material is not higher than the upper surface of solder projection, and the lower surface flush of the lower surface of the protected material bed of material and bonding die film.The utility model at the back side of semiconductor chip by setting bonding die film, it can be ensured that semiconductor chip will not shake in the preparation process such as follow-up plastic packaging；It can prevent the back side of semiconductor chip from rupturing；The protected material bed of material is by semiconductor chip and the side wall plastic packaging of dielectric layer, you can effectively to avoid the steam of outside from penetrating into dielectric layer so that dielectric layer is not allowed easily rupturable, and can prevent effect of the external force to the medium damage layer.
Description
Technical field
Technical field of semiconductor encapsulation is the utility model is related to, more particularly to a kind of wafer stage chip encapsulating structure.
Background technology
, can be in wafer in order to meet the needs of small size development in existing wafer stage chip encapsulating structure (WLCSP)
Low-k dielectric layer (for example, re-wiring layer) is used in level chip-packaging structure, and to be subsequently cut by laser (laser
Saw) or blade cuts (blade saw)；But since low-k dielectric layer is more crisp, especially big compression ring is exposed in low-k dielectric layer
In border, after the steam in air is entered in low-k dielectric layer so that low-k dielectric layer meeting in follow-up cutting process
Slight crack (crack) is easily produced, and the presence of slight crack can seriously affect the performance of encapsulation chip in low-k dielectric layer.Meanwhile cutting
During cutting, due to semiconductor chip the back side directly it is exposed outside, it is easy to cause semiconductor chip to occur from the back side broken
The problems such as splitting (chipping)；In addition, it is typically all to pass through semiconductor chip between peel ply when prepared by existing encapsulating structure
Adhere in Semiconductor substrate, then carry out plastic packaging encapsulation again；Since the bonding force between semiconductor chip and peel ply is poor,
It is easy to cause semiconductor chip to shake in encapsulation process and after encapsulation, so as to cause semiconductor chip and re-wiring layer
Loose contact, and then influence encapsulating structure performance.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of encapsulation of wafer stage chip
Structure, can cause low-k dielectric layer to produce slight crack for solving existing in the prior art in cutting process, and then influence encapsulation
The problem of performance of chip, be easy to cause the problem of semiconductor chip back side ruptures and due to semiconductor chip and peel ply
Between bonding force it is poor, be easy to cause semiconductor chip in encapsulation process and encapsulation after shake, so as to cause partly to lead
The loose contact of body chip and re-wiring layer, and then the problem of the performance of influence encapsulating structure.
In order to achieve the above objects and other related objects, the utility model provides a kind of wafer stage chip encapsulating structure, institute
Stating wafer stage chip encapsulating structure includes：
Semiconductor chip；
Re-wiring layer, is electrically connected positioned at the front of the semiconductor chip, and with the semiconductor chip；
Solder projection, positioned at surface of the re-wiring layer away from the semiconductor chip, and with the rewiring
Layer is electrically connected；
Bonding die film, positioned at the back side of the semiconductor chip；
The protected material bed of material, plastic packaging is in the semiconductor chip, the re-wiring layer, the solder projection and the bonding die
The periphery of film, the upper surface of the protected material bed of material are not higher than the upper surface of the solder projection, and the protected material bed of material
Lower surface and the lower surface flush of the bonding die film.
Preferably, the re-wiring layer includes：
Dielectric layer, positioned at the front of the semiconductor chip；
Metal line layer, in the dielectric layer and the dielectric layer surface, and it is convex with semiconductor chip and the solder
Block is electrically connected.
Preferably, the re-wiring layer includes：
First medium layer, positioned at the front of the semiconductor chip；
At least one layer of metal line layer, is electrically connected in the first medium layer, and with the semiconductor chip；
Second dielectric layer, is covered in the upper surface of the first medium layer and the metal line layer；
Underbump metallization layer, in the second dielectric layer and the second medium layer surface, and with the metal wire
Layer and the solder projection are electrically connected.
Preferably, the protected material bed of material is high polymer waterproof material layer.
Preferably, the protected material bed of material for epoxy resin layer by layer.
Preferably, the bonding die film is DAF films or BSL films.
Preferably, the solder projection includes：
Metal column, is electrically connected positioned at the second surface of the re-wiring layer, and with the re-wiring layer；
Soldered ball, positioned at the surface of the remote semiconductor chip of the metal column.
Preferably, the solder projection is soldered ball.
Preferably, the quantity of the semiconductor chip is one in the wafer stage chip encapsulating structure.
Preferably, the quantity of the semiconductor chip is at least two in the wafer stage chip encapsulating structure, adjacent institute
Stating between semiconductor chip has spacing.
The utility model also provides a kind of preparation method of wafer stage chip encapsulating structure, the wafer stage chip encapsulation knot
The preparation method of structure includes the following steps：
1) wafer is provided, the wafer is interior formed with several semiconductor chips；
2) re-wiring layer is formed in the upper surface of the wafer, the re-wiring layer is electrically connected with the semiconductor chip
Connect；The re-wiring layer include dielectric layer and in the dielectric layer and the dielectric layer upper surface metal connecting line layer；
3) solder projection, the solder projection and metal connecting line layer electricity are formed in the upper surface of the re-wiring layer
Connection；
4) the dielectric layer first groove is run through above and below being formed in the dielectric layer, the first groove is positioned at each described
Between semiconductor chip, and around the semiconductor chip；
5) wafer of the upper surface formed with the re-wiring layer and the solder projection is posted using bonding die film
In on the blue film of a cutting, the lower surface of the wafer is in contact with the bonding die film；
6) it is formed immediately below second groove in the first groove, the second groove is up and down through the wafer and described
Bonding die film, and extend in the blue film of the cutting, be separated from each other, front formed with re-wiring layer and solder projection
And semiconductor chip of the back side formed with bonding die film；
7) carrier is provided, each semiconductor chip that step 6) obtains is removed and posted from the blue film of the cutting
In the surface of the carrier, the bonding die film is in contact with the surface of the carrier, and has between the adjacent semiconductor chip
There is spacing；
8) in the carrier upper surface formed the protected material bed of material, the protected material bed of material fill up the semiconductor chip,
Gap between the re-wiring layer, the solder projection and the bonding die film, and by the semiconductor chip, it is described again
Wiring layer, the solder projection and the bonding die film plastic packaging；
9) carrier is removed；
10) structure for obtaining step 9) is cut, to obtain the wafer stage chip encapsulating structure.
Preferably, in step 7), each semiconductor chip that step 6) is obtained adhere on the carrier surface it
Before, further include in the carrier surface formed peel ply the step of.
As described above, the wafer stage chip encapsulating structure of the utility model, has the advantages that：The utility model
Wafer stage chip encapsulating structure at the back side of semiconductor chip by setting bonding die film so that the bonding of semiconductor chip and carrier
Power greatly increases, and semiconductor chip can be caused to fit in the upper surface of the blue film of cutting or carrier securely, it can be ensured that rear
Semiconductor chip will not shake in the preparation process such as continuous plastic packaging, so that it is guaranteed that the performance of wafer stage chip encapsulating structure；
Back-protective layer of the bonding die film as semiconductor chip, can prevent the back side of semiconductor chip from rupturing；Bonding die film is with protecting
Protective material layer can realize the six dough models envelope to semiconductor chip, and whole plastic packaging process is simple, and cost is relatively low；Protection materials
Layer is by semiconductor chip and the side wall plastic packaging of dielectric layer, you can effectively to avoid the steam of outside from penetrating into dielectric layer so that
Dielectric layer is not allowed easily rupturable, and can play the firm dielectric layer, prevent effect of the external force to the medium damage layer, so that
So that the dielectric layer in the utility model is not in slight crack in cutting process, and then it ensure that the performance of encapsulation chip.
Brief description of the drawings
Fig. 1 is shown as the flow of the preparation method of the wafer stage chip encapsulating structure provided in the utility model embodiment one
Figure.
Fig. 2~Figure 14 is shown as the preparation method of the wafer stage chip encapsulating structure provided in the utility model embodiment one
The structure diagram that each step is presented, wherein, Figure 14 is shown as the structure of the wafer stage chip encapsulating structure of the utility model
Schematic diagram.
Component label instructions
10 wafers
11 semiconductor chips
111 connection weld pads
12 re-wiring layers
121 dielectric layers
1211 first medium layers
1212 second dielectric layer
122 metal connecting line layers
1221 metal line layers
1222 Underbump metallization layers
13 solder projections
14 first grooves
141 lasers
The blue film of 15 cuttings
16 iron rings
17 bonding die films
18 second grooves
19 carriers
The 20 protected material bed of materials
21 peel plies
22 synthesizing knives
Embodiment
Illustrate the embodiment of the utility model below by way of specific instantiation, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints with answering
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Please refer to Fig.1~Figure 14.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though when only display is with related component in the utility model rather than according to actual implementation in diagram
Component count, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during its actual implementation
Become, and its assembly layout form may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the present embodiment provides a kind of preparation method of wafer stage chip encapsulating structure, the wafer stage chip
The preparation method of encapsulating structure includes the following steps：
1) wafer is provided, the wafer is interior formed with several semiconductor chips；
2) re-wiring layer is formed in the upper surface of the wafer, the re-wiring layer is electrically connected with the semiconductor chip
Connect；The re-wiring layer include dielectric layer and in the dielectric layer and the dielectric layer upper surface metal connecting line layer；
3) solder projection, the solder projection and metal connecting line layer electricity are formed in the upper surface of the re-wiring layer
Connection；
4) the dielectric layer first groove is run through above and below being formed in the dielectric layer, the first groove is positioned at each described
Between semiconductor chip, and around the semiconductor chip；
5) wafer of the upper surface formed with the re-wiring layer and the solder projection is posted using bonding die film
In on the blue film of a cutting, the lower surface of the wafer is in contact with the bonding die film；
6) it is formed immediately below second groove in the first groove, the second groove is up and down through the wafer and described
Bonding die film, and extend in the blue film of the cutting, be separated from each other, front formed with re-wiring layer and solder projection
And semiconductor chip of the back side formed with bonding die film；
7) carrier is provided, each semiconductor chip that step 6) obtains is removed and posted from the blue film of the cutting
In the surface of the carrier, the bonding die film is in contact with the surface of the carrier, and has between the adjacent semiconductor chip
There is spacing；
8) in the carrier upper surface formed the protected material bed of material, the protected material bed of material fill up the semiconductor chip,
Gap between the re-wiring layer, the solder projection and the bonding die film, and by the semiconductor chip, it is described again
Wiring layer, the solder projection and the bonding die film plastic packaging；
9) carrier is removed；
10) structure for obtaining step 9) is cut, to obtain the wafer stage chip encapsulating structure.
In step 1), S1 steps and Fig. 2 in please referring to Fig.1, there is provided a wafer 10, if the wafer 10 in formed with
Dry semiconductor chip 11.
As an example, the wafer 10 can be Silicon Wafer, sapphire wafer or gallium nitride wafer etc.；Preferably, this reality
Apply in example, the wafer 10 is Silicon Wafer.
As an example, the semiconductor chip 11 can be any one semiconductor functional chip, the semiconductor chip
11 front is exposed formed with the connection weld pad 111 for drawing its inside function device electricity, the upper surface of the connection weld pad 111
In the upper surface of the semiconductor chip 11, i.e., the upper surface of described connection weld pad 111 and the upper table of the semiconductor chip 11
Face flush.
In step 2), S2 steps and Fig. 3 in please referring to Fig.1, rewiring is formed in the upper surface of the wafer 10
Layer 12, the re-wiring layer 12 is electrically connected with the semiconductor chip 11；The re-wiring layer 12 include dielectric layer 121 and
In the dielectric layer 121 and 121 upper surface of dielectric layer metal connecting line layer 122.
In one example, as shown in figure 3, forming the re-wiring layer 12 including as follows in the upper surface of the wafer 10
Step：
2-1) first medium layer 1211 is formed in the upper surface of the wafer 10；
2-2) in forming the first opening (not shown) in the first medium layer 1211, first opening exposes described
Connect weld pad 111；
2-3) in the described first opening and the first medium layer 1211 of first mouth periphery upper surface shape
Into metal line layer 1221, the metal line layer 1221 is connected with the connection weld pad 111；
2-4) second dielectric layer 1212 is formed in the upper surface of the metal line layer 1221 and the first medium layer 1211；
2-5) in forming the second opening (not shown) in the second dielectric layer 1212, second opening exposes described
Metal line layer 1221；
2-6) in the described second opening and the second dielectric layer 1212 of second mouth periphery upper surface shape
Into Underbump metallization layer 1222, the Underbump metallization layer 1222 is connected with the metal line layer 1221.
Certainly, in other examples, existing any one re-wiring layer preparation process can also be used to prepare includes
The re-wiring layer 12 of the dielectric layer 121, the metal line layer 1221 and the Underbump metallization layer 1222.
It should be noted that the first medium layer 1211 and the second dielectric layer 1212 can be Jie of identical material
Matter layer.
It should be further noted that in a upper example, the first medium layer 1211 and the second dielectric layer
1212 collectively form the dielectric layer 121 of the re-wiring layer 12, the metal line layer 1221 and the Underbump metallization layer
1222 collectively form the metal connecting line layer 122 of the re-wiring layer 12.
In another example, the re-wiring layer 12 includes one layer of dielectric layer 121 and one layer of metal line layer 1221, in institute
The upper surface for stating wafer 10 forms the re-wiring layer 12 and includes the following steps：
2-1) dielectric layer 121 is formed in the upper surface of the wafer 10；
2-2) in forming opening (not shown) in the dielectric layer 121, the opening exposes the connection weld pad 111；
2-3) in the opening and the dielectric layer 121 of the mouth periphery upper surface formed metal line layer
1221, the metal line layer 1221 is connected with the connection weld pad 111.
In step 3), S3 steps and Fig. 4 in please referring to Fig.1, weldering is formed in the upper surface of the re-wiring layer 12
Expect convex block 13, the solder projection 13 is electrically connected with the metal connecting line layer 122.
In one example, solder projection 13 is formed in the upper surface of the re-wiring layer 12 to include the following steps：
3-1) metal column is formed in the upper surface of the re-wiring layer 12；
3-2) soldered ball is formed in the upper surface of the metal column.
As an example, the material of the metal column can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds and
Two or more combined materials, can by physical gas-phase deposition (PVD), chemical vapor deposition method (CVD), sputtering,
Any of plating or chemical plating technique form the metal column.The material of the soldered ball can be copper, aluminium, nickel, gold, silver,
A kind of material or two kinds and two or more combined materials in titanium, can form the soldered ball by planting ball reflux technique.
In another example, can be by planting ball reflux technique as shown in figure 4, the solder projection 13 is a soldered ball
Soldered ball is directly formed as the solder projection 13.
Specifically, when the metal connecting layer 122 in the re-wiring layer 12 includes metal line layer 1221 and described
During Underbump metallization layer 1222, the solder projection 13 is formed at the upper surface of the Underbump metallization layer 1222；When described heavy
When the metal connecting layer 122 in new route layer 12 only includes the metal line layer 1221, the solder projection 13 is formed at
The upper surface of the metal line layer 1221.
In step 4), S4 steps and Fig. 5 in please referring to Fig.1, run through described up and down in being formed in the medium, 121
121 first groove 14 of dielectric layer, the first groove 14 surround the semiconductor between each semiconductor chip 11
Chip 11.
As an example, the laser that laser 141 is launched can be used in the formation first groove in the dielectric layer 121
14, certainly, in other examples, etching technics or mechanical cutting processes can also be used in formation institute in the dielectric layer 121
State first groove 14.
In step 5), S5 steps and Fig. 6 in please referring to Fig.1, using bonding die film 17 by upper surface formed with described heavy
The wafer 10 of new route layer 12 and the solder projection 13 is adhered on a cutting indigo plant film 15, the lower surface of the wafer 10
(back side of i.e. described wafer 10) is in contact with the bonding die film 17.
As an example, the top of the blue film 15 of cutting is formed with the iron ring 16 for fixing the blue film 15 of the cutting.
As an example, the bonding die film 17 can be the bonding die film 17 can be DAF (die-attach film) or
BSL films (Backside lamination film, back side dry film), it is preferable that the bonding die film 17 is to include the first glue-line, height
The laminated construction of heat-conducting resin layer and the second glue-line, first glue-line, the high thermal conductive resin layer and second glue-line according to
It is secondary stacked.Due to being provided with bonding die film 17 between the wafer 10 and the blue film 15 of cutting, can strengthen the wafer 10 with
The adhesion of the blue film 15 of cutting, during cutting, the wafer 10 will not shake, so as to ensure cutting
Accuracy.
In step 6), S6 and Fig. 6 in please referring to Fig.1, second groove 18 is formed immediately below in the first groove 14,
The second groove runs through the wafer 10 and the bonding die film 17 about 18, and extends in the blue film 15 of the cutting, with
To be separated from each other, front formed with the re-wiring layer 12 and solder projection 13 and the back side is formed with the bonding die film 17
Semiconductor chip 11.
As an example, the laser that laser 141 is launched can be used to be formed immediately below described the in the first groove 14
Two grooves 18, certainly, in other examples, can also use etching technics or mechanical cutting processes in the first groove 14 just
The second groove 18 formed below.
In step 7), the S7 in please referring to Fig.1) step and Fig. 7 to Fig. 9, there is provided a carrier 19, step 6) is obtained
Each semiconductor chip 11 is removed from the blue film 15 of the cutting and adheres on the surface of the carrier 19, the bonding die film 17
It is in contact with the surface of the carrier 19, and there is spacing between the adjacent semiconductor chip 11.
As an example, the carrier 19 can be glass carrier, ceramic monolith or wafer etc., do not limit herein.
As an example, as shown in figure 8, each semiconductor chip 11 that step 6) is obtained adheres on the carrier 19
Before surface, further include in the carrier 19 surface formed peel ply 21 the step of.
It should be noted that when the surface of the carrier 19 is formed with the peel ply 21, each institute that step 6) obtains
The surface that semiconductor chip 11 adheres on the peel ply 21 is stated, and the bonding die film 17 is connected with the surface of the peel ply 21
Meet place；I.e. described peel ply 21 is between the bonding die film 17 and the carrier 19.
As an example, bonding back tracking method (bond-on-trace) can be used to use bonding die film 14 by the semiconductor core
Piece 11 face-up adheres on the upper surface of the carrier 19.The bonding back tracking method is known to those skilled in the art, herein not
Tire out again and state.Certainly, the semiconductor chip 11 can also be adhered on using a kind of any other bonding method in the present embodiment
The upper surface of the carrier 19, as shown in Figure 9.
In step 8), S8 steps and Figure 10 in please referring to Fig.1, protection materials are formed in the upper surface of the carrier 19
Layer 20, the protected material bed of material 20 fills up the semiconductor chip 11, the re-wiring layer 12, the solder projection 13 and institute
State the gap between bonding die film 17, and by the semiconductor chip 11, the re-wiring layer 12, the solder projection 13 and institute
State 17 plastic packaging of bonding die film.
As an example, as an example, can use compressing and forming process, transfer modling technique, hydraulic seal moulding process,
Molded underfill technique, capillary underfill technique, vacuum lamination process or spin coating proceeding are in the upper surface of the carrier 19
Form the protected material bed of material 20.Preferably, in the present embodiment, formed and protected in the upper surface of the carrier 19 using transfer modling technique
Protective material layer 20.
As an example, the protected material bed of material 20 is high polymer waterproof material layer；Preferably, in the present embodiment, the guarantor
Protective material layer 20 for epoxy resin layer by layer.
As an example, the upper surface of the protected material bed of material 20 is not higher than the upper surface of the solder projection 13, i.e., it is described
The upper surface of the protected material bed of material 20 is less than the upper surface of the solder projection 13 or upper surface and the institute of the protected material bed of material 20
State the upper surface flush of solder projection 13.Since the back side of the semiconductor chip 11 is equipped with the bonding die film 17, in plastic packaging
During, the semiconductor chip 11 will not shake, so as to ensure preferable plastic packaging effect.
It should be noted that when the upper surface of the carrier 19 is formed with the peel ply 21, the protected material bed of material
20 are formed at the upper surface of the peel ply 21.
In step 9), S9 steps and Figure 11 in please referring to Fig.1, remove the carrier 19.
As an example, grinding technics, reduction process etc. can be used to be removed the carrier 19 and the peel ply 21.
Preferably, in the present embodiment, the peel ply 21 is UV adhesive tapes, can use the mode for tearing the peel ply 21 to remove
State carrier 19.
In step 10), S10 steps and Figure 12 to Figure 14 in please referring to Fig.1, the structure that step 9) is obtained are cut
Cut, to obtain the wafer stage chip encapsulating structure.
As an example, the structure that step 9) is obtained is cut, included with obtaining the wafer stage chip encapsulating structure
Following steps：
10-1) structure for obtaining step 9) is adhered on a cutting indigo plant film 15, as shown in figure 12；
10-2) cut from the region between the semiconductor chip 11, as shown in figure 13, after cutting, will be cut
The wafer stage chip encapsulating structure is removed and obtained to the structure cut from the blue film 15 of the cutting.
As an example, laser cutting parameter can be used or using synthesizing knife between each semiconductor chip 11
Cutting separation is carried out, to obtain including the wafer stage chip encapsulating structure of a semiconductor chip 11, such as Figure 14 institutes
Show.
In another example, laser cutting parameter can also be used or use synthesizing knife from two or more described half
Cutting separation is carried out between conductor chip 11, to obtain the wafer stage chip of two or more semiconductor chips 11 envelope
Assembling structure.
Embodiment two
Please continue to refer to Figure 14, the present embodiment also provides a kind of wafer stage chip encapsulating structure, the wafer stage chip envelope
Assembling structure can use but be not limited only to the preparation method of the wafer stage chip encapsulating structure described in embodiment one and be prepared
Arrive, the wafer stage chip encapsulating structure includes：Semiconductor chip 11；Re-wiring layer 12, the re-wiring layer 12 are located at
The front of the semiconductor chip 11, and be electrically connected with the semiconductor chip 11；Solder projection 13, the solder projection 13
It is electrically connected in surface of the re-wiring layer 12 away from the semiconductor chip 11, and with the re-wiring layer 12；Bonding die
Film 17, the bonding die film 17 are located at the back side of the semiconductor chip 11；The protected material bed of material 20,20 plastic packaging of the protected material bed of material
In the periphery of the semiconductor chip 11, the re-wiring layer 12, the solder projection 13 and the bonding die film 17, the guarantor
The upper surface of protective material layer 20 is not higher than the upper surface of the solder projection 13, and the lower surface of the protected material bed of material 20 and institute
State the lower surface flush of bonding die film 17.
In one example, the re-wiring layer 12 includes：Dielectric layer 121, the dielectric layer 121 are located at the semiconductor
The front of chip 11；Metal line layer 1221, the metal line layer 1221 is located in the dielectric layer 121 and the dielectric layer 121
Surface, and be electrically connected with semiconductor chip 11 and the solder projection 13.
In another example, the re-wiring layer 12 includes：First medium layer 1211,1211, the first medium layer
In the front of the semiconductor chip 11；At least one layer of metal line layer 1221, the metal line layer 1221 are situated between positioned at described first
In matter layer 1211, and it is electrically connected with the semiconductor chip 11；Second dielectric layer 1212, the second dielectric layer 1212 are covered in
The upper surface of the first medium layer 1211 and the metal line layer 121；Underbump metallization layer 1222, the Underbump metallization layer
1222 in the second dielectric layer 1211 and 1212 surface of second dielectric layer, and with the metal line layer 1221 and institute
Solder projection 13 is stated to be electrically connected.The first medium layer 1211 collectively forms the rewiring with the second dielectric layer 1212
The dielectric layer 121 of layer 12, the metal line layer 1221 collectively form the re-wiring layer with the Underbump metallization layer 1222
12 metal connecting line layer 122.
As an example, the protected material bed of material 20 is high polymer waterproof material layer；Preferably, in the present embodiment, the guarantor
Protective material layer 20 for epoxy resin layer by layer.
As an example, the bonding die film 17 is DAF films or BSL films.Preferably, in the present embodiment, the bonding die film 17 is
Include the laminated construction of the first glue-line, high thermal conductive resin layer and the second glue-line, first glue-line, the high thermal conductive resin layer and
Second glue-line is sequentially stacked.
In one example, the solder projection 13 includes：Metal column, it is remote that the metal column is located at the re-wiring layer 12
It is electrically connected from the surface of the semiconductor chip 11, and with the re-wiring layer 12；Soldered ball, the soldered ball are located at the metal
The surface of the remote semiconductor chip 11 of column.
In another example, as shown in figure 14, the solder projection 13 is soldered ball.
In one example, as shown in figure 14, in the wafer stage chip encapsulating structure semiconductor chip 11 quantity
For one.
In another example, the quantity of the semiconductor chip 11 is at least two in the wafer stage chip encapsulating structure
It is a, there is spacing between the adjacent semiconductor chip 11.
In conclusion the wafer stage chip encapsulating structure of the utility model, the wafer stage chip encapsulating structure includes：Half
Conductor chip；Re-wiring layer, is electrically connected positioned at the front of the semiconductor chip, and with the semiconductor chip；Solder is convex
Block, is electrically connected positioned at surface of the re-wiring layer away from the semiconductor chip, and with the re-wiring layer；Bonding die
Film, positioned at the back side of the semiconductor chip；The protected material bed of material, plastic packaging is in the semiconductor chip, the re-wiring layer, institute
The periphery of solder projection and the bonding die film is stated, the upper surface of the protected material bed of material is not higher than the upper table of the solder projection
Face, and the lower surface of the protected material bed of material and the lower surface flush of the bonding die film.The wafer stage chip of the utility model
Encapsulating structure at the back side of semiconductor chip by setting bonding die film so that the bonding force of semiconductor chip and carrier increases
Add, semiconductor chip can be caused to fit in the upper surface of the blue film of cutting or carrier securely, it can be ensured that in follow-up plastic packaging
It will not shake etc. semiconductor chip in preparation process, so that it is guaranteed that the performance of wafer stage chip encapsulating structure；Bonding die film is made
For the back-protective layer of semiconductor chip, it can prevent the back side of semiconductor chip from rupturing；Bonding die film and the protected material bed of material
It can realize the six dough models envelope to semiconductor chip, whole plastic packaging process is simple, and cost is relatively low；The protected material bed of material will partly be led
The side wall plastic packaging of body chip and dielectric layer, you can effectively to avoid the steam of outside from penetrating into dielectric layer so that dielectric layer is not
It is easily broken, and the firm dielectric layer can be played, effect of the external force to the medium damage layer is prevented, so that this reality
Be not in slight crack in cutting process with the dielectric layer in new, and then ensure that the performance of encapsulation chip.
The above embodiments are only illustrative of the principle and efficacy of the utility model, new not for this practicality is limited
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
God and all equivalent modifications completed under technological thought or change, should be covered by the claim of the utility model.
Claims (10)
1. a kind of wafer stage chip encapsulating structure, it is characterised in that the wafer stage chip encapsulating structure includes：
Semiconductor chip；
Re-wiring layer, is electrically connected positioned at the front of the semiconductor chip, and with the semiconductor chip；
Solder projection, positioned at surface of the re-wiring layer away from the semiconductor chip, and it is electric with the re-wiring layer
Connection；
Bonding die film, positioned at the back side of the semiconductor chip；
The protected material bed of material, plastic packaging is in the semiconductor chip, the re-wiring layer, the solder projection and the bonding die film
Periphery, the upper surface of the protected material bed of material are not higher than the upper surface of the solder projection, and the following table of the protected material bed of material
Face and the lower surface flush of the bonding die film.
2. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the re-wiring layer includes：
Dielectric layer, positioned at the front of the semiconductor chip；
Metal line layer, in the dielectric layer and the dielectric layer surface, and with semiconductor chip and solder projection electricity
Connection, metal connecting line layer of the metal line layer as the re-wiring layer.
3. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the re-wiring layer includes：
First medium layer, positioned at the front of the semiconductor chip；
At least one layer of metal line layer, is electrically connected in the first medium layer, and with the semiconductor chip；
Second dielectric layer, is covered in the upper surface of the first medium layer and the metal line layer；
Underbump metallization layer, in the second dielectric layer and the second medium layer surface, and with the metal line layer and
The solder projection is electrically connected；Wherein,
The first medium layer collectively forms the dielectric layer of the re-wiring layer, the metal line layer with the second dielectric layer
The metal connecting line layer of the re-wiring layer is collectively formed with the Underbump metallization layer.
4. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the protected material bed of material is macromolecule
Waterproof layer.
5. wafer stage chip encapsulating structure according to claim 4, it is characterised in that the protected material bed of material is asphalt mixtures modified by epoxy resin
Lipid layer.
6. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the bonding die film is DAF films or BSL
Film.
7. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the solder projection includes：
Metal column, is electrically connected positioned at surface of the re-wiring layer away from the semiconductor chip, and with the re-wiring layer
Connect；
Soldered ball, positioned at the surface of the remote semiconductor chip of the metal column.
8. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the solder projection is soldered ball.
9. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the wafer stage chip encapsulating structure
The quantity of the interior semiconductor chip is one.
10. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the wafer stage chip encapsulation knot
The quantity of the semiconductor chip is at least two in structure, has spacing between the adjacent semiconductor chip.
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| CN107611097A (en) * | 2017-10-13 | 2018-01-19 | 中芯长电半导体（江阴）有限公司 | Wafer stage chip encapsulating structure and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107611097A (en) * | 2017-10-13 | 2018-01-19 | 中芯长电半导体（江阴）有限公司 | Wafer stage chip encapsulating structure and preparation method thereof |
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Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |
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