CN207250483U - Wafer stage chip encapsulating structure - Google Patents
Wafer stage chip encapsulating structure Download PDFInfo
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- CN207250483U CN207250483U CN201721319985.XU CN201721319985U CN207250483U CN 207250483 U CN207250483 U CN 207250483U CN 201721319985 U CN201721319985 U CN 201721319985U CN 207250483 U CN207250483 U CN 207250483U
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- encapsulating structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
The utility model provides a kind of wafer stage chip encapsulating structure, and structure includes：Semiconductor chip；Re-wiring layer, is electrically connected positioned at the front of semiconductor chip, and with semiconductor chip；Solder projection, positioned at surface of the re-wiring layer away from semiconductor chip, and is electrically connected with re-wiring layer；And the protected material bed of material, plastic packaging is in the periphery of semiconductor chip, re-wiring layer and solder projection, and the upper surface of the protected material bed of material is not higher than the upper surface of solder projection, the lower surface of the protected material bed of material and the back side flush of semiconductor chip.Encapsulating structure provided by the utility model and method; the protected material bed of material is by semiconductor chip and the side wall plastic packaging of dielectric layer; it is possible to prevente effectively from exterior steam is penetrated into dielectric layer; so that dielectric layer do not allow it is easily rupturable; prevent effect of the external force to the medium damage layer; five face encapsulating structures and six face encapsulating structures can be formed, process costs are low, and material structure is simple.
Description
Technical field
The utility model belongs to technical field of semiconductor encapsulation, more particularly to a kind of wafer stage chip encapsulating structure.
Background technology
As the integrated circuit that the function of integrated circuit is increasingly stronger, performance and integrated level are higher and higher and new goes out
Existing, encapsulation technology plays an increasingly important role in IC products, shared in the value of whole electronic system
Ratio it is increasing.Meanwhile as integrated circuit feature size reaches nanoscale, transistor to more high density, higher when
Clock frequency develops, and encapsulation also develops to more highdensity direction.
, can be in wafer in order to meet the needs of small size development in existing wafer stage chip encapsulating structure (WLCSP)
Low-k dielectric layer (for example, re-wiring layer) is used in level chip-packaging structure, and to be subsequently cut by laser (laser
Saw) or blade cuts (blade saw)；But since low-k dielectric layer is more crisp, especially big compression ring is exposed in low-k dielectric layer
In border, after the steam in air is entered in low-k dielectric layer so that low-k dielectric layer meeting in follow-up cutting process
Slight crack (crack) is easily produced, and the presence of slight crack can seriously affect the performance of encapsulation chip in low-k dielectric layer.Meanwhile cutting
During cutting, due to semiconductor chip the back side directly it is exposed outside, it is easy to cause semiconductor chip to occur from the back side broken
The problems such as splitting (chipping).
Therefore it provides one kind can protect low-k dielectric layers and prevent from causing low-k dielectric layer to produce slight crack in cutting process
Wafer stage chip encapsulating structure and preparation method thereof be necessary.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of encapsulation of wafer stage chip
Structure, for solution, low-k dielectric layers solution receives moisture infiltration and low k dielectric is easy to cause in cutting process in the prior art
Layer produces the problem of slight crack etc..
In order to achieve the above objects and other related objects, the utility model provides a kind of wafer stage chip encapsulating structure, institute
Stating wafer stage chip encapsulating structure includes：
Semiconductor chip；
Re-wiring layer, is electrically connected positioned at the front of the semiconductor chip, and with the semiconductor chip；
Solder projection, positioned at surface of the re-wiring layer away from the semiconductor chip, and with the rewiring
Layer is electrically connected；And
The protected material bed of material, plastic packaging in the periphery of the semiconductor chip, the re-wiring layer and the solder projection,
And the upper surface of the protected material bed of material is not higher than the upper surface of the solder projection, the lower surface of the protected material bed of material and institute
State the back side flush of semiconductor chip.
As a kind of preferred solution of the utility model, the protected material bed of material is high polymer waterproof material layer.
As a kind of preferred solution of the utility model, the protected material bed of material is epoxy resin layer.
As a kind of preferred solution of the utility model, the re-wiring layer includes：
Dielectric layer, positioned at the front of the semiconductor chip；And
Metal connecting line layer, is located at least in the dielectric layer, and the metal connecting line layer realize the semiconductor chip with
The electrical connection of the solder projection.
As a kind of preferred solution of the utility model, the re-wiring layer includes：
First medium layer, positioned at the front of the semiconductor chip；
At least one layer of metal line layer, is electrically connected in the first medium layer, and with the semiconductor chip；
Second dielectric layer, is covered in the upper surface of the first medium layer and the metal line layer；And
Underbump metallization layer, in the second dielectric layer and the second medium layer surface, and with the metal wire
Layer and the solder projection are electrically connected.
As a kind of preferred solution of the utility model, the solder projection includes：
Metal column, positioned at surface of the re-wiring layer away from the semiconductor chip, with re-wiring layer electricity
Connection；Soldered ball, positioned at the surface of the remote semiconductor chip of the metal column.
As a kind of preferred solution of the utility model, the solder projection includes soldered ball.
As a kind of preferred solution of the utility model, the semiconductor chip in the wafer stage chip encapsulating structure
Quantity is one.
As a kind of preferred solution of the utility model, the semiconductor chip in the wafer stage chip encapsulating structure
Quantity is at least two, and has spacing between the adjacent semiconductor chip.
As a kind of preferred solution of the utility model, the wafer stage chip encapsulating structure further includes protective underlayer layer,
The protective underlayer layer is with the protected material bed of material jointly by the semiconductor chip, the re-wiring layer and the solder
Convex block plastic packaging.
The utility model also provides a kind of preparation method of wafer stage chip encapsulating structure, includes the following steps：
1) wafer is provided, the wafer is interior formed with several semiconductor chips；
2) re-wiring layer is formed in the wafer upper surface, the re-wiring layer is electrically connected with the semiconductor chip
Connect, the re-wiring layer includes dielectric layer and in the dielectric layer and the metal that is located at least in the dielectric layer connects
Line layer；Solder projection is formed in the re-wiring layer upper surface, and the solder projection is electrically connected with the metal connecting line layer；
3) in being formed in the dielectric layer up and down through the first groove of the dielectric layer, the first groove, which corresponds to, to be located at
Between each semiconductor chip, and around the semiconductor chip；
4) the obtained structure of step 3) is shifted and adhered on the first cutting indigo plant film, and the back of the body of the semiconductor chip
Face is in contact with the described first blue film of cutting, is correspondingly formed second groove below the first groove, in the second groove
Run through the wafer down, with the semiconductor chip formed with re-wiring layer and solder projection be separated from each other and positive；
5) carrier is provided, the obtained each semiconductor chip of step 4) is removed from the blue film of the described first cutting
And the upper surface of the carrier is adhered on, the back side of the semiconductor chip is in contact with the upper surface of the carrier, the crystalline substance
The round back side is in contact with the upper surface of the carrier, and has spacing between the adjacent semiconductor chip；
6) the protected material bed of material is formed in the upper surface of the carrier, the protected material bed of material fills up each semiconductor core
Gap between piece, the re-wiring layer and the solder projection, and by the semiconductor chip, the re-wiring layer
And the solder projection plastic packaging, and the upper surface of the protected material bed of material is not higher than the upper surface of the solder projection；And
7) remove the carrier, and cut the structure after the carrier is removed, to obtain the wafer stage chip
Encapsulating structure.
As a kind of preferred solution of the utility model, step 4) further includes step：One retainer ring is provided, and by described
The blue film of one cutting is fixed in the retainer ring.
As a kind of preferred solution of the utility model, in step 7), the structure after the carrier will be removed and cut
The step of include：
The structure after the carrier 7-1) will be removed and adhere on the second cutting indigo plant film surface, and the back of the body of the semiconductor chip
Face is in contact with the blue film of the described second cutting；
The protected material bed of material 7-2) is cut from the region between the semiconductor chip, and it is blue to remove second cutting
Film, to obtain the protected material bed of material plastic packaging in outside the semiconductor chip, the re-wiring layer and the solder projection
The wafer stage chip encapsulating structure enclosed.
As a kind of preferred solution of the utility model, in step 5), by the obtained each semiconductor core of step 4)
Before piece adheres on the upper surface of the carrier, further include in the carrier upper surface formed peel ply the step of.
As described above, the wafer level packaging structure of the utility model, has the advantages that：
1) encapsulating structure provided by the utility model and method, the protected material bed of material is by semiconductor chip and the side wall of dielectric layer
Plastic packaging, it is possible to prevente effectively from exterior steam is penetrated into dielectric layer so that dielectric layer is not allowed easily rupturable, and can play firm
The dielectric layer, prevents effect of the external force to the medium damage layer, so that the dielectric layer in the utility model is being cut
During be not in slight crack, and then ensure that encapsulation chip performance；
2) encapsulating structure provided by the utility model and method, can form the five face encapsulating structures and six of semiconductor chip
Face encapsulating structure, selects, process costs are low, and material structure is simple according to actual demand.
Brief description of the drawings
Fig. 1 is shown as the flow of the preparation method of the wafer stage chip encapsulating structure provided in the utility model embodiment
Figure.
The preparation method that Fig. 2~Figure 15 is shown as the wafer stage chip encapsulating structure provided in the utility model embodiment is each
The structure diagram that step is presented, wherein：
Fig. 2 is shown as providing the structure diagram of wafer in the preparation method of the encapsulating structure of the present invention；
Fig. 3 is shown as being formed the structure diagram of re-wiring layer in the preparation method of the encapsulating structure of the present invention；
Fig. 4 is shown as being formed the structure diagram of solder projection in the preparation method of the encapsulating structure of the present invention；
Fig. 5 is shown as being formed the structure diagram of first groove in the preparation method of the encapsulating structure of the present invention；
Fig. 6 is shown as being formed the structure diagram of second groove in the preparation method of the encapsulating structure of the present invention；
Fig. 7 is shown as providing the structure diagram of carrier in the preparation method of the encapsulating structure of the present invention；
Fig. 8 is shown as being formed the structure diagram of peel ply in the preparation method of the encapsulating structure of the present invention；
Fig. 9 is shown as the signal being positioned over semiconductor chip in the preparation method of the encapsulating structure of the present invention on carrier
Figure；
Figure 10 is shown as being formed the structure diagram of the protected material bed of material in the preparation method of the encapsulating structure of the present invention；
Figure 11 is shown as removing the structure diagram of carrier in the preparation method of the encapsulating structure of the present invention；
Figure 12 is shown as the semiconductor chip formed with the protected material bed of material in the preparation method of the encapsulating structure of the present invention
The structure diagram being positioned on the second cutting indigo plant film；
Figure 13 is shown as cutting the schematic diagram of the protected material bed of material in the preparation method of the encapsulating structure of the present invention；
Figure 14 is shown as the structure diagram of the wafer stage chip encapsulating structure of the present invention.
Figure 15 is shown as the structure diagram of another wafer stage chip encapsulating structure of the present invention.
Component label instructions
10 wafers
11 semiconductor chips
111 connection weld pads
12 re-wiring layers
121 dielectric layers
1211 first medium layers
1212 second dielectric layer
122 metal connecting line layers
1221 metal line layers
1222 Underbump metallization layers
13 solder projections
14 first grooves
141 lasers
The blue film of 15 first cuttings
16 retainer rings
17 second grooves
18 carriers
19 peel plies
The 20 protected material bed of materials
The blue film of 21 second cuttings
22 synthesizing knives
23 protective underlayer layers
S1~Sn steps
Embodiment
Illustrate the embodiment of the utility model below by way of specific instantiation, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints with answering
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Please refer to Fig.1 to Figure 15.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though when only display is with related component in the utility model rather than according to actual implementation in diagram
Component count, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during its actual implementation
Become, and its assembly layout form may also be increasingly complex.
As shown in Fig. 1~15, the present embodiment provides a kind of preparation method of wafer stage chip encapsulating structure, including following step
Suddenly：
1) wafer is provided, the wafer is interior formed with several semiconductor chips；
2) re-wiring layer is formed in the wafer upper surface, the re-wiring layer is electrically connected with the semiconductor chip
Connect, the re-wiring layer includes dielectric layer and the metal connecting line layer being located at least in the dielectric layer；In the cloth again
Line layer upper surface forms solder projection, and the solder projection is electrically connected with the metal connecting line layer；
3) in being formed in the dielectric layer up and down through the first groove of the dielectric layer, the first groove, which corresponds to, to be located at
Between each semiconductor chip, and around the semiconductor chip；
4) the obtained structure of step 3) is shifted and adhered on the first cutting indigo plant film, and the back of the body of the semiconductor chip
Face is in contact with the described first blue film of cutting, is correspondingly formed second groove below the first groove, in the second groove
Run through the wafer down, with the semiconductor chip formed with re-wiring layer and solder projection be separated from each other and positive；
5) carrier is provided, the obtained each semiconductor chip of step 4) is removed from the blue film of the described first cutting
And the upper surface of the carrier is adhered on, the back side of the semiconductor chip is in contact with the upper surface of the carrier, the crystalline substance
The round back side is in contact with the upper surface of the carrier, and has spacing between the adjacent semiconductor chip；
6) the protected material bed of material is formed in the upper surface of the carrier, the protected material bed of material fills up each semiconductor core
Gap between piece, the re-wiring layer and the solder projection, and by the semiconductor chip, the re-wiring layer
And the solder projection plastic packaging, and the upper surface of the protected material bed of material is not higher than the upper surface of the solder projection；And
7) carrier is removed, the structure after the carrier will be removed and cut, obtain the wafer stage chip encapsulation
Structure.
The preparation method of wafer stage chip encapsulating structure provided in this embodiment is illustrated below in conjunction with attached drawing.
As shown in S1 and Fig. 2 in Fig. 1, step 1) is carried out, there is provided a wafer 10, the wafer 10 are interior formed with several
Semiconductor chip 11；
Specifically, the wafer 10 can be Silicon Wafer, sapphire wafer or gallium nitride wafer etc.；Preferably, this implementation
In example, the wafer 10 is Silicon Wafer.
In addition, the semiconductor chip 11 can be any one semiconductor functional chip, the semiconductor chip 11
Front is exposed to institute formed with the connection weld pad 111 for drawing its inside function device electricity, the upper surface of the connection weld pad 111
State the upper surface of semiconductor chip 11, i.e., the upper surface of described connection weld pad 111 and the upper surface phase of the semiconductor chip 11
Concordantly, certainly, in other embodiments, based on actual demand, the surface of the connection weld pad 111 can also be arranged at and be higher than
The surface of the semiconductor chip, is not particularly limited herein.
As shown in the S2 in Fig. 1 and Fig. 3~4, step 2) is carried out, re-wiring layer is formed in 10 upper surface of wafer
12, the re-wiring layer 12 is electrically connected with the semiconductor chip 11, the re-wiring layer 12 include dielectric layer 121 and
The metal connecting line layer 122 being located at least in the dielectric layer 121；Solder projection is formed in 12 upper surface of re-wiring layer
13, and the solder projection 13 is electrically connected with the metal connecting line layer 122；
Specifically, in one example, forming the re-wiring layer 12 in the upper surface of the wafer 10 includes following step
Suddenly：
2-1) first medium layer 1211 is formed in the upper surface of the wafer 10；
2-2) in forming the first opening (not shown) in the first medium layer 1211, first opening exposes described
Connect weld pad 111；
2-3) in the described first opening and the first medium layer 1211 of first mouth periphery upper surface shape
Into metal line layer 1221, the metal line layer 1221 is connected with the connection weld pad 111；
2-4) second dielectric layer 1212 is formed in the upper surface of the metal line layer 1221 and the first medium layer 1211；
2-5) in forming the second opening (not shown) in the second dielectric layer 1212, second opening exposes described
Metal line layer 1221；
2-6) in the described second opening and the second dielectric layer 1212 of second mouth periphery upper surface shape
Into Underbump metallization layer 1222, the Underbump metallization layer 1222 is connected with the metal line layer 1221.
Certainly, in other examples, existing any one re-wiring layer preparation process can also be used to prepare includes
The re-wiring layer 12 of the dielectric layer 121, the metal line layer 1221 and the Underbump metallization layer 1222.
It should be noted that the first medium layer 1211 and the second dielectric layer 1212 can be Jie of identical material
Matter layer.The first medium layer 1211 collectively forms the dielectric layer of the re-wiring layer 12 with the second dielectric layer 1212
121, the metal line layer 1221 collectively forms the metal connecting line of the re-wiring layer 12 with the Underbump metallization layer 1222
Layer 122.In addition, in other examples, multilayer dielectricity layer unit, and multilayer can also be included in the first medium layer 1211
Metal line layer, particular number are set according to actual demand.
In another example, the re-wiring layer 12 includes one layer of dielectric layer 121 and one layer of metal line layer 1221, in institute
The upper surface for stating wafer 10 forms the re-wiring layer 12 and includes the following steps：
2-1) dielectric layer 121 is formed in the upper surface of the wafer 10；
2-2) in forming opening (not shown) in the dielectric layer 121, the opening exposes the connection weld pad 111；
2-3) in the opening and the dielectric layer 121 of the mouth periphery upper surface formed metal line layer
1221, the metal line layer 1221 is connected with the connection weld pad 111.
That is, in this example, the re-wiring layer of formation is simply formed with one layer of dielectric layer and metal connecting line layer.
For the solder projection 13 formed in the step, in one example, in the upper table of the re-wiring layer 12
Face forms solder projection 13 and includes the following steps：
A) metal column is formed in the upper surface of the re-wiring layer 12；
B) soldered ball is formed in the upper surface of the metal column.
Specifically, the material of the metal column can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds and two
The combined material of the kind above, can pass through physical gas-phase deposition (PVD), chemical vapor deposition method (CVD), sputtering, electricity
Any of plating or chemical plating technique form the metal column.The material of the soldered ball can be copper, aluminium, nickel, gold, silver, titanium
In a kind of material or two kinds and two or more combined materials, the soldered ball can be formed by planting ball reflux technique.
In another example, the solder projection 13 is a soldered ball, can directly form weldering by planting ball reflux technique
Ball is as the solder projection 13.
Specifically, when the metal connecting layer 122 in the re-wiring layer 12 includes metal line layer 1221 and described
During Underbump metallization layer 1222, the solder projection 13 is formed at the upper surface of the Underbump metallization layer 1222；When described heavy
When the metal connecting layer 122 in new route layer 12 only includes the metal line layer 1221, the solder projection 13 is formed at
The upper surface of the metal line layer 1221.
As shown in S3 and Fig. 5 in Fig. 1, step 3) is carried out, runs through the medium up and down in being formed in the dielectric layer 121
The first groove 14 of layer 121, the first groove 14 are corresponded between each semiconductor chip 11, and are partly led around described
Body chip 11；
Specifically, the laser that laser 141 is launched can be used in the formation first groove in the dielectric layer 121
14, certainly, in other examples, etching technics or mechanical cutting processes can also be used in formation institute in the dielectric layer 121
First groove 14 is stated, re-wiring layer is cut using laser, protects the internal junction of re-wiring layer to greatest extent
Structure and semiconductor device structure adjacent thereto.
As shown in S4 and Fig. 6 in Fig. 1, step 4) is carried out, the obtained structure of step 3) is shifted and adheres on first
On the blue film 15 of cutting, and the back side of the semiconductor chip 11 is in contact with the blue film 15 of the described first cutting, in first ditch
The lower section of groove 14 is correspondingly formed second groove 17, and the second groove runs through the wafer 10 about 17, with what is be separated from each other
And the positive semiconductor chip 11 formed with re-wiring layer and solder projection；
As an example, using bonding die film by the crystalline substance of the upper surface formed with the re-wiring layer and the solder projection
Circle note is placed on the blue film of the first cutting, and the lower surface of the wafer is in contact with the bonding die film.The bonding die film can be with
Can be DAF (die-attach film) or BSL films for the bonding die film 17, it is preferable that the bonding die film is to include the first glue
The laminated construction of layer, high thermal conductive resin layer and the second glue-line, first glue-line, the high thermal conductive resin layer and second glue
Layer is sequentially stacked.Due to being provided with bonding die film between the wafer and the blue film of cutting, can strengthen the wafer with it is described
The adhesion of the blue film of cutting, during cutting, the wafer will not shake, so as to ensure the accuracy of cutting
A retainer ring 16 is provided specifically, further including, the blue film 15 of the described first cutting is fixed in the retainer ring 16,
The shape of the retainer ring 16 can be circular, rectangle or the shape needed for other, and the blue film 15 of the first cutting has viscous
Property one side phenomena such as being adhesively fixed in the retainer ring 16, the blue film 15 of the described first cutting is fixed, prevents its warpage
Generation, improve stability.
In addition, the material of the retainer ring 16 includes one kind in glass, metal, semiconductor, polymer and ceramics.At this
In embodiment, the material of the retainer ring 16 is glass, and using glass as retainer ring, blue film is cut with described first follow-up
During 15 separation, it is easier to remove, improves separated efficiency and stability.
Specifically, the laser that laser 141 can be used to launch is formed immediately below described second in the first groove 14
Groove 17, certainly, in other examples, can also use etching technics or mechanical cutting processes in the first groove 14 just under
It is square into the second groove 17.In addition, the second groove 17 can be extended in the blue film of the first cutting, to ensure
State semiconductor chip and complete cutting, be unlikely to damage chip in transfer process.
As shown in the S5 in Fig. 1 and Fig. 7~9, step 5) is carried out, there is provided a carrier 18, step 4) is obtained each
The semiconductor chip 11 is removed from the blue film 15 of the described first cutting and adheres on the upper surface of the carrier 18, described partly to lead
The back side of body chip 11 is in contact with the upper surface of the carrier 18, and has spacing between the adjacent semiconductor chip 11；
Specifically, the carrier 18 can be glass carrier, ceramic monolith or wafer etc., do not limit herein.
As an example, as shown in figure 8, each semiconductor chip 11 that step 4) is obtained adheres on the carrier 18
Before surface, further include in the carrier 18 surface formed peel ply 19 the step of.
Specifically, when the surface of the carrier 18 is formed with the peel ply 19, what step 4) obtained each described partly leads
Body chip 11 adheres on the surface of the peel ply 19, and positioned at the back side of the semiconductor chip 11 and the peel ply 19
Surface connection, i.e., described peel ply 19 is between 11 back side of semiconductor chip and the carrier 18.
As shown in S6 and Figure 10 in Fig. 1, step 6) is carried out, the protected material bed of material 20 is formed in the upper surface of the carrier,
The protected material bed of material 20 is filled up between each semiconductor chip 11, the re-wiring layer 12 and the solder projection 13
Gap, and by 13 plastic packaging of the semiconductor chip 11, the re-wiring layer 12 and the solder projection, and the protection
The upper surface of material layer 20 is not higher than the upper surface of the solder projection 13；
Specifically, compressing and forming process, transfer modling technique, hydraulic seal moulding process, molding bottom can be used to fill out
Fill technique, capillary underfill technique, vacuum lamination process or spin coating proceeding and form protected material in the upper surface of the carrier 18
The bed of material 20, it is preferable that in the present embodiment, the protected material bed of material is formed in the upper surface of the carrier 18 using transfer modling technique
20.It should be noted that when the upper surface of the carrier 18 is formed with the peel ply 19, the protected material bed of material 20 is formed
In the upper surface of the peel ply 19.
As an example, the protected material bed of material 20 can be high polymer waterproof material layer；Preferably, in the present embodiment, institute
State 20 selected as epoxy resin layer of the protected material bed of material.
Specifically, the upper surface of the protected material bed of material 20 is not higher than the upper surface of the solder projection 13, i.e., described guarantor
The upper surface of protective material layer 20 less than the solder projection 13 upper surface or the protected material bed of material 20 upper surface with it is described
The upper surface flush of solder projection 13.
As shown in the S7 in Fig. 1 and Figure 11~15, step 7) is carried out, removes the carrier 18, and the carrier will be removed
Structure after 18 is cut, to obtain the wafer stage chip encapsulating structure.
Specifically, grinding technics, reduction process etc. can be used to be removed the carrier 18 and the peel ply 19, it is excellent
Selection of land, in the present embodiment, the peel ply 19 is UV adhesive tapes, and the mode for tearing the peel ply 19 can be used described to remove
Carrier 18, after the step, forms the structure of five faces encapsulation.
As an example, in step 7), will remove the step of structure after the carrier 18 is cut includes：
The structure after the carrier 18 7-1) will be removed and adhere on 21 surface of the second cutting indigo plant film；
The protected material bed of material 20 7-2) is cut from the region between the semiconductor chip 11, and removes described second and cuts
Blue film 21 is cut, to obtain 20 plastic packaging of the protected material bed of material in the semiconductor chip 11, the re-wiring layer 12 and institute
State the wafer stage chip encapsulating structure of the periphery of solder projection 13.
Specifically, can use laser cutting parameter or using synthesizing knife between each semiconductor chip 11 into
Row cutting separation, in another example, can also use laser cutting parameter or use synthesizing knife from two or more institutes
State and carry out cutting separation between semiconductor chip 11, to obtain the wafer scale core of two or more semiconductor chips 11
Chip package, in the present embodiment, selection is cut using synthesizing knife 22, in whole process, using laser and brill
Stone synthesizes the cooperation of knife, can further realize the protection of chip, reduce the infringement to chip.
As an example, the lower surface for further including the wafer stage chip encapsulating structure after cutting forms protective underlayer layer 23
Step, the protective underlayer layer 23 and the protected material bed of material 20 are jointly by the semiconductor chip 11, the rewiring
Layer 12 and the solder projection 13, especially, the low-k dielectric layers employed in the re-wiring layer are able to protected
Come, the failure of the even whole device architecture of chip is further resulted in so as to avoid steam from invading, and after intrusion, so that
Realize the six faces encapsulation of the semiconductor chip.
It should be noted that the protected material bed of material and the protective underlayer layer formed below, by semiconductor chip and dielectric layer
Side wall plastic packaging, it is possible to prevente effectively from exterior steam is penetrated into dielectric layer so that dielectric layer is not allowed easily rupturable, and can rise
To the firm dielectric layer, effect of the external force to the medium damage layer is prevented, so that the dielectric layer in the utility model
Be not in slight crack in cutting process, and then ensure that the performance of encapsulation chip.
As shown in Figure 14 and Figure 15, the utility model also provides a kind of wafer stage chip encapsulating structure, states wafer stage chip
Encapsulating structure include but are not limited to prepare using the preparation method of the wafer stage chip encapsulating structure described in the present embodiment and
Obtained structure, the wafer stage chip encapsulating structure include：
Semiconductor chip 11；
Re-wiring layer 12, is electrically connected positioned at the front of the semiconductor chip 11, and with the semiconductor chip 11；
Solder projection 13, positioned at surface of the re-wiring layer 12 away from the semiconductor chip 11, and with it is described heavy
New route layer 12 is electrically connected；And
The protected material bed of material 20, plastic packaging is in the semiconductor chip 11, the re-wiring layer 12 and the solder projection
13 periphery, and the upper surface of the protected material bed of material 20 is not higher than the upper surface of the solder projection 13, the protection materials
The lower surface of layer 20 and the back side flush of the semiconductor chip 11.
As an example, the protected material bed of material 20 is high polymer waterproof material layer, it is preferable that the protected material bed of material 20 is
Epoxy resin layer.
It should be noted that the protected material bed of material by semiconductor chip and the side wall plastic packaging of dielectric layer, can effectively be kept away
The steam for exempting from outside is penetrated into dielectric layer so that dielectric layer is not allowed easily rupturable, and can play the firm dielectric layer, prevent
Effect of the external force to the medium damage layer, so that the dielectric layer in the utility model is not in split in cutting process
Trace, and then ensure that the performance of encapsulation chip, certainly, the material of the protected material bed of material 20 can be above-mentioned arbitrarily to have the function of
Material layer, be not particularly limited herein.
As an example, the re-wiring layer 12 includes：
Dielectric layer 121, positioned at the front of the semiconductor chip 11；And metal connecting line layer 122, it is located at least in being given an account of
In matter layer 121, and the metal connecting line layer 122 realizes being electrically connected for the semiconductor chip 11 and the solder projection 13.
In another example, the re-wiring layer 12 includes：
First medium layer 1211, positioned at the front of the semiconductor chip 11；
Metal line layer 1221, in the first medium layer 1211, is electrically connected with the semiconductor chip 11；
Second dielectric layer 1212, is covered in the upper surface of the first medium layer 1211 and the metal line layer 1221；With
And
Underbump metallization layer 1222, in the second dielectric layer 1212 and 1212 surface of second dielectric layer, and
It is electrically connected with the metal line layer 1221 and the solder projection 13.Wherein, the first medium layer 1211 is situated between with described second
Matter layer 1212 collectively forms the dielectric layer 121 of the re-wiring layer 12, the metal line layer 1221 and the Underbump metallization
Layer 1222 collectively forms the metal connecting line layer 122 of the re-wiring layer 12.
As an example, the solder projection 13 includes：Metal column, positioned at the re-wiring layer 12 away from the semiconductor
The surface of chip 11, is electrically connected with the re-wiring layer 12；And soldered ball, positioned at the remote semiconductor of the metal column
The surface of chip 11.
In another example, the solder projection 13 includes soldered ball.
As an example, the quantity of the semiconductor chip 11 is one in the wafer stage chip encapsulating structure.
As an example, the quantity of the semiconductor chip 11 is at least two in the wafer stage chip encapsulating structure, and
There is spacing between the adjacent semiconductor chip 11.
As an example, the wafer stage chip encapsulating structure further includes protective underlayer layer 23, the protective underlayer layer 23 with
The protected material bed of material 20 jointly moulds the semiconductor chip 11, the re-wiring layer 12 and the solder projection 13
Envelope.
In conclusion the utility model provides a kind of wafer stage chip encapsulating structure, encapsulating structure includes：Semiconductor core
Piece；Re-wiring layer, is electrically connected positioned at the front of the semiconductor chip, and with the semiconductor chip；Solder projection, is located at
Surface of the re-wiring layer away from the semiconductor chip, and be electrically connected with the re-wiring layer；And protection materials
Layer, plastic packaging is in the periphery of the semiconductor chip, the re-wiring layer and the solder projection, and the protected material bed of material
Upper surface be not higher than the upper surface of the solder projection, the lower surface of the protected material bed of material and the back of the body of the semiconductor chip
Face flush.Through the above technical solutions, encapsulating structure provided by the utility model and method, the protected material bed of material is by semiconductor core
The side wall plastic packaging of piece and dielectric layer, it is possible to prevente effectively from exterior steam is penetrated into dielectric layer so that dielectric layer is not allowed fragile
Split, and the firm dielectric layer can be played, effect of the external force to the medium damage layer is prevented, so that the utility model
In dielectric layer be not in slight crack in cutting process, and then ensure that encapsulation chip performance；It is provided by the utility model
Encapsulating structure and method, can form the five face encapsulating structures and six face encapsulating structures of semiconductor chip, be selected according to actual demand
Select, process costs are low, and material structure is simple.So the utility model effectively overcomes various shortcoming of the prior art and has
High industrial utilization.
The above embodiments are only illustrative of the principle and efficacy of the utility model, new not for this practicality is limited
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
God and all equivalent modifications completed under technological thought or change, should be covered by the claim of the utility model.
Claims (10)
1. a kind of wafer stage chip encapsulating structure, it is characterised in that the wafer stage chip encapsulating structure includes：
Semiconductor chip；
Re-wiring layer, is electrically connected positioned at the front of the semiconductor chip, and with the semiconductor chip；
Solder projection, positioned at surface of the re-wiring layer away from the semiconductor chip, and it is electric with the re-wiring layer
Connection；And
The protected material bed of material, plastic packaging is in the periphery of the semiconductor chip, the re-wiring layer and the solder projection, and institute
The upper surface for stating the protected material bed of material is not higher than the upper surface of the solder projection, the lower surface of the protected material bed of material and described half
The back side flush of conductor chip.
2. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the protected material bed of material includes high score
Sub- waterproof layer.
3. wafer stage chip encapsulating structure according to claim 2, it is characterised in that the protected material bed of material includes epoxy
Resin bed.
4. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the re-wiring layer includes：
Dielectric layer, positioned at the front of the semiconductor chip；And
Metal connecting line layer, is located at least in the dielectric layer, and the metal connecting line layer realize the semiconductor chip with it is described
The electrical connection of solder projection.
5. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the re-wiring layer includes：
First medium layer, positioned at the front of the semiconductor chip；
Metal line layer, is electrically connected in the first medium layer, and with the semiconductor chip；
Second dielectric layer, is covered in the upper surface of the first medium layer and the metal line layer；And
Underbump metallization layer, in the second dielectric layer and the second medium layer surface, and with the metal line layer and
The solder projection is electrically connected.
6. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the solder projection includes：
Metal column, is electrically connected positioned at surface of the re-wiring layer away from the semiconductor chip, and with the re-wiring layer
Connect；
Soldered ball, positioned at the surface of the remote semiconductor chip of the metal column.
7. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the solder projection includes soldered ball.
8. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the wafer stage chip encapsulating structure
The quantity of the interior semiconductor chip is one.
9. wafer stage chip encapsulating structure according to claim 1, it is characterised in that the wafer stage chip encapsulating structure
The quantity of the interior semiconductor chip is at least two, and has spacing between the adjacent semiconductor chip.
10. the wafer stage chip encapsulating structure according to any one in claim 1~9, it is characterised in that the wafer
Level chip-packaging structure further includes protective underlayer layer, and the protective underlayer layer is with the protected material bed of material jointly by the semiconductor
Chip, the re-wiring layer and the solder projection plastic packaging.
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| CN201721319985.XU CN207250483U (en) | 2017-10-13 | 2017-10-13 | Wafer stage chip encapsulating structure |
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| CN201721319985.XU CN207250483U (en) | 2017-10-13 | 2017-10-13 | Wafer stage chip encapsulating structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107611092A (en) * | 2017-10-13 | 2018-01-19 | 中芯长电半导体（江阴）有限公司 | Wafer stage chip encapsulating structure and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107611092A (en) * | 2017-10-13 | 2018-01-19 | 中芯长电半导体（江阴）有限公司 | Wafer stage chip encapsulating structure and preparation method thereof |
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Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |