CN102593018A - Packaging method for wafer-level semiconductor chip and semiconductor chip packaging body - Google Patents
Packaging method for wafer-level semiconductor chip and semiconductor chip packaging body Download PDFInfo
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- CN102593018A CN102593018A CN2011100099189A CN201110009918A CN102593018A CN 102593018 A CN102593018 A CN 102593018A CN 2011100099189 A CN2011100099189 A CN 2011100099189A CN 201110009918 A CN201110009918 A CN 201110009918A CN 102593018 A CN102593018 A CN 102593018A
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- passivation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a packaging method for a wafer-level semiconductor chip and a semiconductor chip packaging body. The semiconductor chip packaging body is characterized by comprising a semiconductor substrate, a protecting layer and conductive contacts, wherein the semiconductor substrate is provided with an electric contact formation surface and at least one electric contact formed on the electric contact formation surface; the protecting layer is formed on the formation surface of the semiconductor substrate and is provided with a plurality of exposing holes which expose an electric contact respectively; a conductive contact is formed in each exposing hole; and a conductive contact is formed outside each of the exposing holes and above each conductive contact.
Description
Technical field
The present invention relates to a kind of wafer level semiconductor wafer package method and a kind of semiconductor chip package.
Background technology
At present, be at first to be coated with a tin paste layer on the weld pad at this semiconductor wafer in the method major part that forms the tin ball on the weld pad of semiconductor wafer.Then, see through reflow and handle, the tin paste layer on each weld pad just forms a tin ball.Yet this fabrication schedule and finished product thereof have the tin ball and break away from and the tin ball is difficult to control and then causes the shortcoming that comes in contact phenomenon bad or that at all be not connected when being electrically connected with external circuit easily from the surface of wafer to the height on the top of tin ball from the weld pad of semiconductor wafer easily.In addition, formation tin ball is also not enough to some extent on output on single wafer.
In view of this, this case inventor then is engaged in the many years of experience of the sector with it, and in line with excelsior spirit, the active research improvement has the present invention's " wafer level semiconductor wafer package method and semiconductor chip package " to produce then.
Summary of the invention
The objective of the invention is for a kind of wafer level semiconductor wafer package method and a kind of semiconductor chip package are provided.
According to characteristic of the present invention; A kind of wafer level semiconductor wafer package method is provided; This method comprises following step: a semiconductor crystal wafer is provided; This semiconductor crystal wafer has several wafer areas, and each wafer area has an electrode formation surface and is formed at this electric terminal and forms lip-deep electric terminal with at least one; Photoresist layer of coating is being borrowed exposure and development treatment on the formation surface in all wafers zone, and this photoresist layer is formed with several exposing hole that respectively exposes the electric terminal of a correspondence to the open air; Filled conductive material and see through reflow and handle and make the electric conducting material that is filled within each exposing hole form a conductive contact within each exposing hole of this photoresist layer; Remove this photoresist layer and form protective layer that covers all conductive contacts of coating on the surface at the electric terminal of these wafer areas; Grind this protective layer till the top of each conductive contact is exposed to the open air; Passivation layer of coating on the surface of this protective layer, this passivation layer see through exposure and are formed with the exposing hole that several respectively expose the conductive contact of a correspondence to the open air with development treatment; Make the electric conducting material within each exposing hole that is filled in this passivation layer form a conductive contact at filled conductive material within the exposing hole of this passivation layer and through the reflow processing; And remove this passivation layer.
According to another characteristic of the invention; A kind of semiconductor wafer package method is provided; This semiconductor wafer package method comprises following step: a semiconductor crystal wafer is provided; This semiconductor crystal wafer has several wafer areas; Each wafer area have an electrode formation surface, one and this electric terminal form surperficial opposing backside surface, at least one be formed at this electric terminal form lip-deep electric terminal, and at least one be formed at the metal gasket on this back side with respect to this at least one electric terminal, this at least one metal gasket of at least one electric terminal and this is to be communicated with by a through hole; Filled conductive material within each through hole; See through reflow and handle the outside conductive contact of metal gasket that makes one of the electric conducting material formation that is filled within each through hole have an end to protrude out correspondence; Protective layer that covers all conductive contacts of coating on the back side of these wafer areas; Grind this protective layer till the top of each conductive contact is exposed to the open air; Passivation layer of coating on the surface of this protective layer, this passivation layer see through exposure and are formed with the exposing hole that several respectively expose the conductive contact of a correspondence to the open air with development treatment; Make the electric conducting material within each exposing hole that is filled in this passivation layer form a conductive contact at filled conductive material within the exposing hole of this passivation layer and through the reflow processing; And remove this passivation layer.
According to another feature again of the present invention; A kind of semiconductor wafer package method is provided; This semiconductor wafer package method comprises following step: a semiconductor crystal wafer is provided; This semiconductor crystal wafer has several wafer areas, and each wafer area has an electrode formation surface and is formed at this electric terminal and forms lip-deep electric terminal with at least one; Photoresist layer of coating is being borrowed exposure and development treatment on the formation surface in all wafers zone, and this photoresist layer is formed with several exposing hole that respectively exposes the electric terminal of a correspondence to the open air; Filled conductive material and see through reflow and handle and make the electric conducting material that is filled within each exposing hole form a conductive contact within each exposing hole of this photoresist layer; Grind this photoresist layer till the top of each conductive contact is exposed to the open air; Passivation layer of coating on the surface of this photoresist layer, this passivation layer see through exposure and are formed with the exposing hole that several respectively expose the conductive contact of a correspondence to the open air with development treatment; Make the electric conducting material within each exposing hole that is filled in this passivation layer form a conductive contact at filled conductive material within the exposing hole of this passivation layer and through the reflow processing; And remove this passivation layer.
The accompanying drawing summary
Fig. 1 to Figure 10 is the exemplary flow cutaway view for the wafer level semiconductor wafer package method that shows first preferred embodiment of the present invention;
Figure 11 to Figure 13 is the exemplary flow cutaway view for the wafer level semiconductor wafer package method that shows second preferred embodiment of the present invention;
The diagrammatic side view that is connected of Figure 14 is semiconductor chip package that to be a demonstration encapsulated by method for packing of the present invention and a carrier;
Figure 15 to Figure 24 is the exemplary flow cutaway view for the wafer level semiconductor wafer package method that shows the 3rd preferred embodiment of the present invention;
Figure 25 is to be the schematic sectional view of the aspect that is stacked of semiconductor chip package that a demonstration is encapsulated by method for packing of the present invention; And
Figure 26 to Figure 33 is the exemplary flow cutaway view for the wafer level semiconductor wafer package method that shows the 4th preferred embodiment of the present invention.
[main element symbol description]
1 semiconductor crystal wafer
10 wafer areas
100 electric terminals form the surface
101 electric terminals
102 back sides
103 metal gaskets
104 through holes
105 semiconductor substrates
2 photoresist layers
20 exposing hole
3 electric conducting materials
30 conductive contacts
4 protective layers
40 exposing hole
5 passivation layers
50 exposing hole
6 electric conducting materials
60 conductive contacts
8 printed circuit board (PCB)s
80 circuit trace form the surface
81 circuit trace
9 electric conducting materials
Embodiment
In the detailed description of the preferred embodiments of the present invention at the back, identical or similar elements is to be indicated by identical label, and their detailed description will be omitted.In addition, disclose characteristic of the present invention for clear, the element in graphic is not to describe by actual ratio.
Fig. 1 to Figure 10 is the schematic flow diagram in order to the wafer level semiconductor wafer package method that first preferred embodiment of the present invention is described.
Please cooperate and consult Fig. 1 to shown in Figure 10, at first, a semiconductor crystal wafer 1 is provided.This semiconductor crystal wafer 1 has several wafer areas 10, and each wafer area 10 has a semiconductor substrate 105.Each semiconductor substrate 105 has an electric terminal and forms surface 100 and be formed at this electric terminal with at least one and form the electric terminal 101 that surface being used on 100 is electrically connected with the external circuit (not shown).
Then, a photoresist layer 2 is that the electric terminal that is coated on the semiconductor substrate 105 in all wafers zone 10 forms on the surface 100.
Please cooperate and consult shown in Figure 2ly, through overexposure and development treatment, this photoresist layer 2 is to be formed with the exposing hole 20 that several respectively expose a corresponding electric terminal 101 to the open air.
Subsequently, borrowing any suitable mode, is to be filled with electric conducting material 3 within each exposing hole 20.In the present embodiment, electric conducting material 3 is for most preferably, as shown in Fig. 3 with tin cream.
See also shown in Figure 4ly, after reflow is handled, be filled in electric conducting material 3 (see figure 3)s within each exposing hole 20 and can form one and have the roughly conductive contact 30 of curved appearance.
Then, these photoresist layer 2 (see figure 4)s are removed through chemical cleaning, and are as shown in fig. 5.
Please cooperate and consult Fig. 6 and shown in Figure 7, after this photoresist layer 2 was removed, the electric terminal that the protective layer 4 of all conductive contacts 30 of covering is coated on these wafer areas 10 formed on the surface 100.Then, these protective layer 4 experience milled processed are till the top of each conductive contact 30 is exposed to the open air.
Should be noted that between the two adjacent conductive contacts 30 (electric terminal 101) short circuit can through protective layer 4 be used for avoid.On the other hand, in the present embodiment, this protective layer 4 is preferably formed by material transparent.
Then, passivation layer 5 is coated on the surface of this protective layer 4 and sees through exposure and is formed with the exposing hole 50 that several respectively expose the conductive contact 30 of a correspondence to the open air with development treatment.Then, in each exposing hole 50, be filled with electric conducting material 6.In the present embodiment, electric conducting material 6 as electric conducting material 3 with tin cream for most preferably.
See also shown in Figure 8ly, after reflow is handled, be filled in electric conducting material 6 (see figure 7)s within each exposing hole 50 and can form one and have the roughly conductive contact 60 of curved appearance.
At last, these passivation layer 5 (see figure 8)s are to be removed, and are as shown in fig. 9.Can become several along the cutting process of line of cut CL and can directly be installed to semiconductor chip package (see figure 10) as long as see through subsequently at this semiconductor crystal wafer 1 shown in Fig. 9 just like the carrier (not shown) as the circuit board.
Should be noted that; An electric terminal forms surface 100 and at least one is formed on the electric terminal 101 on this formation surface 100 because the semiconductor substrate 105 of each wafer area 10 has; Therefore the present invention can be applicable to the semiconductor wafer of any kind, includes but not limited to diode, light-emitting diode, CPU, RFID and/or TFT drive IC.On the other hand; The formation of conductive contact 60 mainly is to increase electric terminal in order to be installed on like the carrier as the circuit board at semiconductor chip package to form the distance between surface 100 and the carrier, is installed on the yield on the carrier thereby can promote semiconductor chip package.
In addition; Because of the height of photoresist layer 2 and passivation layer 5 can be controlled so that form exposing hole 20 accurately; The height of 50 hole wall is able to controlled accurately; So the conductive contact 30 that forms, thereby 60 height also is able to the controlled accurately purpose that can reach each conductive contact 30,60 high balanceization.On the other hand, milled processed such as also helps to obtain at high conductive contact 30,60.
Figure 11 to Figure 13 is the schematic flow diagram in order to wafer level semiconductor wafer package method that second preferred embodiment of the present invention is described.
Please cooperate and consult Figure 11 and shown in Figure 12; The wafer level semiconductor wafer package method of second preferred embodiment is after conductive contact 60 is formed that with the different place of wafer level semiconductor wafer package method of first preferred embodiment protective layer 7 that covers all conductive contacts 60 is coated on the surface of this protective layer 4.Then, these protective layer 7 experience milled processed are till the top of each conductive contact 60 is exposed to the open air.Should be noted that the top of conductive contact 60 can be polished a little in the process of grinding.At last, this protective layer 7 is removed.
Can become several as can directly being installed to semiconductor chip package shown in Figure 13 as long as see through cutting process subsequently at this semiconductor crystal wafer 1 shown in Figure 12 like the carrier (not shown) as the circuit board.
Figure 14 is the schematic sectional view that a demonstration is installed on the semiconductor chip package of accomplishing via the method for packing encapsulation of the first embodiment of the present invention one printed circuit board (PCB) 8.
As shown in Figure 14, this printed circuit board (PCB) 8 has a circuit tracks surface 80 and is formed at the circuit trace 81 of being scheduled on this layings surface 80 with several.As the electric conducting material 9 as the tin cream can coat will with circuit trace 81 that the corresponding conductive contact 60 of semiconductor chip package is electrically connected on.Then, this semiconductor chip package is installed on the laying surface 80 of this printed circuit board (PCB) 8 so that these conductive contacts 60 place corresponding electric conducting material 9.Subsequently, handle via reflow, the conductive contact 60 of this semiconductor chip package can be securely be electrically connected with the circuit trace 81 of this printed circuit board (PCB) 8.
Figure 15 to Figure 24 is the schematic flow diagram that shows the wafer level semiconductor wafer package method of the 3rd preferred embodiment of the present invention.
See also Figure 15 to shown in Figure 16, identical with previous embodiment, at first, a semiconductor crystal wafer 1 is provided.This semiconductor crystal wafer 1 has several wafer areas 10, and each wafer area 10 has a semiconductor substrate 105.Each semiconductor substrate 105 has an electric terminal and forms that 100, one on surface and this electric terminal form surperficial 100 opposing backside surface 102, at least one is formed at this electric terminal and forms electric terminal 101 on the surface 100, reaches at least one and be formed at the metal gasket 103 on this back side 102 with respect to this at least one electric terminal 101.Each electric terminal 101 is communicated with through a through hole 104 that runs through this semiconductor substrate 105 with corresponding metal gasket 103.
Then, borrow any suitable mode, within each through hole 104, be filled with electric conducting material 3.In the present embodiment, electric conducting material 3 with tin cream for most preferably, as shown in Fig..
See also shown in Figure 180ly, after handling, be filled in electric conducting material 3 (seeing Figure 17) within each through hole 104 and can form one and have an end to protrude out the outside conductive contact 30 of this metal gasket 103 through reflow.
Then, protective layer 4 that covers all conductive contacts 30 is coated on the back side 100 of these semiconductor substrates 105 (seeing Figure 19).Then, these protective layer 4 experience milled processed are till the top of each conductive contact 30 is exposed to the open air (seeing Figure 20).Should be noted that in the present embodiment, the top section of each conductive contact 30 is polished.
Please cooperate and consult shown in Figure 21ly, then, passivation layer 5 is coated on the surface of this protective layer 4 and sees through exposure and is formed with the exposing hole 50 that several respectively expose the conductive contact 30 of a correspondence to the open air with development treatment.Then, in each exposing hole 50, be filled with electric conducting material 6.In the present embodiment, electric conducting material 6 as electric conducting material 3 with tin cream for most preferably.
See also shown in Figure 22ly, after reflow is handled, be filled in electric conducting material 6 (seeing Figure 21) within each exposing hole 50 and can form one and have the roughly conductive contact 60 of curved appearance.
At last, this passivation layer 5 (seeing Figure 22) is removed, as shown in Figure 23.Can become several as can directly being installed to semiconductor chip package shown in Figure 24 as long as see through cutting process subsequently at this semiconductor crystal wafer 1 shown in Figure 23 just like the carrier (not shown) as the circuit board.Perhaps, the semiconductor chip package that cuts out can stack together as shown in Figure 25 and be mounted to (not shown) on the carrier again.Certainly, these semiconductor chip packages also can be to be mounted to one of them semiconductor chip package on one carrier earlier and then to get on remaining semiconductor chip package is stacked.
Figure 26 to Figure 33 is the schematic flow diagram in order to the wafer level semiconductor wafer package method that the 4th preferred embodiment of the present invention is described.
Please cooperate and consult Figure 26 to shown in Figure 33, at first, a semiconductor crystal wafer 1 is provided.This semiconductor crystal wafer 1 has several wafer areas 10, and each wafer area 10 has a semiconductor substrate 105.Each semiconductor substrate 105 has an electric terminal and forms surface 100 and be formed at this electric terminal with at least one and form the electric terminal 101 that surface being used on 100 is electrically connected with the external circuit (not shown).
Then, photoresist layer 2 is coated on the formation surface 100 of semiconductor substrate 105 in all wafers zone 10.
Please cooperate and consult shown in Figure 27ly, through overexposure and development treatment, this photoresist layer 2 is formed with several exposing hole 20 that respectively exposes a corresponding electric terminal 101 to the open air.
Subsequently, borrow any suitable mode, within each exposing hole 20, be filled with electric conducting material 3.In the present embodiment, electric conducting material 3 is for most preferably, as shown in Figure 28 with tin cream.
See also shown in Figure 29ly, after reflow is handled, be filled in electric conducting material 3 (seeing Figure 28) within each exposing hole 20 and can form one and have the roughly conductive contact 30 of curved appearance.
Then, as shown in Figure 30, these photoresist layer 2 experience milled processed are till the top of each conductive contact 30 is exposed to the open air.
Then, passivation layer 5 is coated on the surface of this photoresist layer 2 and sees through exposure and is formed with the exposing hole 50 that several respectively expose the conductive contact 30 of a correspondence to the open air with development treatment.Then, in each exposing hole 50, be filled with electric conducting material 6.In the present embodiment, electric conducting material 6 as electric conducting material 3 with tin cream for most preferably.
See also shown in Figure 31ly, after reflow is handled, be filled in electric conducting material 6 (seeing Figure 30) within each exposing hole 50 and can form one and have the roughly conductive contact 60 of curved appearance.
At last, this passivation layer 5 (seeing Figure 31) is removed, as shown in Figure 32.Can become several as can directly being installed to semiconductor chip package shown in Figure 33 as long as see through cutting process subsequently at this semiconductor crystal wafer 1 shown in Figure 32 just like the carrier (not shown) as the circuit board.
In sum; " wafer level semiconductor wafer package method and semiconductor chip package " of the present invention; Really can be through the above-mentioned structure that discloses, device; Reach its intended purposes and effect, and be not shown in the also unexposed use of publication before the application, meet the important documents such as novelty, creativeness of patent of invention.
Above-mentioned disclosed graphic and explanation is merely embodiments of the invention, and is non-for limiting embodiments of the invention; Other equivalences that those skilled in the art are done according to characteristic category of the present invention change or modify, and all should be encompassed in the claim protection range of this case.
Claims (16)
1. semiconductor wafer package method is characterized in that comprising:
A semiconductor crystal wafer is provided; This semiconductor crystal wafer has several wafer areas; Each wafer area has a semiconductor substrate, and each semiconductor substrate has an electrode formation surface and is formed at this electric terminal and forms lip-deep electric terminal with at least one;
Photoresist layer of coating is being borrowed exposure and development treatment on the formation surface of the regional semiconductor substrate of all wafers, and this photoresist layer is formed with several exposing hole that respectively exposes the electric terminal of a correspondence to the open air;
Filled conductive material and see through reflow and handle and make the electric conducting material that is filled within each exposing hole form a conductive contact within each exposing hole of this photoresist layer;
Remove this photoresist layer and form protective layer that covers all conductive contacts of coating on the surface at the electric terminal of these wafer areas;
Grind this protective layer till the top of each conductive contact is exposed to the open air;
Passivation layer of coating on the surface of this protective layer, this passivation layer see through exposure and are formed with the exposing hole that several respectively expose the conductive contact of a correspondence to the open air with development treatment;
Make the electric conducting material within each exposing hole that is filled in this passivation layer form a conductive contact at filled conductive material within the exposing hole of this passivation layer and through the reflow processing; And
Remove this passivation layer.
2. method for packing as claimed in claim 1 is characterized in that, in the step of this protective layer of coating, this protective layer is formed by material transparent.
3. method for packing as claimed in claim 1 wherein, before removing the step of passivation layer, also comprises a step of grinding this passivation layer so that the flush of the top of these conductive contacts within the exposing hole of this passivation layer and this passivation layer.
4. method for packing as claimed in claim 1 after removing the step of passivation layer, also comprises the step that cuts into this semiconductor crystal wafer other semiconductor chip package.
5. semiconductor wafer package method is characterized in that being to comprise:
A semiconductor crystal wafer is provided; This semiconductor crystal wafer has several wafer areas; Each wafer area has a semiconductor substrate; Each semiconductor substrate have an electrode formation surface, one and this electric terminal form surperficial opposing backside surface, at least one be formed at this electric terminal form lip-deep electric terminal, and at least one be formed at the metal gasket on this back side with respect to this at least one electric terminal, this at least one metal gasket of at least one electric terminal and this is to be communicated with by a through hole that runs through this semiconductor substrate;
Filled conductive material within each through hole;
See through reflow and handle the outside conductive contact of metal gasket that makes one of the electric conducting material formation that is filled within each through hole have an end to protrude out correspondence;
Protective layer that covers all conductive contacts of coating on the back side of the semiconductor substrate of these wafer areas;
Grind this protective layer till the top of each conductive contact is exposed to the open air;
Passivation layer of coating on the surface of this protective layer, this passivation layer see through exposure and are formed with the exposing hole that several respectively expose the conductive contact of a correspondence to the open air with development treatment;
Make the electric conducting material within each exposing hole that is filled in this passivation layer form a conductive contact at filled conductive material within the exposing hole of this passivation layer and through the reflow processing; And
Remove this passivation layer.
6. method for packing as claimed in claim 5 is characterized in that, in the step of this protective layer of coating, this protective layer is formed by material transparent.
7. method for packing as claimed in claim 5; It is characterized in that; Before removing the step of passivation layer, also comprise a step of grinding this passivation layer so that the flush of the top of these conductive contacts within the exposing hole of this passivation layer and this passivation layer.
8. method for packing as claimed in claim 1 after removing the step of passivation layer, also comprises the step that cuts into this semiconductor crystal wafer other semiconductor chip package.
9. semiconductor wafer package method is characterized in that comprising:
A semiconductor crystal wafer is provided; This semiconductor crystal wafer has several wafer areas; Each wafer area has a semiconductor substrate, and each semiconductor substrate has an electrode formation surface and is formed at this electric terminal and forms lip-deep electric terminal with at least one;
Photoresist layer of coating is being borrowed exposure and development treatment on the formation surface of the regional semiconductor substrate of all wafers, and this photoresist layer is formed with several exposing hole that respectively exposes the electric terminal of a correspondence to the open air;
Filled conductive material and see through reflow and handle and make the electric conducting material that is filled within each exposing hole form a conductive contact within each exposing hole of this photoresist layer;
Grind this photoresist layer till the top of each conductive contact is exposed to the open air;
Passivation layer of coating on the surface of this photoresist layer, this passivation layer see through exposure and are formed with the exposing hole that several respectively expose the conductive contact of a correspondence to the open air with development treatment;
Make the electric conducting material within each exposing hole that is filled in this passivation layer form a conductive contact at filled conductive material within the exposing hole of this passivation layer and through the reflow processing; And
Remove this passivation layer.
10. method for packing as claimed in claim 9; It is characterized in that; Before removing the step of passivation layer, also comprise a step of grinding this passivation layer so that the flush of the top of these conductive contacts within the exposing hole of this passivation layer and this passivation layer.
11. method for packing as claimed in claim 9 after removing the step of passivation layer, also comprises the step that cuts into this semiconductor crystal wafer other semiconductor chip package.
12. semiconductor chip package that method for packing as claimed in claim 4 encapsulates.
13. one kind like claim 8 semiconductor chip package that described method for packing encapsulates.
14. semiconductor chip package that method for packing as claimed in claim 11 encapsulates.
15. a semiconductor chip package is characterized in that comprising:
Semiconductor substrate, this semiconductor substrate have an electrode formation surface and are formed at this electric terminal and form lip-deep electric terminal with at least one;
The lip-deep protective layer of formation that is formed on this semiconductor substrate, this protective layer are formed with several exposing hole that respectively exposes the electric terminal of a correspondence to the open air;
Be formed at the conductive contact within each exposing hole; And
Be formed at the conductive contact outside exposing hole on each conductive contact.
16. semiconductor chip package as claimed in claim 15 is characterized in that, this protective layer is to be formed by material transparent.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110009918.9A CN102593018B (en) | 2011-01-11 | 2011-01-11 | Wafer level semiconductor wafer package method and semiconductor chip package |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110009918.9A CN102593018B (en) | 2011-01-11 | 2011-01-11 | Wafer level semiconductor wafer package method and semiconductor chip package |
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| Publication Number | Publication Date |
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| CN102593018A true CN102593018A (en) | 2012-07-18 |
| CN102593018B CN102593018B (en) | 2016-04-20 |
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| CN201110009918.9A Expired - Fee Related CN102593018B (en) | 2011-01-11 | 2011-01-11 | Wafer level semiconductor wafer package method and semiconductor chip package |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103633051A (en) * | 2013-12-12 | 2014-03-12 | 宁波芯健半导体有限公司 | Laminated chip wafer-level copper bump packaging structure |
| CN107808871A (en) * | 2016-09-08 | 2018-03-16 | 安世有限公司 | Wafer level semiconductor device with wettable flank |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1355556A (en) * | 2000-11-30 | 2002-06-26 | 陈怡铭 | Semiconductor chip device and its package method |
| US20070259517A1 (en) * | 2004-08-27 | 2007-11-08 | Micron Technology, Inc. | Low temperature methods of forming back side redistribution layers in association with through wafer interconnects |
| US20090294899A1 (en) * | 2008-05-27 | 2009-12-03 | Stats Chippac, Ltd. | Semiconductor device and method of forming embedded passive circuit elements interconnected to through hole vias |
| US20100301473A1 (en) * | 2007-11-01 | 2010-12-02 | Dai Nippon Printing Co., Ltd. | Component built-in wiring board and manufacturing method of component built-in wiring board |
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2011
- 2011-01-11 CN CN201110009918.9A patent/CN102593018B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1355556A (en) * | 2000-11-30 | 2002-06-26 | 陈怡铭 | Semiconductor chip device and its package method |
| US20070259517A1 (en) * | 2004-08-27 | 2007-11-08 | Micron Technology, Inc. | Low temperature methods of forming back side redistribution layers in association with through wafer interconnects |
| US20100301473A1 (en) * | 2007-11-01 | 2010-12-02 | Dai Nippon Printing Co., Ltd. | Component built-in wiring board and manufacturing method of component built-in wiring board |
| US20090294899A1 (en) * | 2008-05-27 | 2009-12-03 | Stats Chippac, Ltd. | Semiconductor device and method of forming embedded passive circuit elements interconnected to through hole vias |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103633051A (en) * | 2013-12-12 | 2014-03-12 | 宁波芯健半导体有限公司 | Laminated chip wafer-level copper bump packaging structure |
| CN107808871A (en) * | 2016-09-08 | 2018-03-16 | 安世有限公司 | Wafer level semiconductor device with wettable flank |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102593018B (en) | 2016-04-20 |
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