CN108117042A - A kind of semiconductor devices and preparation method, electronic device - Google Patents
A kind of semiconductor devices and preparation method, electronic device Download PDFInfo
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- CN108117042A CN108117042A CN201611064783.5A CN201611064783A CN108117042A CN 108117042 A CN108117042 A CN 108117042A CN 201611064783 A CN201611064783 A CN 201611064783A CN 108117042 A CN108117042 A CN 108117042A
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C3/00—Assembling of devices or systems from individually processed components
- B81C3/001—Bonding of two components
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
- B81C2203/0785—Transfer and j oin technology, i.e. forming the electronic processing unit and the micromechanical structure on separate substrates and joining the substrates
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
- B81C2203/0785—Transfer and j oin technology, i.e. forming the electronic processing unit and the micromechanical structure on separate substrates and joining the substrates
- B81C2203/0792—Forming interconnections between the electronic processing unit and the micromechanical structure
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Abstract
The present invention relates to a kind of semiconductor devices and preparation method, electronic devices.The described method includes：The first wafer is provided, first wafer has the first surface and second surface being oppositely arranged, is formed with the first bonding ring on the first surface, and the edge of the first surface on the outside of the described first bonding ring is formed with the first cutting groove；The second wafer is provided, the surface of second wafer is formed with the second bonding ring；Described first bonding ring and the second bonding ring are bonded, by first wafer and second wafer bonding；The second surface of first wafer is thinned to first cutting groove is exposed, to expose the Cutting Road region of second wafer；First wafer and second wafer are cut.The advantage of the invention is that：1. simplifying cutting technique flow (omission is blind to cut (blind dicing) and multiple alignment function) and reducing cutting frequency, process costs are effectively reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, are filled in particular to a kind of semiconductor devices and preparation method, electronics
It puts.
Background technology
In consumer electronics field, multifunctional equipment is increasingly liked be subject to consumer, compared to the simple equipment of function,
Multifunctional equipment manufacturing process will be more complicated, than the chip if desired for integrated multiple and different functions in circuit version, thus go out
3D integrated circuits (integrated circuit, IC) technology, 3D integrated circuits (integrated circuit, IC) quilt are showed
A kind of system-level integrated morphology is defined as, multiple chips are stacked in vertical plane direction, so as to save space.
With the development of 3D IC technologies, MEMS product is increasingly abundanter, and portioned product still using traditional handicraft, is being cut
It cuts and some resolution charts (test key) is added in slot (scribe lane), for carrying out the test (Wafer of electrical property
Acceptance Test).Since many MEMS products need the encapsulation of vacuum and leakproofness.Meanwhile upper and lower two panels silicon chip all needs
It is thinned.Then, the Cutting Road of the first wafer is cut first, and thickness is measured；Then the second wafer is cut again
Cutting Road.
But problem is following, it is necessary to which there are three problems when crystal grain cutting (die saw)：
1st, there is no any alignment mark after upper and lower two panels wafer thinning, it is necessary to silicon chip edge carry out it is blind cut, such ability
Expose figure, carry out crystal grain cutting alignment (die saw alignment)；Meanwhile first the depth of cut of knife cannot encounter
The figure on two surfaces is, it is necessary to carry out the adjustment of the first knife penetraction depth.The two actions can all lose some crystal grain (die),
And it also needs to more experienced engineer and carries out.
2nd, since the size of thickness is larger, value >=200um of first wafer apart from the size at edge, so, the first wafer
It needs to cut twice, just the silicon chip on Cutting Road can be made to drop, but this silicon chip to drop is bigger, easy breaking knife draws
Rocking for cutter is played, causes fragmentation (chipping).
3rd, due to being that two panels silicon chip is cut, there is cavity in centre, and the risk of horizontal fragmentation (lateral chipping) compares
Height, and compare and be difficult to observe, the fragmentation figures of the first wafer die cut surface can only be passed through, thus it is speculated that horizontal fragmentation (lateral
Chipping situation), so as to judge that crystal grain cutting (die saw) is bonded ring (bonding ring) either with or without damage Al/Ge,
Cause integrity problem (reliability issue).
Other methods are when MEMS product is cut in technique at present, because product is special, is confined space structure, does at present
Method:Because upper and lower wafer is without cutting alignment mark (mark), therefore must carry out blind cut to covering wafer (cap wafer) edge will cut
Slot exposes (recipe-1)；Can not be touched by being directed at (alignment) to the cutting groove region exposed and surveying knife up
Two wafer patterns (touch wafer2pattern)；Full wafer covering wafer (cap wafer (recipe- are cut after being aligned again
2)), but since width of first wafer apart from edge is larger, cutting easily damages blade and generates fragmentation when dropping
(chipping)；The wafer being completely exposed is aligned and cuts full wafer MEMS+CMOS wafers (wafer (recipe-
3)).Whole flow process is extremely cumbersome, and needs manual operation (manual handling), virtually increases risk and burden, and
In cutting process wafer (Si crack), easily damage Al/Ge is bonded ring (bonding ring).
Therefore, although in the prior art there are above-mentioned various drawbacks, the problem of above-mentioned drawback becomes urgent need to resolve, with into one
Step improves the performance and yield of device.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will in specific embodiment part into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In order to overcome the problems, such as that presently, there are the present invention provides a kind of preparation method of semiconductor devices, the methods
Including：
The first wafer is provided, first wafer has the first surface and second surface being oppositely arranged, described first
The first bonding ring is formed on surface, the edge of the first surface on the outside of the described first bonding ring is formed with the first cutting
Slot；
The second wafer is provided, the surface of second wafer is formed with the second bonding ring；
Described first bonding ring and the second bonding ring are bonded, by first wafer and the second wafer key
It closes；
The second surface of first wafer is thinned to first cutting groove is exposed, to expose second wafer
Cutting Road region；
First wafer and second wafer are cut.
Optionally, first cutting groove be around first crystal round fringes straight-flanked ring groove structure, described first
Bonding ring is rectangle ring structure.
Optionally, when the width of the Cutting Road between the described first bonding ring first cutting groove corresponding with outside
During more than 200 μm, the second cutting groove is also formed between first cutting groove and the first bonding ring.
Optionally, second cutting groove is parallel to corresponding one side in the Q-RING, second cutting groove
Both ends connected with both sides vertical with second cutting groove in the Q-RING.
Optionally, the width of first cutting groove is 10~200um, and depth is 30~400um.
Optionally, the width of first cutting groove is 80~200um, and depth is 100~400um；
Optionally, cut using blade, infrared cutting or deep reaction ion etching form first cutting groove.
Optionally, forming the method for the first bonding ring includes：
First wafer is provided, dielectric layer and bonded layer are formed on the first surface of first wafer；
The dielectric layer and the bonded layer are patterned, to form described the first of loop configuration on the first surface
It is bonded ring.
Optionally, after the first bonding ring is formed, the method may further include the first bonding ring
Inside formed cavity pattern.
Optionally, before first wafer is thinned, the method still further comprises thinned second wafer
Step.
Optionally, the first bonding ring uses one kind in Al, Au and Cu；The second bonding ring using Ge, Au and
One kind in Cu.
Optionally, the first bonding ring and the second bonding ring phase key by way of alloy bonding or thermocompression bonding
It closes.
The present invention also provides a kind of semiconductor devices, the semiconductor devices is prepared by the above method.
The present invention also provides a kind of electronic device, the electronic device includes above-mentioned semiconductor devices.
The present invention is existing in the prior art in order to solve the problems, such as, the first wafer (such as covering wafer, CAP wafer),
After completing original technique, hemisect or etching are carried out, a cutting groove, example are formed in the Cutting Road of the first crystal round fringes
A cutting groove is such as formed when Cutting Road width is less than or equal to 200um, and in the place of cutting road width, such as cut road width
Degree is more than>Two cutting grooves 200um) are cut out altogether.Then, the bonding of the first original wafer and the second wafer is carried out, and it is first right
Second wafer is thinned, and then carries out the first wafer again and is thinned, when carrying out being thinned to cutting groove to the first wafer, cuts road width
Part silicon chip fritter is automatically separated, and separating interface is distant from Al/Ge bonding rings, it is not easy to be damaged to bonding ring and sealing
Ring.
The advantage of the invention is that：
1. simplify cutting technique flow (omission is blind to cut (blind dicing) and multiple alignment function) and reduce cutting frequency
Rate effectively reduces process costs.
2. the Al/Ge bonded interfaces (bonding interface) that stress cutting belt is come is avoided to damage and cause reliability
Problem (reliability issue).
The semiconductor devices of the present invention, as a result of above-mentioned manufacturing method, thus equally has the advantages that above-mentioned.The present invention
Electronic device, as a result of above-mentioned semiconductor device, thus equally have the advantages that above-mentioned.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 shows the preparation technology flow chart of semiconductor devices of the present invention；
Fig. 2A -2H show that the preparation method implementation of semiconductor devices described in one embodiment of the invention obtains cuing open for structure
Face schematic diagram；
Fig. 3 shows the schematic diagram of electronic device according to an embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer or
There may be element or layer between two parties.On the contrary, when element be referred to as " on directly existing ... ", " with ... direct neighbor ", " be directly connected to
To " or " being directly coupled to " other elements or during layer, then there is no elements or layer between two parties.It should be understood that although art can be used
Language first, second, third, etc. describe various elements, component, area, floor and/or part, these elements, component, area, floor and/or portion
Dividing should not be limited by these terms.These terms are used merely to distinguish an element, component, area, floor or part and another
Element, component, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, component, area,
Floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and being used describe an element shown in figure or feature with it is other
The relation of element or feature.It should be understood that in addition to orientation shown in figure, spatial relationship term intention further include using and
The different orientation of device in operation.For example, if the device overturning in attached drawing, then, is described as " below other elements "
Or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to illustrate this
Invent the technical solution proposed.Presently preferred embodiments of the present invention is described in detail as follows, however in addition to these detailed descriptions, this hair
It is bright to have other embodiment.
In order to solve the above problem present in current technique, the present invention provides a kind of preparation sides of semiconductor devices
Method, the described method includes：
The first wafer is provided, first wafer has the first surface and second surface being oppositely arranged, described first
The first bonding ring is formed on surface, the edge of the first surface on the outside of the described first bonding ring is formed with the first cutting
Slot；
The second wafer is provided, the surface of second wafer is formed with the second bonding ring；
Described first bonding ring and the second bonding ring are bonded, by first wafer and the second wafer key
It closes；
The second surface of first wafer is thinned to exposing first cutting groove, while it is brilliant to expose described second
Round cutting groove region；
First wafer and second wafer are cut.
Specifically, the width of the Cutting Road on the outside of the first bonding ring is different, such as when the bonding
When ring is square, the width of the Cutting Road in the outside on four sides of the square button cyclization is different, when the width of the Cutting Road
When degree is respectively less than 200 μm, first cutting groove is only formed, can be removed during subsequent by first cutting groove
The part at edge.
Optionally, first cutting groove is the Q-RING groove structure around first crystal round fringes, but not
The shape is confined to, such as first cutting groove can also be the shapes such as toroidal cavity, polygon annular groove, according to
The wafer shape and the shape of the first bonding ring are designed.
The width of first cutting groove is 10~200um, and depth is 30~400um.
Optionally, the width of first cutting groove is 80~200um, and depth is 100~400um.
Specifically, cut using blade, infrared cutting or deep reaction ion etching dry etching form described first and cut
Cut slot.
When blade cutting, infrared cutting is used to form first cutting groove, the cutting width of first cutting groove
For 80~200um, depth is 100~400um.
When deep reaction ion etching dry etching is used to form first cutting groove, etching width is 10~200um,
Depth is 30~400um.
Wherein, the final thickness after being thinned is less than the depth of first cutting groove, to expose first cutting groove.
When the width of Cutting Road on the outside of the described first bonding ring is more than 200 μm, as shown in Figure 2 E, cut described first
It cuts and forms the second cutting groove 20 between slot 10 and the first bonding ring.
Optionally, second cutting groove is parallel to one of the width of Cutting Road described in the Q-RING more than 200 μm
Side, the both ends of second cutting groove are connected with the other both sides of the Q-RING.
Specifically, as shown in Figure 2 E, first cutting groove is the square ring groove knot around first crystal round fringes
Structure is more than 200 μm, therefore first cutting groove in the leftmost side and first bonding in the width of the Cutting Road of the leftmost side
Second cutting groove is set between ring, second cutting groove parallel to first cutting groove left side, and with upper and lower two
First cutting groove on side is connected, therefore works as and the first wafer is carried out to be thinned to the first cutting groove and second cutting groove
When, the part between first cutting groove and second cutting groove can be automatically separated and separating interface is bonded from Al/Ge
Ring is distant, it is not easy to be damaged to bonding ring and sealing ring.
Further, forming the method for the first bonding ring includes：
First wafer is provided, dielectric layer and bonded layer are formed on the first surface of first wafer；
The dielectric layer and the bonded layer are patterned, to form described the first of loop configuration on the first surface
It is bonded ring.
Embodiment one
Below with reference to the accompanying drawings the preparation method of the semiconductor devices of the present invention is described in detail, Fig. 1 shows the present invention
The preparation technology flow chart of the semiconductor devices；Fig. 2A -2H show the system of semiconductor devices described in one embodiment of the invention
Preparation Method is implemented to obtain the diagrammatic cross-section of structure.
The present invention provides a kind of preparation method of semiconductor devices, as shown in Figure 1, the key step bag of the preparation method
It includes：
Step S1：The first wafer is provided, first wafer has the first surface and second surface being oppositely arranged, in institute
It states and the first bonding ring is formed on first surface, the edge of the first surface on the outside of the described first bonding ring is formed with the
One cutting groove；
Step S2：The second wafer is provided, the surface of second wafer is formed with the second bonding ring；
Step S3：By the described first bonding ring and the second bonding ring bonding, by first wafer and described the
Two wafer bondings；
Step S4：The second surface of first wafer is thinned to first cutting groove is exposed, with described in exposing
The Cutting Road region of second wafer；
Step S5：First wafer and second wafer are cut.
In the following, the specific embodiment of the preparation method of the semiconductor devices of the present invention is described in detail.
First, perform step 1, the first wafer 201 be provided, first wafer have the first surface that is oppositely arranged and
Second surface is formed with the first bonding ring on the first surface, the first surface on the outside of the described first bonding ring
Edge be formed with the first cutting groove.
Specifically, as shown in Figure 2 A, first wafer 201 can be at least one of following material being previously mentioned：
Silicon, silicon-on-insulator (SOI) are stacked silicon (SSOI) on insulator, are stacked SiGe (S-SiGeOI) and insulation on insulator
SiGe (SiGeOI) etc. on body.
The semiconductor devices can be MEMS device in the present invention, and first wafer 201 is covering wafer, described
Second wafer is MEMS wafer, and pressure sensor, acceleration transducer, cmos image can be formed in the MEMS wafer and is passed
Device of the routine such as sensor etc. and active device, other MEMS device and interconnection architecture etc..
First wafer 201 for covering wafer, after first wafer and second wafer are engaged
Cavity is formed between first wafer and second wafer, the second wafer described in first wafer with protection and described
Various devices formed in two wafers etc..
Wherein, dielectric layer 202 is formed on first wafer 201, optionally, the dielectric layer 202 selects oxide,
Such as select silica.
The deposition method of its dielectric layer 202 can select chemical vapor deposition (CVD) method, physical vapour deposition (PVD) (PVD)
Low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the choosing of the formation such as method or atomic layer deposition (ALD) method
Select one kind in epitaxial growth (SEG).Preferred chemical vapor deposition (CVD) method in the present invention.
Bonded layer 203 is formed on the dielectric layer 202, for forming the first bonding ring, as shown in Figure 2 A.
Wherein, the bonded layer 203 uses one kind in Al, Au and Cu.
Then the dielectric layer 202 and the bonded layer 203 are patterned, to form the first bonding ring.
Wherein, the bonding ring is the shapes such as Q-RING, circular ring shape, polygon annular, but is not limited to the shape.
The bonding ring is Q-RING in this embodiment.
Patterned method is carried out to the dielectric layer 202 and the bonded layer 203 and includes but is not limited to following steps：
Patterned photoresist layer or organic distribution layer (Organic are formed on the bonded layer 203 first
Distribution layer, ODL), siliceous bottom antireflective coating (Si-BARC) and the patterning positioned at top
Photoresist layer (not shown), wherein pattern definition on the photoresist pattern of the bonding ring, then with described
Photoresist layer etches organic distribution layer for mask layer, bottom antireflective coating forms the pattern of bonding ring, then with described
Organic distribution layer, bottom antireflective coating are mask, etch the bonded layer 203 and the dielectric layer 202, to form described the
One bonding ring, as shown in Figure 2 B.
Dry etching or wet etching are selected in this step, and preferred C-F etchants are described to etch in the present invention
First wafer, the C-F etchants are CF4、CHF3、C4F8And C5F8In one or more.In this embodiment, it is described dry
Method etching can select CF4、CHF3, in addition plus N2、CO2In it is a kind of as etching atmosphere, wherein gas flow be CF4 10-
200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm, the etching pressure is 30-150mTorr, during etching
Between for 5-120s, be preferably 5-60s, more preferably 5-30s.
Then the first cutting groove 10 and/or the second cutting groove 20 are formed in the outside of the described first bonding ring, such as Fig. 2 D institutes
Show.
Specifically, the width of the Cutting Road on the outside of the first bonding ring is different, such as when the bonding
When ring is square, the width of the Cutting Road in the outside on four sides of the square button cyclization is different, when the width of the Cutting Road
When degree is respectively less than 200 μm, first cutting groove is only formed, can be removed during subsequent by first cutting groove
The part at edge.
Optionally, first cutting groove is the Q-RING groove structure around first crystal round fringes, but not
The shape is confined to, such as first cutting groove can also be the shapes such as toroidal cavity, polygon annular groove, according to
The wafer shape and the shape of the first bonding ring are designed.
The width of first cutting groove is 10~200um, and depth is 30~400um.Optionally, first cutting groove
Width for 80~200um, depth is 100~400um.
Wherein, the final thickness after being thinned is less than the depth of first cutting groove, to expose first cutting groove.
When the width of Cutting Road on the outside of the described first bonding ring is more than 200 μm, as shown in Figure 2 E, cut described first
It cuts and forms the second cutting groove 20 between slot 10 and the first bonding ring.
Optionally, second cutting groove is parallel to one of the width of Cutting Road described in the Q-RING more than 200 μm
Side, the both ends of second cutting groove are connected with the other both sides of the Q-RING.
Specifically, as shown in Figure 2 E, first cutting groove is the square ring groove knot around first crystal round fringes
Structure is more than 200 μm, therefore first cutting groove in the leftmost side and first bonding in the width of the Cutting Road of the leftmost side
Second cutting groove is set between ring, second cutting groove parallel to first cutting groove left side, and with upper and lower two
First cutting groove on side is connected, therefore works as and the first wafer is carried out to be thinned to the first cutting groove and second cutting groove
When, the part between first cutting groove and second cutting groove can be automatically separated and separating interface is bonded from Al/Ge
Ring is distant, it is not easy to be damaged to bonding ring and sealing ring.
There are two ways to forming first cutting groove and second cutting groove in the present invention：The first is use
Blade cutting, infrared cutting form first cutting groove, and second is uses deep reaction ion etching dry etching formation institute
State the first cutting groove.
And when blade cutting, infrared cutting is used to form first cutting groove, the cutting of first cutting groove
Width is 80~200um, and depth is 100~400um.
When deep reaction ion etching dry etching is used to form first cutting groove, etching width is 10~200um,
Depth is 30~400um.
Deep reaction ion etching (DRIE) method is selected to form first cutting groove and described second in this step to cut
Slot is cut, reactive ion etching is that the active group generated using high frequency glow discharge is chemically reacted with the material that is corroded, shape
Into volatile products sample surfaces atom is made to come off from lattice, the equipment prepared so as to fulfill sample surfaces Micropicture.
Gas hexa-fluoride (SF is selected in the deep reaction ion etching (DRIE) step6) as process gas, it applies
Add radio-frequency power supply so that hexa-fluoride reaction air inlet forms high ionization, controls in the etching step operating pressure to be
20mTorr-8Torr, power 600W, frequency 13.5MHz, Dc bias can the continuous control in -500V-1000V, protect
The needs of anisotropic etching are demonstrate,proved, select deep reaction ion etching (DRIE) that very high etching photoresist can be kept to select ratio.
Deep reaction ion etching (DRIE) system can select the common equipment of ability, it is not limited to a certain model.
It is described after the first bonding ring is formed, before formation first cutting groove and second cutting groove
The inside that method may further include the first bonding ring forms cavity pattern, as shown in Figure 2 C.
Formed the cavity method be included in it is described first bonding ring on the inside of the first surface on form photoresist
Layer simultaneously patterns, brilliant using the photoresist layer as described in mask etch first to form groove pattern in the photoresist layer
Circle, to form the cavity pattern, what the method was merely exemplary.
Step 2 is performed, provides the second wafer 204, the surface of second wafer is formed with the second bonding ring 205, by institute
The first bonding ring and the second bonding ring bonding are stated, by first wafer and second wafer bonding.
Specifically, as shown in Figure 2 E, by described first after first cutting groove and second cutting groove is formed
Wafer is inverted, and the first bonding ring of first wafer is bonded 205 phase of ring with the second of second wafer
Engagement.
The first bonding ring uses one kind in Al, Au and Cu；The second bonding ring uses one in Ge, Au and Cu
Kind.
Thermocompression bonding (Thermal-compression Bonding) is selected in the engaging process or by described in
First bonding ring and the second bonding ring are integrated by Van der Waals force eutectic bonding.
Optionally, it is described by first wafer and the side of second wafer bonding bonding in an embodiment of the present invention
Formula can be alloy bondings or the thermocompression bondings such as Al-Ge, Au-Au or Cu-Cu.
Optionally, prerinse can also be carried out to first wafer, to improve the Joint Properties of first wafer.
Specifically, in this step with diluted hydrofluoric acid DHF (wherein comprising HF, H2O2And H2O it is) brilliant to described first
Round surface carries out prerinse, so that first wafer has good performance (lead good mechanism).
Wherein, the concentration of the DHF does not limit strictly, in the present invention preferred HF:H2O2:H2O=0.1-1.5:1:
5。
Step 3 is performed, second wafer is thinned.
Specifically, as shown in Figure 2 F, the device first after reversion bonding, is then thinned second wafer, described to be thinned
Method can be that grinding is thinned.
Wherein, the grinding reduction steps can be including one in mechanical planarization step and grinding steps or more
A combination.
Step 4 is performed, the second surface of first wafer is thinned to first cutting groove is exposed, reveals simultaneously
Go out the cutting groove region of second wafer.
Specifically, as shown in Figure 2 G, when carrying out being thinned to the first cutting groove and second cutting groove to the first wafer, institute
State the part between the first cutting groove and second cutting groove can be automatically separated and also separating interface from Al/Ge bonding ring compare
Far, it is not easy to be damaged to bonding ring and sealing ring.
Cavity can be formed when that will carry out to the first wafer and be thinned to the first cutting groove and second cutting groove simultaneously to reveal
Go out the Cutting Road of second wafer.
It grinds in this step and the second surface of first wafer is thinned to exposing first cutting groove and described the
Stop during two cutting grooves, expose the first cutting groove in first wafer and second cutting groove by the method
Come, but also can to avoid photoetching and etching the step of, so as to simplify processing step, and then reduce production cost, improve yield.
Described thin in step for example can first be planarized, and be planarized to apart from first cutting groove and described
Two cutting grooves perform grinding steps when nearer, to ensure its surface more smooth, it is easier to control.
The present invention is thinned (grinding) using grinding and opens the first cutting groove and second cutting groove, without being directed to
It grinds the crystal column surface after (grinding) and carries out the photoetching of zero layer mark, etching, the method is simpler efficiently.
Step 5 is performed, first wafer and second wafer are cut.
Specifically, as illustrated in figure 2h, second wafer is installed in cutting frame in this step, will cut.
Wherein, the cutting frame can select various cutting frames commonly used in the art, and effect is to protect
The front of the device wafers.
Wherein, the purpose of chip cutting is that the chip (Die) of many on the wafer for machining preceding processing procedure is cut
Cut separation.Such as first have to form the figuratum blue film (blue tape) that sticks on one side in wafer and be placed on the annulus of steel,
The process is known as wafer bonding die (wafer mount), then send again to being cut on chip cutting machine.After having cut, one
Chip it is well-regulated be arranged on adhesive tape, simultaneously because the support of frame can avoid blue film fold and chip is made mutually to collide
It hits, and annulus props up adhesive tape in order to carry.
The preparation process of device is improved in the present invention, device wafers are also in key described in cutting process
The state of conjunction, chip surface are protected, and sheet cutting quality is easily guaranteed that, reduces the risk of fragmentation.
So far, the introduction of the correlation step of the semiconductor devices preparation of the embodiment of the present invention is completed.Above-mentioned steps it
Afterwards, other correlation steps can also be included, details are not described herein again.Also, in addition to the foregoing steps, the preparation side of the present embodiment
Method can also include other steps among above-mentioned each step or between different steps, these steps can be by existing
Various techniques in technology realize that details are not described herein again.
The present invention is existing in the prior art in order to solve the problems, such as, the first wafer (such as covering wafer, CAP wafer),
After completing original technique, hemisect or etching are carried out, a cutting groove, example are formed in the Cutting Road of the first crystal round fringes
A cutting groove is such as formed when Cutting Road width is less than or equal to 200um, and in the place of cutting road width, such as cut road width
Degree is more than>Two cutting grooves 200um) are cut out altogether.Then the bonding of the first original wafer and the second wafer is carried out, and first to
Two wafers are thinned, and then carry out the first wafer again and are thinned, when carrying out being thinned to cutting groove to the first wafer, cut the portion of road width
Silicon chip fritter is divided to be automatically separated, and separating interface is distant from Al/Ge bonding rings, it is not easy to be damaged to bonding ring and sealing
Ring.
The advantage of the invention is that：
1. simplify cutting technique flow (omission is blind to cut (blind dicing) and multiple alignment function) and reduce cutting frequency
Rate effectively reduces process costs；
2. the Al/Ge bonded interfaces (bonding interface) that stress cutting belt is come is avoided to damage and cause reliability
Problem (reliability issue).
Embodiment two
The present invention also provides a kind of semiconductor devices, the semiconductor devices is prepared by method described in embodiment one
It obtains.
The semiconductor devices includes：
First wafer；
First cutting groove and the second cutting groove, in first wafer；
Second wafer, second wafer are combined into one with first wafer.
First wafer 201 can be at least one of following material being previously mentioned：Silicon, silicon-on-insulator (SOI),
Silicon (SSOI) is stacked on insulator, SiGe (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) are stacked on insulator
Deng.
The semiconductor devices can be MEMS device in the present invention, and first wafer 201 is covering wafer, described
Second wafer is MEMS wafer, and pressure sensor, acceleration transducer, cmos image can be formed in the MEMS wafer and is passed
Device of the routine such as sensor etc. and active device, other MEMS device and interconnection architecture etc..
First wafer 201 for covering wafer, after first wafer and second wafer are engaged
Cavity is formed between first wafer and second wafer, the second wafer described in first wafer with protection and described
Various devices formed in two wafers etc..
Wherein, the first bonding ring is formed on first wafer 201, the first bonding ring includes dielectric layer 202 and key
Close layer 203.
Optionally, the dielectric layer 202 selects oxide, such as selects silica.
The deposition method of its dielectric layer 202 can select chemical vapor deposition (CVD) method, physical vapour deposition (PVD) (PVD)
Low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the choosing of the formation such as method or atomic layer deposition (ALD) method
Select one kind in epitaxial growth (SEG).Preferred chemical vapor deposition (CVD) method in the present invention.
Bonded layer 203 is formed on the dielectric layer 202, for forming the first bonding ring, as shown in Figure 2 A.
Wherein, the bonded layer 203 uses one kind in Al, Au and Cu.
The first cutting groove 10 and/or the second cutting groove 20 are formed on the outside of the described first bonding ring, as shown in Figure 2 D.
Specifically, the width of the Cutting Road on the outside of the first bonding ring is different, such as when the bonding
When ring is square, the width of the Cutting Road in the outside on four sides of the square button cyclization is different, when the width of the Cutting Road
When degree is respectively less than 200 μm, first cutting groove is only formed, can be removed during subsequent by first cutting groove
The part at edge.
Optionally, first cutting groove is the Q-RING groove structure around first crystal round fringes, but not
The shape is confined to, such as first cutting groove can also be the shapes such as toroidal cavity, polygon annular groove, according to
The wafer shape and the shape of the first bonding ring are designed.
The width of first cutting groove is 10~200um, and depth is 30~400um.Optionally, first cutting groove
Width for 80~200um, depth is 100~400um.
Specifically, cut using blade, infrared cutting or deep reaction ion etching dry etching form described first and cut
Cut slot.
Wherein, the final thickness after being thinned is less than the depth of first cutting groove, to expose first cutting groove.
When the width of Cutting Road on the outside of the described first bonding ring is more than 200 μm, as shown in Figure 2 E, cut described first
It cuts and forms the second cutting groove 20 between slot 10 and the first bonding ring.
Optionally, second cutting groove is parallel to one of the width of Cutting Road described in the Q-RING more than 200 μm
Side, the both ends of second cutting groove are connected with the other both sides of the Q-RING.
Specifically, as shown in Figure 2 E, first cutting groove is the square ring groove knot around first crystal round fringes
Structure is more than 200 μm, therefore first cutting groove in the leftmost side and first bonding in the width of the Cutting Road of the leftmost side
Second cutting groove is set between ring, second cutting groove parallel to first cutting groove left side, and with upper and lower two
First cutting groove on side is connected, therefore works as and the first wafer is carried out to be thinned to the first cutting groove and second cutting groove
When, the part between first cutting groove and second cutting groove can be automatically separated and separating interface is bonded from Al/Ge
Ring is distant, it is not easy to be damaged to bonding ring and sealing ring.
The surface of second wafer is formed with the second bonding ring 205, and the first bonding ring and second key
Cyclization is mutually bonded, by first wafer and second wafer bonding.
The first bonding ring uses one kind in Al, Au and Cu；The second bonding ring uses one in Ge, Au and Cu
Kind.
Thermocompression bonding (Thermal-compression Bonding) is selected in the engaging process or by described in
First bonding ring and the second bonding ring are integrated by Van der Waals force eutectic bonding.
Optionally, it is described by first wafer and the side of second wafer bonding bonding in an embodiment of the present invention
Formula can be alloy bondings or the thermocompression bondings such as Al-Ge, Au-Au or Cu-Cu.
After the second surface of first wafer is thinned, you can expose first cutting groove, while expose institute
State the cutting groove region of the second wafer.
The semiconductor devices of the present invention, as a result of above-mentioned manufacturing method, thus equally has the advantages that above-mentioned.
Embodiment three
An alternative embodiment of the invention provides a kind of electronic device, and including semiconductor devices, which is
Half obtained by the preparation method of semiconductor devices in previous embodiment two or the semiconductor devices according to embodiment one
Conductor device.
The electronic device, can be mobile phone, tablet computer, laptop, net book, game machine, television set, VCD,
Any electronic product such as DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment or have
The intermediate products of above-mentioned semiconductor device, such as：Cell phone mainboard with the integrated circuit etc..
Since the semiconductor devices part included has higher performance, which equally has the advantages that above-mentioned.
Wherein, Fig. 3 shows the example of mobile phone handsets.Mobile phone handsets 300, which are equipped with, to be included in shell 301
Display portion 302, operation button 303, external connection port 34, loud speaker 305, microphone 306 etc..
Wherein described mobile phone handsets include foregoing semiconductor devices or the preparation method according to embodiment one
Obtained semiconductor devices
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
Member is it is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (14)
1. a kind of preparation method of semiconductor devices, which is characterized in that the described method includes：
The first wafer is provided, first wafer has the first surface and second surface being oppositely arranged, in the first surface
On be formed with the first bonding ring, the edge of the first surface on the outside of the described first bonding ring is formed with the first cutting groove；
The second wafer is provided, the surface of second wafer is formed with the second bonding ring；
Described first bonding ring and the second bonding ring are bonded, by first wafer and second wafer bonding；
The second surface of first wafer is thinned to first cutting groove is exposed, to expose cutting for second wafer
Cut region；
First wafer and second wafer are cut.
2. according to the method described in claim 1, it is characterized in that, first cutting groove is around first crystal round fringes
Straight-flanked ring groove structure, it is described first bonding ring be rectangle ring structure.
3. according to the method described in claim 2, it is characterized in that, when the described first bonding ring corresponding with outside described the
When the width of Cutting Road between one cutting groove is more than 200 μm, between first cutting groove and the first bonding ring also
It is formed with the second cutting groove.
4. according to the method described in claim 3, it is characterized in that, second cutting groove parallel in the Q-RING therewith
Corresponding one side, the both ends of second cutting groove are connected with both sides vertical with second cutting groove in the Q-RING.
5. according to the method described in claim 1, it is characterized in that, the width of first cutting groove be 10~200um, depth
For 30~400um.
6. according to the method described in claim 1, it is characterized in that, the width of first cutting groove be 80~200um, depth
For 100~400um.
7. it according to the method described in claim 1, it is characterized in that, is cut using blade, infrared cutting or deep reactive ion
Etching forms first cutting groove.
8. according to the method described in claim 1, it is characterized in that, forming the method for the first bonding ring includes：
First wafer is provided, dielectric layer and bonded layer are formed on the first surface of first wafer；
The dielectric layer and the bonded layer are patterned, to form first bonding of loop configuration on the first surface
Ring.
9. according to the method described in claim 1, it is characterized in that, after the first bonding ring is formed, the method is also
Further comprise forming cavity pattern in the inside of the described first bonding ring.
10. according to the method described in claim 1, it is characterized in that, be thinned first wafer before, the method also into
The step of one step includes second wafer is thinned.
11. according to the method described in claim 1, it is characterized in that, the first bonding ring uses one in Al, Au and Cu
Kind；The second bonding ring uses one kind in Ge, Au and Cu.
12. according to the method described in claim 1, it is characterized in that, the first bonding ring and the second bonding ring pass through
Alloy bonding or the mode of thermocompression bonding are mutually bonded.
13. a kind of semiconductor devices, which is characterized in that the semiconductor devices passes through one of claim 1 to 12 the method
It is prepared.
14. a kind of electronic device, which is characterized in that the electronic device includes the semiconductor devices described in claim 13.
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| CN108117042B (en) | 2020-09-08 |
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