CN106032267B - A kind of MEMS and preparation method thereof and electronic installation - Google Patents
A kind of MEMS and preparation method thereof and electronic installation Download PDFInfo
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Abstract
The present invention provides a kind of MEMS and preparation method thereof and electronic installation, is related to technical field of semiconductors.Methods described includes：Semiconductor substrate is provided, sacrifice layer is formed in the front of Semiconductor substrate；Sacrificial patterned, to form the surface for the expose portion Semiconductor substrate that is open, wherein, the pattern of opening is consistent with the pattern of the predetermined bottom electrode formed；Deposition forms polysilicon layer on the surface of the Semiconductor substrate of exposure in the surface of sacrifice layer and the opening；Patterned polysilicon layer, to form the Top electrode above sacrifice layer and the bottom electrode on open bottom semiconductor substrate surface；The back side of the Semiconductor substrate of part corresponding to the lower pole region is etched, until the exposure bottom electrode；The part sacrifice layer of exposure is removed, to discharge the Top electrode.The preparation method of the present invention, can reduce the manufacturing process of the single wafer in MEMS manufacture craft, reduce process costs, simplify processing step.
Description
Technical field
The present invention relates to technical field of semiconductors, is filled in particular to a kind of MEMS and preparation method thereof and electronics
Put.
Background technology
Increasingly increase for the semiconductor storage demand of high power capacity, the integration density of these semiconductor storages
It is concerned by people, in order to increase the integration density of semiconductor storage, employs many different sides in the prior art
Method, such as multiple memory cell are formed on single wafer by reducing wafer size and/or changing inner structure unit, for
For the method for increasing integration density by changing cellular construction, carry out attempting horizontal layout of the ditch by changing active area
Or change cell layout and carry out reduction unit area.
In consumer electronics field, multifunctional equipment is increasingly liked by consumer, compared to the simple equipment of function,
Multifunctional equipment manufacturing process will be more complicated, than the chip if desired for integrated multiple difference in functionalitys in circuit version, thus go out
3D integrated circuits (integrated circuit, IC) technology is showed.
Wherein, microelectromechanical systems (MEMS) has in volume, power consumption, weight and in price fairly obvious excellent
Gesture, has developed a variety of different sensors so far, for example, pressure sensor, acceleration transducer, inertial sensor and
Other sensors.
Due to device requirement in MEMS fields, often it is related in MEMS manufacturing process to single wafer
(Single Wafer) is bonded (Bonding) one by one and manufacturing process such as (tape) of taping, therefore cause higher
Cost and larger production consumption.
Therefore need to be improved further the preparation method of current MEMS, to eliminate above-mentioned various drawbacks.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
In order to overcome the problem of presently, there are, the present invention provides a kind of preparation method of MEMS, including：
Step A1：Semiconductor substrate is provided, sacrifice layer is formed in the front of the Semiconductor substrate；
Step A2：The sacrifice layer is patterned, to form the surface of Semiconductor substrate described in opening expose portion, wherein,
The pattern of the opening is consistent with the pattern of the predetermined bottom electrode formed；
Step A3：In the surface of the sacrifice layer and the opening shape is deposited on the surface of the Semiconductor substrate of exposure
Into polysilicon layer；
Step A4：The polysilicon layer is patterned, to form Top electrode above the sacrifice layer and positioned at described
Bottom electrode described in open bottom on semiconductor substrate surface；
Step A5：The back side of the Semiconductor substrate of part corresponding to the lower pole region is etched, until described in exposure
Bottom electrode；
Step A6：The part sacrifice layer of exposure is removed, to discharge the Top electrode.
Further, it is further comprising the steps of after the step A2 and before the step A3：
In the opening laying is formed on the surface of the Semiconductor substrate of exposure.
Further, the material of the sacrifice layer and the laying is oxide.
Further, the thickness range of the sacrifice layer is 30~60 μm.
Further, the bottom electrode and the Top electrode are interdigitated electrodes, and the Top electrode and bottom electrode be not positioned at
Same layer and the composition interdigitated electrodes array from in-plane.
Further, the step A4 comprises the following steps：
Photoresist layer is sprayed on the polysilicon layer；
The photoresist layer is patterned, to define the pattern of the Top electrode and the bottom electrode；
Using the photoresist layer of patterning as mask, the polysilicon layer is etched, it is upper above the sacrifice layer to be formed
Electrode and positioned at the bottom electrode described in the open bottom on semiconductor substrate surface；
Remove the photoresist layer of the patterning.
Further, the etching is wet etching.
Further, the etching agent of the wet etching includes hydrofluoric acid and nitric acid.
Further, it is further comprising the steps of after the step A4 and before the step A5：
The part sacrifice layer of the Top electrode side is etched, with the front of expose portion Semiconductor substrate；
Metal is formed with the front of the part Semiconductor substrate of exposure on the Top electrode part surface respectively to connect
Touch.
Further, the process for forming the metal contact comprises the following steps：
On the front of the Top electrode, the bottom electrode, the sacrifice layer and the Semiconductor substrate of the exposure
Form metal level；
The metal level is patterned, to form the part described half for being located at respectively on the Top electrode part surface and exposing
The metal contact of conductor substrate face.
Further, the thickness of the metal level is 2 μm, and the material of the metal level is gold.
The embodiment of the present invention two provides a kind of MEMS made using preceding method.
The embodiment of the present invention three provides a kind of electronic installation, and the electronic installation includes foregoing MEMS.
In summary, according to the preparation method of the present invention, by the side for forming Top electrode and bottom electrode on one substrate
Method, the manufacturing process of the single wafer in MEMS manufacture craft can be reduced, reduces process costs, simplify technique step
Suddenly, at the same obtain device there is high yield and performance.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
The section that Figure 1A-Fig. 1 N are obtained device by a kind of preparation method correlation step of existing MEMS is illustrated
Figure；
Fig. 2A-Fig. 2 L show that the section for implementing obtained MEMS successively according to the preparation method of the present invention is illustrated
Figure；
Fig. 3 is shown obtains the Top electrode of MEMS and the layout of bottom electrode according to the preparation method of the present invention；
Fig. 3 A- Fig. 3 C show the diagrammatic cross-section for obtaining device along Fig. 3 section lines A-A ', B-B ', C-C ' respectively；
Fig. 4 shows the process chart according to preparation method of the invention successively implementation steps.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be element or layer between two parties.On the contrary, when element be referred to as " on directly existing ... ", " with ... direct neighbor ", " be directly connected to
To " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.It should be understood that although art can be used
Language first, second, third, etc. describe various elements, part, area, floor and/or part, these elements, part, area, floor and/or portion
Dividing to be limited by these terms.These terms are used merely to distinguish an element, part, area, floor or part and another
Element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, part, area,
Floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with it is other
The relation of element or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of with
The different orientation of device in operation.For example, if the device upset in accompanying drawing, then, is described as " below other elements "
Or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to explain proposition of the present invention
Technical scheme.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention can be with
With other embodiment.
At present, a kind of preparation method of MEMS is as shown in Figure 1A -1N, first, as shown in Figure 1A, there is provided the first substrate
100, form bonded layer 101 in the front of the first substrate 100；
Then, as shown in Figure 1B, first substrate 100 is inverted, makes the back side of the first Semiconductor substrate 100 upward；
Then, as shown in Figure 1 C, there is provided the second substrate 200, some grooves are formed in the front etching of second substrate
201；
Then, as shown in figure iD, thermal oxide is formed in the front of the second substrate 200 and the side wall of groove 201 and bottom
Silica 202；
Then, as referring to figure 1E, 101 and second substrate of bonded layer, the 200 positive thermal oxide of the first substrate 100 is aoxidized
Silicon 202 is bonded；
Then, as shown in fig. 1F, the back side to the first substrate 100 is carried out into backgrind to be thinned；
Then, as shown in Figure 1 G, the first substrate 100 is patterned, to form Top electrode 100a；
Then, as shown in fig. 1H, bonded layer 101 and thermal oxide silica 202 are patterned, to expose Top electrode 100a both sides
The second substrate 200 part surface；
Then, as shown in Figure 1 I, the Au on the surface for covering the Top electrode 100a and second substrate 200 exposure is formed
Metal level；
Then, as shown in figure iJ, the Au metal levels are patterned, are served as a contrast with being formed on the Top electrode 100a of part with second
Metal contact 203 on the part surface of bottom 200；
Then, as shown in figure iK, the first substrate 100 and the second substrate 200 are inverted, so that the back side court of the second substrate 200
On；
, as can be seen in 1L, pair then the back side with the second substrate 200 of Top electrode 100a position correspondences performs etching, institute
State non-the second substrate of break-through 200 of etching；
Then, as depicted in figure iM, wet etching removes the part bonded layer 101 and thermal oxide silica 202 of exposure, so that
Top electrode 100a suspends；
Then, as shown in Fig. 1 N, overturn again, so that Top electrode 100a is upward, the correspondence below Top electrode 100a
Part 200 bottom electrode as device of the second substrate, so far complete final element manufacturing.
Above-mentioned manufacturing process, due to needing the processing procedure before being bonded respectively to the first substrate and the second substrate, moreover, relating to
And also to carry out pasting processing procedure etc. of Protection glue band during backgrind technique to device, complex technical process, cause it is higher into
This and larger production consume.
Therefore, it is necessary to be improved further to current methods described, so as to eliminate above-mentioned various problems.
Embodiment one
The preparation method of the MEMS of the present invention is described in detail next, with reference to Fig. 2A-Fig. 2 L, Fig. 3 and Fig. 4.
Wherein, Fig. 2A-Fig. 2 L show the diagrammatic cross-section for implementing obtained MEMS successively according to the preparation method of the present invention；Figure
3 show according to the present invention preparation method obtain the Top electrode of MEMS and the layout of bottom electrode；Fig. 3 A- Fig. 3 C show
The diagrammatic cross-section of device is gone out to obtain along Fig. 3 section lines A-A ', B-B ', C-C ' respectively；Fig. 4 is shown according to the present invention
Preparation method implementation steps successively process chart.
The preparation method of the MEMS of the present invention, comprises the following steps：
First, as shown in Figure 2 A, there is provided Semiconductor substrate 300, sacrifice layer is formed in the front of the Semiconductor substrate 300
301。
The Semiconductor substrate 300 can be at least one of following material being previously mentioned：Silicon, silicon-on-insulator
(SOI) silicon (SSOI), is laminated on insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator
And germanium on insulator (GeOI) etc. (SiGeOI).In the present embodiment, the material of the Semiconductor substrate is silicon.The semiconductor
Active device and/or passive device are also formed with substrate, wherein the species and number of the active device and passive device
It can be selected according to specific needs, it is not limited to a certain.In one example, shape is gone back in the Semiconductor substrate
Into there is cmos device.
The material of the sacrifice layer 301 can be selected from the materials such as oxide, nitride, nitrogen oxides, amorphous carbon, preferably
Ground, the material of sacrifice layer is oxide.It can deposit to form sacrifice layer 301 using any method well known to those skilled in the art,
For example, chemical vapour deposition technique, atomic layer deposition method etc., it is therefore preferable to use plasma chemical vapor deposition.Formed
The thickness range of sacrifice layer 301 can be 30~60 μm, but be not limited to above-mentioned thickness range, can be carried out according to actual process
Appropriate adjustment, its difference in height depended between the predetermined Top electrode formed and bottom electrode.In the present embodiment, the sacrifice layer
301 thickness is 50 μm.
Then, as shown in Figure 2 B, the sacrifice layer 301 is patterned, to form semiconductor lining described in 302 expose portions of opening
The surface at bottom 300, wherein the pattern of the opening 302 is consistent with the pattern of the predetermined bottom electrode formed.
The method that the method for sacrificial patterned 300 can use photoetching process and etching technics combination, i.e., sacrificing first
Photoresist layer is formed in layer surface, goes out the pattern for the bottom electrode for making a reservation for be formed defined in photoresist layer using photoetching process, with photoresistance
Layer is mask etching sacrifice layer, forms opening 302, and the opening has consistent with the pattern of the bottom electrode of predetermined formation.
Then, as shown in Figure 2 C, lining is formed on the surface of the Semiconductor substrate 300 of exposure in the opening 302
Bed course 303.
Laying 303 can include any one of several gasket materials, include but is not limited to：Silicon oxide liner cushion material and
Silicon nitride liner material, laying preferably include silicon oxide liner cushion material.It can use and include but is not limited to：Chemical vapor deposition
Method and physical gas-phase deposite method form laying.Generally, laying 303 has from about 200 to about 1000 angstroms of thickness
Degree.It is preferred that laying 303 and sacrifice layer 301 are formed from the same material, in order to which the follow-up step process of warp can
So that both to be removed simultaneously, for example, the material of the sacrifice layer and the laying is oxide.Optionally perform formation
The step of laying 303.
Then, as shown in Figure 2 D, on the surface of the sacrifice layer 301 and opening 302 internal liner sheet 303 surface
Deposition forms polysilicon layer 304.
Low-pressure chemical vapor phase deposition (LPCVD) technique can be selected in the forming method of polysilicon layer 304.Form the polysilicon
The process conditions of layer include：Reacting gas is silane (SiH4), the range of flow of the silane can be 100~200 cubic centimetres/
Minute (sccm), such as 150sccm；Temperature range can be 700~750 degrees Celsius in reaction chamber；React cavity pressure can be 250~
350 milli millimetress of mercury (mTorr), such as 300mTorr；Buffer gas, the buffer gas are may also include in the reacting gas
Can be helium (He) or nitrogen, the range of flow of the helium and nitrogen can be 5~20 liters/min (slm), such as 8slm, 10slm
Or 15slm.
In one example, if not forming laying in the bottom of opening 302, the polysilicon layer formed is deposited directly to
In opening on the surface of the Semiconductor substrate of exposure.
The polysilicon layer 304 that deposition is formed covers the surface of whole sacrifice layer 301 and side wall and the bottom of opening 302.
Then, as shown in Fig. 2 E-2G, the polysilicon layer is patterned, to be formed positioned at the upper of the top of sacrifice layer 301
Electrode 304a and positioned at the bottom electrode 304b described in 302 bottoms of the opening in Semiconductor substrate 300.
Specifically, as shown in Figure 2 E, first, photoresist layer 305 is sprayed on the polysilicon layer 304, patterns the light
Resistance layer 305, to define the pattern of Top electrode and bottom electrode.Then, as shown in Figure 2 F, it is mask with the photoresist layer 305 of patterning,
The polysilicon layer is etched, to be formed positioned at the Top electrode 304a of the top of sacrifice layer 301 and positioned at 302 bottoms of the opening
Bottom electrode 304b on the surface of Semiconductor substrate 300.In the step, in the side wall of opening 302 and sacrifice layer 301
Top electrode 304a pattern beyond polysilicon layer all etching remove.Etching in the step can be dry etching or wet
Method etches, and in the present embodiment, can preferably be selected the quarter for including hydrofluoric acid and nitric acid from wet etching, the wet etching
Lose agent.Afterwards, as shown in Figure 2 G, the photoresist layer of patterning is removed.It can be gone using any method well known to those skilled in the art
Except the photoresist layer, for example, method or wet-cleaning of ashing etc..
In one example, the Top electrode 304a and bottom electrode 304b of formation plane figure, as shown in figure 3, under described
The electrode 304a and Top electrode 304b is interdigitated electrodes, and the Top electrode 304a and bottom electrode 304b are located at different layers
And interdigitated electrodes array is formed from in-plane.Interdigitated electrodes by the first electrode part that extends in a first direction and
Formed with some second electrode parts that first electrode part intersects vertically, and interdigitated electrodes array is then by two interdigitations
Electrode crossing is formed.Wherein, Fig. 3 A show the diagrammatic cross-section that device is obtained along Fig. 3 section lines A-A ', in the region,
A Top electrode 304a part is located on the surface of sacrifice layer 301, and Fig. 3 B, which are shown along Fig. 3 section lines B-B ', obtains device
Diagrammatic cross-section, in the region, Top electrode 304a and bottom electrode 304b are positioned at different layers and form and hand over from in-plane
Interdigitation, Top electrode 304a is located on the surface of sacrifice layer 301, and bottom electrode 304b is located on the surface of Semiconductor substrate 300,
Fig. 3 C show the diagrammatic cross-section that device is obtained along Fig. 3 section lines C-C ', and in the region, bottom electrode 304b is positioned at half
On the surface of conductor substrate 300.
Then, as shown in Fig. 2 H- Fig. 2 I, the part sacrifice layer 301 of the Top electrode 304a sides is etched, with exposure
The front of part semiconductor substrate 300, respectively on the Top electrode 304a part surfaces and exposure the part semiconductor
The front of substrate 300 forms metal contact 306.
Specifically, first, as illustrated in figure 2h, in the Top electrode 304a, the bottom electrode 304b, the sacrifice layer 301
Metal level 306 ' is formed with the front of the Semiconductor substrate 300 of the exposure.The material of the metal level 306 ' can be with
Selected from metals such as aluminium, copper, gold, silver, platinum, tin.Exemplarily, the thickness of the metal level is 2 μm, and the material of the metal level is
Gold.Low-pressure chemical vapor deposition (LPCVD), plasma auxiliary chemical vapor deposition (PECVD), Organometallic Chemistry can be passed through
Vapour deposition (MOCVD) and ald (ALD) or other advanced deposition techniques form metal level 306 '.
As shown in figure 2i, pattern the metal level, with formed respectively on the Top electrode 304a part surfaces and
The positive metal contact 306 of the exposed part Semiconductor substrate 300.
Then, as shown in fig. 2j, the back of the body of the Semiconductor substrate 300 of part corresponding to the bottom electrode 304b regions is etched
Face, until the exposure bottom electrode 304b.
The back side for making the Semiconductor substrate 300 upward, etches part corresponding to the bottom electrode 304b regions described half
The back side of conductor substrate 300.Exemplarily, it is also formed between the bottom electrode 304b and the front of the Semiconductor substrate
Laying 303, then the etching in this step can stop in laying 303.The techniques such as dry etching or wet etching can be used
Realize the etching to the back side of Semiconductor substrate 300.It is preferred that from dry etching, dry method etch technology includes but is not limited to：
Reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Preferably by one or more RIE
Step carries out dry etching.
Then, as shown in figure 2k, the exposed part sacrifice layer is removed, to discharge the Top electrode 304a.
The method of wet etching can be used to remove the sacrifice layer, the etching has the etching selectivity to sacrificing floor height.
In this step, also the portions of pads layer of remaining exposure in step before can be removed simultaneously.
Finally, as shown in figure 2l, Semiconductor substrate 300 is overturn, makes its face-up.
So far, the introduction of the correlation step of the MEMS making of the embodiment of the present invention is completed.After the above step,
Other correlation steps can also be included, here is omitted.Also, in addition to the foregoing steps, the preparation method of the present embodiment
Other steps can also be included among above-mentioned each step or between different steps, these steps can pass through existing skill
Various techniques in art realize that here is omitted.
In summary, according to the preparation method of the present invention, by the side for forming Top electrode and bottom electrode on one substrate
Method, the manufacturing process of the single wafer in MEMS manufacture craft can be reduced, reduces process costs, simplify technique step
Suddenly, at the same obtain device there is high yield and performance.
Reference picture 4, the process chart for a step of embodiment of the invention is implemented successively is shown, for letter
The flow of whole manufacture craft is shown.
In step S401, there is provided Semiconductor substrate, sacrifice layer is formed in the front of the Semiconductor substrate；
In step S402, the sacrifice layer is patterned, to form the surface of Semiconductor substrate described in opening expose portion,
Wherein, the pattern of the opening is consistent with the pattern of the predetermined bottom electrode formed；
In step S403, in the surface of the sacrifice layer and the opening on the surface of the Semiconductor substrate of exposure
Deposition forms polysilicon layer；
In step s 404, the polysilicon layer is patterned, to form Top electrode and the position above the sacrifice layer
In the bottom electrode described in the open bottom on semiconductor substrate surface；
In step S405, the back side of the Semiconductor substrate of part corresponding to the lower pole region, Zhi Daobao are etched
Reveal the bottom electrode；
In step S406, the exposed part sacrifice layer is removed, to discharge the Top electrode.
Embodiment two
Present invention also offers a kind of MEMS, the MEMS is made to by method described in embodiment one
Arrive.
The MEMS includes but is not limited to sensor, microsensor, resonator, brake, micro- brake, microelectronics
Device and converter etc..
Because the preparation method in embodiment one has excellent technique effect, therefore formed using the preparation method
MEMS its there is higher Performance And Reliability.
Embodiment three
The present invention also provides a kind of electronic installation in addition, and it includes foregoing MEMS.Or it includes using embodiment
A kind of method makes the MEMS obtained.
Due to including MEMS there is higher performance, the electronic installation equally has above-mentioned advantage.
The electronic installation, can be mobile phone, tablet personal computer, notebook computer, net book, game machine, television set, VCD,
Any electronic product such as DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment or have
The intermediate products of above-mentioned MEMS, such as：Cell phone mainboard with the integrated circuit etc..
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (11)
1. a kind of preparation method of MEMS, including：
Step A1：Semiconductor substrate is provided, sacrifice layer is formed in the front of the Semiconductor substrate；
Step A2：The sacrifice layer is patterned, to form the surface of Semiconductor substrate described in opening expose portion, wherein, it is described
The pattern of opening is consistent with the pattern of the predetermined bottom electrode formed；
Step A3：Deposition formation is more on the surface of the Semiconductor substrate of exposure in the surface of the sacrifice layer and the opening
Crystal silicon layer；
Step A4：The polysilicon layer is patterned, to form Top electrode above the sacrifice layer and positioned at the opening
Bottom electrode described in bottom on semiconductor substrate surface；
Step A5：The back side of the Semiconductor substrate of part corresponding to the lower pole region is etched, until the exposure lower electricity
Pole；
Step A6：The part sacrifice layer of exposure is removed, to discharge the Top electrode.
2. preparation method according to claim 1, it is characterised in that after the step A2 and before the step A3
It is further comprising the steps of：
In the opening laying is formed on the surface of the Semiconductor substrate of exposure.
3. preparation method according to claim 2, it is characterised in that the material of the sacrifice layer and the laying is oxygen
Compound.
4. preparation method according to claim 1, it is characterised in that the thickness range of the sacrifice layer is 30~60 μm.
5. preparation method according to claim 1, it is characterised in that the bottom electrode and the Top electrode are interdigitation
Electrode, the Top electrode and bottom electrode form interdigitated electrodes array positioned at different layers and from in-plane.
6. preparation method according to claim 1, it is characterised in that the step A4 comprises the following steps：
Photoresist layer is sprayed on the polysilicon layer；
The photoresist layer is patterned, to define the pattern of the Top electrode and the bottom electrode；
Using the photoresist layer of patterning as mask, the polysilicon layer is etched, to form the Top electrode above the sacrifice layer
With positioned at the bottom electrode described in the open bottom on semiconductor substrate surface；
Remove the photoresist layer of the patterning.
7. preparation method according to claim 6, it is characterised in that the etching is wet etching.
8. preparation method according to claim 7, it is characterised in that the etching agent of the wet etching include hydrofluoric acid and
Nitric acid.
9. preparation method according to claim 1, it is characterised in that after the step A4 and before the step A5
It is further comprising the steps of：
The part sacrifice layer of the Top electrode side is etched, with the front of expose portion Semiconductor substrate；
Respectively metal contact is formed on the Top electrode part surface with the front of the part Semiconductor substrate of exposure.
10. preparation method according to claim 9, it is characterised in that form the process of the metal contact including following
Step：
Formed on the front of the Top electrode, the bottom electrode, the sacrifice layer and the Semiconductor substrate of the exposure
Metal level；
The metal level is patterned, to form the part semiconductor on the Top electrode part surface with exposure respectively
The metal contact of substrate face.
11. preparation method according to claim 10, it is characterised in that the thickness of the metal level is 2 μm, the metal
The material of layer is gold.
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| CN109186575B (en) * | 2018-09-20 | 2022-02-01 | 北方电子研究院安徽有限公司 | Preparation method of double-electrode micro-cylindrical resonant gyroscope based on SOI |
| CN109873060B (en) * | 2019-04-18 | 2020-11-13 | 广东省半导体产业技术研究院 | Method for manufacturing micro light-emitting diode array |
| CN112520689B (en) * | 2020-11-17 | 2024-06-07 | 绍兴中芯集成电路制造股份有限公司 | Semiconductor device and method for manufacturing the same |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1677621A (en) * | 2004-03-29 | 2005-10-05 | 台湾积体电路制造股份有限公司 | Method of forming MIM capacitor electrodes |
| CN101774531A (en) * | 2010-01-05 | 2010-07-14 | 上海集成电路研发中心有限公司 | MEMS microbridge structure contact hole preparation method |
| CN103402164A (en) * | 2013-08-02 | 2013-11-20 | 上海集成电路研发中心有限公司 | MEMS (micro-electromechanical system) microphone structure and manufacturing method thereof |
| CN103413694A (en) * | 2013-07-24 | 2013-11-27 | 南京大学 | Method for manufacturing plane solid state supercapacitor |
| CN104244152A (en) * | 2013-06-13 | 2014-12-24 | 无锡芯奥微传感技术有限公司 | Micro electro mechanical system microphone package and packaging method |
| CN204097077U (en) * | 2014-10-16 | 2015-01-14 | 中芯国际集成电路制造(北京)有限公司 | A kind of MEMS structure |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005275174A (en) * | 2004-03-25 | 2005-10-06 | Miyota Kk | Method of manufacturing optical switch |
| DE102006024668A1 (en) * | 2006-05-26 | 2007-11-29 | Robert Bosch Gmbh | Micromechanical component e.g. sensor, for e.g. hearing aid`s microphone, has counter unit with passage hole in rear volume formed by hollow space below unit, where hollow space contacts upper side of membrane below counter unit via opening |
| JP2013000825A (en) * | 2011-06-15 | 2013-01-07 | Topcon Corp | Method of manufacturing three-dimensional structure, and three-dimensional structure manufactured by the same |
-
2015
- 2015-03-19 CN CN201510121611.6A patent/CN106032267B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1677621A (en) * | 2004-03-29 | 2005-10-05 | 台湾积体电路制造股份有限公司 | Method of forming MIM capacitor electrodes |
| CN101774531A (en) * | 2010-01-05 | 2010-07-14 | 上海集成电路研发中心有限公司 | MEMS microbridge structure contact hole preparation method |
| CN104244152A (en) * | 2013-06-13 | 2014-12-24 | 无锡芯奥微传感技术有限公司 | Micro electro mechanical system microphone package and packaging method |
| CN103413694A (en) * | 2013-07-24 | 2013-11-27 | 南京大学 | Method for manufacturing plane solid state supercapacitor |
| CN103402164A (en) * | 2013-08-02 | 2013-11-20 | 上海集成电路研发中心有限公司 | MEMS (micro-electromechanical system) microphone structure and manufacturing method thereof |
| CN204097077U (en) * | 2014-10-16 | 2015-01-14 | 中芯国际集成电路制造(北京)有限公司 | A kind of MEMS structure |
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