TW201407695A - 封裝載板及其製作方法 - Google Patents
封裝載板及其製作方法 Download PDFInfo
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- TW201407695A TW201407695A TW101128619A TW101128619A TW201407695A TW 201407695 A TW201407695 A TW 201407695A TW 101128619 A TW101128619 A TW 101128619A TW 101128619 A TW101128619 A TW 101128619A TW 201407695 A TW201407695 A TW 201407695A
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- 238000004519 manufacturing process Methods 0.000 title abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 77
- 229910000679 solder Inorganic materials 0.000 claims abstract description 32
- 239000004020 conductor Substances 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 148
- 238000000034 method Methods 0.000 claims description 46
- 239000002335 surface treatment layer Substances 0.000 claims description 18
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 12
- 229910052737 gold Inorganic materials 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 12
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 claims description 12
- 229910052709 silver Inorganic materials 0.000 claims description 12
- 239000004332 silver Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- 238000007772 electroless plating Methods 0.000 claims description 8
- 239000003822 epoxy resin Substances 0.000 claims description 6
- 239000000945 filler Substances 0.000 claims description 6
- 229920000647 polyepoxide Polymers 0.000 claims description 6
- 239000002861 polymer material Substances 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 6
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 5
- 229910052707 ruthenium Inorganic materials 0.000 claims description 5
- 239000000654 additive Substances 0.000 claims description 4
- 238000001746 injection moulding Methods 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 8
- 238000010438 heat treatment Methods 0.000 description 10
- 239000003755 preservative agent Substances 0.000 description 4
- 230000035882 stress Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012044 organic layer Substances 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
- H01L21/447—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428 involving the application of pressure, e.g. thermo-compression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/642—Heat extraction or cooling elements characterized by the shape
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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- Wire Bonding (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
一種封裝載板的製作方法。提供一絕緣基材。絕緣基材具有一上表面、一下表面、多個位於下表面的凹槽及多個貫穿絕緣基材且分別連通至凹槽的貫孔。凹槽與貫孔定義出多個通孔。形成一填滿通孔的導電材料以定義出多個導電柱。形成一具有一頂表面及多個從頂表面延伸至導電柱的盲孔的絕緣層於絕緣基材的上表面上。形成一填滿盲孔、連接導電柱並暴露出部分頂表面的圖案化線路層於絕緣層的頂表面上。形成一防焊層於圖案化線路層上且覆蓋圖案化線路層及其所暴露出之部分頂表面。防焊層具有多個暴露出部分圖案化線路層的開口而定義出多個接墊。
Description
本發明是有關於一種封裝結構及其製作方法,且特別是有關於一種封裝載板及其製作方法。
晶片封裝的目的在於保護裸露的晶片、降低晶片接點的密度及提供晶片良好的散熱。傳統的打線(wire bonding)技術通常採用導線架(leadframe)作為晶片的承載器(carrier)。隨著晶片的接點密度逐漸提高,導線架已無法再提供更高的接點密度,故可利用具有高接點密度的封裝載板(package carrier)來取代之,並藉由金屬導線或凸塊(bump)等導電媒體,將晶片封裝至封裝載板上。
以目前常用的發光二極體封裝結構來說,由於發光二極體晶片在使用前需先進行封裝,且發光二極體晶片在發出光線時會產生大量的熱能。倘若,發光二極體晶片所產生的熱能無法逸散而不斷地堆積在發光二極體封裝結構內,則發光二極體封裝結構的溫度會持續地上升。如此一來,發光二極體晶片可能會因為過熱而導致亮度衰減及使用壽命縮短,嚴重者甚至造成永久性的損壞。
隨著積體電路之積集度的增加,由於發光二極體晶片與封裝載板之間的熱膨脹係數不匹配(mismatch),其所產生的熱應力(thermal stress)與翹曲(warpage)的現象也日漸嚴重,而此結果將導致發光二極體晶片與封裝載板
之間的可靠度(reliability)下降。因此,現今封裝技術除著眼於提高光汲取效率外,另一重要關鍵技術是降低封裝結構的熱應力,以增加使用壽命及提高可靠度。
本發明提供一種封裝載板,可有效降低承載一發熱元件時之熱膨脹差異,可提高使用的可靠度。
本發明提供一種封裝載板的製作方法,用以製作上述之封裝載板。
本發明提出一種封裝載板的製作方法,其包括以下步驟。提供一絕緣基材。絕緣基材具有彼此相對之一上表面與一下表面、多個凹槽以及多個貫孔。凹槽位於下表面,而貫孔貫穿絕緣基材且分別連通至凹槽,以定義出多個通孔。形成一導電材料於通孔內,其中導電材料填滿通孔,而定義出多個導電柱。形成一絕緣層於絕緣基材的上表面上。絕緣層具有相對遠離絕緣基材之上表面的一頂表面以及多個從頂表面延伸至導電柱的盲孔。形成一圖案化線路層於絕緣層的頂表面上。圖案化線路層填滿盲孔且連接導電柱。圖案化線路層暴露出絕緣層的部分頂表面。形成一防焊層於圖案化線路層上。防焊層覆蓋圖案化線路層及其所暴露出之絕緣層的部分頂表面。防焊層具有多個開口,其中開口暴露出部分圖案化線路層,而定義出多個接墊。
在本發明之一實施例中,上述絕緣基材的材質包括ABF樹脂、高分子材料、矽填充物或環氧樹脂。
在本發明之一實施例中,上述絕緣基材之凹槽的形成方法包括雷射成孔法或射出成形法。
在本發明之一實施例中,上述絕緣基材之貫孔的形成方法包括雷射成孔法。
在本發明之一實施例中,上述形成導電材料於通孔的步驟,包括:進行一無電電鍍步驟,以於絕緣基材的上表面、下表面、通孔內形成導電材料,其中導電材料覆蓋絕緣基材的上表面與下表面且填滿通孔;以及移除位於絕緣基材之上表面與下表面上的部分導電材料,以暴露出絕緣基材的上表面與下表面,而定義出導電柱。
在本發明之一實施例中,上述每一導電柱具有彼此相對之一第一表面以及一第二表面。每一導電柱的第一表面與絕緣基材的上表面齊平,而每一導電柱的第二表面與絕緣基材的下表面齊平。
在本發明之一實施例中,上述形成絕緣層的方法包括熱壓合法。
在本發明之一實施例中,上述絕緣層的材質包括ABF樹脂、高分子材料、矽填充物或環氧樹脂。
在本發明之一實施例中,上述絕緣層之盲孔的形成方法包括雷射成孔法。
在本發明之一實施例中,上述形成圖案化線路層的方法包括無電電鍍法或半加成法。
在本發明之一實施例中,上述於形成防焊層之後,更包括形成一表面處理層於接墊上。
在本發明之一實施例中,上述表面處理層包括一電鍍金層、一電鍍銀層、一還原金層、一還原銀層、一電鍍鎳鈀金層、一化鎳鈀金層或一有機保焊劑(organic solderability preservatives,OSP)層。
本發明提出一種封裝載板,適於承載一發熱元件。封裝載板包括一絕緣基材、多個導電柱、一絕緣層、一圖案化線路層以及一防焊層。絕緣基材具有一彼此相對之一上表面與一下表面、多個凹槽以及多個貫孔。凹槽位於下表面,而貫孔貫穿絕緣基材且分別連通至凹槽,以定義出多個通孔。導電柱分別配置於通孔內,且每一導電柱具有彼此相對之一第一表面與一第二表面。每一導電柱的第一表面與絕緣基材的上表面齊平,而每一導電柱的第二表面與絕緣基材的下表面齊平。絕緣層配置於絕緣基材的上表面上。絕緣層具有相對遠離絕緣基材之上表面的一頂表面以及多個從頂表面延伸至導電柱的盲孔。圖案化線路層配置於絕緣層的頂表面上且暴露出絕緣層的部分頂表面。圖案化線路層填滿盲孔且連接導電柱。防焊層配置於圖案化線路層上。防焊層覆蓋圖案化線路層及其所暴露出之絕緣層的部分頂表面。防焊層具有多個開口,其中開口暴露出部分圖案化線路層,以定義出多個接墊,而發熱元件配置於接墊上。
在本發明之一實施例中,上述之封裝載板更包括一表面處理層,配置於接墊上。
在本發明之一實施例中,上述表面處理層包括一電鍍
金層、一電鍍銀層、一還原金層、一還原銀層、一電鍍鎳鈀金層、一化鎳鈀金層或一有機保焊劑(organic solderability preservatives,OSP)層。
基於上述,本發明之封裝載板是使用具有理想之熱膨脹係數的絕緣基材作為核心(core),因此當後續使用在發熱元件(如:晶片)的封裝時,有效縮小封裝基板及其所載發熱元件間之熱膨脹係數的差異,可避免發熱元件與絕緣基材之間因熱膨脹係數差異過大而導致相互之間的應力增加,可有效防止發熱元件剝落、壞損的現象產生,進而可提高封裝載板的使用可靠度。
為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
圖1A至圖1H為本發明之一實施例之一種封裝載板的製作方法的剖面示意圖。依照本實施例的封裝載板的製作方法,首先,請參考圖1A,首先,提供一絕緣基材110。絕緣基材110具有彼此相對之一上表面112與一下表面114以及多個凹槽116,其中凹槽116位於絕緣基材110的下表面114。於此,形成絕緣基材110之凹槽116的方法例如是雷射成孔法或射出成形法。此外,絕緣基材110的材質例如是ABF樹脂、高分子材料、矽填充物或環氧樹脂。
接著,請參考圖1B,於絕緣基材110的上表面112
上形成貫穿絕緣基材110且分別連通至凹槽116的貫孔118。於此,每一貫孔118與對應的凹槽116可定義出一通孔T,且每一貫孔118的孔徑實質上小於每一凹槽116的孔徑。此外,形成貫孔118的方法例如是雷射成孔法。
接著,請參考圖1C,進行一無電電鍍步驟,以於絕緣基材110的上表面112、下表面114、通孔T內形成一導電材料120。導電材料120覆蓋絕緣基材110的上表面112與下表面114且填滿通孔T,其中導電材料120例如是銅。
接著,請參考圖1D,移除位於絕緣基材110之上表面112與下表面114上的部分導電材料120,以暴露出絕緣基材110的上表面112與下表面114,而定義出多個導電柱120a。於此,每一導電柱120a具有彼此相對之一第一表面122以及一第二表面124。每一導電柱120a的第一表面122與絕緣基材110的上表面112實質上齊平,而每一導電柱120a的第二表面124與絕緣基材110的下表面114實質上齊平。
接著,請參考圖1E,形成一絕緣層130於絕緣基材110的上表面112上,其中絕緣層130具有相對遠離絕緣基材110之上表面112的一頂表面132。於此,形成絕緣層130的方法例如是熱壓合法。此外,絕緣層130的材質例如是ABF樹脂、高分子材料、矽填充物或環氧樹脂。
接著,請參考圖1F,形成多個從絕緣層130之頂表面132延伸至導電柱120a的盲孔B,其中盲孔B分別暴露出
導電柱120a的第一表面122。於此,絕緣層130之盲孔B的形成方法例如是雷射成孔法。
之後,請參考圖1G,形成一圖案化線路層140於絕緣層130的頂表面132上,其中圖案化線路層140填滿盲孔B且結構性及電性連接導電柱120a,並且圖案化線路層140暴露出絕緣層130的部分頂表面132。於此,形成圖案化線路層140的方法例如是無電電鍍法或半加成法,於此並不加以限制。
最後,請參考圖1H,形成一防焊層150於圖案化線路層140上,其中防焊層150覆蓋圖案化線路層140及其所暴露出之絕緣層130的部分頂表面132。於此,防焊層150具有多個開口152,其中開口152暴露出部分圖案化線路層140,而定義出多個接墊142。此外,本實施例之封裝載板的製作方法更可包括形成一表面處理層160於接墊142上,其中表面處理層160例如是一電鍍金層、一電鍍銀層、一還原金層、一還原銀層、一電鍍鎳鈀金層、一化鎳鈀金層或一有機保焊劑(organic solderability preservatives,OSP)層。於此,形成表面處理層160的方法例如是電鍍法或無電電鍍法,於此並不加以限制。至此,已完成封裝載板100的製作。
在結構上,請再參考圖1H,本實施例之封裝載板100包括絕緣基材110、導電柱120a、絕緣層130、圖案化線路層140以及防焊層150。絕緣基材110具有彼此相對之上表面112與下表面114、凹槽116以及貫孔118,其中每
一貫孔118的孔徑實質上小於每一凹槽116的孔徑。凹槽116位於下表面114,而貫孔118貫穿絕緣基材110且分別連通至凹槽116,以定義出通孔T。導電柱120a分別配置於通孔T內,且每一導電柱120a具有彼此相對之第一表面122與第二表面124。每一導電柱120a的第一表面122與絕緣基材110的上表面112實質上齊平,而每一導電柱120a的第二表面124與絕緣基材110的下表面114實質上齊平。絕緣層130配置於絕緣基材110的上表面112上。絕緣層130具有相對遠離絕緣基材110之上表面112的頂表面132以及從頂表面132延伸至導電柱120a的盲孔B。圖案化線路層140配置於絕緣層130的頂表面132上且暴露出絕緣層130的部分頂表面132。圖案化線路層140填滿盲孔B且連接導電柱120a。防焊層150配置於圖案化線路層140上,且防焊層150覆蓋圖案化線路層140及其所暴露出之絕緣層130的部分頂表面132。防焊層150具有多個開口152,其中開口152暴露出部分圖案化線路層140,而定義出接墊142。此外,本實施例之封裝載板100可更包括配置於接墊142上的表面處理層160,其中表面處理層160例如是一電鍍金層、一電鍍銀層、一還原金層、一還原銀層、一電鍍鎳鈀金層、一化鎳鈀金層或一有機保焊劑(organic solderability preservatives,OSP)層。
由於本實施例是採用絕緣基材110來作為封裝載板100的核心(core),其中絕緣基材110具有理想之熱膨脹係數(例如是與後續應用之發熱元件的熱膨脹係數相近),
因此當將封裝載板100使用在後續發熱元件(未繪示)封裝時,可縮小封裝載板100及其所載發熱元件間之熱膨脹係數的差異,可避免發熱元件與絕緣基材110之間因熱膨脹係數差異過大而導致相互之間的應力增加,可有效防止發熱元件剝落、壞損的現象產生,進而可提高封裝載板100的使用可靠度。此外,由於本實施例之圖案化線路層140是採用無電電鍍法或半加成法所形成,因此圖案化線路層140的寬度可符合細線路的規格。
圖2為本發明之圖1H之封裝載板承載一發熱元件的剖面示意圖。在本實施例中,封裝載板100適於承載一發熱元件200,其中發熱元件200配置於對應防焊層150之開口152所暴露出之接墊142上方的表面處理層160上,而發熱元件200例如是一電子晶片或一光電元件,但並不以此為限。舉例來說,電子晶片可以是一積體電路晶片,其例如為一繪圖晶片、一記憶體晶片、一半導體晶片等單一晶片或是一晶片模組。光電元件例如是一發光二極體(LED)、一雷射二極體或一氣體放電光源等。在此,發熱元件200是以一發光二極體(LED)作為舉例說明。
詳細來說,發熱元件200(例如是半導體晶片)可透過覆晶接合的方式而電性連接至表面處理層160。由於本實施例是採用具有理想之熱膨脹係數的絕緣基材110來作為封裝載板10的核心(core),因此發熱元件200與封裝載板100彼此之間的熱膨脹係數差異可漸近式的逐漸減少。如此一來,可避免發熱元件200與封裝載板100之間
因熱膨脹係數差異過大而導致相互之間的應力增加,可有效防止發熱元件200剝落、壞損的現象產生,進而可提高封裝載板100的使用可靠度。再者,當將發熱元件200配置於封裝載板100上時,發熱元件200所產生的熱可透過表面處理層160、圖案化線路層140及導熱柱120a而快速地傳遞至外界。如此一來,本實施例之封裝載板100可以有效地排除發熱元件200所產生的熱,進而改善發熱元件200的使用效率與使用壽命。此外,本實施例之封裝載板100之絕緣基材110的下表面114亦可設置多個銲球210,而封裝載板100透過銲球210可與外部電路(未繪示)電性連接,可有效增加封裝載板100的應用性。
綜上所述,本發明之封裝載板是使用具有理想之熱膨脹係數的絕緣基材作為核心(core),因此當後續使用在發熱元件(如:晶片)的封裝時,可有效縮小封裝基板及其所載發熱元件間之熱膨脹係數的差異,可避免發熱元件與絕緣基材之間因熱膨脹係數差異過大而導致相互之間的應力增加,可有效防止發熱元件剝落、壞損的現象產生,進而可提高封裝載板的使用可靠度。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧封裝載板
110‧‧‧絕緣基材
112‧‧‧上表面
114‧‧‧下表面
116‧‧‧凹槽
118‧‧‧貫孔
120‧‧‧導電材料
120a‧‧‧導電柱
122‧‧‧第一表面
124‧‧‧第二表面
130‧‧‧絕緣層
132‧‧‧頂表面
140‧‧‧圖案化線路層
142‧‧‧接墊
150‧‧‧防焊層
152‧‧‧開口
160‧‧‧表面處理層
200‧‧‧晶片
210‧‧‧銲球
B‧‧‧盲孔
T‧‧‧通孔
圖1A至圖1H為本發明之一實施例之一種封裝載板的製作方法的剖面示意圖。
圖2為本發明之圖1H之封裝載板承載一發熱元件的剖面示意圖。
100‧‧‧封裝載板
110‧‧‧絕緣基材
112‧‧‧上表面
114‧‧‧下表面
116‧‧‧凹槽
118‧‧‧貫孔
120a‧‧‧導電柱
122‧‧‧第一表面
124‧‧‧第二表面
130‧‧‧絕緣層
132‧‧‧頂表面
140‧‧‧圖案化線路層
142‧‧‧接墊
150‧‧‧防焊層
152‧‧‧開口
160‧‧‧表面處理層
B‧‧‧盲孔
T‧‧‧通孔
Claims (15)
- 一種封裝載板的製作方法,包括:提供一絕緣基材,該絕緣基材具有彼此相對之一上表面與一下表面、多個凹槽以及多個貫孔,其中該些凹槽位於該下表面,而該些貫孔貫穿該絕緣基材且分別連通至該些凹槽,以定義出多個通孔;形成一導電材料於該些通孔內,其中該導電材料填滿該些通孔,而定義出多個導電柱;形成一絕緣層於該絕緣基材的該上表面上,其中該絕緣層具有相對遠離該絕緣基材之該上表面的一頂表面以及多個從該頂表面延伸至該些導電柱的盲孔;形成一圖案化線路層於該絕緣層的該頂表面上,其中該圖案化線路層填滿該些盲孔且連接該些導電柱,該圖案化線路層暴露出該絕緣層的部分該頂表面;以及形成一防焊層於該圖案化線路層上,該防焊層覆蓋該圖案化線路層及其所暴露出之該絕緣層的部分該頂表面,且該防焊層具有多個開口,其中該些開口暴露出部分該圖案化線路層,而定義出多個接墊。
- 如申請專利範圍第1項所述之封裝載板的製作方法,其中該絕緣基材的材質包括ABF樹脂、高分子材料、矽填充物或環氧樹脂。
- 如申請專利範圍第1項所述之封裝載板的製作方法,其中該絕緣基材之該些凹槽的形成方法包括雷射成孔法或射出成形法。
- 如申請專利範圍第1項所述之封裝載板的製作方法,其中該絕緣基材之該些貫孔的形成方法包括雷射成孔法。
- 如申請專利範圍第1項所述之封裝載板的製作方法,其中形成該導電材料於該些通孔的步驟,包括:進行一無電電鍍步驟,以於該絕緣基材的該上表面、該下表面、該些通孔內形成該導電材料,其中該導電材料覆蓋該絕緣基材的該上表面與該下表面且填滿該些通孔;以及移除位於該絕緣基材之該上表面與該下表面上的部分該導電材料,以暴露出該絕緣基材的該上表面與該下表面,而定義出該些導電柱。
- 如申請專利範圍第1項所述之封裝載板的製作方法,其中各該導電柱具有彼此相對之一第一表面以及一第二表面,各該導電柱的該第一表面與該絕緣基材的該上表面齊平,而各該導電柱的該第二表面與該絕緣基材的該下表面齊平。
- 如申請專利範圍第1項所述之封裝載板的製作方法,其中形成該絕緣層的方法包括熱壓合法。
- 如申請專利範圍第1項所述之封裝載板的製作方法,其中該絕緣層的材質包括ABF樹脂、高分子材料、矽填充物或環氧樹脂。
- 如申請專利範圍第1項所述之封裝載板的製作方法,其中該絕緣層之該些盲孔的形成方法包括雷射成孔法。
- 如申請專利範圍第1項所述之封裝載板的製作方法,其中形成該圖案化線路層的方法包括無電電鍍法或半加成法。
- 如申請專利範圍第1項所述之封裝載板的製作方法,更包括:於形成該防焊層之後,形成一表面處理層於該些接墊上。
- 如申請專利範圍第11項所述之封裝載板的製作方法,其中該表面處理層包括一電鍍金層、一電鍍銀層、一還原金層、一還原銀層、一電鍍鎳鈀金層、一化鎳鈀金層或一有機保焊劑層。
- 一種封裝載板,適於承載一發熱元件,該封裝載板包括:一絕緣基材,具有彼此相對之一上表面與一下表面、多個凹槽以及多個貫孔,其中該些凹槽位於該下表面,而該些貫孔貫穿該絕緣基材且分別連通至該些凹槽,以定義出多個通孔;多個導電柱,分別配置於該些通孔內,且各該導電柱具有彼此相對之一第一表面與一第二表面,其中各該導電柱的該第一表面與該絕緣基材的該上表面齊平,而各該導電柱的該第二表面與該絕緣基材的該下表面齊平;一絕緣層,配置於該絕緣基材的該上表面上,其中該絕緣層具有相對遠離該絕緣基材之該上表面的一頂表面以及多個從該頂表面延伸至該些導電柱的盲孔; 一圖案化線路層,配置於該絕緣層的該頂表面上且暴露出該絕緣層的部分該頂表面,該圖案化線路層填滿該些盲孔且連接該些導電柱;以及一防焊層,配置於該圖案化線路層上,該防焊層覆蓋該圖案化線路層及其所暴露出之該絕緣層的部分該頂表面,且該防焊層具有多個開口,其中該些開口暴露出部分該圖案化線路層,以定義出多個接墊,而該發熱元件配置於該些接墊上。
- 如申請專利範圍第13項所述之封裝載板,更包括一表面處理層,配置於該些接墊上。
- 如申請專利範圍第14項所述之封裝載板,其中該該表面處理層包括一電鍍金層、一電鍍銀層、一還原金層、一還原銀層、一電鍍鎳鈀金層、一化鎳鈀金層或一有機保焊劑層。
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CN201310004256.5A CN103579011B (zh) | 2012-08-08 | 2013-01-07 | 封装载板及其制作方法 |
JP2013011674A JP5509353B2 (ja) | 2012-08-08 | 2013-01-25 | パッケージキャリアおよびその製造方法 |
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TWI562293B (en) * | 2015-04-24 | 2016-12-11 | Qi Ding Technology Qinhuangdao Co Ltd | Manufacturing method of chip packaging structure |
TWI594383B (zh) * | 2016-07-04 | 2017-08-01 | 欣興電子股份有限公司 | 封裝基板及其製造方法 |
TWI841502B (zh) * | 2023-08-28 | 2024-05-01 | 景碩科技股份有限公司 | 抗彎折強化載板 |
TWI843121B (zh) * | 2022-06-10 | 2024-05-21 | 旭德科技股份有限公司 | 散熱基板 |
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CN104241466A (zh) * | 2014-09-29 | 2014-12-24 | 广东威创视讯科技股份有限公司 | Led基板的转接结构、pcb转接层的设计方法及led显示屏 |
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JP2004179575A (ja) * | 2002-11-29 | 2004-06-24 | Ngk Spark Plug Co Ltd | 配線基板用コア基板及びその製造方法、並びにそれを用いたビルドアップ配線基板 |
CN100383936C (zh) * | 2002-12-20 | 2008-04-23 | 国际商业机器公司 | 三维器件制造方法 |
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CN1220415C (zh) * | 2003-04-15 | 2005-09-21 | 威盛电子股份有限公司 | 制作多层电路板的方法 |
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KR100618343B1 (ko) * | 2004-10-28 | 2006-08-31 | 삼성전자주식회사 | 패키징 기판의 제조방법 및 이를 이용한 패키징 방법. |
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TWI470757B (zh) * | 2009-10-22 | 2015-01-21 | Unimicron Technology Corp | 封裝基板及其製法 |
TW201230260A (en) * | 2011-01-14 | 2012-07-16 | Subtron Technology Co Ltd | Package carrier and manufacturing method thereof |
-
2012
- 2012-08-08 TW TW101128619A patent/TWI487041B/zh not_active IP Right Cessation
- 2012-09-14 US US13/615,698 patent/US20140041922A1/en not_active Abandoned
-
2013
- 2013-01-07 CN CN201310004256.5A patent/CN103579011B/zh not_active Expired - Fee Related
- 2013-01-25 JP JP2013011674A patent/JP5509353B2/ja active Active
-
2014
- 2014-11-19 US US14/547,147 patent/US9204560B2/en not_active Expired - Fee Related
Cited By (6)
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TWI562293B (en) * | 2015-04-24 | 2016-12-11 | Qi Ding Technology Qinhuangdao Co Ltd | Manufacturing method of chip packaging structure |
CN106298692A (zh) * | 2015-04-24 | 2017-01-04 | 碁鼎科技秦皇岛有限公司 | 芯片封装基板、芯片封装结构及其制作方法 |
CN106298692B (zh) * | 2015-04-24 | 2019-02-01 | 碁鼎科技秦皇岛有限公司 | 芯片封装结构的制作方法 |
TWI594383B (zh) * | 2016-07-04 | 2017-08-01 | 欣興電子股份有限公司 | 封裝基板及其製造方法 |
TWI843121B (zh) * | 2022-06-10 | 2024-05-21 | 旭德科技股份有限公司 | 散熱基板 |
TWI841502B (zh) * | 2023-08-28 | 2024-05-01 | 景碩科技股份有限公司 | 抗彎折強化載板 |
Also Published As
Publication number | Publication date |
---|---|
US20150068034A1 (en) | 2015-03-12 |
US20140041922A1 (en) | 2014-02-13 |
CN103579011A (zh) | 2014-02-12 |
CN103579011B (zh) | 2016-05-25 |
JP2014036222A (ja) | 2014-02-24 |
TWI487041B (zh) | 2015-06-01 |
JP5509353B2 (ja) | 2014-06-04 |
US9204560B2 (en) | 2015-12-01 |
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