TW201336032A - 封裝的半導體元件及半導體元件封裝與其形成方法 - Google Patents

封裝的半導體元件及半導體元件封裝與其形成方法 Download PDF

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TW201336032A
TW201336032A TW101116457A TW101116457A TW201336032A TW 201336032 A TW201336032 A TW 201336032A TW 101116457 A TW101116457 A TW 101116457A TW 101116457 A TW101116457 A TW 101116457A TW 201336032 A TW201336032 A TW 201336032A
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package
semiconductor die
conductive
molding compound
semiconductor
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TW101116457A
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TWI567899B (zh
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Yu-Feng Chen
Chun-Hung Lin
Han-Ping Pu
Ming-Da Cheng
Kai-Chiang Wu
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Taiwan Semiconductor Mfg
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Abstract

本發明提供封裝上封裝的連接物之形成方法，可減少連接物的尺寸與間距，進而縮減封裝尺寸並增加連接數目。一封裝上的導電單元係部份埋置於封裝的模塑化合物中，以接合至另一封裝上的接觸物或金屬墊。藉由埋置導電單元，可縮小導電單元，並使導電單元與模塑化合物之間無溝槽。連接物之間的間距取決於連接物的最大寬度與外增邊區。其他封裝上的多種接觸物可接合至導電單元。

Description

封裝的半導體元件及半導體元件封裝與其形成方法
本發明係關於半導體元件，更特別關於其封裝結構。
半導體元件可應用於多種電子裝置，比如個人電腦、手機、數位相機、及其他電子設備。一般的半導體元件製程依序為沉積隔離層或介電層、導電層、與半導體層於半導體基板上，再微影圖案化上述層狀材料以形成電路構件與單元。
在半導體產業中，持續縮小元件尺寸亦可持續改善多種電子構件(比如電晶體、二極體、電阻、電容、或類似物)的積體密度，即特定面積可整合更多構件。在某些應用中，更小的電子構件需要更小的封裝(比如更低的封裝高度及/或更小的面積)。
如此一來，需發展新的封裝技術如封裝上封裝(PoP)，使某一元件晶粒的頂部封裝係接合至另一元件晶粒的底部封裝。藉由新的封裝技術，可增加封裝的積體等級。這些相對較新的半導體封裝技術將面對製程挑戰。
本發明一實施例提供一種封裝的半導體元件，包括：半導體晶粒埋置於模塑化合物中；導電單元埋置於模塑化合物中，其中導電單元露出於模塑化合物之表面上；以及金屬墊，其中金屬墊接觸導電單元並電性連接至半導體晶粒中的多個元件。
本發明一實施例提供一種半導體元件封裝，包括：第一半導體晶粒封裝具有導電單元埋置於模塑化合物中，其中導電單元露出於模塑化合物之表面上，其中模塑化合物覆蓋至少一第一半導體晶粒；以及第二半導體晶粒封裝，且第二半導體晶粒封裝之表面上具有導電接觸物，其中第一半導體晶粒封裝之導電單元接合至第二半導體晶粒封裝之導電接觸物，以形成連接物。
本發明一實施例提供一種半導體元件封裝的形成方法，包括：製備第一半導體晶粒封裝，第一半導體晶粒封裝具有多個導電單元埋置於模塑化合物中，其中導電單元露出於模塑化合物之表面上；提供第一半導體晶粒封裝；提供第二半導體晶粒封裝；以及接合第一半導體晶粒封裝之導電單元至第二半導體晶粒封裝上的多個接觸物。
下述內容將詳述如何製造及使用的實施例。可以理解的是，這些實施例提供之多種發明概念可用以實施於多種特定方式。下述的特定實施例僅用以舉例而非侷限本發明。
第1A圖係本發明某些實施例中封裝100之透視圖。封裝100中的封裝110接合至另一封裝120，而封裝120更接合至基板130。每一封裝如封裝110或120，均包含至少一半導體晶粒(未圖示)。半導體晶粒包含用以製作半導體積體電路的基板，而積體電路係形成於基板中或基板上。半導體基板的組成為半導體材料，包含但不限於基體矽、半導體晶圓、絕緣層上矽(SOI)基板、或矽鍺基板。半導體基板亦可為其他半導體材料，比如III族元素、IV族元素、或V族元素。基板130可進一步包含多個隔離結構(未圖示)，比如淺溝槽隔離結構或局部氧化矽(LOCOS)結構。隔離結構可定義並隔離多種微電子單元。形成於基板130中的微電子單元可為電晶體如金氧半場效電晶體(MOSFET)、互補式金氧半(CMOS)電晶體、雙極接面電晶體(BJT)、高電壓電晶體、高頻電晶體、p型通道及/或n型通道場效電晶體(PFET/NFET)、或其他電晶體，電阻，二極體，電容，電導，熔絲，或其他合適單元。用以形成微電子單元的多種製程包含沉積、蝕刻、佈植、微影、回火、及其他合適製程。微電子單元可藉由內連線形成積體電路元件，比如邏輯元件、記憶元件(如SRAM)、射頻元件、輸出/輸入(I/O)元件、系統晶片(SoC)元件、上述之組合、或其他合適元件。
基板130可為半導體晶圓或部份的晶圓。在某些實施例中，基板130包含矽、砷化鎵、絕緣層上矽(SOI)、或其他類似材料。在某些實施例中，基板130包含被動元件如電阻、電容、電導、或類似物，亦可包含主動元件如電晶體。在某些實施例中，基板130包含額外積體電路。基板130可進一步包含穿透基板穿孔(TSV)以作為中介片。此外，基板130可由其他材料組成。舉例來說，某些實施例中的基板130為多層電路板。在其他實施例中，基板130包含雙馬來醯亞胺三嗪(BT)樹脂、FR-4(玻璃纖維織布與環氧樹脂黏結劑組成的防火複合材料)、陶瓷、玻璃、塑膠、帶狀物、薄膜、或其他合適的支撐材料，以負載可接收導電末端之導電墊片。
封裝110經由連接物115接合至封裝120，且封裝120經由連接物125接合至基板130。第1B圖係第1A圖的封裝中，沿著切線P-P之部份剖視圖。如第1B圖所示，連接物115與125接近封裝100的邊緣。在某些實施例中，連接物125係接近封裝120的中心。在某些實施例中，第1B圖標示的區域150為矩形並詳述於第1C圖中。
第1C圖進一步詳述第1B圖之區域150。封裝110包含半導體晶粒區域A，其中模塑化合物111覆蓋半導體晶粒(未圖示)。在某些實施例中，模塑化合物111一開始為液態，但在施加至半導體晶粒上後乾燥並覆蓋至少部份的半導體晶粒。舉例來說，模塑化合物111可包含環氧樹脂、填充物、溶劑、或類似物。在某些實施例中，模塑化合物111之施加方式可為移轉模造法，先將模塑材料(通常為熱塑性材料)預加熱至液態，再施加至基板上。之後再加熱模塑材料以完成模塑步驟。模塑化合物材料可採用多種樹脂。
封裝110亦包含再佈線區域B，其具有內連線結構。在內連線結構中，一或多個再佈線層(RDL)藉由連接物115連接封裝中的半導體晶粒。同樣地，封裝120包含半導體晶粒區域A*，其中半導體晶粒(未圖示)係埋置於模塑化合物121中。封裝120亦包含再佈線區域B*，其亦具有內連線結構。在內連線結構中，一或多個再佈線層(RDL)藉由連接物125連接封裝中的半導體晶粒。
形成封裝110與120之機制可參考美國專利申請號13/228,244如附件，名稱為「採用晶粒貼合膜之封裝方法與結構」，且申請日為2011年9月8號。
如第1C圖所示，連接物115接觸封裝110之金屬墊112與封裝120之金屬墊122，而連接物125接觸封裝120之金屬墊123與基板130之金屬墊131。金屬墊112電性連接至封裝110中的半導體晶粒(未圖示)中的元件。金屬墊122電性連接至封裝120中的半導體晶粒(未圖示)中的元件。如第1C圖所示，連接物115係埋置於封裝120之模塑化合物121中。在某些實施例中，用以埋置連接物115之開口的形成方法為雷射鑽孔。如第1D圖所示，某些實施例以雷射鑽孔移除部份的模塑化合物121，以形成可埋置連接物115之開口114。開口114之剖視形狀為上寬下窄，以利於開口中置入導電單元如焊料球。在某些實施例中，由於雷射鑽孔的製程限制，開口114之頂部寬度W介於0.2mm至0.4mm之間。在形成開口114後，導電物116(虛線標示)如焊料球係置於開口114中。如第1D圖所示，開口頂部與導電物116之間隔有距離G。藉由後續的再流動製程，可讓導電物116接觸封裝110之金屬墊112上的導電材料，以形成導電物115。如第1C圖所示，再流動製程後的導電物115將接觸金屬墊122，且模塑化合物121之上表面與接觸物之間具有溝槽O。在某些實施例中，導電物116直接接觸金屬墊112以形成連接物115，且無任何其他導電材料形成於導電物116與金屬墊112上。
導電物115之間的間距P取決於開口114之寬度W。在某些實施例中，開口的最大寬度介於約0.23mm至約0.50mm之間。在某些實施例中，間距P介於約0.35mm至約0.6mm之間。在某些實施例中，高度H需足以維持整個封裝的形成高度。封裝110與120之間的高度C亦受開口114中的連接物尺寸所影響。在某些實施例中，高度C介於約0.25mm至約0.35mm之間。
在高等封裝中，需縮減連接物之間的間距P以符合更小的封裝尺寸與額外連接。如此一來，需以新的機制形成更小間距P的連接物115。如第2A圖所示的某些實施例中，晶粒封裝120’具有導電單元117’埋置於模塑化合物121’中。先形成導電單元117’金屬墊122上，接著再形成模塑化合物121’於晶粒封裝120’之再佈線區域B*上。舉例來說，可先將導電單元117’電鍍至金屬墊122上，接著使其再流動為球形。接著形成模塑化合物121’於導電單元117’上。在另一實施例中，先將金屬球置於金屬墊122上，再將其接合至金屬墊以形成導電單元117’。導電單元117’之組成可為任何低電阻的導電材料。舉例來說，導電單元117’可為焊料、焊料合金、金、金合金、或類似物。焊料合金可包含錫、鉛、銀、銅、鎳、鉍、或上述之組合。
如第2B圖所示，某些實施例移除部份的模塑化合物121’以露出導電單元117’。移除製程160可為適當製程如研磨、拋光、或類似製程。露出的導電單元117’具有寬度W1。由於導電單元117’在露出前即先埋置於模塑化合物121’中，因此不需雷射鑽孔形成開口以埋置導電單元117’。如此一來，模塑化合物121’之上表面與導電單元117’之間將不具有溝槽，比如第1C圖所示的溝槽O。此外，導電單元117’之尺寸(或寬度W1)不受雷射鑽孔形成的開口114尺寸限制，導電單元117’之尺寸(或寬度W1)可小於導電單元116。如此一來，第2B圖所示之間距P1可小於第1C圖所示之間距P。在某些實施例中，間距P1介於約100μm至約500μm之間。在某些實施例中，寬度W1介於約100μm至約400μm之間，即小於或等於第1D圖所示之開口的寬度W。
在另一實施例中，部份的導電單元117”係埋置於模塑化合物中，並露出其他部份的導電單元117”，如第2C圖所示。在形成模塑化合物121”時，以模具或薄膜施壓至模塑化合物121”與導電單元117”，即可露出部份的導電單元117”。露出的導電單元117”具有寬度W2。由於導電單元117”係埋置於模塑化合物121”中，導電單元117”之間距P2亦小於第1C圖所示之間距P。在某些實施例中，間距P2介於約100μm至約500μm之間。在某些實施例中，間距P2介於約100μm至約400μm之間。
第3A圖係本發明某些實施例中，具有接觸物104A之封裝110A與具有導電單元117A之封裝120A。接觸物104A係形成於金屬墊122A上，且接觸物104A之組成為導電材料。在某些實施例中，接觸物104A之組成為焊料。封裝120A之導電單元117A的形成方法，與某些實施例中形成第2A及2B圖之結構的前述製程類似。如第3B圖所示，某些實施例以再流動製程，可接合接觸物104A與導電單元117A以形成連接物115A。連接物115A具有高度HA。
第3C圖係本發明某些實施例中，具有接觸物104B之封裝110B與具有導電單元117B之封裝120B。接觸物104B係形成於金屬墊122B上，且接觸物104B之組成為導電材料。在某些實施例中，接觸物104B之組成為焊料。封裝120B之導電單元117B的形成方法，即某些實施例中形成第2C圖之結構的前述製程。如第3D圖所示，某些實施例以再流動製程，可接合接觸物104B與導電單元117B以形成連接物115B。連接物115B具有高度HB。
在某些其他的實施例中，封裝110C不具有接觸物於金屬墊122C上，如第3E圖所示。如第3F圖所示，導電單元117C直接接觸金屬墊122C以形成連接物115C。連接物115C具有高度HC。
第4A圖為某些實施例中，金屬墊405上的焊料球401經再流動製程的形態。金屬墊405之寬度為約200μm，且金屬墊405包含凸塊下金屬化(UBM)層402。凸塊下金屬化層可包含黏著層及/或濕潤層。在某些實施例中，凸塊下金屬化層402亦可作為擴散阻障層。在某些實施例中，凸塊下金屬化層402之組成為鈦、氮化鈦、氮化鉭、鉭、或類似物。在某些實施例中，凸塊下金屬化層402更包含銅晶種層。
在某些實施例中，凸塊下金屬化層402之厚度介於約0.05μm至約0.5μm之間。焊料球401之形成方法為再流動凸塊下金屬化層402上的焊料球(直徑約250μm)。如第4A圖所示，焊料將展開於凸塊下金屬化層402的表面上，且表面張力讓焊料球401之直徑為約246μm。焊料球401之高度為約216μm。凸塊下金屬化層上的焊料球經再流動製程後的形狀，可藉由模擬器模擬。模擬器可為SURFACE EVOLVER或ANSYS FLUENT. SURFACE EVOLVER等以表面張力及其他能量計算表面形狀的互動程式。SURFACE EVOLVER係由明尼蘇達大學的幾何學中心研發，而ANSYS FLUENT. SURFACE EVOLVER為ANSYS INC. OF CANONSBURG,PENNSYLVANIA擁有的模擬器。上述模擬器可用以模擬不同寬度與高度的焊料球。
第4B圖係某些實施例中，以再流動的焊料球之模擬高度，對應其直徑(最大寬度)與凸塊下金屬化層之尺寸(寬度)的圖示。線段410為再流動前的焊料球直徑，與焊料球下方之凸塊下金屬化層寬度(或尺寸)相同時，不同凸塊下方金屬化層之尺寸所對應之焊球高度。線段410指出當直徑為200μm之焊料球以再流動方式接合至半徑為200μm之凸塊下金屬化層時，再流動後的焊料球高度為152μm。當直徑為250μm之焊料球以再流動方式接合至半徑為250μm之凸塊下金屬化層時，再流動後的焊料球高度為186μm。線段420指出當直徑為200μm之焊料球以再流動方式接合至半徑為200μm之凸塊下金屬化層時，再流動後的焊料球寬度為218μm。當直徑為250μm之焊料球以再流動方式接合至半徑為250μm之凸塊下金屬化層時，再流動後的焊料球寬度為274μm。再流動前的焊料球尺寸與凸塊下金屬化層之寬度(或尺寸)相關，因此線段410與420為線性。
第4B圖之資料411指的是直徑為250μm的焊料球經再流動製程後，接合至直徑為150μm之凸塊下金屬化層後的焊料球高度。資料411指出再流動後的焊料球高度為223μm。第4B圖中的資料412為再流動製程後的焊料球之最大寬度。資料412指出再流動製程後的焊料球其最大寬度為256μm。資料411與412顯示，焊料球的高度與直徑取決於再流動製程前的焊料球尺寸。
再流動製程後的焊料球其最大寬度的資料，可用以確認最小間距以避免短路。沿著最大寬度新增邊區，即可作為連接物的最小間距。在某些實施例中，線段450為間距。在連接物之最大寬度外新增邊區M，兩者總合即最小間距。邊區M可隨再流動前的焊料球尺寸改變。在某些實施例中，邊區M占再流動的焊料球之最大寬度的幾個百分比。在某些實施例中，邊區M占再流動的焊料球之最大寬度的約5%至約70%之間。在某些實施例中，邊區M占再流動的焊料球之最大寬度的約5%至約30%之間。
第5圖係某些實施例中，以再流動的連接物115B之模擬高度HB，對應再流動前的焊料球露出的寬度W2(如第2C圖所示)的圖示。第5圖中的實心三角形為封裝120B與110B的連接物資料，這些實心三角形可回歸至線段510。線段510中，埋置於封裝120B中的焊料球的直徑為250μm，而凸塊下金屬化層之直徑亦為250μm。線段510中，封裝110B之焊料球的直徑為200μm，而凸塊下金屬化層之直徑為250μm。線段510顯示當埋置的焊料球露出的寬度W2越大，再流動的連接物115B之模擬高度HB越小。
空心菱形可回歸至線段520。線段520中，埋置於封裝120B中的焊料球的直徑為250μm，而凸塊下金屬化層之直徑亦為200μm(小於線段510中的凸塊下金屬化層之直徑250μm)。線段520中，封裝110B之焊料球的直徑亦為200μm。線段520與510幾乎重疊，即凸塊下金屬化層之寬度差距為50μm時幾乎不造成影響。
第5圖之資料511為第3F圖之連接物115C，其中封裝110C的每一金屬墊112C上不具有焊料球。資料511中，封裝120C亦具有直徑250μm的焊料球於直徑200μm的凸塊下金屬化層上。與線段510及520相較，由於資料511之封裝110C上不具有焊料球，連接物115C之高度可減少約80μm。第5圖中的實心方形為封裝的連接物資料，這些實心方形可回歸至線段530。線段530中，埋置於封裝120B中的焊料球的直徑為250μm，而凸塊下金屬化層之直徑亦為200μm。線段530中位於封裝120B上之再流動前的焊料球，小於線段510與520中位於封裝120B上之再流動前的焊料球。線段530中，封裝110B之焊料球的直徑為200μm，而凸塊下金屬化層之直徑為250μm。線段530中位於封裝110B上之焊料球，與線段510與520中位於封裝110B上之焊料球類似。由於封裝120B上的焊料球尺寸較小，線段530上的資料小於線段510與520上的資料。
如前所述，需採用較小的封裝總高度以達到較小的製程參數。如第5圖所示，當埋置的焊料球的露出寬度越大，則連接物的高度越小。為了降低連接物高度，需增加埋置的焊料球露出的寬度。當封裝之埋置焊料球露出的寬度大於或等於約100μm時，連接物的總高度將小於或等於約300μm。
第6A圖顯示本發明某些實施例中，封裝100A”之封裝120A”具有埋置的焊料球。封裝100A”與前述之封裝100類似，除了封裝120A”不似第2C、3C、及3E圖一樣具有埋置的焊料球於模塑化合物中，而是以第1B圖之雷射鑽孔取代。第6B圖顯示本發明某些實施例中，封裝100B”之封裝120B”具有埋置的焊料球。封裝100B”與前述之封裝100A”類似，除了封裝110B”上的焊料球體積為封裝110A”上的焊料球體積之兩倍。如此一來，第6B圖中的高度HB”大於第6A圖之高度HA”。在應力模擬中，若角落的連接物125A”之應力比(SR)定為1，則連接物115A”之應力比(SR)為1.2。相反地，第6B圖中角落的連接物125B”之應力比(SR)為1.17，高於第6A圖中角落的連接物125A”的應力比(1)。此外，連接物115B”之應力比(SR)為0.85，小於連接物115A”之應力比(1.2)。
上述兩種結構的應力比差異係來自於封裝110B”的焊料體積為封裝110A”的焊料體積之兩倍，且高度HB”大於高度HA”。在某些實施例中，為了最佳化製程產率，可設定封裝110A”或110B”上的焊料球中的焊料體積。舉例來說，若角落的連接物上的焊料球具有碎裂風險(比如具有高應力之角落的連接物125B”)，則需採用第6A圖之結構以降低封裝110A”上的焊料球體積，並降低封裝的高度HA”。另一方面，若角落的連接物125B”不具有碎裂風險，反而是連接器125A”之焊料具有碎裂風險時，則需採用第6B圖所示之結構。這是因為第6B圖中的連接器115B”具有較低應力。上述應力的模擬可採用ANSYS應力模擬器。
第3A至3D圖與6A至6B圖的封裝結構中，較上方的封裝110A、110B、110A”、與110B”的接觸物104為焊料球，可連接至較下方的封裝120A、120B、120A”、及120B”之導電單元117’或117”。然而接觸物104可為其他導電材料與具有其他形狀。舉例來說，某些實施例中的接觸物104*可為銅柱，如第7A圖所示。在某些實施例中，銅柱的接觸物104*可形成於凸塊下金屬化層102*上，而凸塊下金屬化層102*覆蓋金屬墊112*。在某些實施例中，銅柱的接觸物104*之寬度W*介於約100μm至約250μm之間。在某些實施例中，銅柱的接觸物104*之高度H*介於約10μm至約200μm之間。在另一實施例中，接觸物104**可為寬度小於凸塊下金屬化層102**之銅柱，如第7B圖所示。在某些實施例中，二個或多個較小的銅柱係位於凸塊下金屬化層102**上，且金屬凸塊下金屬化層102**覆蓋金屬墊112**。第7C圖係某些實施例中，接觸物104**的不同上視圖。如第7C圖所示，兩個或多個接觸物104**具有多種形狀。舉例來說，接觸物104**可為圓柱、細長柱、或具有圓潤角的方柱。第7C圖中的實施例僅用以舉例，接觸物亦可為其他構形。舉例來說，凸塊下金屬化層102**除了圖示的圓形外亦可為其他形狀。
上述實施例中封裝上封裝的連接物之形成機制，可縮小連接物及連接物之間的間距。與現有的連接物相較，上述的連接物可縮小封裝尺寸與增加連接數目。某一封裝上的導電單元係部份埋置於封裝的模塑化合物中，且接合至另一封裝上的金屬墊或接觸物。藉由埋置導電單元，可縮小導電單元並避免任何溝槽形成於導電單元與模塑化合物之間。連接物之間的間距取決於連接物的最大寬度與外增邊區。其他封裝上的多種接觸物可接合至導電單元。
本發明某些實施例提供封裝的半導體元件，包括：半導體晶粒埋置於模塑化合物中，與導電單元埋置於模塑化合物中。導電單元露出於模塑化合物之表面上。金屬墊接觸導電單元並電性連接至半導體晶粒中的多個元件。
本發明某些其他實施例提供半導體元件封裝，包括：第一半導體晶粒封裝具有導電單元埋置於模塑化合物中。導電單元露出於模塑化合物之表面上，且模塑化合物覆蓋至少一第一半導體晶粒。第二半導體晶粒封裝之表面上具有導電接觸物。第一半導體晶粒封裝之導電單元接合至第二半導體晶粒封裝之導電接觸物，以形成連接物。
本發明某些其他實施例提供半導體元件封裝的形成方法，包括：製備第一半導體晶粒封裝，第一半導體晶粒封裝具有多個導電單元埋置於模塑化合物中，其中導電單元露出於模塑化合物之表面上。提供第一半導體晶粒封裝。提供第二半導體晶粒封裝。接合第一半導體晶粒封裝之導電單元至第二半導體晶粒封裝上的多個接觸物。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
A、A*．．．半導體晶粒區域
B、B*．．．再佈線區域
C、H、HA、HB、HC、HA”、HB”、H*．．．高度
G．．．距離
M．．．邊區
O．．．溝槽
P、P1、P2．．．間距
P-P．．．切線
W、W1、W2、W*．．．寬度
100、100A”、100B”、110、110A、110A”、110B、110B”、110C、120、120A、120A”、120B、120B”．．．封裝
104A、140B、104*、104**．．．接觸物
111、121、121’．．．模塑化合物
112、112*、112**、122、122A、122B、122C、123、131、405．．．金屬墊
114．．．開口
115、115A、115A”、115B、115B”、115C、125、125A”、125B”．．．連接物
116．．．導電物
117’、117A、117B、117C．．．導電單元
120’．．．晶粒封裝
130．．．基板
150．．．區域
160．．．移除製程
401．．．焊料球
102*、102**、402．．．凸塊下金屬化層
410、420、450、510．．．線段
411、412、511．．．資料
第1A圖係某些實施例中，封裝的透視圖；
第1B圖係第1A圖的封裝中，沿著切線P-P之部份剖視圖；
第1C圖係第1B圖之區域150的放大圖；
第1D圖係某些實施例中，雷射鑽孔移除部份的模塑化合物以形成可埋置導電連接物之開口的示意圖；
第2A圖係某些實施例中，晶粒封裝具有導電單元埋置於模塑化合物中的示意圖；
第2B圖係某些實施例中，移除部份模塑化合物以露出導電單元的示意圖；
第2C圖係某些實施例中，晶粒封裝具有導電單元埋置於模塑化合物中的示意題；
第3A至3F圖係某些實施例中，形成連接物的三種製程順序之封裝製程的剖視圖；
第4A圖係某些實施例中，位於金屬墊上的焊料球之示意圖；
第4B圖係某些實施例中，以再流動的焊料球之最大高度與直徑，對應凸塊下金屬化層之尺寸(寬度)的圖示；
第5圖係某些實施例中，以再流動的連接物之高度，對應再流動前的焊料球露出的寬度的圖示；
第6A及6B圖係某些實施例中，進行應力模擬之連接物的封裝示意圖；以及
第7A至7C圖係多種實施例中，封裝上的接觸物之示意圖。
P2．．．間距
W2．．．寬度
117”．．．導電單元
120”．．．封裝
121”．．．模塑化合物
122．．．金屬墊

Claims (10)

  1. 一種封裝的半導體元件，包括：一半導體晶粒埋置於一模塑化合物中；一導電單元埋置於該模塑化合物中，其中該導電單元露出於該模塑化合物之表面上；以及一金屬墊，其中該金屬墊接觸該導電單元並電性連接至該半導體晶粒中的多個元件。
  2. 如申請專利範圍第1項所述之封裝的半導體元件，更包括：另一金屬墊，係用以接合至一基板的多個接觸物。
  3. 如申請專利範圍第1項所述之封裝的半導體元件，其中該導電單元之平整表面與該模塑化合物之表面等高。
  4. 如申請專利範圍第1項所述之封裝的半導體元件，其中該導電單元具有一弧狀表面。
  5. 一種半導體元件封裝，包括：一第一半導體晶粒封裝具有一導電單元埋置於一模塑化合物中，其中該導電單元露出於該模塑化合物之表面上，其中該模塑化合物覆蓋至少一第一半導體晶粒；以及一第二半導體晶粒封裝，且該第二半導體晶粒封裝之表面上具有一導電接觸物，其中該第一半導體晶粒封裝之該導電單元接合至該第二半導體晶粒封裝之該導電接觸物，以形成一連接物。
  6. 如申請專利範圍第5項所述之半導體元件封裝，其中該導電單元與該模塑化合物之間不具有任何溝槽。
  7. 如申請專利範圍第5項所述之半導體元件封裝，更包括：一金屬墊埋置於該第一半導體晶粒封裝中，其中該導電單元接觸該金屬墊，其中該金屬墊電性連接至該第一半導體晶粒封裝中的一半導體晶粒中的一元件。
  8. 如申請專利範圍第7項所述之半導體元件封裝，更包括：另一金屬墊以接合至一基板之一接觸物。
  9. 一種半導體元件封裝的形成方法，包括：製備一第一半導體晶粒封裝，該第一半導體晶粒封裝具有多個導電單元埋置於一模塑化合物中，其中該導電單元露出於該模塑化合物之表面上；提供該第一半導體晶粒封裝；提供一第二半導體晶粒封裝；以及接合該第一半導體晶粒封裝之該些導電單元至該第二半導體晶粒封裝上的多個接觸物。
  10. 如申請專利範圍第9項所述之半導體元件封裝的形成方法，其中製備該第一半導體晶粒封裝之步驟包括：將該些導電單元置於一半導體晶粒上的多個金屬墊上，其中該些金屬墊連接至該半導體晶粒上的一元件；以及平坦化該些埋置的導電單元與該模塑化合物，以露出該些埋置的導電單元。
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US20130221522A1 (en) 2013-08-29
US20160343691A1 (en) 2016-11-24
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US10553561B2 (en) 2020-02-04
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US9418947B2 (en) 2016-08-16
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