TW201334144A - 透過調整圖案化利用低損互連之異質晶片整合 - Google Patents

透過調整圖案化利用低損互連之異質晶片整合 Download PDF

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TW201334144A
TW201334144A TW101138550A TW101138550A TW201334144A TW 201334144 A TW201334144 A TW 201334144A TW 101138550 A TW101138550 A TW 101138550A TW 101138550 A TW101138550 A TW 101138550A TW 201334144 A TW201334144 A TW 201334144A
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Taiwan
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layer
semiconductor component
electrical
cavity
top surface
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TW101138550A
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TWI502718B (zh
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S Rajendran
Monte R Sanchez
Susan M Eshelman
Douglas R Gentry
Thomas A Hanft
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Raytheon Co
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Abstract

透過調整圖案化形成之低損互連整合半導體組件與基板，包括於該基板中形成腔，將該半導體組件置於其中，以與基板相同或類似介電常數之充填物填充該半導體組件與該基板之間之間隙，並調整圖案化該充填物上之低損互連，於該半導體組件上之接點與該基板上之電跡線之間延伸。使用調整圖案化技術配置及鄰接該接點及引線，其配置及形成低損射頻傳輸線以補償該半導體組件接點與基板引線之間之任何失準。

Description

透過調整圖案化利用低損互連之異質晶片整合
目前說明之發明關於整合包括主動及被動裝置之半導體組件與基板之系統及方法。
半導體整合方法典型地包含經由導線或帶式連接器或於高頻(即，大於(含)10 GHz)下顯示寄生行為之覆晶凸塊，而連接主動及/或被動元件與被動電路。在該些整合方法中，藉由其下材料之介電特性及橋接材料間之空氣間隙中之不連續性(例如，基板材料之電介質至空氣之間之不連接性)造成RF(射頻)傳輸線中之不連續性。帶式連接器、覆晶技術包含高射頻應用中之性能。此外，典型地藉由增加陸面墊尺寸克服半導體組件與基板之間之配置不準確，其導致實質增加於半導體組件與基板之間之轉變中射頻信號損失。該些配置不準確亦導致基板上之組件間的較大間距，及增加基板及組件之尺寸及相關成本。
因此存在用於整合半導體組件與基板之改進的方法及系統之需求，其補償配置不準確而未造成高射頻之性能退化、組件之間之間距增加、或組件尺寸增加。
一實施例為半導體組件與分層基板之整合方法。該方法包括於分層基板中形成腔。該分層基板包括配置於該分層基板之第二層上之第一層，使得該第二層界定該腔之底部。該方法亦包括於該腔中配置半導體組件，使得該半導體組件上之電接點之頂面實質上與該分層基板之該第一層上之電跡線的頂面共平面。該方法亦包括於該第一層上配置至少一固定基標。該方法亦包括於該半導體組件上配置至少一固定基標。該方法亦包括依據該第一層上之該至少一固定基標與該半導體組件上之該至少一固定 基標的相對位置，於該第一層上之該電跡線與該半導體組件上之該電接點之間形成電互連，其中，該第一層上之該電跡線的位置相對於該第一層上之該至少一固定基標是固定的，及該半導體組件上之該電接點的位置相對於該半導體組件上之該至少一固定基標是固定的。
在若干實施例中，形成該腔之步驟包含調整該腔尺寸使得該半導體組件與該腔之壁部之間存在0-40微米間隙。在若干實施例中，該半導體組件與該腔之壁部之間存在25-35微米間隙。在若干實施例中，該方法包括以介電材料填充該半導體與該腔之壁部之間之該間隙使得該介電材料之頂面實質上與該半導體組件之該頂面與該第一層之該頂面共平面。在若干實施例中，該方法選擇地包括於該腔之底部與該半導體組件之間施加黏合劑。在若干實施例中，該方法選擇地包括於該腔之底部與該半導體組件之間施加焊接劑。在若干實施例中，該方法包括於該腔中配置該半導體組件，使得該半導體組件之該頂面上之該電接點實質上與該分層基板之該第一層上之該電跡線對齊，其中，對齊包括配置該第一層上之該至少一固定基標與該半導體組件上之該至少一固定基標的該相對位置。
在若干實施例中，方法包括圖案化電跡線以補償半導體組件上之一或多個接點與一或多個相應電跡線之間互連長度之變化。在一實施例中，方法包括伸展、壓縮、調動或旋轉電跡線圖型之至少一項，以調節腔內半導體組件之配置變化。
在若干實施例中，方法包括使用低能量雷射以局部顯影施加於電裝置之光阻劑，藉此調整圖案化於一或多個接點之一與一或多個電跡線之一相應者之間延伸之個別電互連，藉此調節失準。在若干實施例中，低能量雷射為355 nm雷射，以52 mm/sec線性掃描速率之30 KHz雷射發射頻率產生3.5 mw功率，並具有16微米之雷射光點尺寸。
在一實施例中，方法包括使用筆、沖壓程序、或直接寫由金、銀、或銅製成之導體的直接寫程序之一項形成該電互連。
在若干實施例中，方法包括塗佈光阻劑之第一層跨越該第一層及半導體組件之頂面，以雷射曝光及顯影沿該電互連圖型打開該光阻劑之第一層。方法包括至少沿於該光阻劑之第一層中打開之該電互連圖型沈積導電種子層，及塗佈光阻劑之第二層跨越該第一層、該半導體組件及該 種子層之頂面。方法包括以雷射曝光及顯影沿該電互連圖型打開該光阻劑之第二層，沿該電互連圖型電鍍該種子層，並移除該光阻劑之第一層、該光阻劑之第二層及若存在之配置於其間之未電鍍種子層。
在若干實施例中，低能量雷射為355 nm雷射，以52 mm/sec線性掃描速率之30 KHz雷射發射頻率產生3.5 mw功率，並具有16微米之雷射光點尺寸。
另一實施例為電裝置。電裝置包括分層基板，其包含配置於該分層基板之第二層上之第一層。電裝置亦包括形成於該分層基板中之腔，使得該第二層界定該腔之底部，及配置於該腔中之半導體組件，使得該半導體組件上之電接點之頂面實質上與該分層基板之該第一層上之電跡線的頂面共平面。電裝置亦包括於該第一層上之該電跡線與該半導體組件上之該電接點之間延伸之電互連。該電互連之路徑係依據該第一層上之至少一固定基標與該半導體組件上之至少一固定基標的相對位置。該第一層上之該電跡線的位置相對於該第一層上之該至少一固定基標是固定的，及該半導體組件上之該電接點的位置相對於該半導體組件上之該至少一固定基標是固定的。
在若干實施例中，存在於半導體組件與腔之壁部之間之間隙為0-40微米。在若干實施例中，電裝置包括半導體與腔之壁部之間間隙之介電材料填充物，且該介電材料之頂面實質上與該半導體組件之該頂面與該第一層之該頂面共平面。在若干實施例中，該半導體組件係配置於該腔中，使得依據該第一層上之該至少一固定基標與該半導體組件上之該至少一固定基標的相對位置，該半導體組件之該頂面上之該電接點實質上與該分層基板之該第一層上之該電跡線對齊。
從下列詳細說明結合僅藉由範例描繪本發明之原理的附圖，本發明之其他方面及優點將變得顯而易見。
100‧‧‧電裝置
103‧‧‧附著機構
105‧‧‧半導體組件
106‧‧‧腔底部
107、113、117、121、 129、134‧‧‧頂面
108‧‧‧腔
109‧‧‧分層基板
110‧‧‧第一層
111‧‧‧壁
115‧‧‧第二層
120‧‧‧介電材料
122‧‧‧間隙
125‧‧‧電互連
130‧‧‧電跡線
135‧‧‧接點
140、145‧‧‧基標
參照下列詳細說明結合附圖，本發明之各式實施例的上述特徵將更易理解，其中：圖1為依據描繪實施例之整合半導體組件及基板之側視圖的示意描繪。
圖2為依據另一描繪實施例之整合半導體組件及基板之側視圖的示意描繪。
圖3為依據描繪實施例之整合半導體組件及基板之俯視圖的示意描繪。
圖4為依據描繪實施例之半導體組件及基板的整合方法流程圖。
圖1、2、及3為依據描繪實施例之電裝置100的示意描繪。如以下參照圖4所說明，描繪組件整合在一起後之電裝置100。圖1為依據描繪實施例之電裝置100的側視圖(Z-X平面)。圖2為依據另一描繪實施例之電裝置100之側視圖(Z-X平面)。圖3為圖1及2之電裝置100之實施例之俯視圖(X-Y平面)。電裝置100包括配置於形成於分層基板109之腔108中之半導體組件105。分層基板109包括至少配置於第二層115上之第一層110。以不同材料(例如，GaN、GaAs、SiGe、及Si)，使用不同裝置技術(例如，p-HEMT、m-HEMT、SOI、及CMOS)製成並具有不同厚度之主動及被動半導體組件105很容易整合進入分層基板109。半導體組件105包括例如主動及被動組件，諸如高頻率分離裝置場效電晶體(FET)、單片微波積體電路(MMIC)、開關、衰減器、電容器、電阻器、電感器、及循環器。
在若干實施例中，第一層110為適於製造射頻(RF)匹配網路之低損材料。例如，第一層110之低損材料可為液晶聚合物(LCP)材料、苯並還丁烯(BCB)、或Teflon®之一種。第一層110之材料具有介電常數及可匹配半導體組件105上之接點135寬度與第一層110上之電跡線130寬度的材料厚度(沿Z軸)，以達所欲RF阻抗。在一實施例中，第一層110係由低損RF材料製成，諸如具有0.002損耗因數及2.9介電常數之1千分之一吋(mil)厚之LCP材料。
參照圖1及2之描繪實施例，電裝置100包括於分層基板109中形成之不同深度的一或多個腔108以接收一或多個半導體組件105。在若干實施例中，主動及被動之多類型組件，及多個腔異質整合於相同分層基板內。可藉由各式半導體製造技術(例如，蝕刻或切除)形成腔108。 腔108之深度(沿Z軸)係依據其中接收之半導體組件105的厚度(沿Z軸)決定，使得半導體組件105上之接點135的頂面134實質上與分層基板109之第一層110上之軌線130的頂面129共平面。考量接點135與網路軌線130之間之任何高度差而對齊接點135之頂面與軌線130之頂面，並獲致接點135與軌線130之間定形之電互連125中的適當連續性。
於分層基板109中形成腔108，使得第二層115界定腔底部106。參照圖1，第二層115之頂面117界定腔底部106。另一方面，如圖2中所描繪，第二層115之中間部分界定腔底部106。在一實施例中，半導體組件105為0.05 mm(2 mil)厚，第一層110為0.025mm(1 mil)厚及腔108延伸0.03 mm(1.2 mil)進入第二層115。腔108之深度因而調節半導體組件105之厚度(沿Z軸)，以及配置於半導體組件105與腔底部106之間之附著機構103(例如黏合劑或焊接劑)的厚度(沿Z軸)，同時仍維持半導體組件105上之接點135之頂面134與第一層110.上之軌線130之頂面129之共平面性。
在若干實施例中，第二層115係從高度熱傳導材料形成，其形成用於高功率電裝置105散熱之熱平面。第二層115亦形成電裝置105之RF信號及第一層110之基板之連續接地平面。熱耗散材料可為例如銅、諸如鉬-銅及鎢之銅合金-銅、AlSiC、AlN、或矽之一項。
基於位於腔108中之半導體組件105，電互連125於第一層110上之電跡線130及半導體組件105上之電接點135之間延伸。圖1描繪電跡線130及電接點135上電互連125之相對薄沈積。在若干實施例中，電互連係於所有表面上電鍍相同厚度(即，在電跡線130、第一層110、介電材料120、及電接點135之表面上)。製造電互連125以調節半導體組件105之配置變化而未負面影響電互連125之性能，其形成控制阻抗RF傳輸線。電互連125之製造包括補償半導體組件105上之接點135與電跡線130之間之任何失準。電互連125之製造不僅處理電互連125之軌道(即表面上電互連之路徑)，亦處理厚度及寬度，使得接點135與電跡線130之間之阻抗匹配，且高頻率作業位準下RF損耗極低(例如，100 GHz下介於0dB及0.05dB之間)。
在若干實施例中，例如可藉由沈積金、銀或銅導體之直接寫 技術形成電互連125。在若干實施例中，電互連125之製造包括施加光阻劑至電裝置100之整個頂面，並僅在將形成每一電互連125之區域以低能量雷射局部顯影光阻劑。因此，低能量雷射調整定形每一個別電互連125，並調節半導體組件105上之一或多個接點135與分層基板109之第一層110上之一或多個相應電跡線130之間之對齊變化(X-Y平面)。使用低能量雷射曝光避免共同使用之雷射切除技術所導致之材料損壞。例如，在一實施例中，雷射曝光包括以52 mm/sec線性掃描速率之30 KHz雷射發射頻率產生3.5 mw功率並具有16微米之雷射光點尺寸的355 nm雷射。一實施例包括採用二連續雷射掃描，其曝光諸如AZ-4620之7微米厚正保護層。該保護層接著於是當化學中顯影(移除)。
在一實施例中，調整互連製造程序包含施加光阻劑之第一層跨越分層基板109及一或多個半導體組件105之頂面，以雷射曝光及顯影(即移除)沿每一所需電互連圖型之個別、獨特路徑打開該光阻劑，以及透過濺鍍沈積導電金屬之薄種子層(例如，1000埃厚)。種子層覆蓋至少曝光區域，但在實施例中，種子層可覆蓋若干或全部光阻劑之第一層的剩餘部分。調整互連製造程序接著包括以光阻劑之第二層塗佈電裝置100，以低能量雷射沿每一電互連125之個別、獨特路徑重新打開光阻劑(即，曝光導電種子層)，最後電鍍導電種子層以形成完整電互連125，其調節每一電導體135與電跡線130之間之對齊變化。在電鍍程序之後，將光阻劑之第一及第二層及應用至光阻劑之第一層之種子層的任何未電鍍部分從環繞電鍍之一或多個電互連125之電裝置100的所有表面移除。此程序留下於半導體組件105上之電接點135與分層基板109上之電跡線130之間延伸之調整定形的每一電互連125。
在其他實施例中，亦可藉由以銅、金或銀導體墨水直接寫而形成電互連125。共同RF電路設計工具，諸如Agilent®先進設計系統及Ansoft® HFSS，可用以決定用於電跡線130之特定厚度的電互連125之寬度。在實施例中，電互連125之形成方法包含使用軟體演算法以定位相對於第一層110上之基標145的半導體組件上之基標140之位置，並依據RF電路設計工具提供之RF特性的習知知識計算電互連125之輪廓(即，寬度及錐體)。使用低能量雷射曝光及顯影出光阻劑使得可局部曝光及局部化 調整圖案化每一電互連125。此技術考量標準晶圓遮罩技術未考量之小變化，標準晶圓遮罩技術類似地處理晶圓上之所有軌線而未思及每一電接點135與電跡線130之間對齊之個別化變化。因此此技術調節電接點135與電跡線130之間對齊之變化，同時提供有效控制之阻抗RF傳輸線。
在若干描繪實施例中，半導體組件105係配置於腔108中，使得半導體組件105之頂面107上之電接點135於電互連125形成之前實質上對齊(沿Z軸)分層基板109之第一層110上之電跡線130。
參照圖3，X-Y平面中電互連125之軌道係依據第一層110上之至少一固定基標145與半導體組件105上之至少一固定基標140之相對位置。第一層110上之電跡線130的位置相對於第一層110上之至少一固定基標145是固定的，且半導體組件105上之電接點135的位置相對於半導體組件105上之至少一固定基標140是固定的。
電裝置100包括半導體組件105與腔108之壁111之間之間隙122。在圖3中所示之描繪實施例中，在裝置之各側與鄰近之腔108之相應壁111之間之間隙122近似相等。在若干實施例中，間隙122介於0-40微米，在若干描繪實施例中，半導體組件105與腔108之壁111之間之間隙122介於25-35微米。
半導體組件105與腔108之壁111之間之間隙122係以低收縮(例如12%或更低)、低黏性材料之介電材料120填充，其有效地填充間隙122。介電材料具有低固化溫度(例如，約攝氏200度)。介電材料120為低損並具有匹配第一層110之材料的介電常數。例如，在一實施例中，填充間隙122之介電材料120為Intervia 8023-10、BCB、或Teflon®之一項，並具有約3.0之介電常數。
在若干實施例中，介電材料120填充間隙122使得介電材料120之頂面121實質上與半導體組件105之頂面107及第一層110之頂面113共平面。在若干實施例中，介電材料120旋塗跨越整個電裝置100並藉由光刻而被選擇性移除，僅留下間隙122中之介電材料120。間隙122中之介電材料120接著固化，使得介電材料120之頂面121與第一層110之頂面113共平面。形成電互連125跨越第一層110、介電材料120及半導體組件105之共平面表面以達成接點135與軌線130之間之匹配阻抗。例如， 在實施例中，電互連125可為例如50歐姆或70歐姆之阻抗轉變構件，以匹配分層基板109與半導體組件105之電特性，並製造RF傳輸線。在若干實施例中，電互連125於100 GHz下具有介於0 dB及0.05 dB之RF信號損失，且從上到下(即，沿Z軸)測量為3至5微米厚。因此介電材料120排除與存在導線/帶式連接器及覆晶整合技術相關之RF傳輸線中的任何不連接性。填充環繞半導體組件105之間隙122的介電材料120排除其下支撐結構中的任何不連接性並藉由於半導體組件105、第一層110及接點135與軌線130之間之介電材料120上調整定形之電互連125形成連續微帶互連。
在若干描繪實施例中，黏合劑以隱約之糊狀或固態膜形式施加於腔底部106。適當黏合劑具有低於約攝氏200度之固化溫度，並可包含任何一項或多項下列功能：各向同性或各向異性導電、電絕緣、熱傳導、強力黏附於貴金屬或非貴金屬、防潮、耐化學腐蝕、低排氣、熱穩定、及彈性或應力吸收。適當黏合劑為例如單一成分銀或銀合金填充糊及膜，其為各向同性導電、熱傳導、應力吸收、強力黏附於金金屬、及/或於低於約攝氏150度下固化。較佳的糊黏合劑亦呈現於攝氏25度下低於60,000 cps之黏性，介於約2及5之觸變指數，大於約1.5 W-m/K之熱傳導，低溢膠，高純度，金金屬上之良好溼潤，於攝氏25度下大於約17MPa(2,500 psi)之剪切強度，低離子含量，及低於5x10-4 ohm-cm之體積電阻率。適當膜黏合劑亦呈現低於0.08mm(0.003in)之雛形厚度，大於約1.5 W-m/K之熱傳導，低溢膠，高純度，金金屬上之良好黏著，於攝氏25度下大於約17MPa(2,500 psi)之剪切強度，低離子含量，低於5x10-4 ohm-cm之體積電阻率，及低於約103kPa(15 psi)之應用壓力。
在若干實施例中，焊接劑係以助熔膠形式或非助熔固態雛形施加於腔底部106。適當焊接劑配方為共熔及非共熔合金，具低於約攝氏250度之液態溫度，及高於約攝氏150度之固態溫度。適當合金包括錫引線、無引線及特定(非錫/引線)配方，如IPC/EIA J-STD-006「電子級焊接劑合金及電子焊接之助熔及非助熔固態焊接劑應用的需求」(Requirements for Electronic Grade Solder Alloys and Fluxed and Non-Fluxed Solid Solders for Electronic Soldering Applications)中所界定。較佳焊接劑合金具有於約攝氏 170度以上之固態及約攝氏230度以下之液態。較佳錫引線配方包括例如：Sn63Pb37、Sn62Pb36Ag2、Sn70Pb30、Sn90Pb10、Sn50Pb48.5Cu1.5、Sn50Pb50、Sn50Pb50Sb0.4、In20Sn54Pb26、Sn60Pb37.5Bi2.5、Sn60Pb38Cu2、Sn60Pb40、Sn60Pb40Sb0.4、Sn62Pb36Ag02Sb0.4、Sn63Pb37Sb0.4、及Sn70Pb30Sb0.4。無引線配方包括例如：Sn96.3Ag3.7、Sn95.5Ag3.8Cu0.7、Sn95.8Ag3.5Cu0.7、Sn95Ag4Cd1、Sn96Ag2.5Cu0.5Bi1、Sn96.3Ag2.5Cu0.7Sb0.5、Sn96.4Ag3.2Cu0.4、Sn96.5Ag3.5、及Sn99.3Cu0.7。較佳特定合金包括：In40Pb60、In50Pb50、及In60Pb40。
圖4為整合半導體組件與分層基板以製造高頻率電裝置(例如，圖1之裝置的半導體組件105及分層基板109)之方法流程圖。在一實施例中，方法產生毫米波頻率電裝置，在另一實施例中，方法產生以100GHz以上作業之電裝置。如以上所指出，電裝置可包括以不同材料(例如，GaN、GaAs、SiGe及Si)、不同裝置技術(例如，p-HEMT、m-HEMT、SOI、CMOS及其他)及不同厚度製成之主動及被動半導體組件，其異質整合進入分層基板。
方法包括於S205在分層基板中形成腔(例如，圖1之分層基板109中之腔108)，分層基板包括配置第二層上之第一層，使得第二層界定腔底部。方法包括於S210在腔中配置半導體組件，使得半導體組件中之導體墊的頂面實質上與分層基板之第一層上之導體軌線的頂面共平面。在若干實施例中，多種主動及被動半導體組件及多腔異質整合於相同分層基板內。方法包括於S215定位第一層上之至少一固定基標，及於S220定位半導體組件上之至少一固定基標。方法包括於S225依據第一層上之至少一固定基標與半導體組件上之至少一固定基標之相對位置，形成第一層上之電跡線與半導體組件上之電接點之間之電互連，其中，第一層上之電跡線的位置相對於第一層上之至少一固定基標是固定的，半導體組件上之電接點的位置相對於半導體組件上之至少一固定基標是固定的。電跡線可藉由例如高度精準導體直接寫程序或光阻劑之雷射曝光、電鍍及蝕刻程序而予形成。
在一實施例中，於S205之腔的形成步驟包括於S207調整腔的尺寸使得半導體組件與腔之壁部之間存在間隙。應注意的是S207之調 整腔的尺寸可發生於S205中形成腔之前。在若干實施例中，於S205形成腔需要於分層基板之第一層及第二層中獨立形成腔的部分。例如，相對於圖2之實施例，可於層115中蝕刻腔108，接著在沈積於層115上之後於層110中形成腔。
在一實施例中，半導體組件與腔之壁部之間之間隙為0-40微米。在另一實施例中，半導體組件與腔之壁部之間之間隙為25-35微米。在一實施例中，方法進一步包括於S214以介電材料填充半導體組件與腔之壁部之間之間隙，使得介電材料上之軌線的頂面實質上與半導體組件上之接點的頂面及第一層之頂面共平面。在若干實施例中，方法包括於S208在腔底部與半導體組件之間施加黏合劑，在其他實施例中，方法包括於S208在腔底部與半導體組件之間施加S208。
返回於S225在電跡線與電接點之間形成電互連之步驟，方法包括調整圖案化電互連至第一層、電介質填充物及半導體組件之共平面頂面上，使得組件之間之阻抗匹配，並於低介電常數之連續固態表面上形成低損、高頻率RF傳輸線。在實施例中，電互連具有100GHz下僅介於0dB及0.05dB之RF信號損失。在一實施例中，電互連係使用光阻劑之局部雷射曝光及電鍍技術而定形於電裝置上，在其他實施例中，使用筆、沖壓程序、或直接寫由金、銀、或銅製成之導體的直接寫程序而實施電互連。
在實施例中，方法採用用於在S215定位半導體組件上之至少一固定基標及在S220定位第一層上之至少一固定基標的圖案化工具。在若干實施例中，在於腔中配置半導體組件之前，方法包括於S212實質上對齊半導體組件上之接點與分層基板之第一層上之電跡線。此進一步改進於S225形成電互連之正確性及效率。
工具採用軟體機構，其調整電互連之圖型以達成適當阻抗匹配，同時補償半導體組件上之接點與分層基板之第一層上之相應網路軌線之間之互連長度中任何變化。實施例包括視需要伸展、壓縮、調動及/或旋轉電互連之圖型以調節腔內半導體組件及相對於分層基板上之軌線的配置變化，並獲得最佳高頻電性能(即，在100GHz下極少或無RF損耗之性能，諸如0dB至0.05dB)。例如，調整圖型可包括調動X-Y平面中電互連之位置，及/或伸展電互連以增加長度及/或寬度而連接接點及軌線並匹 配該些元件之間之阻抗。方法因此調節半導體組件之配置變化，同時匹配接點及軌線之間之阻抗以確保高作業頻率下最小或無RF損耗。一旦軟體已調整電互連之圖型，圖案化工具定形電互連以適於接點及軌線之間之真實轉變。方法因此藉由識別半導體組件之位置及圖案化半導體組件與形成於分層基板上之網路軌線之間之高準確導體(即，電互連)而透過極低損調整電互連整合半導體組件。
包含、包括及/或複數形式均為無限制的，及包括所列零件，並包括未列出之其餘零件。及/或為無限制的，及包括所一或多個所列零件及所列零件之組合。
熟悉本技藝之人士將理解本發明可以其他特定形式實施，而為偏離其精神或基本特徵。上述實施例因此在各方面均被視為描繪而非侷限文中所說明之本發明。因而，本發明之範圍係由申請項而非上述說明表示，因此希望在申請項之等效意義及範圍內的所有改變均包含於其中。
100‧‧‧電裝置
103‧‧‧附著機構
105‧‧‧半導體組件
106‧‧‧腔底部
107、113、117、 121、129、134‧‧‧頂面
108‧‧‧腔
109‧‧‧分層基板
110‧‧‧第一層
111‧‧‧壁
115‧‧‧第二層
120‧‧‧介電材料
122‧‧‧間隙
125‧‧‧電互連
130‧‧‧電跡線
135‧‧‧接點

Claims (32)

  1. 一種半導體組件與分層基板之整合方法，包含：a)於分層基板中形成一腔，該分層基板包括配置於該分層基板之第二層上之第一層，使得該第二層界定該腔之底部；b)於該腔中配置半導體組件，使得該半導體組件上之電接點之頂面實質上與該分層基板之該第一層上之電跡線的頂面共平面；c)於該第一層上配置至少一固定基標；d)於該半導體組件上配置至少一固定基標；以及e)依據該第一層上之該至少一固定基標與該半導體組件上之該至少一固定基標的相對位置，於該第一層上之該電跡線與該半導體組件上之該電接點之間形成電互連，其中，該第一層上之該電跡線的位置相對於該第一層上之該至少一固定基標是固定的，及該半導體組件上之該電接點的位置相對於該半導體組件上之該至少一固定基標是固定的。
  2. 如申請專利範圍第1項之方法，其中，形成該腔之步驟包含調整該腔尺寸使得該半導體組件與該腔之壁部之間存在間隙。
  3. 如申請專利範圍第2項之方法，其中，該半導體組件與該腔之壁部之間之該間隙為0-40微米。
  4. 如申請專利範圍第3項之方法，其中，該半導體組件與該腔之壁部之間之該間隙為25-35微米。
  5. 如申請專利範圍第2項之方法，進一步包含以介電材料填充該半導體組件與該腔之壁部之間之該間隙使得該介電材料之頂面實質上與該半導體組件之該頂面與該第一層之該頂面共平面。
  6. 如申請專利範圍第1項之方法，進一步包含於該腔之底部與該半導體組件之間施加黏合劑或焊接劑。
  7. 如申請專利範圍第1項之方法，其中，該第一層為液晶聚合物(LCP)材料。
  8. 如申請專利範圍第1項之方法，其中，該整合半導體組件及基板為單片微波積體電路，包含一或多個場效電晶體(FET)及一或多個被動組件。
  9. 如申請專利範圍第1項之方法，其中，該第二層係以諸如銅(Cu)之熱耗散材料製造。
  10. 如申請專利範圍第1項之方法，其中，該整合半導體組件及基板形成毫米波頻率裝置。
  11. 如申請專利範圍第1項之方法，其中，該電互連為受控的阻抗轉變構件或射頻(RF)傳輸線。
  12. 如申請專利範圍第1項之方法，其中，該電互連於100 GHz時具有0dB與0.05dB之間之射頻(RF)信號損失。
  13. 如申請專利範圍第1項之方法，其中，該電互連為3至5微米厚。
  14. 如申請專利範圍第1項之方法，其中，該第二層之該頂面界定該腔之底部。
  15. 如申請專利範圍第1項之方法，其中，該第二層之內部界定該腔之底部。
  16. 如申請專利範圍第1項之方法，其中，該半導體組件係配置於該腔中，使得該半導體組件之該頂面上之該電接點實質上與該分層基板之該第一層上之該電跡線對齊，其中，對齊包括配置該第一層上之該至少一固定基標與該半導體組件上之該至少一固定基標的該相對位置。
  17. 如申請專利範圍第1項之方法，進一步包含圖案化該電互連以補償該半導體組件上之一或多個接點與該分層基板之該第一層上之一或多個相應電跡線之間之電互連長度的變化。
  18. 如申請專利範圍第17項之方法，進一步包含伸展、壓縮、調動或旋轉該電互連圖型之至少一項以調節該腔內之該半導體組件的配置變化。
  19. 如申請專利範圍第17項之方法，進一步包含使用筆、沖壓程序、或對由金、銀、或銅製成之導體進行直接寫的直接寫程序之其中一者來形成該電互連。
  20. 如申請專利範圍第17項之方法，進一步包含以雷射局部顯影光阻劑來調整於該一或多個接點之一與該一或多個電跡線之一相應者之間延伸之個別電互連圖型，藉以調節失準。
  21. 如申請專利範圍第20項之方法，其中，該雷射為355 nm雷射，以52 mm/sec線性掃描速率之30 KHz雷射發射頻率產生3.5 mw功率，並具有16微米之雷射光點尺寸。
  22. 如申請專利範圍第17項之方法，進一步包含：a)塗佈光阻劑之第一層跨越該第一層及半導體組件之頂面；b)以雷射曝光及顯影沿該電互連圖型打開該光阻劑之第一層；c)至少沿於該光阻劑之第一層中打開之該電互連圖型沈積導電種子層；d)塗佈光阻劑之第二層跨越該第一層、該半導體組件及該種子層之頂面；e)以雷射曝光及顯影沿該電互連圖型打開該光阻劑之第二層；f)沿該電互連圖型電鍍該種子層；以及g)移除該光阻劑之第一層、該光阻劑之第二層、及若存在之配置於其 間之未電鍍種子層。
  23. 如申請專利範圍第22項之方法，其中，該雷射為355 nm雷射，以52 mm/sec線性掃描速率之30 KHz雷射發射頻率產生3.5 mw功率，並具有16微米之雷射光點尺寸。
  24. 一種電裝置，包含：a)分層基板，其包含配置於該分層基板之第二層上之第一層；b)形成於該分層基板中之腔，使得該第二層界定該腔之底部；c)配置於該腔中之半導體組件，使得該半導體組件上之電接點之頂面實質上與該分層基板之該第一層上之電跡線的頂面共平面；以及d)於該第一層上之該電跡線與該半導體組件上之該電接點之間延伸之電互連，其中，該電互連之路徑係依據該第一層上之至少一固定基標與該半導體組件上之至少一固定基標的相對位置，及其中，該第一層上之該電跡線的位置相對於該第一層上之該至少一固定基標是固定的，及該半導體組件上之該電接點的位置相對於該半導體組件上之該至少一固定基標是固定的。
  25. 如申請專利範圍第24項之電裝置，進一步包含該半導體組件與該腔之壁部之間之間隙。
  26. 如申請專利範圍第25項之電裝置，其中，該半導體組件與該腔之壁部之間之該間隙為0-40微米。
  27. 如申請專利範圍第25項之電裝置，其中，該半導體組件與該腔之壁部之間之該間隙為25-35微米。
  28. 如申請專利範圍第24項之電裝置，進一步包含填充該間隙之介電材料，使得該介電材料之頂面實質上與該半導體組件之該頂面與該第一層之該頂面共平面。
  29. 如申請專利範圍第24項之電裝置，其中，該電裝置為毫米波頻率裝置或包含一或多個場效電晶體(FET)及一或多個被動組件之單片微波積體電路。
  30. 如申請專利範圍第24項之電裝置，其中，該第二層之該頂面界定該腔之底部。
  31. 如申請專利範圍第24項之電裝置，其中，該第二層之內部界定該腔之底部。
  32. 如申請專利範圍第24項之電裝置，其中，該半導體組件係配置於該腔中，使得該半導體組件之該頂面上之該電接點實質上與該分層基板之該第一層上之該電跡線對齊，其中，對齊包括配置該第一層上之該至少一固定基標與該半導體組件上之該至少一固定基標的相對位置。
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