TW201320331A - 半導體結構及形成閘極堆疊之方法 - Google Patents
半導體結構及形成閘極堆疊之方法 Download PDFInfo
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- TW201320331A TW201320331A TW101141727A TW101141727A TW201320331A TW 201320331 A TW201320331 A TW 201320331A TW 101141727 A TW101141727 A TW 101141727A TW 101141727 A TW101141727 A TW 101141727A TW 201320331 A TW201320331 A TW 201320331A
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Classifications
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- H01L21/02041—Cleaning
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- H01L21/02057—Cleaning during device manufacture
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
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- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/3105—After-treatment
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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Abstract
本發明提供一種半導體結構,包括:一半導體基底;及一閘極堆疊,位於半導體基底上,其中閘極堆疊包括:一高介電常數材料層;一蓋層,位於高介電常數材料層上;一金屬層,位於蓋層上,其中蓋層和高介電常數材料層具有一腳(foot)結構。
Description
本發明係有關於一種電子元件及其製造方法,特別是有關於一種半導體元件及其製造方法。
在先進的積體電路工業技術節點中,例如金氧半導體場效電晶體(MOSFET)之場效電晶體係使用高介電常數材料和金屬形成閘極堆疊。在現今的圖案化金屬閘極堆疊中,由於薄膜的均勻度,金屬閘極堆疊之金屬層的功函數在閘極的邊緣係朝向中間帶(mid gap),因此,造成起始電壓不預期的改變,短通道控制在常定次臨界漏電流(constant subthreshold leakage current)的劣化。此外,由於源汲極延伸阻抗(source drain extension resistance)的增加,驅動電流係降低。更甚者,現今方法形成金屬薄膜不夠好的均勻度導致閘極中更劣化的功函數變動。因此,需要金屬閘極堆疊結構和其形成方法,以解決上述的問題。
根據上述,本發明提供一種半導體結構,包括:一半導體基底;及一閘極堆疊,位於半導體基底上,其中閘極堆疊包括:一高介電常數材料層;一蓋層,位於高介電常數材料層上;一金屬層,位於蓋層上,其中蓋層和高介電常數材料層具有一腳(foot)結構。
本發明提供一種半導體結構,包括:一半導體基底;及一閘極堆疊,位於半導體基底上,其中閘極堆疊包括:一閘極介電層,包括一高介電常數材料層;一蓋層,位於
高介電常數材料層上;及一金屬層,位於蓋層上,其中金屬層具有凹陷(reentrant)的側壁輪廓。
本發明提供一種形成閘極堆疊之方法,包括:形成複數個閘極材料層於一半導體基底上,其中上述閘極材料層包括一閘極介電層、一位於閘極介電上之層蓋層和一位於蓋層上之多晶矽層;使用一第一蝕刻劑,進行一第一乾蝕刻,以圖案化多晶矽層;使用一不同於第一蝕刻劑之第二蝕刻劑,進行一第二乾蝕刻,以控制圖案化多晶矽層之側壁,使圖案化多晶矽層之側壁凹陷(reentrant);進行一第三乾蝕刻,以圖案化蓋層,使蓋層包括一第一腳圖樣;及進行一第四乾蝕刻,以圖案化閘極介電層,使閘極介電層包括一第二腳圖樣。
為讓本發明之特徵能更明顯易懂,下文特舉實施例,並配合所附圖式,作詳細說明如下:
以下詳細討論實施本發明之實施例。可以理解的是,實施例提供許多可應用的發明概念,其可以較廣的變化實施。所討論之特定實施例僅用來發明使用實施例的特定方法,而不用來限定發明的範疇。以下將針對特定實施例的構成與排列方式作簡要描述,當然,以下之描述僅是範例,但非用來限定本發明。舉例來說,於第一圖樣”上方”或”之上”形成第二圖樣之敘述可包括第一圖樣和第二圖樣直接接觸的實施例,但亦包括一額外之圖樣形成於第一圖樣和第二圖樣間的實施例,而使第一圖樣和第二圖樣沒有直接接觸。此外,本發明在各範例中可能會出現重複的圖樣標
號,但上述之重複僅是用來簡要和清楚的描述本發明,並不代表各實施範例和結構之間有必然關聯。
第1圖顯示本發明一實施例具有閘極堆疊之半導體元件製作方法100的流程圖。第2圖至第7圖顯示本發明一實施例具有閘極堆疊之半導體結構200製作在各階段的剖面圖,以下將配合第1圖至第7圖描述半導體結構200和其製造方法100。
首先方法100進行步驟102,提供一半導體基底210,半導體基底210包括矽。在另一實施例中,基底210包括鍺或矽鍺。在其它的實施例中,基底210可使用其它的半導體材料,例如鑽石、碳化矽、砷化鎵、GaAsP、AlInAs、AlGaAs、GaInP或上述適當的結合。
半導體基底亦可包括各種的摻雜區,例如適合技術(如離子佈植)形成之n井和p井。半導體基底210亦可包括各種的隔離結構,例如淺溝槽隔離結構(shallow trench isolation,簡稱STI),形成於基底中,以分隔各種元件。淺溝槽隔離結構之形成包括於一基底中蝕刻出一溝槽,且於溝槽中填入絕緣材料,例如氧化矽、氮化矽或氮氧化矽。填入之溝槽中可具有多層結構,例如熱氧化襯層和填入溝槽中的氮化矽。在一實施例中,淺溝槽隔離結構可以連續的製程形成,例如:成長一墊氧化物,形成一低壓化學氣相沉積(LPCVD)氮化層,使用光阻和罩幕圖案化出一STI開口,於基底蝕刻出一溝槽,視需要的成長一熱氧化溝槽襯層以改進溝槽介面,於溝槽中填入化學氣相沉積氧化物和使用化學機械平坦化(CMP)製程進行研磨和平坦化。
請參照第2圖,方法100進行至步驟104,於半導體基底210上形成各金屬閘極堆疊材料層。在一實施例中,一高介電常數材料層214形成於半導體基底210上。一蓋層216形成於高介電常數材料層214上。一多晶矽層220形成於蓋層216上。一中間層212(interfacial layer,簡稱IL)可設置於半導體基底210和高介電常數材料層214間。
在形成高介電常數材料層214前,中間層212係形成於矽基底210上。中間層212可包括適當技術形成之氧化矽,技術形成例如原子層沉積法(ALD)、熱氧化法、紫外光-臭氧氧化法(UV-Ozone oxidation)。中間層212之厚度可小於10埃。
高介電常數材料層214包括介電常數高於熱氧化矽(約為3.9)之介電材料。高介電常數材料層214可以適合之製程形成,例如原子層沉積法(ALD)。其它形成高介電常數材料層之方法包括有機化學氣相沉積法(MOCVD)、物理氣相沉積法(PVD)、紫外光-臭氧氧化法或原子束磊晶法。在一實施例中,高介電常數材料包括HfO2。在另一實施例中,高介電常數材料層包括金屬氮化物、金屬矽化物或金屬氧化物。
蓋層216係形成於高介電常數材料層214上。在一實施例中,蓋層216包括氮化鈦。在另一實施例中,氮化鈦層之厚度為5埃~20埃。蓋層216可另包括其它適合的材料。蓋層216是以適合的技術形成,例如物理氣相沉積法。
多晶矽層220係形成於蓋層216上。多晶矽層220是以適合的技術形成,例如化學氣相沉積法。在一範例中,
多晶矽層220是未摻雜的。在另一範例中,多晶矽層220之厚度為500埃~1000埃。
一圖案化罩幕222形成於多層金屬閘極上,且用作形成金屬閘極之罩幕。如第2圖所示,圖案化罩幕222係形成於多晶矽層220上。圖案化罩幕222定義出各閘極區和各開口,暴露要移除的閘極堆疊材料。圖案化罩幕222包括一硬式罩幕,例如氮化矽及/或氧化矽,或光阻。
在一範例中,圖案化罩幕層222包括具有氮化矽和氧化矽之圖案化罩幕層。如一範例,氮化矽層係以低壓化學氣相沉積法(LPCVD)沉積於多晶矽層上。包括二氯矽烷(DCS或SiH2Cl2)、雙(叔丁基氨基)矽烷(BTBAS or C8H22N2Si)、二矽乙烷(DS or Si2H6)之前驅物係使用於化學氣相沉積製程,以形成氮化矽層。一氧化矽層係藉由適合的技術形成氮化矽上,例如使用包括六氯矽烷(HCD or Si2Cl6)、二氯矽烷(DCS或SiH2Cl2)、雙(叔丁基氨基)矽烷(BTBAS or C8H22N2Si)、二矽乙烷(DS or Si2H6)之前驅物。進一步使用之微影和蝕刻製程,將氧化矽層和氮化矽層圖案化,其係形成圖案化光阻層且蝕刻圖案化光阻層開口中的氧化矽層和氮化矽層。其它的實施例可使用另外的介電材料作為圖案化硬式罩幕。舉例來說,氮氧化矽可以用作硬式罩幕。
在另一實施例中,圖案化硬式罩幕層222包括以微影製程形成的圖案化光阻層。示範之微影製程可包括以下製程步驟:塗佈光阻、軟烤、光罩對準、曝光、曝光後烘烤、光阻顯影和硬烤。微影曝光亦可以其它適合之方法取代,
例如無光罩微影、電子束寫入、離子束寫入和分子印跡(molecular imprinting)。
本實施例之方法包括圖案化多晶矽層220。在一實施例中,乾蝕刻製程使用含氟電漿蝕刻多晶矽。舉例來說,蝕刻氣體包括CF4和Cl2。在一特定的實施例中,Cl2和CF4之氣體比例約介於0.1~0.8之間。在另一實施例中,偏壓(bias power)約介於5W~300W之間。在另一範例中,蝕刻溫度(在相應蝕刻製程中的基底溫度)約介於10℃~70℃之間。
在此實施例中,多晶矽蝕刻包括考量材料和製程微調的步驟,特別是,第一步驟係調整至更有效的蝕刻氧化矽,第二步驟係調整至不會對蓋層造成損害。以下將更詳細的描述兩步驟蝕刻多晶矽層220之製程。
請參照第3圖,方法100進行至步驟106,藉由以圖案化罩幕層222作為蝕刻罩幕,進行第一蝕刻製程,圖案化多晶矽層220之頂部部分。藉由第一蝕刻製程,移除圖案化罩幕層222開口中之多晶矽層的頂部部分。在一範例中,第一蝕刻製程係調整至有效的移除氧化矽。在另一範例中,多晶矽層220之頂部部分之厚度約介於50埃至600埃之間。
請參照第4圖,方法100進行至步驟108,使用圖案化罩幕222作為蝕刻罩幕,進行一第二蝕刻製程,圖案化多晶矽層220之底部部分。藉由第二蝕刻製程移除圖案化罩幕222開口中的多晶矽層之底部部分。在一範例中,第二蝕刻製程係調整以避免損傷蓋層216。在一特別的範例
中,第二蝕刻製程之偏壓(bias power)係調整,使其偏壓小於第一蝕刻製程之偏壓。
請參照第5A圖和第5B圖,方法100進行至步驟110,進行一第三蝕刻製程,形成一具有角度之多晶矽層220的側壁輪廓。第三蝕刻製程係設計成具有較高程度的側向蝕刻,以控制多晶矽層220之側壁,使多晶矽層220之側壁226在接近底部時向內傾斜或凹入。多晶矽層220之側壁226不垂直基底,但與基底之表面230或蓋層216之頂部表面具有一角度,如第5A圖所示。角度228係小於90。。在一範例中,側壁226的角度228約介於85。至90。之間。
第5B圖進一步揭示圖案化多晶矽層220之剖面圖。圖案化多晶矽層220在頂部和底部,沿著電流從源極流經通道至汲極之方向,具有不同的尺寸。特別是,圖案化多晶矽層220在頂部表面具有第一尺寸D1,在底部表面具有第二尺寸D2,D1大於D2。
第三蝕刻製程是使用HBr前驅物之乾蝕刻製程,以控制多晶矽層220之側壁輪廓。在一範例中,第三蝕刻製程之偏壓小於第一蝕刻製程和第二蝕刻製程之偏壓。在另一實施例中,第三蝕刻製程之氣體壓力大於第一蝕刻製程之氣體壓力和第二蝕刻製程之氣體壓力。在一範例中,蝕刻氣體包括HBr,且其流量約為10 sccm至200 sccm之間。在另一範例中,蝕刻氣體更包括CF4和Ar(例如CF4約佔40%,Ar約佔60%),以避免對蓋層造成損傷,及/或避免其它損傷。在另一範例中,氣體壓力約為2 mTorr至5 mTorr之間。在又另一範例中,偏壓約介於5W至300W之間。
在另一範例中,蝕刻溫度約介於10℃至70℃之間。在另一範例中,蝕刻製程的時間約為15秒至100秒之間。
請參照第6圖,方法100進行至步驟112,進行第四蝕刻製程,圖案化蓋層216。在此實施例中,第四蝕刻製程是設計成蝕刻蓋層216之乾蝕刻。在一實施例中,此乾蝕刻使用含Cl2和HBr之電漿,以蝕刻蓋層。舉例來說,蝕刻氣體包括Cl2和HBr。在一特別的範例中,Cl2和HBr之氣體比例約為0.1至0.8之間。在另一範例中,第四蝕刻製程更包括具有適當流量之N2載氣,例如在一範例中,N2流量約為10 sccm至300 sccm。在另一範例中,氣體壓力約為1mTorr至30 mTorr。在另一範例中,偏壓約介於10W至300W之間。在另一範例中,蝕刻溫度約介於10℃至70℃之間。在另一範例中,蝕刻製程的時間約為1秒至100秒之間。
在完成第四蝕刻製程之後,圖案化蓋層216,使蓋層216之邊緣從多晶矽層之底部邊緣偏移,其係稱為腳(footing)。在一特別的範例中,圖案化蓋層之邊緣大體上對準多晶矽層之頂部邊緣或硬式罩幕層222之邊緣。如第6圖所示,蓋層216的腳沿著閘極長度方向具有尺寸H1。
方法100包括圖案化閘極介電物。在此實施例中,閘極介電物包括中間層212和高介電常數材料層214。請參照第7圖,方法100進行至步驟114,進行第五蝕刻製程,圖案化閘極介電層。在此實施例中,第五蝕刻製程是一設計成蝕刻包括中間層和高介電常數材料層之閘極介電物的乾蝕刻製程。在一實施例中,此乾蝕刻製程使用含氯氣體
蝕刻閘極介電物。在此實施例中,第五蝕刻製程之乾蝕刻使用包含Cl2和BCl3之前驅物。在一特別之範例中,氣體壓力約介於0.2mTorr至30mTorr之間。在其它的範例中,蝕刻溫度約介於10℃~70℃之間。在步驟114之後,圖案化閘極介電層,使其具有腳(footing)結構。舉例來說,如第7圖所示,圖案化閘極介電層之邊緣係從圖案化多晶矽層220之底部沿著閘極長度之方向偏移H2之尺寸。在一範例中,在第五蝕刻製程之後,腳尺寸之範圍約介於3nm~5nm之間。
在此實施例中,閘極介電層之腳更受到控制,以調整閘電極和源極/汲極間之重疊,改善元件的效能。舉例來說,可進行一清洗製程,後續進行一蝕刻製程,以控制腳結構。以下將會更詳細的描述。
方法100進行至步驟116,進行一清洗製程,以移除副產物,例如在各蝕刻製程中形成於半導體結構200上的之聚合殘留物。清洗製程可包括濕製程或乾製程。在一範例中,在多晶矽/蓋層蝕刻製程之後,聚合殘留物會形成在包括基底、圖案化多晶矽層和蓋層之各表面上。在一特定的範例中,多晶矽層蝕刻會產生多種的多晶矽層殘留物,包括含氯高分子、含碳高分子、含氟高分子、含HBr高分子及/或含矽高分子。在另一範例中,金屬蝕刻會產生多種的多晶矽層殘留物,例如含鈦高分子、含氯高分子及/或含HBr高分子。
副產物會有蝕刻罩幕的功能,防止更進一步蝕刻閘極介電材料。藉由對半導體結構200進行清洗製程,可移除
不希望產生的硬式罩幕副產物。清洗製程可使用任何適當的溶液,例如HF、氫氯酸-過氧化氫-水之混合(HPM)、氨-過氧化氫-水之混合(APM)或上述之組合。
在一實施例中,進行浸泡稀釋HF之製程,以有效的移除聚合副產物。在一範例中,稀釋HF溶液之濃度為500:1(水為500單位,HF為一單位)。在另一範例中,後續更進一步使用包括HCl、H2O2和H2O之HPM溶液。此溶液係為標準的清洗化學物,且將其稱為SC2。SC2浸泡製程可有效的清洗半導體結構200,且移除浸泡HF產生的副產物。在另一實施例中,稀釋HF和稀釋HCl可結合為一混和溶液,且半導體結構200可以此混和溶液清洗,以移除聚合殘留物和其它副產物。
在另一實施例中,清洗製程為包括NH4OH和H2O2之APM(或SC1)溶液。在另一範例中,此清洗製程可使用包括H2SO4和H2O2之溶液。
後續,方法100進行至步驟118,進行一第六蝕刻製程,更進一步的蝕刻閘極介電層。在此實施例中,第六蝕刻製程係類似於第五蝕刻製程,但其係微調以控制腳結構。在一實施例中,第六蝕刻製程包括使用含氯電漿之乾蝕刻製程。更進一步的來說,第六蝕刻製程之乾蝕刻使用包括Cl2和BCl3之前驅物。在一特定的範例中,第六蝕刻製程之氣體壓力約為0.2 mTorr至30 mTorr之間,蝕刻溫度約介於10℃至70℃之間。第六蝕刻製程之蝕刻製程的時間約為1秒至200秒之間。在第六蝕刻製程之後,腳結構之尺寸H2係減少之約0.5nm至2.5nm之間。
因此,形成之半導體結構200包括腳結構。特別是,腳結構包括蓋層216之第一腳圖樣和閘極介電物(包括高介電常數材料層214和中間層212)之第二腳圖樣。第一腳圖樣沿著閘極長度之方向具有第一尺寸H1,第二腳圖樣沿著閘極長度之方向具有第二尺寸H2。
在方法100之前,之中或之後可進行其它步驟。舉例來說,在方法100之後可移除圖案化罩幕層222。在此範例中係進行蝕刻製程(包括HF和磷酸),在兩個蝕刻步驟中移除圖案化罩幕秒222。
第8圖顯示本發明一實施例於半導體結構300上形成金屬閘極堆疊方法250之流程圖。在一範例中,半導體結構300是和半導體結構200相同。在其它範例中,方法250是方法200的延續,以形成金屬閘極堆疊。第9圖和第12圖是一範例具有閘極堆疊之半導體結構300在各階段的剖面圖。半導體結構300和其製造方法250會配合第8圖至第12圖描述。
請參照第9圖,方法250包括步驟252,於基底中形成源極和汲極。在此實施例中,半導體結構300除了兩個隔離圖樣外,與半導體結構200係相同,隔離圖樣302係形成於基底210中且於其間定義一主動區。在步驟252,於閘極堆疊之側壁形成閘極間隙壁304。源極和汲極306係形成於基底210上,且其間係包括閘極堆疊。
閘極間隙壁304包括一個或是多個介電材料,例如氧化矽、氮化矽、氮氧化矽或其組合。在一實施例中,閘極間隙壁304包括一位於閘極堆疊之側壁上的密封間隙壁和
位於密封間隙壁上之主要間隙壁,密封間隙壁和主要間隙壁係以沉積和蝕刻製程形成。
源極和汲極306包括以適當技術(例離子佈植)植入半導體基底210之摻雜物。在一實施例中,閘極堆疊係設置於主動區中,以形成n型場效電晶體,源極和汲極之摻雜物是n型,例如磷或砷。在另一實施例中,閘極堆疊係設置於主動區中,以形成p型場效電晶體,源極和汲極之摻雜物是p型,例如硼或鎵。在又另一實施例中,源極和汲極306包括輕摻雜汲極(LDD)圖樣和重摻雜源極/汲極圖樣,兩者一起稱為源極和汲極。輕摻雜汲極(LDD)圖樣和重摻雜源極/汲極圖樣係以離子佈植形成。在此實施例中,輕摻雜汲極(LDD)圖樣係在形成密封間隙壁後形成,以避免中間層再成長(IL re-growth)。後續進行一個或多個退火製程,以活化摻雜物。源極和汲極在熱退火製程中會產生擴散。
另外可於源極和汲極區上形成矽化圖樣,以減少接觸電阻。形成矽化圖樣可以稱為自對準矽化(salicide)技術,其包括沉積金屬(例如鎳)於矽基底上,進行熱退火製程使金屬和矽反應形成矽化物,和蝕刻製程以移除未反應之金屬。
在另一實施例中,源極和汲極區可包括磊晶成長半導體材料,以產生適當的應變效果,增加載子於通道中的移動率。在一實施例中,矽鍺係磊晶成長於p型場效電晶體之源極和汲極區中,在另一實施例中,矽鍺係磊晶成長於n型場效電晶體之源極和汲極區中。形成應變結構之方法
包括於基底中蝕刻形成凹槽,且於凹槽中磊晶成長結晶半導體材料。
請參照第10圖,方法250進行至步驟254,於基底和閘極堆疊上形成層間介電層308(ILD)。層間介電層308(ILD)是以適當的技術形成,例如化學氣相沉積。層間介電層308包括介電材料,例如氧化矽、低介電常數材料或其組合。後續,可進行化學機械研磨製程,以平坦化層間介電層308之表面。在一範例中,化學機械研磨製程暴露閘極堆疊,以進行後續的製程步驟。在硬式罩幕層222在先前步驟未移除之另一範例中,化學機械研磨製程一併移除硬式罩幕層222。在另一範例中,化學機械研磨製程係停止在硬式罩幕層222上,且硬式罩幕層222在後續步驟係以蝕刻製程移除。
後續以一個或是多個金屬材料取代多晶矽層,形成金屬閘極。對應的製程稱為後閘極(gate-last)製程,因此形成的電路稱為後閘極系統(gate-last scheme)。
請參照第11圖,方法250進行至步驟256,移除閘極堆疊中的多晶矽層220,產生閘極溝槽310。多晶矽層係以適合之蝕刻製程移除,例如濕蝕刻。
請參照第12圖,方法250進行至步驟258,於閘極溝槽310中填入一個或是多個金屬材料,形成金屬閘極堆疊。在此實施例中,具有適當功函數之第一金屬312係沉積閘極溝槽310中,且一第二金屬314係沉積於閘極溝槽310中之第一金屬上。第一金屬亦稱為功函數金屬。
更甚著,在n型場效電晶體中,第一金屬312之功函
數大體上等於或小於4.2eV,且其稱為n型金屬。在p型場效電晶體中,第一金屬312之功函數大體上等於或大於5.2eV,且其稱為p型金屬。在一範例中,n型金屬包括鋁化鈦或鋁化鉭。在另一範例中,p型金屬包括氮化鈦或氮化鉭。功函數金屬係以適合之技術形成。在此實施例中,功函數金屬係以物理氣相沉積法形成。
在各實施例中,第二金屬314包括鋁、鎢或其它適合的金屬。第二金屬314係以適合的技術沉積,例如物理氣相沉積法或電鍍法。在另一實施例中,進行化學機械研磨製程,以移除多餘的金屬,例如位於層間介電層308上的金屬。因此形成之金屬層(312、314)亦具有凹入的結構,其中金屬層312、314的側壁至基底頂部表面包括一角度,此角度為85°至90°之間。
後續可進行其它製程步驟以形成功能性電路。例如,於基底上形成內連線結構,且其係設計成耦接各電晶體和其它元件,以形成功能性電路。功能性電路包括各導電圖樣,例如例如金屬線以進行水平連接,和接觸/通孔(via)以進行垂直連接。各內連線圖樣可以各導電金屬材料形成,包括銅、鎢或矽化物。在一範例中,係使用鑲嵌製程,形成以銅為基礎多層內連線結構。在另一範例中,係使用鎢以於接觸孔洞中形成鎢插塞。
本發明各實施例之方法100、半導體結構200、方法250和半導體結構300可具有各種優點。在一實施例中,閘極堆疊之腳結構係以蝕刻和清洗製程調整。此調整過之閘極堆疊的腳結構(例如蓋層之腳和閘極介電物之腳)可達
成輕摻雜汲極(LDD)與閘電極重疊且控制載子聚集和阻抗降低。因此,可改進元件的效能。
在另一實施例中,所揭示的結構和方法可達成一凹陷的閘極結構,其側壁至基底之角度係為85°至90°。因此,可改善功函數金屬之沉積和填入。特別是,可改善功函數金屬之均勻度。功函數金屬之均勻度係定義為閘極邊緣功函數金屬之厚度與閘極中央功函數金屬之厚度的比例。
在另一實施例中,由於具有閘極腳和凹陷閘極輪廓,本實施例可達成阻抗的降低(密封間係壁存在)。因此,密封間係壁係保留,而不需對其進行薄化,而可有效的抑制中間層再成長(interfacial re-growth)。在另一實施例中,藉由於輸入/輸出區域形成腳結構可解決崩潰電壓失效的問題。所揭示的腳(包括高介電常數材料的腳和蓋層的腳)可保護輸入/輸出閘極介電物,防止其在佈植製程中造成損壞。
半導體結構200(或300)僅是執行方法100(或250)形成之元件的範例。半導體結構200(或300)及其製造方法100(或250)可用於其它具有高介電常數和金屬閘極圖樣之半導體元件,例如應變半導體基底、異質半導體元件或無施加應力(stress-free)隔離結構。
本揭示不限定於半導體結構包括場效電晶體(例如金氧半導體電晶體)之應用,本揭示可延伸至其它具有金屬閘極堆疊之積體電路。例如,半導體結構200(或300)可包括動態隨機存取記憶體(DRAM)晶胞、單一電子電晶體(single electron transistor,SET)及/或其它微電子元件(以上在此一
起稱作微電子元件)。在另一實施例中,半導體結構200包括鰭式場效電晶體(FinFET)。本揭示亦可應用於其它型態的電晶體,包括單一閘極電晶體、雙閘極電晶體和其它的多閘極電晶體,且本揭示可使用於許多不同的應用,包括感測器晶胞、記憶晶胞、邏輯晶胞和其它元件。
雖然本說明書上述已詳細的描述本揭示的實施例,熟悉本技術領域的人士可了解其在不違背本揭示之精神,可做各種的變化。在一實施例中,閘電極可包括其它適合的金屬材料。形成腳的過程中可進行其它有效的清洗製程。所揭示的方法可用於,但不限定僅使用於電晶體(例如n型金氧半導體場效電晶體)。例如,複數個n型金氧半導體場效電晶體(nMOSFET)和複數個p型金氧半導體場效電晶體(pMOSFET)係形成於相同的基底上,n型金氧半導體場效電晶體(nMOSFET)和p型金氧半導體場效電晶體(pMOSFET)係於共同的程序形成,而一些圖樣係分別的形成。在一特定的範例中,n型金屬係形成於n型金氧半導體場效電晶體(nMOSFET)區中,而p型金氧半導體場效電晶體(pMOSFET)區係覆蓋n型金屬。
在另一實施例中,半導體基底可包括磊晶層,例如基底可以於主半導體上具有一磊晶層。更甚者,基底可包括絕緣層(例如埋藏介電層)上有矽(SOI)結構。在另一實施例中,基底可包括例如埋藏氧化層(buried oxide,BOX)之埋藏介電層,例如其可以氧離子布植隔離矽晶(separated by implanted oxygen,SIMOX)技術、晶圓接合、選擇性磊晶成長(SEG)或其它適合之方法形成。
因此,本揭示提供一半導體結構,包括:一半導體基底;及一閘極堆疊,位於半導體基底上,其中閘極堆疊包括:一高介電常數材料層;一蓋層,位於高介電常數材料層上;一金屬層,位於蓋層上,其中蓋層和高介電常數材料層具有一腳(foot)結構。
在一實施例中,腳(foot)結構包括從金屬層之一底部邊緣延伸的部分高介電常數材料層。在另一實施例中,腳(foot)結構包括從金屬層之一底部邊緣水平延伸的部分蓋層。在又另一實施例中,腳結構沿著閘極堆疊一閘極長度方向具有大體上介於0.5nm~2.5nm之間一水平尺寸。
在另一實施例中,金屬層包括:一功函數(work function)金屬薄膜,位於蓋層上;及另一金屬薄膜,位於功函數金屬薄膜上。在又另一實施例中,蓋層包括氮化鈦。在又另一實施例中,半導體結構更包括一中間(interfacial)層,位於半導體基底和高介電常數材料層之間。
在另一實施例中,金屬層包括凹陷(reentrant)的側壁輪廓。在又另一實施例中,金屬層之側壁與半導體基底之頂部表面具有一角度,角度大體上介於85°至90°之間。
本揭示於另一實施例提供一半導體結構,包括:一半導體基底;及一閘極堆疊,位於半導體基底上,其中閘極堆疊包括:一閘極介電層,包括一高介電常數材料層;一蓋層,位於高介電常數材料層上;及一金屬層,位於蓋層上,其中金屬層具有凹陷(reentrant)的側壁輪廓。
在一實施例中,半導體基底具有一頂部表面,且其中閘極堆疊係位於頂部表面上,且金屬層具有一傾斜側壁,
其中傾斜側壁與半導體基底之頂部表面間的角度大體上小於90°。在另一實施例中,角度大體上大於85°。
在另一實施例中,閘極介電層和蓋層包括一腳(foot)圖樣。在另一實施例中,腳圖樣沿著一閘極長度方向具有大體上介於0.5nm~2.5nm的尺寸。
在又另一實施例中,閘極介電層更包括一中間材料層;且蓋層包括氮化鈦。在又另一實施例中,金屬層包括:一功函數(work function)金屬薄膜,位於蓋層上;及另一金屬薄膜,位於功函數金屬薄膜上。
本揭示亦提供一種形成閘極堆疊之方法,包括:形成複數個閘極材料層於一半導體基底上,其中閘極材料層包括一閘極介電層、一位於閘極介電上之層蓋層和一位於蓋層上之多晶矽層;使用一第一蝕刻劑,進行一第一乾蝕刻,以圖案化多晶矽層;使用一不同於第一蝕刻劑之第二蝕刻劑,進行一第二乾蝕刻,以控制圖案化多晶矽層之側壁,使圖案化多晶矽層之側壁凹陷(reentrant);進行一第三乾蝕刻,以圖案化蓋層,使蓋層包括一第一腳圖樣;及進行一第四乾蝕刻,以圖案化閘極介電層,使閘極介電層包括一第二腳圖樣。
在一實施例中,第一蝕刻劑包括Cl2和CF4,且第二蝕刻劑包括HBr。在另一實施例中,第一乾蝕刻更包括一第一蝕刻步驟和一第二蝕刻步驟,其中第一蝕刻步驟變為有效的蝕刻氧化矽,第二蝕刻步驟變為避免損傷蓋層。
在又另一實施例中,第三乾蝕刻使用包括Cl2和HBr之一第三蝕刻劑,且第四乾蝕刻使用包括Cl2和BCl3之一
第四蝕刻劑。在又另一實施例中,第四乾蝕刻包括:使用第四蝕刻劑之第一蝕刻步驟;後續,一清洗步驟;及後續,使用第四蝕刻劑以控制第二腳圖樣之第二蝕刻步。
在另一實施例中,此方法更包括以一包括功函數金屬之金屬層取代多晶矽層。
雖然本發明之較佳實施例說明如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧方法
102‧‧‧步驟
104‧‧‧步驟
106‧‧‧步驟
108‧‧‧步驟
110‧‧‧步驟
112‧‧‧步驟
114‧‧‧步驟
116‧‧‧步驟
118‧‧‧步驟
200‧‧‧半導體結構
210‧‧‧半導體基底
212‧‧‧中間層
214‧‧‧高介電常數材料層
216‧‧‧蓋層
220‧‧‧多晶矽層
222‧‧‧罩幕
226‧‧‧側壁
228‧‧‧角度
230‧‧‧表面
250‧‧‧方法
252‧‧‧步驟
254‧‧‧步驟
256‧‧‧步驟
258‧‧‧步驟
300‧‧‧半導體結構
302‧‧‧隔離圖樣
304‧‧‧閘極間隙壁
306‧‧‧源極汲極
308‧‧‧層間介電層
310‧‧‧閘極溝槽
312‧‧‧第一金屬
314‧‧‧第二金屬
第1圖顯示本發明一實施例具有金屬閘極堆疊之半導體元件製作方法的流程圖。
第2-4圖、第5A圖和第6-7圖顯示本發明一實施例具有閘極堆疊之半導體結構製作在各階段的剖面圖。
第5B圖顯示第5A圖半導體元件之多晶矽層的剖面圖。
第8圖顯示本發明一實施例具有金屬閘極堆疊之半導體元件製作方法的流程圖。
第9-12圖顯示本發明一實施例具有閘極堆疊之半導體結構製作在各階段的剖面圖。
210‧‧‧半導體基底
212‧‧‧中間層
214‧‧‧高介電常數材料層
216‧‧‧蓋層
300‧‧‧半導體結構
302‧‧‧隔離圖樣
304‧‧‧閘極間隙壁
306‧‧‧源極汲極
308‧‧‧層間介電層
312‧‧‧第一金屬
314‧‧‧第二金屬
Claims (10)
- 一種半導體結構,包括:一半導體基底;及一閘極堆疊,位於該半導體基底上,其中該閘極堆疊包括:一高介電常數材料層;一蓋層,位於該高介電常數材料層上;及一金屬層,位於該蓋層上,其中該蓋層和該高介電常數材料層具有一腳(foot)結構。
- 如申請專利範圍第1項所述之半導體結構,其中該腳(foot)結構包括從該金屬層之一底部邊緣延伸的部分高介電常數材料層。
- 如申請專利範圍第1項所述之半導體結構,其中該腳(foot)結構包括從該金屬層之一底部邊緣延伸的部分蓋層。
- 如申請專利範圍第1項所述之半導體結構,其中該金屬層包括:一功函數(work function)金屬薄膜,位於該蓋層上;及另一金屬薄膜,位於該功函數金屬薄膜上。
- 如申請專利範圍第1項所述之半導體結構,其中該金屬層包括凹陷(reentrant)的側壁輪廓。
- 如申請專利範圍第5項所述之半導體結構,其中該金屬層之側壁與該半導體基底之頂部表面具有一角度,該角度大體上介於85°至90°之間。
- 一種半導體結構,包括: 一半導體基底;及一閘極堆疊,位於該半導體基底上,其中該閘極堆疊包括:一閘極介電層,包括一高介電常數材料層;一蓋層,位於該高介電常數材料層上;及一金屬層,位於該蓋層上,其中該金屬層具有凹陷(reentrant)的側壁輪廓。
- 一種形成閘極堆疊之方法,包括:形成複數個閘極材料層於一半導體基底上,其中該些閘極材料層包括一閘極介電層、一位於該閘極介電上之層蓋層和一位於該蓋層上之多晶矽層;使用一第一蝕刻劑,進行一第一乾蝕刻,以圖案化該多晶矽層;使用一不同於該第一蝕刻劑之第二蝕刻劑,進行一第二乾蝕刻,以控制該圖案化多晶矽層之側壁,使該圖案化多晶矽層之側壁凹陷(reentrant);進行一第三乾蝕刻,以圖案化該蓋層,使該蓋層包括一第一腳圖樣;及進行一第四乾蝕刻,以圖案化該閘極介電層,使該閘極介電層包括一第二腳圖樣。
- 如申請專利範圍第8項所述之形成閘極堆疊之方法,其中該第一蝕刻劑包括Cl2和CF4;及該第二蝕刻劑包括HBr。
- 如申請專利範圍第8項所述之形成閘極堆疊之方法,其中該第四乾蝕刻包括: 使用一第四蝕刻劑之第一蝕刻步驟;後續,一清洗步驟;及後續,使用該第四蝕刻劑以控制該第二腳圖樣之第二蝕刻步驟。
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI587510B (zh) * | 2014-10-01 | 2017-06-11 | 台灣積體電路製造股份有限公司 | 半導體結構及其形成方法 |
US10195816B2 (en) | 2014-12-01 | 2019-02-05 | Industrial Technology Research Institute | Metal/polymer composite material and method for fabricating the same |
US10463500B2 (en) | 2014-11-07 | 2019-11-05 | Industrial Technology Research Institute | Medical composite material, method for fabricating the same and applications thereof |
TWI715543B (zh) * | 2014-12-22 | 2021-01-11 | 美商英特爾股份有限公司 | 為了效能及閘極填充的最佳化的閘極輪廓 |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150021699A1 (en) * | 2013-07-18 | 2015-01-22 | International Business Machines Corporation | FIN Field Effect Transistors Having Multiple Threshold Voltages |
US9520474B2 (en) * | 2013-09-12 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company Limited | Methods of forming a semiconductor device with a gate stack having tapered sidewalls |
US9590065B2 (en) | 2013-12-04 | 2017-03-07 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device with metal gate structure comprising work-function metal layer and work-fuction adjustment layer |
US9620621B2 (en) * | 2014-02-14 | 2017-04-11 | Taiwan Semiconductor Manufacturing Company Ltd. | Gate structure of field effect transistor with footing |
US10084060B2 (en) * | 2014-08-15 | 2018-09-25 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method of the same |
US10840105B2 (en) | 2015-06-15 | 2020-11-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate structure with insulating structure and method for manufacturing the same |
US10050147B2 (en) * | 2015-07-24 | 2018-08-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20170301780A1 (en) | 2016-04-15 | 2017-10-19 | Macom Technology Solutions Holdings, Inc. | High-voltage gan high electron mobility transistors with reduced leakage current |
US10985284B2 (en) | 2016-04-15 | 2021-04-20 | Macom Technology Solutions Holdings, Inc. | High-voltage lateral GaN-on-silicon schottky diode with reduced junction leakage current |
JP7071175B2 (ja) * | 2017-04-18 | 2022-05-18 | 東京エレクトロン株式会社 | 被処理体を処理する方法 |
KR102328279B1 (ko) * | 2017-08-11 | 2021-11-17 | 삼성전자주식회사 | 반도체 소자 |
KR102323733B1 (ko) | 2017-11-01 | 2021-11-09 | 삼성전자주식회사 | 콘택 플러그를 갖는 반도체 소자 및 그 형성 방법 |
US11233047B2 (en) | 2018-01-19 | 2022-01-25 | Macom Technology Solutions Holdings, Inc. | Heterolithic microwave integrated circuits including gallium-nitride devices on highly doped regions of intrinsic silicon |
US10950598B2 (en) | 2018-01-19 | 2021-03-16 | Macom Technology Solutions Holdings, Inc. | Heterolithic microwave integrated circuits including gallium-nitride devices formed on highly doped semiconductor |
US11056483B2 (en) | 2018-01-19 | 2021-07-06 | Macom Technology Solutions Holdings, Inc. | Heterolithic microwave integrated circuits including gallium-nitride devices on intrinsic semiconductor |
US10644125B2 (en) * | 2018-06-14 | 2020-05-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal gates and manufacturing methods thereof |
CN109065445B (zh) * | 2018-07-13 | 2020-10-09 | 上海华力集成电路制造有限公司 | 金属栅极结构的制造方法 |
US10714347B2 (en) | 2018-10-26 | 2020-07-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cut metal gate processes |
TWI685085B (zh) * | 2019-02-26 | 2020-02-11 | 華邦電子股份有限公司 | 記憶元件及其製造方法 |
WO2021195506A1 (en) | 2020-03-26 | 2021-09-30 | Macom Technology Solutions Holdings, Inc. | Microwave integrated circuits including gallium-nitride devices on silicon |
WO2021208020A1 (en) * | 2020-04-16 | 2021-10-21 | Innoscience (Zhuhai) Technology Co., Ltd. | Semiconductor device and fabrication method thereof |
US11631745B2 (en) * | 2020-05-15 | 2023-04-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure with uneven gate profile |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7595248B2 (en) * | 2005-12-01 | 2009-09-29 | Intel Corporation | Angled implantation for removal of thin film layers |
KR100868768B1 (ko) * | 2007-02-28 | 2008-11-13 | 삼성전자주식회사 | Cmos 반도체 소자 및 그 제조방법 |
US7790592B2 (en) * | 2007-10-30 | 2010-09-07 | International Business Machines Corporation | Method to fabricate metal gate high-k devices |
JP2009123944A (ja) | 2007-11-15 | 2009-06-04 | Panasonic Corp | 半導体装置及びその製造方法 |
US7776755B2 (en) | 2008-09-05 | 2010-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Solution for polymer and capping layer removing with wet dipping in HK metal gate etching process |
US8258587B2 (en) * | 2008-10-06 | 2012-09-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistor performance with metal gate |
US8405143B2 (en) * | 2009-07-27 | 2013-03-26 | United Microelectronics Corp. | Semiconductor device |
DE102009047307B4 (de) * | 2009-11-30 | 2012-10-31 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verfahren zur Vergrößerung der Stabilität eines Gatedielektrikums mit großem ε in einem Gatestapel mit großem ε durch eine sauerstoffreiche Titannitriddeckschicht |
US8476126B2 (en) * | 2010-02-08 | 2013-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate stack for high-K/metal gate last process |
US8691638B2 (en) * | 2010-12-10 | 2014-04-08 | Globalfoundries Singapore Pte. Ltd. | High-K metal gate device |
US8314022B1 (en) * | 2011-05-20 | 2012-11-20 | Intermolecular, Inc. | Method for etching gate stack |
-
2012
- 2012-04-03 US US13/438,451 patent/US8912610B2/en active Active
- 2012-09-11 CN CN201210335590.4A patent/CN103107198B/zh active Active
- 2012-10-17 KR KR20120115604A patent/KR101496518B1/ko active IP Right Grant
- 2012-11-09 TW TW101141727A patent/TWI555201B/zh active
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI587510B (zh) * | 2014-10-01 | 2017-06-11 | 台灣積體電路製造股份有限公司 | 半導體結構及其形成方法 |
US9716161B2 (en) | 2014-10-01 | 2017-07-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate structure having designed profile and method for forming the same |
US10529822B2 (en) | 2014-10-01 | 2020-01-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate structure having designed profile |
US10463500B2 (en) | 2014-11-07 | 2019-11-05 | Industrial Technology Research Institute | Medical composite material, method for fabricating the same and applications thereof |
US10195816B2 (en) | 2014-12-01 | 2019-02-05 | Industrial Technology Research Institute | Metal/polymer composite material and method for fabricating the same |
TWI715543B (zh) * | 2014-12-22 | 2021-01-11 | 美商英特爾股份有限公司 | 為了效能及閘極填充的最佳化的閘極輪廓 |
US11205707B2 (en) | 2014-12-22 | 2021-12-21 | Intel Corporation | Optimizing gate profile for performance and gate fill |
Also Published As
Publication number | Publication date |
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TWI555201B (zh) | 2016-10-21 |
CN103107198B (zh) | 2016-06-08 |
US8912610B2 (en) | 2014-12-16 |
CN103107198A (zh) | 2013-05-15 |
KR101496518B1 (ko) | 2015-02-26 |
US20130119487A1 (en) | 2013-05-16 |
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