TW201304064A - Semiconductor device, fabrication method for a semiconductor device and electronic apparatus - Google Patents

Semiconductor device, fabrication method for a semiconductor device and electronic apparatus Download PDF

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Publication number
TW201304064A
TW201304064A TW101121190A TW101121190A TW201304064A TW 201304064 A TW201304064 A TW 201304064A TW 101121190 A TW101121190 A TW 101121190A TW 101121190 A TW101121190 A TW 101121190A TW 201304064 A TW201304064 A TW 201304064A
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Taiwan
Prior art keywords
film
electrode
layer
insulating film
semiconductor
Prior art date
Application number
TW101121190A
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Chinese (zh)
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TWI495041B (en
Inventor
Yoshihisa Kagawa
Kenichi Aoyagi
Yoshiya Hagimoto
Nobutoshi Fujii
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Sony Corp
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Priority claimed from JP2011168021A external-priority patent/JP5982748B2/en
Priority claimed from JP2011170666A external-priority patent/JP5803398B2/en
Priority claimed from JP2011210142A external-priority patent/JP6127360B2/en
Priority claimed from JP2012006356A external-priority patent/JP6031765B2/en
Application filed by Sony Corp filed Critical Sony Corp
Publication of TW201304064A publication Critical patent/TW201304064A/en
Application granted granted Critical
Publication of TWI495041B publication Critical patent/TWI495041B/en

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Abstract

Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.

Description

半導體裝置、用於半導體裝置之製造方法及電子設備 Semiconductor device, manufacturing method for semiconductor device, and electronic device

本技術係關於一種其中複數個基板彼此接合以在電極或配接線之間實施連結之半導體裝置、一種用於該半導體裝置之製造方法及一種包含該半導體裝置之電子設備。 The present technology relates to a semiconductor device in which a plurality of substrates are bonded to each other to perform bonding between electrodes or wirings, a manufacturing method for the semiconductor device, and an electronic device including the semiconductor device.

已開發一種使兩個晶圓或基板彼此接合以使形成於半導體基板上之連結電極彼此連結之技術並在(例如)日本專利特許公開案第2000-299379號中揭示該技術。 A technique has been developed in which two wafers or substrates are bonded to each other to connect the connection electrodes formed on the semiconductor substrate to each other, and the technique is disclosed in, for example, Japanese Patent Laid-Open Publication No. 2000-299379.

進一步言之，已提出其中上面形成元件及配接線之兩個基板經層壓且彼此接合之三維結構作為用於達成半導體裝置之較高整合之結構之一者。當欲製造剛剛描述之此三維結構之一半導體裝置時，首先製備上面形成元件之兩個基板，且將用於連結之電極(即，接合襯墊)引出至該等基板之接合正面。此後，例如，應用稱為鑲嵌技術之一嵌入式佈線技術以形成經組態使得用於連結之由銅(Cu)製成之電極被一絕緣膜包圍之一接合面。此後，該兩個基板被安置為其等之接合面彼此相對，且接著經層壓使得設置在其等之接合面上之電極彼此對應，且在此狀態中，實施熱處理。藉此實施基板(其等之間該等電極連結在一起)之接合。對於所描述之該製造方法，參考(例如)日本專利特許公開案第2006-191081號(在下文稱為專利文件1)。 Further, a three-dimensional structure in which two substrates on which elements and wirings are formed are laminated and bonded to each other has been proposed as one of the structures for achieving higher integration of a semiconductor device. When a semiconductor device of one of the three-dimensional structures just described is to be fabricated, the two substrates on which the elements are formed are first prepared, and the electrodes for bonding (i.e., bonding pads) are taken out to the bonded front faces of the substrates. Thereafter, for example, an embedded wiring technique called one of the damascene techniques is applied to form an interface in which an electrode made of copper (Cu) for bonding is surrounded by an insulating film. Thereafter, the two substrates are disposed such that their joint faces are opposed to each other, and then laminated so that the electrodes provided on the joint faces thereof and the like correspond to each other, and in this state, heat treatment is performed. Thereby, the bonding of the substrates (the electrodes are joined together) is carried out. For the described manufacturing method, for example, Japanese Patent Laid-Open Publication No. 2006-191081 (hereinafter referred to as Patent Document 1) is referred to.

例如，以下列方式實施一般嵌入式佈線技術形成電極。首先，在覆蓋基板表面之一絕緣膜上形成一溝槽圖案，且 接著在該絕緣膜上形成相對於銅(Cu)具有一障壁性質之一導電基底層或障壁金屬層，形成的狀態係該導電基底層或障壁金屬層覆蓋該溝槽圖案之一內壁。接著，在該障壁金屬層上形成使用銅(Cu)之一電極膜，形成的狀態係該溝槽圖案被填滿，且接著拋光該電極膜直到曝露該障壁金屬層。進一步言之，拋光該障壁金屬層及該電極膜直到曝露該絕緣膜。因此，形成其中一電極膜嵌入形成於該絕緣膜中之溝槽圖案中(該障壁金屬層內插於該電極膜與該溝槽圖案之間)之一嵌入式電極。 For example, an electrode is formed by implementing a general embedded wiring technique in the following manner. First, a groove pattern is formed on an insulating film covering one surface of the substrate, and Then, a conductive base layer or a barrier metal layer having a barrier property with respect to copper (Cu) is formed on the insulating film in a state in which the conductive base layer or the barrier metal layer covers one of the inner walls of the groove pattern. Next, an electrode film using copper (Cu) is formed on the barrier metal layer in a state in which the trench pattern is filled, and then the electrode film is polished until the barrier metal layer is exposed. Further, the barrier metal layer and the electrode film are polished until the insulating film is exposed. Therefore, one of the electrode electrodes is formed to be embedded in one of the trench patterns formed in the insulating film (the barrier metal layer is interposed between the electrode film and the trench pattern).

運用前述嵌入式佈線技術，該電極膜之拋光可自動地停止在拋光該電極膜直到曝露該障壁金屬層時之一時間點。然而，在隨後實施之電極膜及障壁金屬層之拋光中，該電極膜之拋光無法自動地停止在曝露該絕緣膜時之一時間點。因此，在一拋光面中，其中過度拋光該溝槽圖案中之電極膜之表面凹陷或其中取決於一電極佈置過度拋光該溝槽圖案中之電極膜之腐蝕易於發生，且難以獲得一平坦拋光面。因此，提出一種方法，其中在形成該電極膜之前移除該絕緣膜上之障壁金屬層使得該障壁金屬層僅留在該溝槽圖案之內面上，且接著在剩餘障壁金屬層上形成一電極膜且接著拋光該電極膜。例如，在日本專利特許公開案第2000-12540號(在下文稱為專利文件2)中揭示該方法。 With the aforementioned embedded wiring technique, the polishing of the electrode film can be automatically stopped at one time point when the electrode film is polished until the barrier metal layer is exposed. However, in the subsequent polishing of the electrode film and the barrier metal layer, the polishing of the electrode film cannot automatically stop at one time point when the insulating film is exposed. Therefore, in a polished surface, the surface of the electrode film in the groove pattern is excessively polished, or the etching of the electrode film in the groove pattern is excessively polished depending on an electrode arrangement, and it is difficult to obtain a flat polishing. surface. Therefore, a method is proposed in which the barrier metal layer on the insulating film is removed before the electrode film is formed such that the barrier metal layer remains only on the inner surface of the trench pattern, and then a barrier layer metal layer is formed on the remaining barrier metal layer The electrode film is then polished. This method is disclosed, for example, in Japanese Patent Laid-Open Publication No. 2000-12540 (hereinafter referred to as Patent Document 2).

順便提及，對於藉由如上述之此接合獲得之三維結構之一半導體裝置，要求一結構：其中保證兩個基板之接合強 度及電極之間之連結強度，並同時防止一電極材料擴散至一絕緣膜中。然而，專利文件1中揭示之用於一半導體裝置之製造方法未能防止一電極材料擴散至一絕緣膜中。 Incidentally, for a semiconductor device having a three-dimensional structure obtained by the bonding as described above, a structure is required in which the bonding of the two substrates is ensured to be strong Degree and the strength of the connection between the electrodes, and at the same time prevent an electrode material from diffusing into an insulating film. However, the manufacturing method for a semiconductor device disclosed in Patent Document 1 fails to prevent an electrode material from diffusing into an insulating film.

另一方面，運用專利文件2中揭示之嵌入式佈線技術，因為一電極膜具備一障壁金屬層或一基底層，所以可防止一電極材料擴散至一電極膜中。然而，此嵌入式佈線技術未考慮基板之接合，且將該障壁金屬層置於其中該障壁金屬層曝露於藉由連同該電極膜及該絕緣膜一起拋光而獲得之一平坦面之一狀態中。因此，難以保證該平坦面之總體面積之足夠接合強度。 On the other hand, with the embedded wiring technique disclosed in Patent Document 2, since an electrode film is provided with a barrier metal layer or a base layer, it is possible to prevent an electrode material from diffusing into an electrode film. However, the embedded wiring technique does not consider the bonding of the substrate, and the barrier metal layer is placed in a state in which the barrier metal layer is exposed to one of the flat faces obtained by polishing together with the electrode film and the insulating film. . Therefore, it is difficult to ensure a sufficient joint strength of the entire area of the flat surface.

因此，意欲設置一種三維結構之半導體裝置，其中，在其中藉由使兩個基板彼此接合實施使電極彼此連結之一結構中，保證接合強度並同時防止一電極材料擴散至一絕緣材料中以藉此達成可靠性之增強。而且意欲設置一種用於如剛剛描述之一半導體裝置之製造方法及一種包含該半導體裝置之電子設備。 Accordingly, it is intended to provide a semiconductor device having a three-dimensional structure in which one of the electrodes is bonded to each other by bonding the two substrates to each other, thereby ensuring bonding strength while preventing diffusion of an electrode material into an insulating material. This achieves an increase in reliability. Further, it is intended to provide a manufacturing method for a semiconductor device as just described and an electronic device including the same.

根據本技術之一第一實施例，設置一種半導體裝置，其包含：一第一基板，其包含一第一電極及由該第一電極之一擴散防止材料組態且覆蓋該第一電極之一周邊之一第一絕緣膜，該第一電極與該第一絕緣膜彼此協調以組態一接合面；及一第二基板，其接合至該第一基板且設置在該第一基板上，且包含連結至該第一電極之一第二電極及由該第二電極之一擴散防止材料組態且覆蓋該第二電極之一周邊之一第二絕緣膜，該第二電極與該第二絕緣膜彼此協調 以組態至該第一基板之一接合面。 According to a first embodiment of the present technology, a semiconductor device is provided, comprising: a first substrate comprising a first electrode and a diffusion preventing material configured by the first electrode and covering one of the first electrodes a first insulating film, the first electrode and the first insulating film are coordinated with each other to configure a bonding surface; and a second substrate bonded to the first substrate and disposed on the first substrate, and And including a second electrode coupled to one of the first electrodes and a diffusion preventing material configured by the second electrode and covering a periphery of one of the second electrodes, the second electrode and the second insulation Membrane coordination To configure an interface to one of the first substrates.

根據本技術之第一實施例，可藉由用於一半導體裝置之一製造方法製造該半導體裝置，該方法包含：在兩個基板之各者上形成由一電極材料之一擴散防止材料組態之一絕緣膜且在該絕緣膜上形成一溝槽圖案；在該等基板之各者之絕緣膜上形成由該電極材料組態之一電極膜，形成的狀態為該電極膜填滿形成於該絕緣膜上之溝槽圖案；拋光該等基板之各者之電極膜直到曝露該絕緣膜以形成一電極圖案使得該電極膜嵌入該溝槽圖案中；及接合該兩個基板，電極形成在該兩個基板上，接合的狀態為該等電極連結在一起之一狀態中接合其等之各者上形成該電極之兩個基板。 According to a first embodiment of the present technology, the semiconductor device can be fabricated by a manufacturing method for a semiconductor device, the method comprising: forming a diffusion preventing material configuration by one of the electrode materials on each of the two substrates An insulating film and a groove pattern formed on the insulating film; an electrode film configured by the electrode material is formed on an insulating film of each of the substrates, and the electrode film is formed in a state in which the electrode film is filled and formed a groove pattern on the insulating film; polishing an electrode film of each of the substrates until the insulating film is exposed to form an electrode pattern such that the electrode film is embedded in the groove pattern; and bonding the two substrates, the electrode is formed at On the two substrates, the bonded state is the two substrates on which the electrodes are formed in the state in which the electrodes are joined together.

運用該半導體裝置及該製造方法，在其中藉由兩個基板之接合實施使電極彼此連結之組態中，保證接合強度並同時防止一電極材料之擴散。因此，該三維結構之半導體裝置可達成可靠性之增強。 With the semiconductor device and the manufacturing method, in the configuration in which the electrodes are connected to each other by bonding of the two substrates, the bonding strength is secured while preventing the diffusion of an electrode material. Therefore, the three-dimensional structure of the semiconductor device can achieve an increase in reliability.

根據本技術之一第二實施例，設置一半導體裝置，其包含一第一基板，其具有曝露一第一電極及一第一絕緣膜之一接合面、經組態以覆蓋該第一基板之接合面之一絕緣薄膜；及一第二基板，其具有曝露一第二電極及一第二絕緣膜之一接合面且接合至該第一基板，接合的狀態為該絕緣薄膜夾置在該第二基板之接合面與該第一基板之接合面之間且該第一電極與該第二電極透過該絕緣薄膜彼此電連接。 According to a second embodiment of the present technology, a semiconductor device is provided, comprising a first substrate having a bonding surface exposing a first electrode and a first insulating film, configured to cover the first substrate An insulating film of the bonding surface; and a second substrate having a bonding surface exposing a second electrode and a second insulating film and bonding to the first substrate, wherein the bonding state is such that the insulating film is interposed The first electrode and the second electrode are electrically connected to each other through the insulating film between the bonding surface of the two substrates and the bonding surface of the first substrate.

根據本技術之第二實施例，可藉由用於一半導體裝置之一製造方法製造該半導體裝置，該方法包含：製備各自具有曝露一電極及一絕緣膜之一接合面之兩個基板；形成一絕緣薄膜，形成的狀態為該絕緣薄膜覆蓋該兩個基板之至少一者之接合面；及安置該兩個基板使得其等之接合面跨該絕緣薄膜彼此相對；將該兩個基板定位成其中其等之電極透過該絕緣薄膜彼此電連接之一狀態；及在該定位狀態中接合兩個基板。 According to a second embodiment of the present technology, the semiconductor device can be manufactured by a manufacturing method for a semiconductor device, the method comprising: preparing two substrates each having an exposed surface of an electrode and an insulating film; forming An insulating film formed in a state in which the insulating film covers a bonding surface of at least one of the two substrates; and the two substrates are disposed such that their bonding faces face each other across the insulating film; positioning the two substrates into An electrode in which the electrodes are electrically connected to each other through the insulating film; and the two substrates are bonded in the positioned state.

在本發明之半導體裝置(電子設備)及其製造方法中，連結至該第一金屬膜之第二金屬膜之連結側表面之面積小於該第一金屬膜之連結側表面之面積。進一步言之，在該第一金屬膜在該連結介面側上之面區域之部分(包含其中該第一金屬膜未連結至該第二金屬膜之面區域)中，設置介面障壁膜。運用剛剛描述之組態，可進一步抑制連結介面處之一電特性之劣化，藉此該連結介面具備更高的可靠性。 In the semiconductor device (electronic device) of the present invention and the method of manufacturing the same, the area of the connection side surface of the second metal film connected to the first metal film is smaller than the area of the connection side surface of the first metal film. Further, in a portion of the surface region of the first metal film on the side of the bonding interface (including a surface region in which the first metal film is not bonded to the second metal film), a via barrier film is provided. With the configuration just described, the deterioration of one of the electrical characteristics at the joint interface can be further suppressed, whereby the joint interface has higher reliability.

根據本技術之一第三實施例，設置一種半導體裝置，其包含：一第一半導體部分，其在一連結介面側上具有形成於該第一半導體部分之表面上之一第一金屬膜；一第二半導體部分，其在該連結介面上具有連結至第一金屬膜之一第二金屬膜，且在該連結介面側上具有小於該第一金屬膜在該連結介面側上之一表面積之一表面積，且設置為其中該第二半導體部分在該連結介面上接合至該第一半導體部分之一狀態；及一介面障壁部分，其設置於該第一金屬膜 在該連結介面側上之一面區域之一部分(包含其中該第一金屬膜未連結至該第二金屬膜之一面區域)中。 According to a third embodiment of the present technology, a semiconductor device includes: a first semiconductor portion having a first metal film formed on a surface of the first semiconductor portion on a bonding interface side; a second semiconductor portion having a second metal film bonded to the first metal film on the bonding interface and having a surface area smaller than the first metal film on the bonding interface side on the bonding interface side a surface area, and configured to be in a state in which the second semiconductor portion is bonded to the first semiconductor portion on the bonding interface; and a via barrier portion disposed on the first metal film a portion of one of the surface regions on the side of the bonding interface (including a region in which the first metal film is not bonded to the second metal film).

根據本技術之第三實施例，進一步設置一種電子設備，其包含一半導體裝置，該半導體裝置包含：一第一半導體部分，該第一半導體部分在一連結介面側上具有形成於該第一半導體部分之表面上之一第一金屬膜；一第二半導體部分，其在該連結介面上具有連結至第一金屬膜之一第二金屬膜，且在該連結介面側上具有小於該第一金屬膜在該連結介面側上之一表面積之一表面積，且設置為其中該第二半導體部分在該連結介面上接合至第一半導體部分之一狀態；及一介面障壁部分，其設置於該第一金屬膜在該連結介面側上之一面區域之一部分(包含其中該第一金屬膜未連結至該第二金屬膜之一面區域)中；及一信號處理電路，其經組態以處理該半導體裝置之一輸出信號。 According to a third embodiment of the present technology, an electronic device is further provided, comprising: a semiconductor device, the semiconductor device comprising: a first semiconductor portion having a first semiconductor formed on a connection interface side a first metal film on a portion of the surface; a second semiconductor portion having a second metal film bonded to the first metal film on the bonding interface, and having less than the first metal on the bonding interface side a surface area of one surface of the film on the side of the bonding interface, and is disposed in a state in which the second semiconductor portion is bonded to the first semiconductor portion on the bonding interface; and a interface barrier portion disposed on the first a portion of a metal film on a side of the bonding interface side (including a region in which the first metal film is not bonded to the second metal film); and a signal processing circuit configured to process the semiconductor device One of the output signals.

根據本技術之第三實施例，可藉由用於一半導體裝置之一製造方法製造該半導體裝置，該方法包含：製造一第一半導體部分，該第一半導體部分在一連結介面側上具有形成於該第一半導體部分之一表面上之一第一金屬膜；製造一第二半導體部分，其在該連結介面側上具有一第二金屬膜，該第二金屬膜具有小於該第一金屬膜在該連結介面側上之一表面積之一表面積；及使該第一半導體部分在第一金屬膜側上之表面及該第二半導體部分在該第二金屬膜側上之表面彼此接合以使該第一金屬膜與該第二金屬膜彼此連結；及在該第一金屬膜在該連結介面側上之面區域之一 部分(包含其中該第一金屬膜未連結至該第二金屬膜之面區域)處設置一介面障壁部分。 According to a third embodiment of the present technology, the semiconductor device can be fabricated by a method for fabricating a semiconductor device, the method comprising: fabricating a first semiconductor portion having a formation on a side of a bonding interface a first metal film on a surface of one of the first semiconductor portions; a second semiconductor portion having a second metal film on the side of the bonding interface, the second metal film having a smaller than the first metal film a surface area of one surface area on the side of the bonding interface; and bonding the surface of the first semiconductor portion on the first metal film side and the surface of the second semiconductor portion on the second metal film side to each other to The first metal film and the second metal film are connected to each other; and one of the surface regions of the first metal film on the side of the bonding interface A portion (including a surface region in which the first metal film is not bonded to the second metal film) is provided with a dielectric barrier portion.

根據本技術之一第四實施例，設置一種半導體裝置，該半導體裝置包含一半導體基板；形成於該半導體基板上之一絕緣層；形成於該絕緣層之一表面上之一連結電極；及一保護層，其形成於該絕緣層之一表面上且包圍該連結電極，其中該絕緣層內插於該保護層與該連結電極之間。 According to a fourth embodiment of the present technology, a semiconductor device includes: a semiconductor substrate; an insulating layer formed on the semiconductor substrate; one of the electrodes formed on one surface of the insulating layer; and a And a protective layer formed on a surface of the insulating layer and surrounding the connecting electrode, wherein the insulating layer is interposed between the protective layer and the connecting electrode.

根據本技術之第四實施例，可藉由用於一半導體裝置之一製造方法製造該半導體裝置，該方法包含：在一半導體基板上形成一絕緣層；在該絕緣層之一表面上形成一連結電極；及在該絕緣層之表面之一位置處形成一保護層，該位置在該保護層包圍該連結電極，其中該絕緣層內插於該保護層與該連結電極之間之處。 According to a fourth embodiment of the present technology, the semiconductor device can be fabricated by a manufacturing method for a semiconductor device, the method comprising: forming an insulating layer on a semiconductor substrate; forming a surface on one surface of the insulating layer And a protective layer is formed at a position of the surface of the insulating layer, wherein the protective layer surrounds the connecting electrode, wherein the insulating layer is interposed between the protective layer and the connecting electrode.

根據本技術之一第五實施例，設置一種電子設備，其包含一半導體裝置，該半導體裝置包含：一半導體基板；形成於該半導體基板上之一絕緣層；形成於該絕緣層之一表面上之一連結電極；及一保護層，其形成於該絕緣層之一表面上且包圍該連結電極，其中該絕緣層內插於該保護層與該連結電極之間；及一信號處理電路，其用於處理該半導體裝置之一輸出信號。 According to a fifth embodiment of the present technology, an electronic device is provided, comprising: a semiconductor device comprising: a semiconductor substrate; an insulating layer formed on the semiconductor substrate; formed on a surface of the insulating layer a bonding electrode; and a protective layer formed on a surface of the insulating layer and surrounding the connecting electrode, wherein the insulating layer is interposed between the protective layer and the connecting electrode; and a signal processing circuit For processing an output signal of one of the semiconductor devices.

結合隨附圖式將自下列描述及隨附申請專利範圍明白本技術之上述及其他特徵及優點，其中相同的元件符號標示相同的部件或元件。 The above and other features and advantages of the present invention are apparent from the following description and the appended claims.

第一實施例 First embodiment

<<1.第一實施例之半導體裝置之一般組態之實例>> <<1. Example of General Configuration of Semiconductor Device of First Embodiment>>

圖1展示作為應用本技術之三維結構之一半導體裝置之一實例之一固態影像擷取裝置之一般組態。參考圖1，所示之半導體裝置1係三維結構之一半導體裝置(即，一固態影像擷取設備)，其包含作為一第一基板之一感測器基板2及作為一第二基板以一層壓狀態接合至該感測器基板2之之一電路基板7。在下列描述中，作為一第一基板之感測器基板2僅僅稱為感測器基板2，且作為一第二基板之電路基板7僅僅稱為電路基板7。 1 shows a general configuration of a solid-state image capturing device as one example of a semiconductor device to which a three-dimensional structure of the present technology is applied. Referring to FIG. 1, the semiconductor device 1 is a semiconductor device (ie, a solid-state image capturing device) having a three-dimensional structure, including a sensor substrate 2 as a first substrate and a layer as a second substrate. The voltage state is bonded to one of the circuit substrates 7 of the sensor substrate 2. In the following description, the sensor substrate 2 as a first substrate is simply referred to as a sensor substrate 2, and the circuit substrate 7 as a second substrate is simply referred to as a circuit substrate 7.

在該感測器基板2之一正面上設置其中各包含一光電轉換元件之複數個像素3規則地成二維陣列之一像素區域4。該像素區域4在一列方向上具有位於其中之複數個像素驅動線5及在一行方向上具有位於其中之複數個垂直信號線6。該等像素3經安置使得其等之各者連接至該等像素驅動線5之一者及該等垂直信號線6之一者。該等像素3之各者包含由一光電轉換元件組態之一像素電路、一電荷累積部分、各呈一金氧半導體(MOS)電晶體之形式之複數個電晶體、一電容性元件等等。應注意複數個像素可共同使用某像素電路。 A plurality of pixels 3 each including a photoelectric conversion element are regularly disposed on one of the front sides of the sensor substrate 2 in a pixel array 4 of a two-dimensional array. The pixel region 4 has a plurality of pixel drive lines 5 located therein in a column direction and a plurality of vertical signal lines 6 located therein in a row direction. The pixels 3 are arranged such that each of them is connected to one of the pixel drive lines 5 and one of the vertical signal lines 6. Each of the pixels 3 includes a pixel circuit configured by a photoelectric conversion element, a charge accumulation portion, a plurality of transistors each in the form of a metal oxide semiconductor (MOS) transistor, a capacitive element, etc. . It should be noted that a plurality of pixels can use a certain pixel circuit in common.

進一步言之，在該電路基板7之一正面上，設置諸如垂直驅動電路8之周邊電路、一行信號處理電路9、一水平驅動電路10及用於控制設置在該感測器基板2上之像素3之一系統控制電路11。 Further, on one front surface of the circuit substrate 7, a peripheral circuit such as a vertical driving circuit 8, a row of signal processing circuit 9, a horizontal driving circuit 10, and a pixel for controlling the sensor substrate 2 are disposed. 3 one of the system control circuits 11.

<<2.第一實施例之半導體裝置之組態>> <<2. Configuration of Semiconductor Device of First Embodiment>>

圖2展示該第一實施例之半導體裝置之一橫截面組態，且展示圖1中所示之三個像素之一橫截面。在下文中，參考圖2之橫截面描述該第一實施例之半導體裝置之一詳細組態。 2 shows a cross-sectional configuration of one of the semiconductor devices of the first embodiment, and shows a cross section of one of the three pixels shown in FIG. 1. Hereinafter, a detailed configuration of one of the semiconductor devices of the first embodiment will be described with reference to the cross section of FIG.

所示之半導體裝置1係三維結構之一固態影像擷取裝置，其中如上所述該感測器基板2與該電路基板7係以一層壓關係彼此接合。該感測器基板2係由一半導體層2a及安置在該半導體層2a在該電路基板7側上之一面上之一配接線層2b及一電極層2c組態。該電路基板7係由一半導體層7a及安置在半導體層7a在該感測器基板2側上之一面上之一第一配接線層7b、一第二配接線層7c及一電極層7d組態。 The illustrated semiconductor device 1 is a solid-state image capturing device of a three-dimensional structure in which the sensor substrate 2 and the circuit substrate 7 are bonded to each other in a laminated relationship as described above. The sensor substrate 2 is configured by a semiconductor layer 2a and a wiring layer 2b and an electrode layer 2c disposed on one side of the semiconductor layer 2a on the side of the circuit substrate 7. The circuit substrate 7 is composed of a semiconductor layer 7a and a first wiring layer 7b, a second wiring layer 7c and an electrode layer 7d disposed on one side of the semiconductor layer 7a on the side of the sensor substrate 2. state.

以如上所述之一方式組態之感測器基板2與電路基板7在作為接合面的該電極層2c之表面及該電極層7d之表面處彼此接合。本實施例之半導體裝置1之特性在於如下文詳細描述之電極層2c及電極層7d之組態。 The sensor substrate 2 and the circuit substrate 7 configured in one of the above manner are joined to each other at the surface of the electrode layer 2c as a bonding surface and the surface of the electrode layer 7d. The semiconductor device 1 of the present embodiment is characterized by the configuration of the electrode layer 2c and the electrode layer 7d as described in detail below.

進一步言之，在該感測器基板2在與該電路基板7相對之側上之面上，按順序層壓一保護膜15、一彩色濾光片層17及晶片上透鏡19。 Further, a protective film 15, a color filter layer 17, and an on-wafer lens 19 are laminated in this order on the side of the sensor substrate 2 on the side opposite to the circuit substrate 7.

現在，繼續描述組態該感測器基板2及該電路基板7之諸層之一詳細組態，且繼續描述該保護膜15、彩色濾光片層17及晶片上透鏡19之一組態。 Now, a detailed configuration of one of the layers configuring the sensor substrate 2 and the circuit substrate 7 will be described, and the configuration of the protective film 15, the color filter layer 17, and the on-wafer lens 19 will be further described.

[半導體層2a(感測器基板2側)] [Semiconductor layer 2a (sensor substrate 2 side)]

該感測器基板2側之半導體層2a係由一半導體基板形成，該半導體基板由(例如)呈一薄膜之形式之單晶矽製成。在該半導體層2a中，在上面安置該彩色濾光片層17、晶片上透鏡19等等之一第一正面上給每一像素設置由(例如)一n型雜質層或一p型雜質層形成之一光電轉換部分21。同時，在該半導體層2a之一第二正面上，設置一浮動擴散區FD及由(例如)一n+型雜質層、未展示之一不同雜質層等等製成之一電晶體Tr之一源極/汲極23。 The semiconductor layer 2a on the side of the sensor substrate 2 is formed of a semiconductor substrate made of, for example, a single crystal germanium in the form of a thin film. In the semiconductor layer 2a, each pixel is provided with, for example, an n-type impurity layer or a p-type impurity layer on a first front surface on which the color filter layer 17, the on-wafer lens 19, and the like are disposed. One of the photoelectric conversion portions 21 is formed. Meanwhile, on a second front surface of the semiconductor layer 2a, a floating diffusion region FD and a source of a transistor Tr made of, for example, an n+ type impurity layer, a different impurity layer not shown, or the like are provided. Pole / bungee 23.

[配接線層2b(感測器基板2側)] [Distribution layer 2b (sensor substrate 2 side)]

針對每一像素，在該感測器基板2之半導體層2a上設置之配接線層2b在其與該半導體層2a的介面側上具有設置於配接線層2b上的一電晶體Tr之一轉移閘極TG及一閘極電極27(其中一閘極絕緣膜25內插於該半導體層2a與該配接線層2b之間)以及未展示之其他電極。該轉移閘極TG及該閘極電極27覆蓋有一層間絕緣膜29，且在設置該層間絕緣膜29中之一溝槽圖案中設置(例如)Cu之一嵌入式配接線31。 For each pixel, the wiring layer 2b disposed on the semiconductor layer 2a of the sensor substrate 2 has a transfer of a transistor Tr disposed on the wiring layer 2b on the interface side thereof with the semiconductor layer 2a. A gate TG and a gate electrode 27 (one of which is interposed between the semiconductor layer 2a and the wiring layer 2b) and other electrodes not shown. The transfer gate TG and the gate electrode 27 are covered with an interlayer insulating film 29, and one of the Cu embedded wirings 31 is provided, for example, in one of the trench patterns provided in the interlayer insulating film 29.

在此情況中，使用(例如)氧化矽組態該層間絕緣膜29。另一方面，若密集地佈置該等嵌入式配接線31，則可使用具有低於氧化矽之一介電常數之一介電常數之一材料組態該層間絕緣膜29以減小該等嵌入式配接線31之間之電容。在剛剛描述之此一層間絕緣膜29中，形成朝該電路基板7側開口之溝槽圖案使得其等部分延伸至該等轉移閘極TG或該等閘極電極27。 In this case, the interlayer insulating film 29 is configured using, for example, yttrium oxide. On the other hand, if the embedded wirings 31 are densely arranged, the interlayer insulating film 29 may be configured to reduce the embedding using a material having a dielectric constant lower than one of the dielectric constants of the cerium oxide. The capacitance between the type of wiring 31. In the inter-layer insulating film 29 just described, a groove pattern opening toward the side of the circuit substrate 7 is formed such that its portion is extended to the transfer gates TG or the gate electrodes 27.

在如上所述之此等溝槽圖案之各者中，設置由銅(Cu)製 成之一配接線層31b，其中一障壁金屬層31a內插於該等溝槽圖案與該配接線層31b之間，且該等嵌入式配接線31係由該兩層組態。該障壁金屬層31a係用於防止銅(Cu)擴散至由氧化矽或具有低於氧化矽之一介電常數之一介電常數之一材料製成之層間絕緣膜29中之一層，且係使用(例如)鉭(Ta)或氮化鉭(TaN)組態。 In each of the groove patterns as described above, the copper (Cu) is provided. One of the wiring layers 31b is disposed, and a barrier metal layer 31a is interposed between the trench patterns and the wiring layer 31b, and the embedded wirings 31 are configured by the two layers. The barrier metal layer 31a is for preventing copper (Cu) from diffusing to one of the interlayer insulating films 29 made of yttria or a material having a dielectric constant lower than a dielectric constant of one of yttria, and Use, for example, tantalum (Ta) or tantalum nitride (TaN) configurations.

應注意如上所述之此一配接線層2b可組態為一層壓多層配接線層。 It should be noted that the wiring layer 2b as described above can be configured as a laminated multilayer wiring layer.

[電極層2c(感測器基板2側)] [Electrode layer 2c (sensor substrate 2 side)]

設置在該配接線層2b上之感測器基板2側上之電極層2c針對每一像素包含引出至該感測器基板2在該電路基板7側上之表面之一第一電極33及用於覆蓋該第一電極33之周邊之一第一絕緣膜35。該第一電極33及該第一絕緣膜35組態該感測器基板2至該電路基板7之一接合面41。 The electrode layer 2c disposed on the side of the sensor substrate 2 on the wiring layer 2b includes, for each pixel, a first electrode 33 which is taken out to the surface of the sensor substrate 2 on the side of the circuit substrate 7, and A first insulating film 35 covering one of the periphery of the first electrode 33 is provided. The first electrode 33 and the first insulating film 35 configure the sensor substrate 2 to the bonding surface 41 of the circuit substrate 7.

該第一電極33係由(例如)使用銅(Cu)之一單一材料層組態。剛剛描述之此一第一電極33係組態為嵌入該第一絕緣膜35中之一嵌入式配接線。 The first electrode 33 is configured, for example, by using a single material layer of one of copper (Cu). The first electrode 33 just described is configured to be embedded in one of the first insulating films 35.

該第一絕緣膜35係以覆蓋該配接線層2b之方式設置，且包含朝該電路基板7側開口之一溝槽圖案35a及嵌入該溝槽圖案35a中之一第一電極33。換言之，該第一絕緣膜35經設置接觸該第一電極33之周邊。應注意，雖然未展示，但是設置在該第一絕緣膜35中之溝槽圖案35a部分延伸至嵌入該配接線層2b中之嵌入式配接線31，且以此方式嵌入之第一電極33按場合需求連接至該嵌入式配接線31。 The first insulating film 35 is provided to cover the wiring layer 2b, and includes a trench pattern 35a opening toward the circuit substrate 7 side and one of the first electrodes 33 embedded in the trench pattern 35a. In other words, the first insulating film 35 is disposed to contact the periphery of the first electrode 33. It should be noted that, although not shown, the groove pattern 35a disposed in the first insulating film 35 partially extends to the embedded wiring 31 embedded in the wiring layer 2b, and the first electrode 33 embedded in this manner is pressed. Occasionally, it is required to be connected to the embedded wiring 31.

如上所述之此一第一絕緣膜35係由相對於組態該第一電極33之一材料之一擴散防止材料組態。使用相對於組態該第一電極33之一材料具有一低擴散係數之一材料作為剛剛描述之此一擴散防止材料。特別係在本實施例中，該第一絕緣膜35組態為使用擴散防止材料的單個材料層。進一步言之，在本實施例中，該第一絕緣膜35係由不僅相對於該第一電極33而且相對於組態引出至該電路基板7在該感測器基板2側上之表面之一第二電極67之一材料之一擴散防止材料組態。 The first insulating film 35 as described above is configured by a diffusion preventing material with respect to one of the materials configuring the first electrode 33. As the diffusion preventing material just described, a material having a low diffusion coefficient with respect to a material configuring one of the first electrodes 33 is used. In particular, in the present embodiment, the first insulating film 35 is configured as a single material layer using a diffusion preventing material. Further, in the present embodiment, the first insulating film 35 is one of the surfaces drawn on the side of the sensor substrate 2 not only with respect to the first electrode 33 but also with respect to the configuration to the circuit substrate 7. One of the materials of one of the second electrodes 67 is diffusion preventing material configuration.

例如，若使用銅(Cu)組態該第一電極33及該第二電極67，則使用具有密度大於氧化矽之一分子結構之一無機絕緣材料或一有機絕緣材料作為組態該第一絕緣膜35之擴散防止材料。氮化矽(SiN)、矽碳氮化物(SiCN)、氮氧化矽(SiON)及碳化矽(SiC)可應用為此一無機絕緣材料。同時，苯環丁烯(BCB)、聚苯并噁唑(PBO)、聚醯亞胺及聚芳醚(PAE)可應用為該有機絕緣材料。應注意，因為該電極層2c係該感測器基板2側上之最上層，所以該等第一電極33之佈置亦粗糙。因此，電容不太可能形成於該等第一電極33之間，且該第一絕緣膜35不要求一低介電常數。 For example, if the first electrode 33 and the second electrode 67 are configured using copper (Cu), an inorganic insulating material having a density greater than one of the molecular structures of cerium oxide or an organic insulating material is used as the first insulating material. The diffusion preventing material of the film 35. Cerium nitride (SiN), niobium carbonitride (SiCN), niobium oxynitride (SiON), and niobium carbide (SiC) can be applied to this inorganic insulating material. Meanwhile, benzocyclobutene (BCB), polybenzoxazole (PBO), polyimide and polyarylene ether (PAE) can be applied as the organic insulating material. It should be noted that since the electrode layer 2c is the uppermost layer on the side of the sensor substrate 2, the arrangement of the first electrodes 33 is also rough. Therefore, a capacitor is less likely to be formed between the first electrodes 33, and the first insulating film 35 does not require a low dielectric constant.

如上所述，感測器基板2在該電路基板7上之表面組態為至該電路基板7之接合面41，且處於其中該表面僅係由該第一電極33及該第一絕緣膜35組態之一狀態。此接合面41組態為一平坦面。 As described above, the surface of the sensor substrate 2 on the circuit substrate 7 is configured as a bonding surface 41 to the circuit substrate 7, and the surface is only the first electrode 33 and the first insulating film 35. Configure one of the states. This joint surface 41 is configured as a flat surface.

[半導體層7a(電路基板7側)] [Semiconductor layer 7a (circuit board 7 side)]

藉由形成(例如)由作為薄膜之單晶矽製成之一半導體基板形成該電路基板7側上之該半導體層7a。在該半導體層7a在該感測器基板2側上之表面層上，對每一像素設置一電晶體Tr之一源極/汲極51及圖2中未展示之一雜質層等等。 The semiconductor layer 7a on the side of the circuit substrate 7 is formed by forming, for example, a semiconductor substrate made of a single crystal germanium as a thin film. On the surface layer of the semiconductor layer 7a on the side of the sensor substrate 2, one source/drain 51 of a transistor Tr and one impurity layer not shown in FIG. 2 are provided for each pixel.

[第一配接線層7b(電路基板7側)] [First wiring layer 7b (circuit board 7 side)]

針對每一像素，該電路基板7側上之第一配接線層7b在其與半導體層7a之一介面側上具有設置於該第一配接線層7b上(其中一閘極絕緣膜53內插於該半導體層7a與該第一配接線層7b之間)之一閘極電極55及圖2中未展示之其他電極。該閘極電極55及其他電極覆蓋有一層間絕緣膜57，且在設置在該層間絕緣膜57中之溝槽圖案中設置使用(例如)銅(Cu)形成之嵌入式配接線59。 For each pixel, the first wiring layer 7b on the side of the circuit substrate 7 has a first wiring layer 7b disposed on one of the interface sides of the semiconductor layer 7a (wherein a gate insulating film 53 is interposed) a gate electrode 55 between the semiconductor layer 7a and the first wiring layer 7b) and other electrodes not shown in FIG. The gate electrode 55 and other electrodes are covered with an interlayer insulating film 57, and an embedded wiring 59 formed of, for example, copper (Cu) is provided in a groove pattern provided in the interlayer insulating film 57.

該層間絕緣膜57及該等嵌入式配接線59具有類似於該感測器基板2側之配接線層2b之組態之一組態。特定言之，在該層間絕緣膜57上，形成朝該感測器基板2側開口之溝槽圖案使得其等部分延伸至該閘極電極55或該源極/汲極51。進一步言之，在此等溝槽圖案中設置由銅(Cu)製成之一配接線層59b，其中一障壁金屬層59a內插於該等溝槽圖案與該配接線層59b之間，且該等嵌入式配接線層59係由該兩層組態。 The interlayer insulating film 57 and the embedded wiring 59 have a configuration similar to that of the wiring layer 2b on the side of the sensor substrate 2. Specifically, on the interlayer insulating film 57, a groove pattern opening toward the side of the sensor substrate 2 is formed such that its portion is extended to the gate electrode 55 or the source/drain 51. Further, a wiring layer 59b made of copper (Cu) is disposed in the trench patterns, and a barrier metal layer 59a is interposed between the trench patterns and the wiring layer 59b, and The embedded wiring layer 59 is configured by the two layers.

[第二配接線層7c(電路基板7側)] [Second wiring layer 7c (circuit board 7 side)]

該電路基板7側上之第二配接線層7c在其與第一配接線層7b之一介面側上包含一層間絕緣膜63，該層間絕緣膜63 層壓有內插於該層間絕緣膜63與該第一配接線層7b之間之一擴散防止絕緣層61。在設置在該擴散防止絕緣層61及該層間絕緣膜63中之溝槽圖案之各者中設置使用(例如)銅(Cu)形成之一嵌入式配接線65。 The second wiring layer 7c on the side of the circuit substrate 7 includes an interlayer insulating film 63 on one of the interface sides of the first wiring layer 7b, and the interlayer insulating film 63 A diffusion preventing insulating layer 61 interposed between the interlayer insulating film 63 and the first wiring layer 7b is laminated. In each of the groove patterns provided in the diffusion preventing insulating layer 61 and the interlayer insulating film 63, an embedded wiring 65 formed using, for example, copper (Cu) is provided.

該擴散防止絕緣層61係由相對於組態設置在該第一配接線層7b中之嵌入式配接線59之材料之一擴散防止材料組態。剛剛描述之此一擴散防止絕緣層61係由(例如)氮化矽(SiN)、矽碳氮化物(SiCN)、氮氧化矽(SiON)或碳化矽(SiC)形成。 The diffusion preventing insulating layer 61 is configured by one of diffusion-preventing materials relative to the material of the embedded wiring 59 disposed in the first wiring layer 7b. The diffusion preventing insulating layer 61 just described is formed of, for example, tantalum nitride (SiN), niobium carbonitride (SiCN), niobium oxynitride (SiON) or tantalum carbide (SiC).

該層間絕緣膜63及該等嵌入式配接線65具有類似於該感測器基板2側上之配接線層2b之組態之一組態。特定言之，該層間絕緣膜63在其上形成朝該感測器基板2側開口並部分延伸至該第一配接線層7b之嵌入式配接線59之溝槽圖案。進一步言之，在剛剛描述之此等溝槽圖案中設置由銅(Cu)製成之一配接線層65b，其中一障壁金屬層65a內插於此等溝槽圖案與該配接線層65b之間，且該等嵌入式配接線65係由該兩層組態。 The interlayer insulating film 63 and the embedded wiring 65 have a configuration similar to that of the wiring layer 2b on the side of the sensor substrate 2. Specifically, the interlayer insulating film 63 has a groove pattern formed thereon which is open toward the side of the sensor substrate 2 and partially extends to the embedded wiring 59 of the first wiring layer 7b. Further, a wiring layer 65b made of copper (Cu) is disposed in the trench pattern just described, wherein a barrier metal layer 65a is interposed between the trench patterns and the wiring layer 65b. And the embedded wiring 65 is configured by the two layers.

應注意，如上所述之此一第一配接線層7b及一第二配接線層7c可組態為一層壓多層配接線層。 It should be noted that the first wiring layer 7b and the second wiring layer 7c as described above may be configured as a laminated multilayer wiring layer.

[電極層7d(電路基板7側)] [Electrode layer 7d (circuit board 7 side)]

作為一第二基板之電路基板7之電極層7d針對每一像素包含引出至該電路基板7在該感測器基板2側上之表面且接合至該第一電極33之一第二電極67及覆蓋該第二電極67之周邊之一第二絕緣膜69。該第二電極67及該第二絕緣膜69 組態該電路基板7至該感測器基板2之一接合面71，且類似於如下所述之感測器基板2之電極層2c組態。 The electrode layer 7d of the circuit substrate 7 as a second substrate includes, for each pixel, a surface which is led out to the surface of the circuit substrate 7 on the side of the sensor substrate 2 and bonded to one of the first electrodes 33 and A second insulating film 69 covering one of the periphery of the second electrode 67 is covered. The second electrode 67 and the second insulating film 69 The circuit substrate 7 is configured to one of the bonding surfaces 71 of the sensor substrate 2, and is configured similarly to the electrode layer 2c of the sensor substrate 2 as described below.

特定言之，該第二電極67係由一單一材料層形成，且係由可保持至設置在該感測器基板2側上之第一電極33的良好接合性之一材料組態。因此，該第二電極67可由與該第一電極33之材料相同之材料組態，且使用(例如)銅(Cu)組態。剛剛描述之此一第二電極67組態為嵌入該第二絕緣膜69中之一嵌入式配接線。 Specifically, the second electrode 67 is formed of a single material layer and is configured by one material which can be maintained to a good bondability of the first electrode 33 disposed on the side of the sensor substrate 2. Therefore, the second electrode 67 can be configured of the same material as that of the first electrode 33, and is configured using, for example, a copper (Cu). The second electrode 67 just described is configured to be embedded in one of the second insulating films 69.

進一步言之，該第二絕緣膜69係以覆蓋該第二配接線層7c之方式組態，且針對每一像素具有朝該感測器基板2側開口並具有嵌入其中之一第二電極67之一溝槽圖案69a。換言之，該第二絕緣膜69經設置接觸該第二電極67之周邊。應注意，設置在該第二絕緣膜69中之溝槽圖案69a部分延伸至作為一下伏層之嵌入式配接線65，且嵌入該溝槽圖案69a中之第二電極67按場合需要連接至該嵌入式配接線65。 Further, the second insulating film 69 is configured to cover the second wiring layer 7c, and has an opening toward the sensor substrate 2 side for each pixel and has one of the second electrodes 67 embedded therein. One of the groove patterns 69a. In other words, the second insulating film 69 is disposed to contact the periphery of the second electrode 67. It should be noted that the groove pattern 69a disposed in the second insulating film 69 partially extends to the embedded wiring 65 as a lower layer, and the second electrode 67 embedded in the groove pattern 69a is connected to the occasion as needed. Embedded wiring 65.

如上所述之此一第二絕緣膜69係由相對於組態該第二電極67之材料之一擴散防止材料組態。特別係在本實施例中，該第二絕緣膜69組態為使用擴散防止材料的單個材料層。進一步言之，在本實施例中，該第二絕緣膜69係由不僅相對於該第二電極67而且相對於組態引出至該感測器基板2至該電路基板7之接合面之第一電極33之材料之一擴散防止材料組態。 The second insulating film 69 as described above is configured by a diffusion preventing material with respect to one of the materials configuring the second electrode 67. In particular, in the present embodiment, the second insulating film 69 is configured as a single material layer using a diffusion preventing material. Further, in the present embodiment, the second insulating film 69 is firstly drawn not only to the bonding surface of the sensor substrate 2 to the circuit substrate 7 with respect to the second electrode 67 but also with respect to the configuration. One of the materials of the electrode 33 is diffusion preventing material configuration.

可使用選自關於設置在該感測器基板2側上之第一絕緣 膜35列出之材料之一材料形成剛剛描述之此一第二絕緣膜69。應注意，該第二絕緣膜69係由可保持至該感測器基板2側上之第一絕緣膜35的良好接合性之一材料組態。因此，該第二絕緣膜69可由與該第一絕緣膜35之材料相同之材料組態。進一步言之，因為該電極層7d係該電路基板7側上之最上層，所以亦可粗糙地佈置該等第二電極67。因此，該等第二電極67之間不太可能具有電容，且該第二絕緣膜69不要求一低介電常數。 It is possible to use a first insulation selected from the side disposed on the side of the sensor substrate 2 One of the materials listed in the film 35 forms the second insulating film 69 just described. It should be noted that the second insulating film 69 is configured of one material which is good in adhesion to the first insulating film 35 on the side of the sensor substrate 2. Therefore, the second insulating film 69 can be configured of the same material as that of the first insulating film 35. Further, since the electrode layer 7d is the uppermost layer on the side of the circuit substrate 7, the second electrodes 67 can also be arranged coarsely. Therefore, it is less likely that there is a capacitance between the second electrodes 67, and the second insulating film 69 does not require a low dielectric constant.

如上所述，該電路基板7在該感測器基板2側上之表面組態為至該感測器基板2之接合面71，且係僅由該第二電極67及該第二絕緣膜69組態。此接合面71組態為一平坦面。 As described above, the surface of the circuit substrate 7 on the side of the sensor substrate 2 is configured to be the bonding surface 71 of the sensor substrate 2, and is only composed of the second electrode 67 and the second insulating film 69. configuration. This joint surface 71 is configured as a flat surface.

[保護膜15] [Protective film 15]

覆蓋該感測器基板2之光電轉換部分21之保護膜15係由具有一鈍化性質之一材料膜組態，且係使用(例如)氧化矽膜、氮化矽膜或氮氧化矽膜組態。 The protective film 15 covering the photoelectric conversion portion 21 of the sensor substrate 2 is configured by a material film having a passivation property, and is configured using, for example, a hafnium oxide film, a tantalum nitride film, or a hafnium oxide film. .

[彩色濾光片層17] [Color Filter Layer 17]

彩色濾光片層17係由以與該等光電轉換部分21之一1：1對應關設置之彩色濾光片組態。未限制若干色彩之彩色濾光片陣列。 The color filter layer 17 is configured by a color filter which is disposed 1:1 in correspondence with one of the photoelectric conversion portions 21. A color filter array of several colors is not limited.

[晶片上透鏡19] [On-wafer lens 19]

該等晶片上透鏡19係以與組態該等光電轉換部分21及該等色彩濾光片層17之色彩之彩色濾光片之各者的一1：1對應關係設置，且經組態以聚集該等光電轉換部分21上之入射光。 The on-wafer lens 19 is disposed in a 1:1 correspondence with each of the color filters configuring the photoelectric conversion portion 21 and the color filter layers 17 and configured to The incident light on the photoelectric conversion portions 21 is collected.

[第一實施例之半導體裝置之工作效果] [Working effect of the semiconductor device of the first embodiment]

運用以如上所述之方式組態之半導體裝置1，因為其經結構化使得該第一電極33之周邊覆蓋有由相對於該第一電極33之一擴散防止材料組態之第一絕緣膜35，所以無需在該第一電極33與該第一絕緣膜35之間設置一障壁金屬層。類似地，因為該半導體裝置1經結構化使得該第二電極67之周邊覆蓋有由相對於該第二電極67之一擴散防止材料組態之第二絕緣膜69，所以無需在該第二電極67與該第二絕緣膜69之間設置一障壁金屬層。 The semiconductor device 1 configured in the manner as described above is configured such that the periphery of the first electrode 33 is covered with the first insulating film 35 configured by the diffusion preventing material with respect to one of the first electrodes 33 because it is structured. Therefore, it is not necessary to provide a barrier metal layer between the first electrode 33 and the first insulating film 35. Similarly, since the semiconductor device 1 is structured such that the periphery of the second electrode 67 is covered with the second insulating film 69 configured by the diffusion preventing material with respect to one of the second electrodes 67, there is no need for the second electrode A barrier metal layer is disposed between the 67 and the second insulating film 69.

因此，當該感測器基板2之接合面41及該電路基板7之接合面71係僅分別由該等絕緣膜35及69以及該等電極33及67組態以保證接合強度時，可防止組態該等電極33及67之材料擴散至該等絕緣膜35及69中。 Therefore, when the bonding surface 41 of the sensor substrate 2 and the bonding surface 71 of the circuit substrate 7 are configured only by the insulating films 35 and 69 and the electrodes 33 and 67, respectively, to ensure the bonding strength, it can be prevented. The materials configuring the electrodes 33 and 67 are diffused into the insulating films 35 and 69.

因此，在其中藉由該感測器基板2與該電路基板7之間之接合建立該等電極33與67之間之接合之三維結構之半導體裝置1中，在防止該等電極材料擴散至該等絕緣膜35及69中的同時，保證接合強度且可預期可靠性之增強。 Therefore, in the semiconductor device 1 in which the three-dimensional structure of the bonding between the electrodes 33 and 67 is established by the bonding between the sensor substrate 2 and the circuit substrate 7, the electrode material is prevented from diffusing to the semiconductor device 1 At the same time as in the insulating films 35 and 69, the joint strength is ensured and an increase in reliability can be expected.

<<3.第一實施例之半導體裝置之結構中感測器基板之製造程序>> <<3. Manufacturing Procedure of Sensor Substrate in Structure of Semiconductor Device of First Embodiment>>

圖3A至圖3F圖解說明上文結合該第一實施例描述之組態之半導體裝置之製造中使用之感測器基板之一製造程序之不同步驟。在下文中，描述本實施例中使用之感測器基板之一製造程序。 3A through 3F illustrate different steps in a manufacturing procedure of one of the sensor substrates used in the fabrication of the semiconductor device described above in connection with the first embodiment. Hereinafter, a manufacturing procedure of one of the sensor substrates used in the present embodiment will be described.

[圖3A] [Fig. 3A]

首先，如圖3A中所示製備由(例如)單晶矽製成之一半導體基板20。針對每一像素，在該半導體基板20之一預定深度處形成由一n型雜質製成之一光電轉換部分21，且接著在該光電轉換部分21之一表面層上形成由一n+型雜質層形成之一電荷轉移部分及用於電洞之由一p+型雜質層形成之一電荷累積部分。在該半導體基板20之表面層上形成一浮動擴散區FD、一源極/汲極23及由一n+型雜質層形成之未展示之一進一步雜質層。 First, a semiconductor substrate 20 made of, for example, single crystal germanium is prepared as shown in FIG. 3A. For each pixel, one photoelectric conversion portion 21 made of an n-type impurity is formed at a predetermined depth of one of the semiconductor substrates 20, and then an n + -type impurity layer is formed on one surface layer of the photoelectric conversion portion 21 A charge transfer portion and a charge accumulation portion formed by a p + -type impurity layer for the hole are formed. A floating diffusion FD, a source/drain 23, and a further impurity layer not formed by an n+-type impurity layer are formed on the surface layer of the semiconductor substrate 20.

進一步言之，在該半導體基板20之表面上形成一閘極絕緣膜25，且在該閘極絕緣膜25上形成一轉移閘極TG及一閘極電極27。該轉移閘極TG係形成於該浮動擴散區FD與該光電轉換部分21之間，且該閘極電極27係形成於源極/汲極23之間。進一步言之，在相同步驟處，亦形成未展示之其他電極。 Further, a gate insulating film 25 is formed on the surface of the semiconductor substrate 20, and a transfer gate TG and a gate electrode 27 are formed on the gate insulating film 25. The transfer gate TG is formed between the floating diffusion FD and the photoelectric conversion portion 21, and the gate electrode 27 is formed between the source/drain 23 . Further, at the same step, other electrodes not shown are also formed.

此後，在該半導體基板20上形成由(例如)氧化矽製成之一層間絕緣膜29，形成的狀態為該層間絕緣膜29覆蓋該等轉移閘極TG及該等閘極電極27。 Thereafter, an interlayer insulating film 29 made of, for example, ytterbium oxide is formed on the semiconductor substrate 20 in a state in which the interlayer insulating film 29 covers the transfer gates TG and the gate electrodes 27.

[圖3B] [Fig. 3B]

接著，如圖3B中所示在該層間絕緣膜29上形成溝槽圖案29a。該等溝槽圖案29a經形成呈其中其等在必要位置處延伸至該等轉移閘極TG之一形狀。進一步言之，雖然圖3B中未展示，但是延伸至該等源極/汲極23之溝槽圖案係按場合需要形成於該層間絕緣膜29及該閘極絕緣膜25中。 Next, a trench pattern 29a is formed on the interlayer insulating film 29 as shown in FIG. 3B. The groove patterns 29a are formed in a shape in which they are extended to a position of the transfer gates TG at necessary positions. Further, although not shown in FIG. 3B, the groove pattern extending to the source/drain electrodes 23 is formed in the interlayer insulating film 29 and the gate insulating film 25 as occasion demands.

接著，形成一障壁金屬層31a，形成的狀態為該障壁金 屬層31a覆蓋該等溝槽圖案29a之內壁，且形成由銅(Cu)製成之一配接線層31b，形成的狀態為該配接線層31b嵌入該等溝槽圖案29a中。 Next, a barrier metal layer 31a is formed, and the formed state is the barrier gold The genus layer 31a covers the inner walls of the groove patterns 29a, and forms a wiring layer 31b made of copper (Cu) in a state in which the wiring layer 31b is embedded in the groove patterns 29a.

[圖3C] [Fig. 3C]

此後，如圖3C中所示，藉由化學機械拋光(下文中CMP)移除且平坦化該該配接線層31b直到曝露該障壁金屬層31a，且接著移除且平坦化該障壁金屬層31a直到曝露該層間絕緣膜29。因此，在該等溝槽圖案29a中形成其中嵌入該配接線層31b之嵌入式配接線31，其中該障壁金屬層31a內插於該配接線層31b與該等嵌入式配接線31之間，從而獲得包含該等嵌入式配接線31之一配接線層2b。 Thereafter, as shown in FIG. 3C, the wiring layer 31b is removed and planarized by chemical mechanical polishing (hereinafter CMP) until the barrier metal layer 31a is exposed, and then the barrier metal layer 31a is removed and planarized. Until the interlayer insulating film 29 is exposed. Therefore, the embedded wiring 31 in which the wiring layer 31b is embedded is formed in the trench patterns 29a, wherein the barrier metal layer 31a is interposed between the wiring layer 31b and the embedded wiring 31. Thereby, a wiring layer 2b including one of the embedded wirings 31 is obtained.

上述步驟在步驟程序中未被特別限制且可在一合適的所選擇的普通步驟程序中實施。在本技術中，下列步驟係特性步驟。 The above steps are not particularly limited in the step program and can be implemented in a suitable selected general step procedure. In the present technology, the following steps are characteristic steps.

[圖3D] [Fig. 3D]

特定言之，如圖3D所示在該配接線層2b上形成一第一絕緣膜35。該第一絕緣膜35係使用相對於組態接下來將形成之一第一電極膜之一材料之一擴散防止材料形成。例如，若該第一電極膜係由銅(Cu)製成，則使用具有密度大於氧化矽之一分子結構之一無機絕緣材料或一有機絕緣材料形成該第一絕緣膜35。氮化矽(SiN)、矽碳氮化物(SiCN)、氮氧化矽(SiON)及碳化矽(SiC)可應用為剛剛描述之此一無機絕緣材料。同時，苯環丁烯(BCB)、聚苯并噁唑(PBO)、聚醯亞胺及聚芳醚(PAE)可應用為該有機絕緣材料。 Specifically, a first insulating film 35 is formed on the wiring layer 2b as shown in FIG. 3D. The first insulating film 35 is formed using a diffusion preventing material which is one of the materials forming one of the first electrode films with respect to the configuration. For example, if the first electrode film is made of copper (Cu), the first insulating film 35 is formed using an inorganic insulating material or an organic insulating material having a molecular structure having a density greater than that of one of cerium oxide. Cerium nitride (SiN), niobium carbonitride (SiCN), niobium oxynitride (SiON), and niobium carbide (SiC) can be applied as the inorganic insulating material just described. Meanwhile, benzocyclobutene (BCB), polybenzoxazole (PBO), polyimide and polyarylene ether (PAE) can be applied as the organic insulating material.

由如上所述之此等材料之任一者製成之第一絕緣膜35係藉由適合用於該材料之一形成方法形成。例如，若使用一無機絕緣材料，則應用一化學氣相沈積方法(CVD)，但是若使用一有機絕緣材料，則應用一CVD方法或一塗敷方法。 The first insulating film 35 made of any of the above materials is formed by a method suitable for forming one of the materials. For example, if an inorganic insulating material is used, a chemical vapor deposition (CVD) method is applied, but if an organic insulating material is used, a CVD method or a coating method is applied.

接著，在該第一絕緣膜35中形成溝槽圖案35a。該等溝槽圖案35a具有其中嵌入電極襯墊且電極襯墊在未展示之必要位置處延伸至下層之嵌入式配接線31之一形狀。 Next, a groove pattern 35a is formed in the first insulating film 35. The groove patterns 35a have a shape in which the electrode pads are embedded and the electrode pads extend to the lower layer at a necessary position not shown.

以下列方式形成此等溝槽圖案35a。例如，若該第一絕緣膜35係由一無機絕緣材料製成，則首先藉由一光微影方法在該第一絕緣膜35上形成一光阻圖案，且接著使用該光阻圖案作為一遮罩蝕刻該第一絕緣膜35。另一方面，若該第一絕緣膜35係由一有機絕緣材料製成，則首先在該第一絕緣膜35上形成一無機材料層，且接著在該無機材料層上形成一光阻圖案。接著，使用該光阻圖案作為一遮罩以形成一無機遮罩而蝕刻該無機材料層，且自該無機遮罩上方蝕刻該第一絕緣膜35。藉由該蝕刻形成溝槽圖案35a，且此後自該第一絕緣膜35移除該無機遮罩。 These groove patterns 35a are formed in the following manner. For example, if the first insulating film 35 is made of an inorganic insulating material, a photoresist pattern is first formed on the first insulating film 35 by a photolithography method, and then the photoresist pattern is used as a The first insulating film 35 is etched by the mask. On the other hand, if the first insulating film 35 is made of an organic insulating material, an inorganic material layer is first formed on the first insulating film 35, and then a photoresist pattern is formed on the inorganic material layer. Next, the photoresist pattern is used as a mask to form an inorganic mask to etch the inorganic material layer, and the first insulating film 35 is etched from above the inorganic mask. The trench pattern 35a is formed by the etching, and thereafter the inorganic mask is removed from the first insulating film 35.

[圖3E] [Fig. 3E]

此後，如圖3E中所示，直接在該第一絕緣膜35上形成一第一電極膜33a，形成的狀態為該第一電極膜33a嵌入該等溝槽圖案35a。該第一電極膜33a係由被防止擴散至該第一絕緣膜35中之一材料製成且使用(例如)銅(Cu)組態。例如，藉由憑藉一濺鍍方法形成一薄晶種層且接著使用一電 鍍方法實施剛剛描述之此一第一電極膜33a之形成，其中該晶種層被用作一電極。 Thereafter, as shown in FIG. 3E, a first electrode film 33a is formed directly on the first insulating film 35 in a state in which the first electrode film 33a is embedded in the groove patterns 35a. The first electrode film 33a is made of a material that is prevented from being diffused into the first insulating film 35 and configured using, for example, a copper (Cu). For example, by forming a thin seed layer by means of a sputtering method and then using an electric The plating method performs the formation of the first electrode film 33a just described, wherein the seed layer is used as an electrode.

[圖3F] [Fig. 3F]

接著，如圖3F中所示，藉由一CMP方法移除並平坦化直接在該第一絕緣膜35上形成之第一電極膜33a直到曝露該第一絕緣膜35。此後使用該第一絕緣膜35作為一拋光止擋件，按順序自周圍於拋光面中曝露該第一絕緣膜35之第一電極膜33a部分實施拋光自動停止之此CMP。僅需要該第一電極膜33a由以銅(Cu)代表之化學活性材料製成以實施此CMP。如下使用各種方法。 Next, as shown in FIG. 3F, the first electrode film 33a formed directly on the first insulating film 35 is removed and planarized by a CMP method until the first insulating film 35 is exposed. Thereafter, the first insulating film 35 is used as a polishing stopper, and the CMP in which the polishing is automatically stopped is performed in order from the portion of the first electrode film 33a in which the first insulating film 35 is exposed in the surrounding polishing surface. It is only required that the first electrode film 33a is made of a chemically active material represented by copper (Cu) to carry out this CMP. Various methods are used as follows.

例如，在周圍藉由該第一電極膜33a之CMP拋光推進曝露該第一絕緣膜35之一區域中，發生拋光漿料之一局部溫度變動或拋光面上之第一電極膜33a之填充之一局部變動。因此，可推薦一方法，其中利用此等局部變動之一化學作用係用以局部且自動停止周圍曝露該第一絕緣膜35之第一電極膜33a之一區域中之藉由CMP之拋光推進。 For example, in a region where the first insulating film 35 is exposed by CMP polishing of the first electrode film 33a, local temperature fluctuation of one of the polishing slurry or filling of the first electrode film 33a on the polishing surface occurs. A partial change. Therefore, a method can be recommended in which one of the chemical changes is utilized to locally and automatically stop the polishing advancement by CMP in a region of the first electrode film 33a where the first insulating film 35 is exposed.

可使用另一方法，其中僅該第一電極膜33a之表面降級且僅在未使用一化學蝕刻作用之情況下接觸一拋光襯墊之一位置處推進拋光。在此情況中，在周圍藉由該第一電極膜33a之CMP拋光推進曝露該第一絕緣膜35之第一電極膜33a之區域中，該第一絕緣膜35之表面被用作一參考平面且不再推進該拋光。因此，開始於周圍曝露該第一絕緣膜35之第一電極33之區域按順序自動停止該拋光。特定言之，藉由對Cu「HS-C430」(Hitachi Chemical Co.,Ltd.之 產品名稱)使用研磨顆粒極少的拋光漿料作為拋光漿料實施此CMP。 Another method may be used in which only the surface of the first electrode film 33a is degraded and the polishing is advanced only at a position where one of the polishing pads is contacted without using a chemical etching action. In this case, in a region where the first electrode film 33a of the first insulating film 35 is exposed by CMP polishing of the first electrode film 33a, the surface of the first insulating film 35 is used as a reference plane. This polishing is no longer advanced. Therefore, the polishing starts automatically in the region starting from the periphery where the first electrode 33 of the first insulating film 35 is exposed. Specifically, by using Cu "HS-C430" (Hitachi Chemical Co., Ltd.) Product Name) This CMP was carried out using a polishing slurry with little abrasive particles as a polishing slurry.

就前述而言，其中嵌入該第一電極膜33a之第一電極33形成為該等溝槽圖案35a中之嵌入式電極以獲得包含該等第一電極33之電極層2c。藉此，具有由該等第一電極33及該第一絕緣膜35組態之平坦接合面41之感測器基板2製造為一第一基板。 As described above, the first electrode 33 in which the first electrode film 33a is embedded is formed as an embedded electrode in the groove patterns 35a to obtain the electrode layer 2c including the first electrodes 33. Thereby, the sensor substrate 2 having the flat bonding faces 41 configured by the first electrodes 33 and the first insulating film 35 is fabricated as a first substrate.

<<4.第一實施例之半導體裝置之製造中電路基板之製造程序>> <<4. Manufacturing Procedure of Circuit Board in Manufacturing of Semiconductor Device of First Embodiment>>

圖4A至圖4E圖解說明與製造上文結合該第一實施例描述之組態之半導體裝置一起使用之一電路基板之一製造程序。在下文中，參考圖4A至圖4E描述該實施例中使用之電路基板之製造程序。 4A through 4E illustrate a manufacturing process of one of the circuit substrates used in conjunction with the fabrication of the semiconductor device described above in connection with the first embodiment. Hereinafter, a manufacturing procedure of the circuit substrate used in the embodiment will be described with reference to FIGS. 4A to 4E.

[圖4A] [Fig. 4A]

首先，如圖4A中所示，製備由(例如)單晶矽製成之一半導體基板50。在該半導體基板50之一表面層上形成個別導電類型之源極/汲極51及圖4A中未展示之其他雜質層。進一步言之，在該半導體基板50之表面上形成一閘極絕緣膜53，且在該閘極絕緣膜53上形成閘極電極55。該等閘極電極55形成於該等源極/汲極51之間。進一步言之，在相同步驟處，形成未展示之其他電極。 First, as shown in FIG. 4A, a semiconductor substrate 50 made of, for example, single crystal germanium is prepared. Source/drain 51 of an individual conductivity type and other impurity layers not shown in FIG. 4A are formed on one surface layer of the semiconductor substrate 50. Further, a gate insulating film 53 is formed on the surface of the semiconductor substrate 50, and a gate electrode 55 is formed on the gate insulating film 53. The gate electrodes 55 are formed between the source/drain 51. Further, at the same step, other electrodes not shown are formed.

此後，在該半導體基板50上形成由(例如)氧化矽製成之一層間絕緣膜57，形成的狀態為該層間絕緣膜57覆蓋該等閘極電極55。 Thereafter, an interlayer insulating film 57 made of, for example, ytterbium oxide is formed on the semiconductor substrate 50 in a state in which the interlayer insulating film 57 covers the gate electrodes 55.

此後，在該層間絕緣膜57中形成溝槽圖案57a。該等溝槽圖案57a經形成呈其中其等在必要位置處延伸至閘極電極55之一形狀。進一步言之，雖然圖4A中未展示，但是在該層間絕緣膜57及該閘極絕緣膜53中在必要位置處形成延伸至該等源極/汲極51之溝槽圖案。接著，形成一障壁金屬層59a，形成的狀態為其覆蓋該等溝槽圖案57a之內壁，且在該障壁金屬層59a上形成由銅(Cu)製成之一配接線層59b，形成的狀態為該配接線層59b嵌入該等溝槽圖案57a。此後，藉由CMP相繼平坦化且移除該配接線層59b及該障壁金屬層59a。藉此，在該等溝槽圖案57a中形成其中嵌入配接線層59b之嵌入式配接線59，其中該障壁金屬層59a內插於該配接線層59b與該嵌入式配接線59之間以獲得包含該等嵌入式配接線59之一第一配接線層7b。 Thereafter, a groove pattern 57a is formed in the interlayer insulating film 57. The groove patterns 57a are formed in a shape in which one of them extends to a position of the gate electrode 55 at a necessary position. Further, although not shown in FIG. 4A, a groove pattern extending to the source/drain 51 is formed in the interlayer insulating film 57 and the gate insulating film 53 at necessary positions. Next, a barrier metal layer 59a is formed in a state of covering the inner walls of the trench patterns 57a, and a wiring layer 59b made of copper (Cu) is formed on the barrier metal layer 59a. The state is that the wiring layer 59b is embedded in the groove patterns 57a. Thereafter, the wiring layer 59b and the barrier metal layer 59a are successively planarized by CMP. Thereby, an embedded wiring 59 in which the wiring layer 59b is embedded is formed in the trench patterns 57a, wherein the barrier metal layer 59a is interposed between the wiring layer 59b and the embedded wiring 59 to obtain A first wiring layer 7b of one of the embedded wirings 59 is included.

[圖4B] [Fig. 4B]

如圖4B中所示，一層間絕緣膜63經層壓以在該第一配接線層7b上形成一膜，其中擴散防止絕緣層61內插於該層間絕緣膜63與該第一配接線層7b之間以在該層間絕緣膜63及該擴散防止絕緣層61中形成溝槽圖案63a。該等溝槽圖案63a經形成以在必要位置處延伸至下層之嵌入式配接線59。此後，一配接線層65b嵌入該等溝槽圖案63a中，其中一障壁金屬層65a內插於該配接線層65b與該等溝槽圖案63a之間以形成嵌入式配接線65，藉此以獲得一第二配接線層7c。 As shown in FIG. 4B, an interlayer insulating film 63 is laminated to form a film on the first wiring layer 7b, wherein the diffusion preventing insulating layer 61 is interposed in the interlayer insulating film 63 and the first wiring layer A groove pattern 63a is formed between the interlayer insulating film 63 and the diffusion preventing insulating layer 61 between 7b. The groove patterns 63a are formed to extend to the lower layer of the mating wiring 59 at a necessary position. Thereafter, a wiring layer 65b is embedded in the trench patterns 63a, and a barrier metal layer 65a is interposed between the wiring layer 65b and the trench patterns 63a to form an embedded wiring 65, thereby A second wiring layer 7c is obtained.

上述步驟可以一普通步驟程序實施且並不限於一特定步 驟程序但是可藉由一合適的程序實施。在本技術中，下文描述之步驟係特性步驟。 The above steps can be implemented in a general step procedure and are not limited to a specific step The procedure can be implemented by a suitable procedure. In the present technology, the steps described below are characteristic steps.

[圖4C] [Fig. 4C]

首先，如圖4C中所示，在該第二配接線層7c上形成一第二絕緣膜69。使用相對於組態接著將形成之一第二導電膜之材料之一擴散防止材料形成該第二絕緣膜69。例如，若該第二電極層係由銅(Cu)製成，則使用類似於上述感測器基板2側上之第一絕緣膜35之材料之一材料組態該第二絕緣膜69，且該第二絕緣膜69形成為一膜。 First, as shown in Fig. 4C, a second insulating film 69 is formed on the second wiring layer 7c. The second insulating film 69 is formed using a diffusion preventing material which is one of materials which will form a second conductive film with respect to the configuration. For example, if the second electrode layer is made of copper (Cu), the second insulating film 69 is configured using a material similar to the material of the first insulating film 35 on the side of the sensor substrate 2 described above, and The second insulating film 69 is formed as a film.

接著，在該第二絕緣膜69中形成溝槽圖案69a。該等溝槽圖案69a具有其中嵌入電極襯墊之一形狀，且在必要位置處延伸至形成於該第二配接線層7c中之嵌入式配接線65。類似於形成於上述感測器基板2側上之第一絕緣膜35中之溝槽圖案35a之形成實施此等溝槽圖案69a之形成。 Next, a trench pattern 69a is formed in the second insulating film 69. The groove patterns 69a have a shape in which one of the electrode pads is embedded, and extend to a recessed wiring 65 formed in the second wiring layer 7c at a necessary position. The formation of the groove patterns 69a is performed similarly to the formation of the groove patterns 35a formed in the first insulating film 35 on the side of the above-described sensor substrate 2.

[圖4D] [Fig. 4D]

接著如圖4D中所示，直接在該第二絕緣膜69上形成一第二電極膜67a，形成的狀態為該第二電極膜67a嵌入該等溝槽圖案69a中。該第二電極膜67a由防止擴散至該第二絕緣膜69中之一材料製成，且係使用(例如)銅(Cu)組態。例如，藉由憑藉一濺鍍方法形成一薄晶種膜且接著使用晶種層作為一電極實施一電鍍方法來實施剛剛描述之此第二電極膜67a之形成。 Next, as shown in FIG. 4D, a second electrode film 67a is formed directly on the second insulating film 69 in a state in which the second electrode film 67a is embedded in the groove patterns 69a. The second electrode film 67a is made of a material that prevents diffusion into the second insulating film 69, and is configured using, for example, a copper (Cu). For example, the formation of the second electrode film 67a just described is carried out by forming a thin seed film by a sputtering method and then performing an electroplating method using the seed layer as an electrode.

[圖4E] [Fig. 4E]

接著，如圖4E中所示，藉由一CMP方法平坦化並移除該 第二電極膜67a直到曝露該第二絕緣膜69。藉由CMP實施該第二電極膜67a之平坦化，其中類似於上文參考圖3F描述之第一電極膜33a之平坦化使用該第二絕緣膜69作為一拋光止擋件開始於周圍在該拋光面中曝露該第二絕緣膜69之第二電極膜67a之一部分中按順序自動停止拋光。 Then, as shown in FIG. 4E, the CVD method is used to planarize and remove the The second electrode film 67a is exposed until the second insulating film 69 is exposed. The planarization of the second electrode film 67a is performed by CMP, wherein the planarization of the first electrode film 33a similar to that described above with reference to FIG. 3F is started using the second insulating film 69 as a polishing stopper. The polishing is automatically stopped in order in one of the portions of the second electrode film 67a in which the second insulating film 69 is exposed in the polishing surface.

藉由上述程序，在該等溝槽圖案69a中形成其中嵌入該第二電極膜67a之第二電極67以獲得包含作為嵌入式電極之第二電極67之一電極層7d。進一步言之，具有由該第二電極67及該第二絕緣膜69組態之一接合面71之一電路基板7製造為一第二基板。 By the above procedure, the second electrode 67 in which the second electrode film 67a is embedded is formed in the groove patterns 69a to obtain an electrode layer 7d including the second electrode 67 as an embedded electrode. Further, the circuit substrate 7 having one of the bonding faces 71 configured by the second electrode 67 and the second insulating film 69 is fabricated as a second substrate.

<<5.第一實施例之半導體裝置之製造中該等基板之接合>> <<5. Joining of the substrates in the manufacture of the semiconductor device of the first embodiment>>

現在，參考圖5A及圖5B描述上面形成平坦接合面41之感測器基板2與上面形成平坦接合面71之電路基板7彼此接合之一程序。 Now, a procedure in which the sensor substrate 2 on which the flat bonding surface 41 is formed and the circuit substrate 7 on which the flat bonding surface 71 is formed are bonded to each other will be described with reference to FIGS. 5A and 5B.

[圖5A] [Fig. 5A]

首先，如圖5A中所示，以彼此呈一相對關係安置藉由上述程序組態之感測器基板2及電路基板7，使得該平坦接合面41與該平坦接合面71彼此相對。進一步言之，該感測器基板2及該電路基板7經定位使得該感測器基板2側之第一電極33與該電路基板7側之第二電極67彼此對應。在所示實例中，雖然該等第一電極33與該等第二電極67處於其中其等以一1：1對應關係彼此對應之一狀態中，但是該感測器基板2與該電路基板7之對應關係並不限於此。 First, as shown in FIG. 5A, the sensor substrate 2 and the circuit substrate 7 configured by the above-described procedure are disposed in an opposing relationship with each other such that the flat joint surface 41 and the flat joint surface 71 face each other. Further, the sensor substrate 2 and the circuit substrate 7 are positioned such that the first electrode 33 on the side of the sensor substrate 2 and the second electrode 67 on the side of the circuit substrate 7 correspond to each other. In the illustrated example, the first electrode 33 and the second electrodes 67 are in a state in which they correspond to each other in a 1:1 correspondence relationship, but the sensor substrate 2 and the circuit substrate 7 The correspondence is not limited to this.

應注意，對於該感測器基板2之接合面41及該電路基板7之接合面71，按場合需要藉由一濕式製程或一電漿製程對接合實施預處理。 It should be noted that for the bonding surface 41 of the sensor substrate 2 and the bonding surface 71 of the circuit substrate 7, the bonding is performed by a wet process or a plasma process as occasion demands.

[圖5B] [Fig. 5B]

接著，如圖5B中所示，該感測器基板2及該電路基板7經層壓使得該接合面41與該接合面71彼此接觸。接著，在此狀態中實施熱處理以使該接合面41之第一電極33與該接合面71之第二電極67彼此接合。進一步言之，該接合面41之第一絕緣膜35與該接合面71之第二絕緣膜69彼此接合。此熱處理係基於組態該等第一電極33及該等第二電極67之材料在對形成於該感測器基板2及該電路基板7上之元件及配接線不具有一影響之一範圍內在一溫度下實行並且持續足以容許該等電極33與67彼此接合之時間。 Next, as shown in FIG. 5B, the sensor substrate 2 and the circuit substrate 7 are laminated such that the joint surface 41 and the joint surface 71 are in contact with each other. Next, heat treatment is performed in this state to bond the first electrode 33 of the joint surface 41 and the second electrode 67 of the joint surface 71 to each other. Further, the first insulating film 35 of the bonding surface 41 and the second insulating film 69 of the bonding surface 71 are bonded to each other. The heat treatment is based on the configuration of the first electrode 33 and the second electrode 67 in a range that does not have an influence on the components and wirings formed on the sensor substrate 2 and the circuit substrate 7. It is carried out at a temperature and continues for a time sufficient to allow the electrodes 33 and 67 to engage each other.

例如，在其中該等第一電極33及該等第二電極67係由含有銅(Cu)作為一主要組份之材料組態之情況中，在200℃至600℃下實施熱處理持續約1小時至5小時。此熱處理可在一加壓氛圍下實施或可在其中該感測器基板2與該電路基板7自相對正面彼此按壓之一狀態中實施。作為一實例，在400℃下實施熱處理持續4小時以實施Cu-Cu連結。 For example, in the case where the first electrodes 33 and the second electrodes 67 are configured of a material containing copper (Cu) as a main component, heat treatment is performed at 200 ° C to 600 ° C for about 1 hour. Up to 5 hours. This heat treatment may be performed under a pressurized atmosphere or may be performed in a state in which the sensor substrate 2 and the circuit substrate 7 are pressed against each other from the front side. As an example, heat treatment was performed at 400 ° C for 4 hours to carry out Cu-Cu bonding.

在以如上所述之此一方式在該等連結面41及71處彼此層壓且接合該感測器基板2與該電路基板7後，將該感測器基板2側之半導體基板20薄化成一半導體層2a以曝露該光電轉換部分21。進一步言之，按場合需要，薄化該電路基板7之半導體基板50以形成一半導體層7a。 After the sensor substrate 2 and the circuit substrate 7 are laminated to each other at the joint faces 41 and 71 in such a manner as described above, the semiconductor substrate 20 on the sensor substrate 2 side is thinned into A semiconductor layer 2a is used to expose the photoelectric conversion portion 21. Further, the semiconductor substrate 50 of the circuit substrate 7 is thinned as needed to form a semiconductor layer 7a.

[圖2] [figure 2]

此後，如圖2中所示，在該感測器基板2之光電轉換部分21之曝露面上形成一保護膜15，且接著在該保護膜15上形成一彩色濾光片層17及晶片上透鏡19以藉此完成作為一固態影像擷取裝置之一半導體裝置1。 Thereafter, as shown in FIG. 2, a protective film 15 is formed on the exposed surface of the photoelectric conversion portion 21 of the sensor substrate 2, and then a color filter layer 17 and a wafer are formed on the protective film 15. The lens 19 is thereby completed as a semiconductor device 1 which is one of the solid-state image capturing devices.

[第一實施例之半導體裝置之製造方法之工作效果] [Working effect of the manufacturing method of the semiconductor device of the first embodiment]

運用根據上述第一實施例之製造方法，如上文參考圖3F描述，在該感測器基板2之形成中，藉由CMP平坦化並移除直接在該第一絕緣膜35上形成之第一電極膜33a，其中該第一絕緣膜35被用作一拋光止擋件。此後，因為開始於周圍曝露該第一絕緣膜35之第一電極膜33a之部分按順序實施其中拋光自動停止之CMP，所以可防止在該拋光面之總體面積上發生表面凹陷或腐蝕，且可獲得一平坦拋光面作為該接合面41。 With the manufacturing method according to the first embodiment described above, as described above with reference to FIG. 3F, in the formation of the sensor substrate 2, the first formed directly on the first insulating film 35 is planarized by CMP and removed. The electrode film 33a in which the first insulating film 35 is used as a polishing stopper. Thereafter, since the portion in which the first electrode film 33a of the first insulating film 35 is exposed to the periphery is sequentially subjected to CMP in which the polishing is automatically stopped, surface depression or corrosion may be prevented from occurring on the entire area of the polishing surface, and A flat polished surface is obtained as the joint surface 41.

進一步言之，亦在上文參考圖4E描述之步驟處，類似於前述描述，可獲得一平坦拋光面作為該接合面71。 Further, also at the steps described above with reference to FIG. 4E, similar to the foregoing description, a flat polished surface can be obtained as the joint surface 71.

因此，在上文參考圖5A及圖5B描述之接合步驟處，該感測器基板2與該電路基板7彼此接合於其等之平坦接合面41與平坦接合面71之間。因此，在該接合面41及該接合面71之總體面積上實施建立該等電極33與67之間之良好連結之接合，且可維持該感測器基板2與該電路基板7之間之高接合強度。 Therefore, at the bonding step described above with reference to FIGS. 5A and 5B, the sensor substrate 2 and the circuit substrate 7 are bonded to each other between the flat bonding surface 41 and the flat bonding surface 71 thereof. Therefore, a good connection between the electrodes 33 and 67 is established on the entire area of the bonding surface 41 and the bonding surface 71, and the height between the sensor substrate 2 and the circuit substrate 7 can be maintained. Bonding strength.

進一步言之，組態該感測器基板2側之接合面41之第一絕緣膜35係由相對於該第一電極33之一擴散防止材料組 態。因此，可防止該等第一電極33擴散至該第一絕緣膜35中。類似地，組態該電路基板7側之接合面71之第二絕緣膜69係由相對於該第二電極67之一擴散防止材料組態。因此，可防止該等第二電極67擴散至該第二絕緣膜69中。因此，可達成其中維持如上所述該等電極33與67之間之此連結強度之接合。 Further, the first insulating film 35 configuring the bonding surface 41 on the side of the sensor substrate 2 is composed of a diffusion preventing material group with respect to one of the first electrodes 33 state. Therefore, the first electrodes 33 can be prevented from diffusing into the first insulating film 35. Similarly, the second insulating film 69 configuring the bonding surface 71 on the side of the circuit substrate 7 is configured by a diffusion preventing material with respect to one of the second electrodes 67. Therefore, the second electrodes 67 can be prevented from diffusing into the second insulating film 69. Therefore, the bonding in which the strength of the connection between the electrodes 33 and 67 as described above is maintained can be achieved.

而且，該感測器基板2側之第一絕緣膜35係由相對於該電路基板7側之第二電極67之一擴散防止材料組態，且該電路基板7上之第二絕緣膜69係由相對於該感測器基板2側之第一電極33之一擴散防止材料組態。因此，可防止該感測器基板2與該電路基板7之間之一電極材料互相擴散。 Further, the first insulating film 35 on the side of the sensor substrate 2 is configured by one diffusion preventing material with respect to the second electrode 67 on the side of the circuit substrate 7, and the second insulating film 69 on the circuit substrate 7 is The material configuration is prevented by diffusion of one of the first electrodes 33 with respect to the side of the sensor substrate 2. Therefore, it is possible to prevent one electrode material between the sensor substrate 2 and the circuit substrate 7 from interdifing.

此外，該感測器基板2側上之接合面41係僅由該等第一電極33及該第一絕緣膜35組態，且該電路基板7側上之接合面71係僅由該等第二電極67及該第二絕緣膜69組態。因此，該等接合面41及71並非係由不起化學作用且不太可能維持連結強度之一障壁金屬層組態，且該等接合面之組態得以簡化。而且藉此可維持連結強度。 In addition, the bonding surface 41 on the side of the sensor substrate 2 is configured only by the first electrodes 33 and the first insulating film 35, and the bonding surface 71 on the side of the circuit substrate 7 is only by the first The two electrodes 67 and the second insulating film 69 are configured. Therefore, the joint faces 41 and 71 are not unsuitable for chemical action and are less likely to maintain the barrier metal layer configuration of the joint strength, and the configuration of the joint faces is simplified. Moreover, the strength of the connection can be maintained.

圖6A至圖6C、圖6A'至圖6C'及圖6D圖解說明一比較性實例之一半導體裝置之一製造程序。以下列方式實施圖6A至圖6D中所示之比較性實例之程序。 6A to 6C, 6A' to 6C' and 6D illustrate a manufacturing procedure of one of the semiconductor devices of a comparative example. The procedure of the comparative example shown in Figs. 6A to 6D is carried out in the following manner.

首先，如圖6A中所示，在覆蓋諸基板之一者之表面之一第一絕緣膜101上形成一溝槽圖案101a，且沿該溝槽圖案101a形成一電極材料之一障壁金屬層102，隨後在該障壁金屬層102上形成由銅(Cu)製成之一第一電極膜103a。接 著，如圖6B中所示，藉由CMP平坦化並移除該第一電極膜103a以曝露該障壁金屬層102。藉此，實施其中該障壁金屬層102用作一拋光止擋件之CMP。進一步言之，由於此CMP，開始於周圍曝露該障壁金屬層102於拋光面之第一電極膜103a之一部分按順序實施其中拋光自動停止之CMP。 First, as shown in FIG. 6A, a trench pattern 101a is formed on one of the first insulating films 101 covering one of the surfaces of the substrates, and a barrier metal layer 102 of one of the electrode materials is formed along the trench pattern 101a. Then, a first electrode film 103a made of copper (Cu) is formed on the barrier metal layer 102. Connect As shown in FIG. 6B, the first electrode film 103a is planarized by CMP and removed to expose the barrier metal layer 102. Thereby, a CMP in which the barrier metal layer 102 is used as a polishing stopper is implemented. Further, due to this CMP, the CMP in which the polishing is automatically stopped is sequentially performed in a portion in which the barrier metal layer 102 is exposed to a portion of the first electrode film 103a of the polishing surface.

此後，如圖6C中所示，藉由拋光平坦化並移除該障壁金屬層102以曝露該第一絕緣膜101。藉由前述，形成其中由銅(Cu)製成之第一電極膜103a嵌入該第一絕緣膜101之溝槽圖案101a中，其中該障壁金屬層102內插於該第一電極膜103a與該溝槽圖案101a之間之一第一電極103。 Thereafter, as shown in FIG. 6C, the barrier metal layer 102 is planarized by polishing and the first insulating film 101 is exposed. By the foregoing, the first electrode film 103a made of copper (Cu) is embedded in the trench pattern 101a of the first insulating film 101, wherein the barrier metal layer 102 is interposed in the first electrode film 103a and One of the first electrodes 103 between the trench patterns 101a.

同時，如圖6A'至圖6C'中所示，在另一基板之表面側上，亦藉由一類似程序在一第二絕緣膜201之一溝槽圖案201a中形成一第二電極203，在該第二電極203中嵌入由銅(Cu)製成之一第二電極膜203a，其中一障壁金屬層202內插於該第二電極203與該第二電極膜203a之間。 Meanwhile, as shown in FIGS. 6A' to 6C', on the surface side of the other substrate, a second electrode 203 is formed in a trench pattern 201a of a second insulating film 201 by a similar procedure. A second electrode film 203a made of copper (Cu) is embedded in the second electrode 203, and a barrier metal layer 202 is interposed between the second electrode 203 and the second electrode film 203a.

此後，如圖6D中所示，該等基板經安置使得其等之拋光面彼此相對且在其等彼此面對之第一電極103及第二電極203處連結在一起以彼此接合。 Thereafter, as shown in FIG. 6D, the substrates are disposed such that their polished faces are opposed to each other and joined together at the first electrode 103 and the second electrode 203 which face each other to be joined to each other.

在剛剛描述之比較性實例之此一程序中，在圖6B至圖6C中該障壁金屬層102及該第一電極膜103a之拋光中，起化學作用之由銅(Cu)製成之第一電極膜103a之曝露面積並未發生一突變。因此，無法實施其中開始於周圍曝露該第一絕緣膜101之第一電極膜103a之一部分按順序自動停止 拋光之CMP。因此，無法防止在拋光面中發生表面凹陷或腐蝕，且難以獲得一平坦拋光面。此亦類似地應用於圖6C'中所示之步驟。 In the procedure of the comparative example just described, in the polishing of the barrier metal layer 102 and the first electrode film 103a in FIG. 6B to FIG. 6C, the first chemical action is made of copper (Cu). The exposed area of the electrode film 103a did not undergo a sudden change. Therefore, it is impossible to implement a portion in which the first electrode film 103a which starts to expose the first insulating film 101 is automatically stopped in order Polished CMP. Therefore, it is impossible to prevent surface depression or corrosion from occurring in the polished surface, and it is difficult to obtain a flat polished surface. This also applies similarly to the steps shown in Figure 6C'.

因此，如圖6D中所示，平坦度較差之拋光面即使彼此相對以使該等基板彼此接合，亦無法獲得足夠的接合強度。而且，亦無法足夠地獲得該第一電極103與該第二電極203之間之連結強度。 Therefore, as shown in FIG. 6D, the polishing faces having poor flatness cannot obtain sufficient joint strength even if they are opposed to each other to bond the substrates to each other. Moreover, the strength of the connection between the first electrode 103 and the second electrode 203 cannot be sufficiently obtained.

進一步言之，圖6C中所示之拋光面係由該第一絕緣膜101、該障壁金屬層102及該第一電極103組態。同時，圖6C'中所示之拋光面亦係由該第二絕緣膜201、該障壁金屬層202及該第二電極203組態。因此，在該等拋光面之一連結介面上，亦產生該第一絕緣膜101及該第一電極103與該障壁金屬層202之間之一連結介面以及該第二絕緣膜201及該第二電極203與該障壁金屬層102之間之一連結介面。然而，因為該等障壁金屬層102及202不起化學作用，所以在接合時難以藉由一電漿製程或一濕式製程進行預處理。為此，在曝露該等障壁金屬層102及202之接合面之部分處，無法獲得高連結強度。此使該等基板之間之接合強度之一因數發生明顯的降級。 Further, the polishing surface shown in FIG. 6C is configured by the first insulating film 101, the barrier metal layer 102, and the first electrode 103. Meanwhile, the polishing surface shown in FIG. 6C' is also configured by the second insulating film 201, the barrier metal layer 202, and the second electrode 203. Therefore, a connection interface between the first insulating film 101 and the first electrode 103 and the barrier metal layer 202, and the second insulating film 201 and the second are also formed on one of the bonding surfaces of the polishing surfaces. One interface between the electrode 203 and the barrier metal layer 102 is connected to the interface. However, since the barrier metal layers 102 and 202 do not chemically act, it is difficult to perform pretreatment by a plasma process or a wet process during bonding. For this reason, high joint strength cannot be obtained at the portion where the joint faces of the barrier metal layers 102 and 202 are exposed. This causes a significant degradation in the factor of the bond strength between the substrates.

與如上所述之此一比較性實例相比，在圖2中所示之本實施例之半導體裝置中，在該平坦接合面41與該平坦接合面71之間實施接合，該接合簡化為兩種類型的接合，第一電極33與第二電極67及第一絕緣膜35與第二絕緣膜69的接合。進一步言之，在該第一電極33與該第二電極67之間、 該第一絕緣膜35與該第二絕緣膜69之間、該第一電極33與該第二絕緣膜69之間及該第二電極67與該第一絕緣膜35之間，可獲得足夠的連結強度。因此，在作為一第一基板之感測器基板2與作為一第二基板之電路基板7之間，可獲得足夠的接合強度。 In the semiconductor device of the present embodiment shown in FIG. 2, the bonding is performed between the flat bonding surface 41 and the flat bonding surface 71, which is simplified to two, as compared with the comparative example described above. The bonding of the first type of the first electrode 33 and the second electrode 67 and the first insulating film 35 and the second insulating film 69. Further, between the first electrode 33 and the second electrode 67, Sufficient between the first insulating film 35 and the second insulating film 69, between the first electrode 33 and the second insulating film 69, and between the second electrode 67 and the first insulating film 35 Link strength. Therefore, sufficient joint strength can be obtained between the sensor substrate 2 as a first substrate and the circuit substrate 7 as a second substrate.

<<6.第一實施例之半導體裝置之修改>> <<6. Modification of Semiconductor Device of First Embodiment>>

圖7展示根據該第一實施例之一修改之一半導體裝置1'。參考圖7，可在作為一第一基板之感測器基板2上設置包含一層間絕緣膜35-1及一擴散防止絕緣膜35-2之一第一絕緣膜35'。在此例項中，在由(例如)氧化矽或一低介電材料製成之層間絕緣膜35-1中設置一溝槽圖案35a，且設置該擴散防止絕緣膜35-2，設置的狀態為該擴散防止絕緣膜35-2覆蓋包含該溝槽圖案35a之一內面之層間絕緣膜35-1。進一步言之，在該溝槽圖案35a中設置一第一電極33，其中該擴散防止絕緣膜35-2內插於該第一電極33與該溝槽圖案35a之間。因此，藉由該擴散防止絕緣膜35-2包圍該第一電極33之周邊，且由該第一電極33及該擴散防止絕緣膜35-2組態一接合面41。 Fig. 7 shows a semiconductor device 1' according to one of the modifications of the first embodiment. Referring to FIG. 7, a first insulating film 35' including an interlayer insulating film 35-1 and a diffusion preventing insulating film 35-2 may be disposed on the sensor substrate 2 as a first substrate. In this example, a trench pattern 35a is provided in the interlayer insulating film 35-1 made of, for example, hafnium oxide or a low dielectric material, and the diffusion preventing insulating film 35-2 is provided, and the state is set. The diffusion preventing insulating film 35-2 covers the interlayer insulating film 35-1 including the inner surface of one of the trench patterns 35a. Further, a first electrode 33 is disposed in the trench pattern 35a, and the diffusion preventing insulating film 35-2 is interposed between the first electrode 33 and the trench pattern 35a. Therefore, the diffusion preventing insulating film 35-2 surrounds the periphery of the first electrode 33, and a bonding surface 41 is configured by the first electrode 33 and the diffusion preventing insulating film 35-2.

在作為一第二基板之電路基板7上，亦可類似地設置包含一層間絕緣膜69-1及一擴散防止絕緣膜69-2之一第二絕緣膜69'。因此，藉由該擴散防止絕緣膜69-2包圍該第二電極67之周邊，且由該第二電極67及該擴散防止絕緣膜69-2組態一接合面71。 On the circuit substrate 7 as a second substrate, a second insulating film 69' including an interlayer insulating film 69-1 and a diffusion preventing insulating film 69-2 may be similarly disposed. Therefore, the diffusion preventing insulating film 69-2 surrounds the periphery of the second electrode 67, and a bonding surface 71 is configured by the second electrode 67 and the diffusion preventing insulating film 69-2.

運用具有如上所述之此一組態之半導體裝置1'，亦可僅 由該等擴散防止絕緣膜35-2及69-2及該等電極33及67組態該感測器基板2之接合面41及該電路基板7之接合面71以保證連結強度。而且，可防止組態該等電極33及67之材料擴散至該等層間絕緣膜35-1及69-1中。 By using the semiconductor device 1' having such a configuration as described above, it is also possible to The bonding surfaces 41 of the sensor substrate 2 and the bonding faces 71 of the circuit substrate 7 are disposed by the diffusion preventing insulating films 35-2 and 69-2 and the electrodes 33 and 67 to ensure the bonding strength. Moreover, it is possible to prevent the materials configuring the electrodes 33 and 67 from being diffused into the interlayer insulating films 35-1 and 69-1.

因此，在其中藉由接合該兩個基板2及7將該第一電極33及該第二電極67連結在一起之三維結構之半導體裝置1'中，保證接合強度並同時防止一電極材料之擴散。因此，可達成可靠性之改良。 Therefore, in the semiconductor device 1' in which the first electrode 33 and the second electrode 67 are joined together by joining the two substrates 2 and 7, the bonding strength is ensured while preventing diffusion of an electrode material. . Therefore, an improvement in reliability can be achieved.

進一步言之，在具有如上所述之此一組態之半導體裝置1'之製造中，當製造作為一第一基板之感測器基板2時，可使用該擴散防止絕緣膜35-2作為一止擋件藉由CMP拋光組態該第一電極33之膜。因此，可精確地偵測到曝露該擴散防止絕緣膜35-2之時間點作為拋光之一結束點，且在不產生表面凹陷之情況下可結束CMP以獲得一平坦拋光面作為該接合面41。 Further, in the manufacture of the semiconductor device 1' having such a configuration as described above, when the sensor substrate 2 as a first substrate is manufactured, the diffusion preventing insulating film 35-2 can be used as a The stopper configures the film of the first electrode 33 by CMP polishing. Therefore, the time point at which the diffusion preventing insulating film 35-2 is exposed can be accurately detected as one of the polishing end points, and the CMP can be ended without generating a surface recess to obtain a flat polished surface as the joint surface 41. .

在其中將產生作為一第二基板之電路基板7之情況中，類似地亦可使用該擴散防止絕緣膜69-2作為一止擋件藉由CMP拋光組態該第二電極67之一膜。因此，類似地可獲得一平坦拋光面作為該接合面71。 In the case where the circuit substrate 7 as a second substrate is to be produced, the film of the second electrode 67 can be similarly configured by CMP polishing using the diffusion preventing insulating film 69-2 as a stopper. Therefore, a flat polished surface can be similarly obtained as the joint surface 71.

因此，類似於上述第一實施例之製造方法，實施其中在總體面積上方將該接合面41與該接合面71連結在一起之接合，且可維持該感測器基板2與該電路基板7之間之接合強度。而且，可由相對於該電路基板7側之第二電極67之一擴散防止材料組態該感測器基板2側之擴散防止絕緣膜35- 2，且可由相對於該感測器基板2側之第一電極33之一擴散防止材料組態該電路基板7側之擴散防止絕緣膜69-2。因此，亦可防止該感測器基板2與該電路基板7之間之一電極材料之擴散。此外，該感測器基板2側之接合面41係僅由該第一電極33及該擴散防止絕緣膜35-2組態，且該電路基板7側之接合面71係僅由該第二電極67及該擴散防止絕緣膜69-2組態。因此，該接合面之組態得以簡化，且藉此亦可維持連結強度。 Therefore, similar to the manufacturing method of the first embodiment described above, the bonding in which the bonding surface 41 and the bonding surface 71 are joined together over the entire area is performed, and the sensor substrate 2 and the circuit substrate 7 can be maintained. Joint strength between. Moreover, the diffusion preventing insulating film 35 on the side of the sensor substrate 2 can be configured by diffusion preventing material with respect to one of the second electrodes 67 on the side of the circuit substrate 7. 2. The diffusion preventing insulating film 69-2 on the side of the circuit substrate 7 can be configured by a diffusion preventing material with respect to one of the first electrodes 33 on the side of the sensor substrate 2. Therefore, diffusion of one electrode material between the sensor substrate 2 and the circuit substrate 7 can also be prevented. In addition, the bonding surface 41 on the side of the sensor substrate 2 is configured only by the first electrode 33 and the diffusion preventing insulating film 35-2, and the bonding surface 71 on the side of the circuit substrate 7 is only the second electrode. 67 and the diffusion preventing insulating film 69-2 are configured. Therefore, the configuration of the joint surface is simplified, and thereby the joint strength can be maintained.

第二實施例 Second embodiment

<<1.第二實施例之半導體裝置之組態>> <<1. Configuration of Semiconductor Device of Second Embodiment>>

圖8展示根據本發明之一第二實施例之一半導體裝置之一部分截面組態。在下文中，參考圖8描述本實施例之半導體裝置之一詳細組態。 Figure 8 shows a partial cross-sectional configuration of a semiconductor device in accordance with a second embodiment of the present invention. Hereinafter, a detailed configuration of one of the semiconductor devices of the present embodiment will be described with reference to FIG.

圖8中所示之半導體裝置301係三維結構之一固態影像擷取裝置，其中一第一基板302與一第二基板307彼此接合使得該第一基板302之一接合面341與該第二基板307之一接合面371以一彼此相對關係安置，安置的狀態為一絕緣薄膜312夾置在該接合面341與該接合面371之間。在本實施例中，該半導體裝置301之特性在於該第一基板302與該第二基板307彼此接合，其中該絕緣薄膜312內插於其等之間之結構。 The semiconductor device 301 shown in FIG. 8 is a solid-state image capturing device of a three-dimensional structure in which a first substrate 302 and a second substrate 307 are bonded to each other such that one of the first substrate 302 is bonded to the surface 341 and the second substrate. One of the joint faces 371 of the 307 is disposed in an opposing relationship with each other in a state in which an insulating film 312 is interposed between the joint face 341 and the joint face 371. In the present embodiment, the semiconductor device 301 is characterized in that the first substrate 302 and the second substrate 307 are bonded to each other, and the insulating film 312 is interposed between the structures thereof.

該第一基板302包含自與該第二基板307相對之側按順序層壓之一半導體層302a、一配接線層302b及一電極層302c。該電極層302c之表面組態為至該第二基板307之一 接合面341。同時，該第二基板307包含自與該第一基板302相對之側按順序層壓之一半導體層307a、一配接線層307b及一電極層307c。該電極層307c之表面組態為至該第一基板302之一接合面371。 The first substrate 302 includes a semiconductor layer 302a, a wiring layer 302b and an electrode layer 302c laminated in this order from the side opposite to the second substrate 307. The surface of the electrode layer 302c is configured to be one of the second substrates 307 Joint surface 341. At the same time, the second substrate 307 includes a semiconductor layer 307a, a wiring layer 307b and an electrode layer 307c laminated in this order from the side opposite to the first substrate 302. The surface of the electrode layer 307c is configured to be one of the bonding faces 371 of the first substrate 302.

在該第一基板302在與該第二基板307相對之側上之面上，按如圖8中所示之順序層壓一保護膜315、一彩色濾光片層317及晶片上透鏡319。 On the surface of the first substrate 302 on the side opposite to the second substrate 307, a protective film 315, a color filter layer 317 and an on-wafer lens 319 are laminated in the order shown in FIG.

現在，相繼描述組態該第一基板302及該第二基板307及該絕緣薄膜312之層之一詳細組態，且接著相繼描述該保護膜315、該彩色濾光片層317及該等晶片上透鏡319之一組態。 Now, a detailed configuration of one of the layers of the first substrate 302 and the second substrate 307 and the insulating film 312 is successively described, and then the protective film 315, the color filter layer 317, and the like are sequentially described. One of the upper lenses 319 is configured.

[半導體層302a(第一基板302側)] [Semiconductor layer 302a (first substrate 302 side)]

一第一基板302之半導體層302a係由(例如)單晶矽製成之半導體基板320之一薄膜。在上面安置該彩色濾光片層317、晶片上透鏡319等等之半導體層302a之第一正面上，對每一像素設置由(例如)一n型雜質或一p型雜質形成之一光電轉換部分321。同時，在該半導體層302a之第二面上，設置一浮動擴散區FD及由一n+型雜質層以及未展示之其他雜質層等等形成之一電晶體Tr之一源極/汲極區域323。 The semiconductor layer 302a of a first substrate 302 is a thin film of a semiconductor substrate 320 made of, for example, single crystal germanium. On the first front surface of the semiconductor layer 302a on which the color filter layer 317, the on-wafer lens 319, and the like are disposed, one photoelectric conversion is formed for each pixel by, for example, an n-type impurity or a p-type impurity. Part 321. Meanwhile, on the second surface of the semiconductor layer 302a, a floating diffusion region FD and a source/drain region 323 of one of the transistors Tr are formed by an n+ type impurity layer and other impurity layers not shown. .

[配接線層302b(第一基板302側)] [Distribution layer 302b (on the side of the first substrate 302)]

設置在該第一基板302之半導體層302a上之配接線層302b在其與半導體層302a的介面側上具有該電晶體Tr之一轉移閘極TG及一閘極電極327以及未展示之其他電極，其 等設置為一閘極絕緣膜325內插於該配接線層302b與該半導體層302a之間。該轉移閘極TG及該閘極電極327覆蓋有一層間絕緣膜329，且在該層間絕緣膜329上形成之一溝槽圖案中設置一嵌入式配接線331。該嵌入式配接線331係由覆蓋該溝槽圖案之內壁之一障壁金屬層331a及由銅(Cu)製成且嵌入該溝槽圖案中之一配接線層331b組態，其中該障壁金屬層331a內插於該嵌入式配接線331與該配接線層331b之間。 The wiring layer 302b disposed on the semiconductor layer 302a of the first substrate 302 has a transfer gate TG and a gate electrode 327 and other electrodes not shown on the interface side of the semiconductor layer 302a. ,its A gate insulating film 325 is interposed between the wiring layer 302b and the semiconductor layer 302a. The transfer gate TG and the gate electrode 327 are covered with an interlayer insulating film 329, and an embedded wiring 331 is disposed in a trench pattern formed on the interlayer insulating film 329. The embedded wiring 331 is configured by a barrier metal layer 331a covering an inner wall of the trench pattern and a wiring layer 331b made of copper (Cu) and embedded in the trench pattern, wherein the barrier metal The layer 331a is interposed between the embedded wiring 331 and the wiring layer 331b.

應注意，如上所述之此一配接線層302b可進一步組態為一層壓多層配接線層。 It should be noted that the wiring layer 302b as described above may be further configured as a laminated multilayer wiring layer.

[電極層302c(第一基板302側)] [Electrode layer 302c (first substrate 302 side)]

設置在該第一基板302之配接線層302b上之電極層302c在與該配接線層302b的介面側上包含銅(Cu)之一擴散防止絕緣膜332及層壓在該擴散防止絕緣膜332上之一第一絕緣膜335。該第一絕緣膜335係由(例如)一TEOS膜形成，且在形成於該第一絕緣膜335上之溝槽圖案中設置一第一電極333作為一嵌入式電極。應注意，該TEOS膜係藉由一化學氣相沈積方法(在下文稱為CVD方法)形成之氧化矽膜，其中TEOS氣體(正矽酸乙酯氣體：組合物Si(OC2H5)4)用作源氣體。該第一電極333係由覆蓋該溝槽圖案之內壁之一障壁金屬層333a及由銅(Cu)製成且嵌入該溝槽圖案中之一第一電極膜333b組態，其中該障壁金屬層333a內插於該第一電極膜333b與該溝槽圖案之間。 The electrode layer 302c provided on the wiring layer 302b of the first substrate 302 includes a diffusion preventing insulating film 332 of copper (Cu) on the interface side with the wiring layer 302b and laminated on the diffusion preventing insulating film 332. One of the first first insulating films 335. The first insulating film 335 is formed of, for example, a TEOS film, and a first electrode 333 is disposed as an embedded electrode in the trench pattern formed on the first insulating film 335. It should be noted that the TEOS film is a ruthenium oxide film formed by a chemical vapor deposition method (hereinafter referred to as a CVD method), wherein TEOS gas (ethyl decanoate gas: composition Si(OC 2 H 5 ) 4 ) used as a source gas. The first electrode 333 is configured by a barrier metal layer 333a covering an inner wall of the trench pattern and a first electrode film 333b made of copper (Cu) and embedded in the trench pattern, wherein the barrier metal The layer 333a is interposed between the first electrode film 333b and the trench pattern.

具有如上所述之此一組態之電極層302c之表面被用作該 第一基板302側上至該第二基板307之一接合面。該接合面341經組態使得該第一電極333及該第一絕緣膜335曝露於該接合面341且處於藉由(例如)化學機械拋光(在下文中稱為CMP)平坦化之狀態。 The surface of the electrode layer 302c having such a configuration as described above is used as the One side of the first substrate 302 is bonded to one of the second substrates 307. The bonding surface 341 is configured such that the first electrode 333 and the first insulating film 335 are exposed to the bonding surface 341 and are in a state of being planarized by, for example, chemical mechanical polishing (hereinafter referred to as CMP).

應注意，雖然圖8中未展示，但是設置在該第一絕緣膜335中之溝槽圖案部分延伸至設置在該配接線層302b中之嵌入式配接線331，且按場合需求嵌入該溝槽圖案中之第一電極333處於連接至該嵌入式配接線331之一狀態。 It should be noted that although not shown in FIG. 8, the groove pattern portion disposed in the first insulating film 335 extends to the embedded wiring 331 disposed in the wiring layer 302b, and is embedded in the trench as occasion demands. The first electrode 333 in the pattern is in a state of being connected to one of the embedded wiring wires 331.

[半導體層307a(第二基板307側)] [Semiconductor layer 307a (second substrate 307 side)]

同時，該第二基板307之半導體層307a係由一半導體基板350之一薄膜形成，該半導體基板350由(例如)單晶矽製成。在該半導體層307a在第一基板302側上之表面層上，設置該電晶體Tr之一源極/汲極351及未展示之雜質層。 Meanwhile, the semiconductor layer 307a of the second substrate 307 is formed of a thin film of a semiconductor substrate 350 made of, for example, a single crystal germanium. On the surface layer of the semiconductor layer 307a on the side of the first substrate 302, one source/drain 351 of the transistor Tr and an impurity layer not shown are provided.

[配接線層307b(第二基板307側)] [Distribution wiring layer 307b (second substrate 307 side)]

設置在該第二基板307之半導體層307a上之配接線層307b在與該半導體層307a之介面側上具有具備內插於該半導體層307a與該配接線層307b之間之一閘極絕緣膜353之一閘極電極355及未展示之其他電極。該閘極電極355及該等其他電極覆蓋有一層間絕緣膜357，且在形成在該層間絕緣膜357上之一溝槽圖案中設置一嵌入式配接線359。該嵌入式配接線359係由覆蓋該溝槽圖案之內壁之一障壁金屬層359a及由銅(Cu)製成且嵌入該溝槽圖案中之一配接線層359b組態，其中該障壁金屬層359a內插於該配接線層359b與該溝槽圖案之間。 The wiring layer 307b disposed on the semiconductor layer 307a of the second substrate 307 has a gate insulating film interposed between the semiconductor layer 307a and the wiring layer 307b on the interface side with the semiconductor layer 307a. One of the gate electrodes 355 and other electrodes not shown. The gate electrode 355 and the other electrodes are covered with an interlayer insulating film 357, and an embedded wiring 359 is disposed in a trench pattern formed on the interlayer insulating film 357. The embedded wiring 359 is configured by a barrier metal layer 359a covering an inner wall of the trench pattern and a wiring layer 359b made of copper (Cu) and embedded in the trench pattern, wherein the barrier metal A layer 359a is interposed between the wiring layer 359b and the trench pattern.

應注意，如上所述之此一配接線層307b可具有一多層配接線層結構。 It should be noted that the wiring layer 307b as described above may have a multilayer wiring layer structure.

[電極層307c(第二基板307側)] [Electrode layer 307c (second substrate 307 side)]

設置在該第二基板307之配接線層307b上之電極層307c在其與該配接線層307b之介面側上包含相對於銅(Cu)之一擴散防止絕緣膜361及層壓在該擴散防止絕緣膜361上之一第二絕緣膜369。該第二絕緣膜369係由(例如)一TEOS膜形成，且在形成於該第二絕緣膜369中之一溝槽圖案中設置一第二電極367作為一嵌入式電極。該第二電極367係由覆蓋該溝槽圖案之內壁之一障壁金屬層367a及由銅(Cu)製成且嵌入該溝槽圖案中之一第二電極膜367b組態，其中該障壁金屬層367a內插於該溝槽圖案與該第二電極膜367b之間。該第二電極367經安置以對應於該第一基板302側之第一電極333且電連接至該第一基板302側上之第一電極333，其中絕緣薄膜312內插於該第一電極333與該該第二電極367之間 The electrode layer 307c disposed on the wiring layer 307b of the second substrate 307 includes a diffusion preventing insulating film 361 with respect to copper (Cu) on the interface side with the wiring layer 307b and laminated on the diffusion prevention A second insulating film 369 on the insulating film 361. The second insulating film 369 is formed of, for example, a TEOS film, and a second electrode 367 is disposed as an embedded electrode in one of the trench patterns formed in the second insulating film 369. The second electrode 367 is configured by a barrier metal layer 367a covering an inner wall of the trench pattern and a second electrode film 367b made of copper (Cu) and embedded in the trench pattern, wherein the barrier metal A layer 367a is interposed between the trench pattern and the second electrode film 367b. The second electrode 367 is disposed to correspond to the first electrode 333 on the first substrate 302 side and is electrically connected to the first electrode 333 on the first substrate 302 side, wherein the insulating film 312 is interposed in the first electrode 333 Between the second electrode 367

如上所述之此一電極層307c之表面形成為該第二基板307上至該第一基板302之接合面371。該接合面371經組態使得該第二電極367及該第二絕緣膜369曝露於該接合面371且該接合面371處於藉由(例如)CMP平坦化之一狀態。 The surface of the electrode layer 307c as described above is formed as a joint surface 371 of the second substrate 307 to the first substrate 302. The bonding surface 371 is configured such that the second electrode 367 and the second insulating film 369 are exposed to the bonding surface 371 and the bonding surface 371 is in a state of being planarized by, for example, CMP.

[絕緣薄膜312] [Insulating film 312]

該絕緣薄膜312夾置在該第一基板302側之接合面341與該第二基板307側之接合面371之間，且覆蓋該接合面341及該接合面371之總體面積。換言之，該第一基板302與該 第二基板307彼此接合，其中該絕緣薄膜312內插於其等之間。 The insulating film 312 is interposed between the bonding surface 341 on the first substrate 302 side and the bonding surface 371 on the second substrate 307 side, and covers the entire area of the bonding surface 341 and the bonding surface 371. In other words, the first substrate 302 and the The second substrates 307 are bonded to each other with the insulating film 312 interposed therebetween or the like.

如上所述之此一絕緣薄膜312係由(例如)氧化物膜及氮化物膜形成，且該絕緣薄膜312使用半導體普遍使用的氧化物膜及氮化物膜。在下文中，詳細描述該絕緣薄膜312之一組份材料。 The insulating film 312 as described above is formed of, for example, an oxide film and a nitride film, and the insulating film 312 uses an oxide film and a nitride film which are commonly used in semiconductors. Hereinafter, one component material of the insulating film 312 will be described in detail.

在其中該絕緣薄膜312係由氧化物膜形成之情況中，使用(例如)氧化矽(SiO2)或氧化鉿(HfO2)。在其中該絕緣薄膜312係由氧化物膜形成且該第一電極333及該第二電極367係由銅(Cu)製成之情況中，作為用於該第一電極333及該第二電極367之一電極材料之銅(Cu)易於擴散至該絕緣薄膜312中。因為該絕緣薄膜312之電阻隨著銅(Cu)之此擴散而降低，所以該第一電極333與該第二電極367(其中該絕緣薄膜312內插於其等之間)之間之介電質增強。因此，在其中該絕緣薄膜312係由氧化物膜形成之情況中，可形成相當厚之絕緣薄膜312。 In the case where the insulating film 312 is formed of an oxide film, for example, cerium oxide (SiO 2 ) or cerium oxide (HfO 2 ) is used. In the case where the insulating film 312 is formed of an oxide film and the first electrode 333 and the second electrode 367 are made of copper (Cu), as the first electrode 333 and the second electrode 367 Copper (Cu) of one of the electrode materials is easily diffused into the insulating film 312. Since the resistance of the insulating film 312 decreases as the copper (Cu) diffuses, the dielectric between the first electrode 333 and the second electrode 367 (where the insulating film 312 is interposed between them) Enhanced. Therefore, in the case where the insulating film 312 is formed of an oxide film, a relatively thick insulating film 312 can be formed.

在其中該絕緣薄膜312係由氮化物膜形成之情況中，使用(例如)氮化矽(SiN)。相對於該第一電極333及該第二電極367，由氮化物膜形成之絕緣薄膜312具有一擴散防止性質。 In the case where the insulating film 312 is formed of a nitride film, for example, tantalum nitride (SiN) is used. The insulating film 312 formed of a nitride film has a diffusion preventing property with respect to the first electrode 333 and the second electrode 367.

因此，在相同基板內，可防止出現在相同基板之電極之間之洩漏電流穿過該絕緣薄膜312。換言之，在該第一基板302中，可防止出現在相鄰第一電極333之間之洩漏電流穿過該絕緣薄膜312。類似地，在該第二基板307中，可防 止出現在相鄰第二電極367之間之洩漏電流穿過該絕緣薄膜312。 Therefore, leakage currents between the electrodes of the same substrate can be prevented from passing through the insulating film 312 in the same substrate. In other words, in the first substrate 302, leakage current occurring between adjacent first electrodes 333 can be prevented from passing through the insulating film 312. Similarly, in the second substrate 307, it is preventable Leakage currents occurring between adjacent second electrodes 367 pass through the insulating film 312.

另一方面，在不同基板之間，可防止一電極材料擴散至相對電極側上之一絕緣膜中。換言之，可防止該第一基板302側上之第一電極333擴散至該相對第二基板307側上之第二絕緣膜369中。類似地，可防止該第二基板307側上之第二電極367擴散至該相對第一基板302側上之第一絕緣膜335中。因此，無需在曝露一絕緣膜之基板之接合面之各者之一部分處設置由相對於相對電極側之一電極之一擴散防止材料製成之一障壁膜。 On the other hand, between the different substrates, it is possible to prevent an electrode material from diffusing into one of the insulating films on the opposite electrode side. In other words, the first electrode 333 on the side of the first substrate 302 can be prevented from diffusing into the second insulating film 369 on the side opposite to the second substrate 307. Similarly, the second electrode 367 on the side of the second substrate 307 can be prevented from diffusing into the first insulating film 335 on the side opposite to the first substrate 302. Therefore, it is not necessary to provide a barrier film made of a diffusion preventing material with respect to one of the electrodes on the opposite electrode side at a portion of each of the bonding faces of the substrate on which the insulating film is exposed.

進一步言之，特別係在本實施例中，重要的是該第一基板302側之第一電極333及該第二基板307側之第二電極367彼此電連接，其中該絕緣薄膜312內插於該第一電極333與該第二電極367之間。因此，該絕緣薄膜312之厚度極小。該絕緣薄膜312之膜厚度取決於該絕緣薄膜312之材料而不同且例如就諸如氧化矽(SiO2)及氧化鉿(HfO2)之氧化物及幾乎全部其他材料而言厚度等於或小於約2奈米。然而，取決於該絕緣薄膜312之膜品質，可使用一更厚的膜。在以一相對關係安置之第一電極333與第二電極367(其中該絕緣薄膜312內插於其等之間)之間，隧道電流流動。進一步言之，若施加等於或高於一固定位準之一電壓以引起崩潰，則該第一電極333及該第二電極367相互之間被置於一完全導電狀態中且流動在其等之間電流。 Further, in this embodiment, it is important that the first electrode 333 on the first substrate 302 side and the second electrode 367 on the second substrate 307 side are electrically connected to each other, wherein the insulating film 312 is interposed The first electrode 333 is between the second electrode 367 and the second electrode 367. Therefore, the thickness of the insulating film 312 is extremely small. The film thickness of the insulating film 312 varies depending on the material of the insulating film 312 and is, for example, equal to or less than about 2 for an oxide such as yttrium oxide (SiO 2 ) and hafnium oxide (HfO 2 ) and almost all other materials. Nano. However, depending on the film quality of the insulating film 312, a thicker film can be used. A tunnel current flows between the first electrode 333 and the second electrode 367 (wherein the insulating film 312 is interposed between them) disposed in an opposing relationship. Further, if a voltage equal to or higher than a fixed level is applied to cause a collapse, the first electrode 333 and the second electrode 367 are placed in a fully conductive state and flow in each other. Current.

應注意，在本實施例之半導體裝置301中，該絕緣薄膜 312不一定具有上述一單層結構但可具有相同材料之一層壓結構或不同材料之一層壓結構。 It should be noted that in the semiconductor device 301 of the present embodiment, the insulating film 312 does not necessarily have the above-described single layer structure but may have one laminate structure of the same material or one laminate structure of different materials.

[保護膜315、彩色濾光片層317及晶片上透鏡319] [Protective film 315, color filter layer 317, and on-wafer lens 319]

該保護膜315經設置覆蓋該第一基板302之光電轉換部分321。該保護膜315係由具有一鈍化性質之一材料膜組態，且該保護膜315使用(例如)氧化矽膜、氮化矽膜、氮氧化矽膜或一類似膜。 The protective film 315 is disposed to cover the photoelectric conversion portion 321 of the first substrate 302. The protective film 315 is configured by a material film having a passivation property, and the protective film 315 uses, for example, a hafnium oxide film, a tantalum nitride film, a hafnium oxynitride film, or the like.

該彩色濾光片層317係由以與該等光電轉換部分321之逐一對應關係設置之不同色彩之彩色濾光片組態。該等色彩之彩色濾光片之陣列並無特別限制。 The color filter layer 317 is configured by color filters of different colors set in a one-to-one correspondence with the photoelectric conversion portions 321 . The array of color filters of these colors is not particularly limited.

該等晶片上透鏡319係以與該等光電轉換部分321及組態該彩色濾光片層317之不同色彩之彩色濾光片之逐一對應關係設置且經組態使得入射光聚集在該等光電轉換部分321處。 The on-wafer lens 319 is disposed in a one-to-one correspondence with the photoelectric conversion portions 321 and color filters of different colors configuring the color filter layer 317, and is configured such that incident light is concentrated on the photoelectric The conversion portion 321 is located.

[本實施例之半導體裝置之組態之效果] [Effect of Configuration of Semiconductor Device of the Present Embodiment]

在以如上所述之此一方式組態之本實施例之半導體裝置301中，因為該第一基板302與該第二基板307如圖8中所示般彼此接合，其中該絕緣薄膜312內插於其等之間，所以該第一基板302之接合面341與該第二基板307之接合面371並未彼此直接接觸。因此，防止在其中該等基板之接合面彼此直接連結之組態中沿連結介面產生通常產生之空隙。因此，運用該半導體裝置，該兩個基板之間之連結強度增加並達成可靠性之增強。 In the semiconductor device 301 of the present embodiment configured in such a manner as described above, since the first substrate 302 and the second substrate 307 are bonded to each other as shown in FIG. 8, the insulating film 312 is interposed. Between the two, the bonding surface 341 of the first substrate 302 and the bonding surface 371 of the second substrate 307 are not in direct contact with each other. Therefore, it is prevented that a commonly generated void is generated along the joint interface in a configuration in which the joint faces of the substrates are directly joined to each other. Therefore, with the semiconductor device, the connection strength between the two substrates is increased and the reliability is enhanced.

特別係在其中該第一絕緣膜335及該第二絕緣膜369係由 一TEOS膜形成之情況中，因為該TEOS膜之表面上存在許多OH基團，所以沿連結介面藉由脫水縮合產生空隙，各呈一TEOS膜接觸件之形式之絕緣膜沿該連結介面彼此直接連結。而且在其中一絕緣膜係一TEOS膜之情況中，因為在本實施例之半導體裝置301中基板彼此接合，其中該絕緣薄膜312內插於該等基板之間，所以該等TEOS膜未彼此直接連結且可防止藉由脫水縮合產生空隙。因此，運用該半導體裝置，該兩個基板之間之連結強度增加並達成可靠性之增強。 Specifically, the first insulating film 335 and the second insulating film 369 are In the case of forming a TEOS film, since many OH groups are present on the surface of the TEOS film, voids are generated by dehydration condensation along the bonding interface, and the insulating films each in the form of a TEOS film contact are directly adjacent to each other along the bonding interface. link. Further, in the case where one of the insulating films is a TEOS film, since the substrates are bonded to each other in the semiconductor device 301 of the present embodiment, wherein the insulating film 312 is interposed between the substrates, the TEOS films are not directly adjacent to each other. It is linked and prevents voids from being generated by dehydration condensation. Therefore, with the semiconductor device, the connection strength between the two substrates is increased and the reliability is enhanced.

<<2.第二實施例之半導體裝置之製造中該第一基板(感測器基板)之製造程序>> <<2. Manufacturing Procedure of the First Substrate (Sensor Substrate) in Manufacturing of Semiconductor Device of Second Embodiment>>

圖9A至圖9E圖解說明與該第二實施例之半導體裝置之製造一起使用之一第一基板302之一製造程序。在下文中，參考圖9A至圖9E描述作為本實施例中使用之一感測器基板之第一基板302之一製造程序。 9A to 9E illustrate a manufacturing procedure of one of the first substrates 302 used in conjunction with the manufacture of the semiconductor device of the second embodiment. Hereinafter, a manufacturing procedure of one of the first substrates 302 as one of the sensor substrates used in the present embodiment will be described with reference to FIGS. 9A to 9E.

如圖9A中所示，製備由(例如)單晶矽製成之一半導體基板320。在該半導體基板320之一預定深度處形成由一n型雜質層製成之一光電轉換部分321，且接著在該光電轉換部分321之一表面層上形成由一n+型雜質層形成之一電荷轉移部分及用於電洞之由一p+型雜質層形成之一電荷累積部分。在該半導體基板320之表面層上針對每一像素形成一浮動擴散區FD、一源極/汲極323及由一n+型雜質層形成之未展示之一進一步雜質層。 As shown in FIG. 9A, a semiconductor substrate 320 made of, for example, single crystal germanium is prepared. One photoelectric conversion portion 321 made of an n-type impurity layer is formed at a predetermined depth of one of the semiconductor substrates 320, and then a charge formed by an n + -type impurity layer is formed on one surface layer of the photoelectric conversion portion 321 The transfer portion and a charge accumulation portion formed by a p + -type impurity layer for the hole are formed. A floating diffusion FD, a source/drain 323, and a further impurity layer not formed by an n+-type impurity layer are formed on the surface layer of the semiconductor substrate 320 for each pixel.

接著，在該半導體基板320之表面上形成一閘極絕緣膜 325，且在該閘極絕緣膜325上形成一轉移閘極TG及一閘極電極327。該轉移閘極TG係形成於該浮動擴散區FD與該光電轉換部分321之間，且該閘極電極327係形成於該源極/汲極323之間。進一步言之，在相同步驟處，亦形成未展示之其他電極。 Next, a gate insulating film is formed on the surface of the semiconductor substrate 320. 325, and a transfer gate TG and a gate electrode 327 are formed on the gate insulating film 325. The transfer gate TG is formed between the floating diffusion FD and the photoelectric conversion portion 321, and the gate electrode 327 is formed between the source/drain 323. Further, at the same step, other electrodes not shown are also formed.

應注意，上述步驟可在經適當選擇之一普通製造程序中實施。 It should be noted that the above steps can be carried out in a conventional manufacturing process suitably selected.

此後，在閘極絕緣膜325上形成由(例如)氧化矽製成之一層間絕緣膜329，形成的狀態為該層間絕緣膜329覆蓋該等轉移閘極TG及該等閘極電極327。進一步言之，針對每一像素，在該層間絕緣膜329中形成一溝槽圖案，且在該溝槽圖案中形成其中嵌入一配接線層331b之一嵌入式配接線331，其中一障壁金屬層331a內插於該嵌入式配接線331與該配接線層331b之間。該等嵌入式配接線331經形成使得其等在必要位置處連接至該等轉移閘極TG。進一步言之，雖然未展示，但是一些嵌入式配接線331被形成為接觸該等源極/汲極23。因此，獲得包含該等嵌入式配接線331之一配接線層302b。應注意，為形成該等嵌入式配接線331，應用下文參考圖9B描述之一嵌入式佈線技術等等。 Thereafter, an interlayer insulating film 329 made of, for example, ytterbium oxide is formed on the gate insulating film 325 in a state in which the interlayer insulating film 329 covers the transfer gates TG and the gate electrodes 327. Further, for each pixel, a trench pattern is formed in the interlayer insulating film 329, and an embedded wiring 331 in which a wiring layer 331b is embedded is formed in the trench pattern, wherein a barrier metal layer The 331a is interposed between the embedded wiring 331 and the wiring layer 331b. The embedded mating wires 331 are formed such that they are connected to the transfer gates TG at necessary locations. Further, although not shown, some of the embedded wirings 331 are formed to contact the source/drain electrodes 23. Therefore, a wiring layer 302b including one of the embedded wirings 331 is obtained. It should be noted that in order to form the embedded wiring 331, an embedded wiring technique or the like described below with reference to FIG. 9B is applied.

接著，在該配接線層302b上形成一擴散防止絕緣膜332，且在該擴散防止絕緣膜332上形成一第一絕緣膜335。例如，應用其中使用正矽酸乙酯(TEOS)氣體之一CVD方法以形成由一TEOS膜形成之第一絕緣膜335。此 後，應用下文描述之一嵌入式佈線技術在該第一絕緣膜335上形成第一電極333。 Next, a diffusion preventing insulating film 332 is formed on the wiring layer 302b, and a first insulating film 335 is formed on the diffusion preventing insulating film 332. For example, a CVD method in which a tetraethyl orthosilicate (TEOS) gas is used to form a first insulating film 335 formed of a TEOS film is applied. this Thereafter, the first electrode 333 is formed on the first insulating film 335 by applying one of the embedded wiring techniques described below.

如圖9B中所示，針對每一像素在第一絕緣膜335上形成一溝槽圖案335a。雖然未展示，但是該溝槽圖案335a經形成呈其中其在一必要位置處延伸至該嵌入式配接線331之一形狀。 As shown in FIG. 9B, a groove pattern 335a is formed on the first insulating film 335 for each pixel. Although not shown, the trench pattern 335a is formed in a shape in which it extends to a position of the embedded wiring 331 at a necessary position.

如圖9C中所示，形成一障壁金屬層333a，形成的狀態為該障壁金屬層333a覆蓋該溝槽圖案335a之內壁，且在該障壁金屬層333a上形成一第一電極膜333b，形成的狀態為該第一電極膜333b中嵌入該溝槽圖案335a。該障壁金屬層333a係由具有該第一電極膜333b擴散至該第一絕緣膜335中之一障壁性質之一材料組態，同時該第一電極膜333b係由銅(Cu)製成。然而，該第一電極膜333b之材料並不限於此，但是該第一電極膜333b可由一導電材料組態。 As shown in FIG. 9C, a barrier metal layer 333a is formed in a state in which the barrier metal layer 333a covers the inner wall of the trench pattern 335a, and a first electrode film 333b is formed on the barrier metal layer 333a to form a first electrode film 333b. The state is that the groove pattern 335a is embedded in the first electrode film 333b. The barrier metal layer 333a is configured by one material having one of the barrier properties of the first electrode film 333b diffused into the first insulating film 335, and the first electrode film 333b is made of copper (Cu). However, the material of the first electrode film 333b is not limited thereto, but the first electrode film 333b may be configured by a conductive material.

如圖9D中所示，藉由一CMP平坦化並移除該第一電極膜333b直到曝露該障壁金屬層333a，且平坦化並移除該障壁金屬層333a直到曝露該第一絕緣膜335。藉此，在該溝槽圖案335a中形成其中嵌入該第一電極膜333b之第一電極333，其中該障壁金屬層333a內插於該第一電極333與該第一電極膜333b之間。因此，獲得包含該等第一電極333之一電極層302c。 As shown in FIG. 9D, the first electrode film 333b is planarized and removed by a CMP until the barrier metal layer 333a is exposed, and the barrier metal layer 333a is planarized and removed until the first insulating film 335 is exposed. Thereby, the first electrode 333 in which the first electrode film 333b is embedded is formed in the trench pattern 335a, wherein the barrier metal layer 333a is interposed between the first electrode 333 and the first electrode film 333b. Therefore, one electrode layer 302c including the first electrodes 333 is obtained.

藉由上述步驟，製造具有曝露該等第一電極333及該第一絕緣膜335之一平坦接合面341之第一基板302作為一感測器基板。應注意，按場合需要，藉由一濕式製程或一電 漿製程對該接合面341實施預處理。 Through the above steps, the first substrate 302 having the flat bonding surface 341 of the first electrode 333 and the first insulating film 335 is exposed as a sensor substrate. It should be noted that, depending on the occasion, by a wet process or an electric The bonding process is performed on the bonding surface 341.

前述步驟可按一普通步驟順序實施，且該步驟程序並無特別限制，但是該等步驟可按一合適順序實施。在本技術中，下文一絕緣薄膜之形成係一特性步驟。 The foregoing steps may be carried out in the order of a general step, and the step procedure is not particularly limited, but the steps may be carried out in an appropriate order. In the present technology, the formation of an insulating film is a characteristic step.

[絕緣薄膜之形成步驟] [Step of forming insulating film]

如圖9E中所示，藉由一原子層沈積方法(在下文稱為ALD方法)形成一絕緣薄膜312a，形成的狀態為該絕緣薄膜312a覆蓋該第一基板302之接合面341之總體面積。 As shown in FIG. 9E, an insulating film 312a is formed by an atomic layer deposition method (hereinafter referred to as an ALD method) in a state in which the insulating film 312a covers the entire area of the bonding surface 341 of the first substrate 302.

描述該ALD方法之一程序之一概述。 An overview of one of the programs describing this ALD method.

首先，製備含有待形成之一薄膜之組份元素之一第一反應物及一第二反應物。實施供應含有該第一反應物之氣體給一基板以使該基板吸收該氣體之一第一步驟及供應含有該第二反應物之氣體給該基板以使該基板吸收該氣體之一第二步驟作為一膜形成步驟。進一步言之，在該等步驟之間，供應惰性氣體以淨化未吸收的反應物。藉由實施該膜形成步驟持續一循環，累積一原子層，且藉由重複該膜形成循環，獲得一所要厚度之一膜。應注意，首先可實施該第一步驟及該第二步驟之任一者。 First, one of the component reactants containing a film to be formed and a second reactant are prepared. Performing a first step of supplying a gas containing the first reactant to a substrate to cause the substrate to absorb the gas, and supplying a gas containing the second reactant to the substrate to cause the substrate to absorb the gas. As a film forming step. Further, between the steps, an inert gas is supplied to purify the unabsorbed reactants. By performing the film formation step for one cycle, an atomic layer is accumulated, and by repeating the film formation cycle, a film of a desired thickness is obtained. It should be noted that either of the first step and the second step may be performed first.

如上所述之此一膜形成方法係該ALD方法且具有如下文所述之此等特性。 The film forming method as described above is the ALD method and has such characteristics as described below.

該ALD方法係重複該膜形成步驟之一循環以形成一膜之一方法。藉由調整循環次數，可實施一膜之形成，該膜之膜厚度被控制在以一原子層為一單位之一高精確度。若應用剛剛描述之此一ALD方法以形成該絕緣薄膜312a，則即 使該絕緣薄膜312a極薄，其亦可經形成具有高膜厚度可控性。 The ALD method is a method of repeating one of the film formation steps to form a film. By adjusting the number of cycles, a film formation can be carried out, and the film thickness of the film is controlled to be high precision with one atomic layer as a unit. If the ALD method just described is applied to form the insulating film 312a, then The insulating film 312a is made extremely thin, which can also be formed to have high film thickness controllability.

進一步言之，該ALD方法係可在低於約500℃之一溫度下藉由一低溫製程形成一膜之一方法。因為在形成該絕緣薄膜312a時已形成該電極層302c，所以考慮組態該電極層302c之一金屬之耐熱性質，且為形成該絕緣薄膜312a，要求一低溫製程。因此，若應用此一ALD方法以形成該絕緣薄膜312a，則可藉由該低溫製程形成該絕緣薄膜312a而不損害該電極層302c。 Further, the ALD method is one in which a film can be formed by a low temperature process at a temperature lower than about 500 °C. Since the electrode layer 302c has been formed when the insulating film 312a is formed, it is considered to configure the heat resistance of the metal of one of the electrode layers 302c, and in order to form the insulating film 312a, a low temperature process is required. Therefore, if the ALD method is applied to form the insulating film 312a, the insulating film 312a can be formed by the low temperature process without damaging the electrode layer 302c.

該ALD方法係逐層沈積原子層以形成如上所述之一膜之一方法。若應用此一ALD方法以形成該絕緣薄膜312a，則該接合面341之總體面積可覆蓋有該平坦且均勻絕緣薄膜312而未損害藉由CMP極度平坦化之基板表面之平坦度。 The ALD method is a method of depositing an atomic layer layer by layer to form one of the films as described above. If the ALD method is applied to form the insulating film 312a, the overall area of the bonding surface 341 can be covered with the flat and uniform insulating film 312 without impairing the flatness of the substrate surface which is extremely flattened by CMP.

在下文中，特別描述憑藉由氧化物膜或氮化物膜形成之絕緣薄膜312a之ALD方法之膜形成條件作為一實例。 Hereinafter, the film formation conditions of the ALD method based on the insulating film 312a formed of an oxide film or a nitride film are specifically described as an example.

在其中該絕緣薄膜312a係由諸如SiO2或HfO2之一膜之氧化物膜形成之情況中，在上述ALD方法中使用含有Si之反應物或含有Hf之反應物作為該第一反應物，同時使用含有O之反應物作為該第二反應物。交替地實施供應該等反應物以進行一吸收反應之步驟以在該接合面341上形成由SiO2或HfO2之氧化物膜形成之一絕緣薄膜312a。此處，使用可以諸如矽烷(SiH4)或二氯矽烷(H2SiCl2)之氣體之形式供應之一物質作為含有Si之反應物。使用四-(二甲胺基)-鉿(Hf[N(CH3)2]4)或類似物作為含有Hf之反應物。使用水 蒸氣氣體、臭氧氣體或類似物作為含有O之反應物。 In the case where the insulating film 312a is formed of an oxide film such as a film of SiO 2 or HfO 2 , a reactant containing Si or a reactant containing Hf is used as the first reactant in the above ALD method, The reactant containing O is simultaneously used as the second reactant. The step of supplying the reactants to perform an absorption reaction is alternately performed to form an insulating film 312a formed of an oxide film of SiO 2 or HfO 2 on the bonding face 341. Here, one substance is supplied as a reactant containing Si in the form of a gas such as decane (SiH 4 ) or dichlorosilane (H 2 SiCl 2 ). Tetrakis-(dimethylamino)-hydrazine (Hf[N(CH 3 ) 2 ] 4 ) or the like is used as a reactant containing Hf. A vapor gas, an ozone gas or the like is used as a reactant containing O.

另一方面，在其中該絕緣薄膜312a係由氮化物膜(SiN)或類似物形成之情況中，在上述ALD方法中使用含有Si之反應物作為該第一反應物，同時使用含有N之反應物作為該第二反應物。藉由交替重複供應此等反應物以進行一吸收反應之步驟，在該接合面341上形成由氮化物膜(SiN)形成之一絕緣薄膜312a。此處，使用(例如)氮氣、氨氣或類似物作為含有N之反應物。使用水蒸氣氣體、臭氧氣體或類似物作為含有O之反應物。 On the other hand, in the case where the insulating film 312a is formed of a nitride film (SiN) or the like, a reactant containing Si is used as the first reactant in the above ALD method, and a reaction containing N is used. As the second reactant. An insulating film 312a formed of a nitride film (SiN) is formed on the bonding surface 341 by alternately repeating the steps of supplying the reactants to perform an absorption reaction. Here, for example, nitrogen, ammonia or the like is used as the reactant containing N. A vapor gas, an ozone gas or the like is used as a reactant containing O.

藉由前述製程，在該第一基板302上形成一極薄且均勻的絕緣薄膜312a，形成的狀態為該絕緣薄膜312a覆蓋該接合面341之總體面積。 By the foregoing process, an extremely thin and uniform insulating film 312a is formed on the first substrate 302 in a state in which the insulating film 312a covers the entire area of the bonding surface 341.

<<3.第二實施例之半導體裝置之製造中該第二基板(電路基板)之製造程序>> <<3. Manufacturing procedure of the second substrate (circuit substrate) in the manufacture of the semiconductor device of the second embodiment>>

圖10A及圖10B圖解說明用於製造上述第二實施例之半導體裝置之一第二基板307之一製造程序。在下文中，參考圖10A及圖10B描述該第二實施例中使用之第二基板或電路基板307之一製造程序。 10A and 10B illustrate a manufacturing procedure of one of the second substrates 307 for fabricating the semiconductor device of the second embodiment described above. Hereinafter, a manufacturing procedure of one of the second substrate or circuit substrate 307 used in the second embodiment will be described with reference to FIGS. 10A and 10B.

如圖10A中所示，製備由(例如)單晶矽製成之一半導體基板350。在該半導體基板350之一表面層上針對每一像素形成個別導電型之源極/汲極351及未展示之其他雜質層。藉此獲得一半導體層307a。 As shown in FIG. 10A, a semiconductor substrate 350 made of, for example, single crystal germanium is prepared. A source/drain 351 of an individual conductivity type and other impurity layers not shown are formed for each pixel on one surface layer of the semiconductor substrate 350. Thereby, a semiconductor layer 307a is obtained.

接著，在該半導體層307a上形成一閘極絕緣膜353，且在該閘極絕緣膜353上形成一閘極電極355。該閘極電極 355形成於該源極/汲極351之間。進一步言之，在相同步驟處，形成未展示之其他電極。 Next, a gate insulating film 353 is formed on the semiconductor layer 307a, and a gate electrode 355 is formed on the gate insulating film 353. The gate electrode 355 is formed between the source/drain 351. Further, at the same step, other electrodes not shown are formed.

接著，在該閘極絕緣膜353上形成由(例如)氧化矽製成之一層間絕緣膜357，形成的狀態為該層間絕緣膜357覆蓋該閘極電極355。在該層間絕緣膜357之溝槽圖案中形成其中嵌入一配接線層359b之一嵌入式配接線359(其中一障壁金屬層359a內插於該嵌入式配接線359與該配接線層359b之間)以獲得包含該嵌入式配接線359之一配接線層307b。類似於上述第一電極333之形成應用該嵌入式佈線技術在此處實施該嵌入式配接線359之形成。 Next, an interlayer insulating film 357 made of, for example, ytterbium oxide is formed on the gate insulating film 353 in a state in which the interlayer insulating film 357 covers the gate electrode 355. An embedded wiring 359 in which a wiring layer 359b is embedded is formed in the trench pattern of the interlayer insulating film 357 (a barrier metal layer 359a is interposed between the embedded wiring 359 and the wiring layer 359b) A wiring layer 307b including one of the embedded wirings 359 is obtained. The formation of the embedded wiring 359 is implemented here similarly to the formation of the first electrode 333 described above using the embedded wiring technique.

此後，沈積由(例如)一TEOS膜形成之一第二絕緣膜369以在該配接線層307b上形成一膜，其中一擴散防止絕緣層361內插於其等之間。因此，在該第二絕緣膜369之每一溝槽圖案中形成其中嵌入一第二電極膜367b之一第二電極367(其中一障壁金屬層367a內插於該第二電極367與該第二電極膜367b之間)，藉此以獲得包含該第二電極367之一電極層307c。類似於上述第一電極333之形成在此處實施該第二電極367之形成。 Thereafter, a second insulating film 369 is formed by, for example, a TEOS film to form a film on the wiring layer 307b, and a diffusion preventing insulating layer 361 is interposed between them. Therefore, a second electrode 367 in which a second electrode film 367b is embedded is formed in each of the trench patterns of the second insulating film 369 (wherein a barrier metal layer 367a is interposed in the second electrode 367 and the second Between the electrode films 367b), thereby obtaining an electrode layer 307c including the second electrode 367. The formation of the second electrode 367 is performed here similarly to the formation of the first electrode 333 described above.

藉由上述步驟，製造具有曝露該第二電極367及該第二絕緣膜369之一平坦接合面371之一第二基板307作為一電路基板。 By the above steps, the second substrate 307 having one of the flat bonding faces 371 of the second electrode 367 and the second insulating film 369 is exposed as a circuit substrate.

上述步驟可以一普通步驟程序實施，且該步驟程序並不限於一特殊步驟程序，且該等步驟可以一合適程序實施。在本技術中，下文描述之一絕緣薄膜之形成及基板之接合 係特性步驟。 The above steps can be carried out in a general step procedure, and the step procedure is not limited to a special step procedure, and the steps can be implemented in a suitable procedure. In the present technology, the formation of an insulating film and the bonding of substrates are described below. The characteristic step.

如圖10B中所示，類似於在該第一基板302側上形成該絕緣薄膜312a，藉由一ALD方法在該接合面371上形成一絕緣薄膜312b。 As shown in FIG. 10B, an insulating film 312b is formed on the bonding surface 371 by an ALD method, similarly to the formation of the insulating film 312a on the side of the first substrate 302.

因此，在該第二基板307上形成該極薄且均勻絕緣薄膜312b，形成的狀態為該絕緣薄膜312b覆蓋該接合面371之總體面積。應注意，該絕緣薄膜312b可為與該第一基板302側上之絕緣薄膜312a相同或不同之一膜。 Therefore, the extremely thin and uniform insulating film 312b is formed on the second substrate 307 in a state in which the insulating film 312b covers the entire area of the bonding surface 371. It should be noted that the insulating film 312b may be the same or different film as the insulating film 312a on the side of the first substrate 302.

<<4.第二實施例之半導體裝置之製造中該等基板之接合程序>> <<4. Joining procedure of the substrates in the manufacture of the semiconductor device of the second embodiment>>

參考圖11A及圖11B描述其中在該接合面341上形成該絕緣薄膜312a之第一基板302與其中在該接合面371上形成該絕緣薄膜312b之第二基板307之一接合程序。 One of the joining procedures of the first substrate 302 in which the insulating film 312a is formed on the bonding surface 341 and the second substrate 307 in which the insulating film 312b is formed on the bonding surface 371 is described with reference to FIGS. 11A and 11B.

如圖11A中所示，該第一基板302之接合面341與該第二基板307之接合面371彼此以一相對關係安置，其中一絕緣薄膜內插於該接合面341與該接合面371之間，且接著該接合面341及該接合面371經定位使得該第一基板302之第一電極33與該第二基板307之第二電極367彼此對應。雖然所示之實例圖解說明其中該等第一電極333與該等第二電極以一1：1對應關係彼此對應之一狀態，但是該對應關係並不限於此。 As shown in FIG. 11A, the bonding surface 341 of the first substrate 302 and the bonding surface 371 of the second substrate 307 are disposed in an opposing relationship with each other, and an insulating film is interposed between the bonding surface 341 and the bonding surface 371. Then, the bonding surface 341 and the bonding surface 371 are positioned such that the first electrode 33 of the first substrate 302 and the second electrode 367 of the second substrate 307 correspond to each other. Although the illustrated example illustrates a state in which the first electrodes 333 and the second electrodes correspond to each other in a 1:1 correspondence relationship, the correspondence is not limited thereto.

如圖11B中所示，該第一基板302及該第二基板307在其中該第一基板302之絕緣薄膜312a與該第二基板307上之絕緣薄膜312b彼此相對之一狀態中經歷熱處理以使該絕緣薄 膜312a與該絕緣薄膜312b彼此連結。在對形成於該第一基板302及該第二基板307上之元件及配接線不具有影響之一範圍內在一溫度下實施此熱處理並持續足以容許該等絕緣薄膜312充分連結在一起的一段時間。 As shown in FIG. 11B, the first substrate 302 and the second substrate 307 are subjected to heat treatment in a state in which the insulating film 312a of the first substrate 302 and the insulating film 312b on the second substrate 307 are opposed to each other. The insulation thin The film 312a and the insulating film 312b are connected to each other. The heat treatment is performed at a temperature within a range that does not have an influence on the components and wirings formed on the first substrate 302 and the second substrate 307 and continues for a period of time sufficient to allow the insulating films 312 to be sufficiently joined together. .

例如，在其中使用含有銅(Cu)作為一主要組份之材料組態該等第一電極333及該等第二電極367之情況中，在200℃至600℃下實施熱處理持續約1小時至5小時。此熱處理可在一加壓氛圍下實施或可在其中該第一基板302與該第二基板307自其等相對正面彼此按壓之一狀態中實施。作為一實例，在400℃下實施熱處理持續4小時以實施該等第一電極333與該等第二電極367之間之連接，其中該等絕緣薄膜312內插於其等之間。因此，該絕緣薄膜312a與該絕緣薄膜312b連結在一起，同時該第一基板302與該第二基板307彼此接合。 For example, in the case where the first electrode 333 and the second electrode 367 are configured using a material containing copper (Cu) as a main component, heat treatment is performed at 200 ° C to 600 ° C for about 1 hour to 5 hours. This heat treatment may be performed under a pressurized atmosphere or may be performed in a state in which the first substrate 302 and the second substrate 307 are pressed against each other from their opposite front faces. As an example, the heat treatment is performed at 400 ° C for 4 hours to effect the connection between the first electrodes 333 and the second electrodes 367, wherein the insulating films 312 are interposed between them. Therefore, the insulating film 312a is bonded to the insulating film 312b while the first substrate 302 and the second substrate 307 are bonded to each other.

此處，如上所述，在其中該第一基板302及該第二基板307二者之接合面341及371上形成該等絕緣薄膜312a及312b之情況中，可由一相同材料或由彼此不同之材料組態該等絕緣薄膜312a及312b。 Here, as described above, in the case where the insulating films 312a and 312b are formed on the bonding faces 341 and 371 of the first substrate 302 and the second substrate 307, they may be made of the same material or different from each other. The materials are configured with the insulating films 312a and 312b.

應注意，在本實施例之半導體裝置之製造方法中，僅在該第一基板302及該第二基板307之一者之接合面上形成一絕緣薄膜。例如，可僅在該第一基板302之接合面341上形成該絕緣薄膜312a使得該第一基板302與該第二基板307藉由該第一基板302側之絕緣薄膜312a與該第二基板307側之接合面371之間之連結而彼此接合。 It should be noted that in the method of fabricating the semiconductor device of the present embodiment, an insulating film is formed only on the bonding surface of one of the first substrate 302 and the second substrate 307. For example, the insulating film 312a may be formed only on the bonding surface 341 of the first substrate 302 such that the first substrate 302 and the second substrate 307 are separated from the second substrate 307 by the insulating film 312a on the first substrate 302 side. The joints between the side joint faces 371 are joined to each other.

在該第一基板302與該第二基板307如上所述般彼此接合後，將該第一基板302側之半導體基板320薄化成該半導體層302a中以曝露該光電轉換部分321。進一步言之，按場合需求，可在該第二基板307側之半導體層307a上薄化該半導體基板350。 After the first substrate 302 and the second substrate 307 are bonded to each other as described above, the semiconductor substrate 320 on the first substrate 302 side is thinned into the semiconductor layer 302a to expose the photoelectric conversion portion 321 . Further, the semiconductor substrate 350 can be thinned on the semiconductor layer 307a on the second substrate 307 side as occasion demands.

此後，在該第一基板302之光電轉換部分321之曝露面上形成一保護膜315，且在該保護膜315上形成一彩色濾光片層317及晶片上透鏡319以完成一半導體裝置1或一固態影像擷取裝置。 Thereafter, a protective film 315 is formed on the exposed surface of the photoelectric conversion portion 321 of the first substrate 302, and a color filter layer 317 and an on-wafer lens 319 are formed on the protective film 315 to complete a semiconductor device 1 or A solid-state image capture device.

[第二實施例之半導體裝置之製造方法之效果] [Effect of the method of manufacturing the semiconductor device of the second embodiment]

在如上所述之本實施例之半導體裝置之此一製造方法中，在該第一基板302及該第二基板307上形成該等絕緣薄膜312a及312b，且該第一基板302與該第二基板307藉由連結上面分別形成該等絕緣薄膜312a及312b之第一基板302及第二基板307之諸面而彼此接合。因此，與其中藉由該CMP平坦化之接合面341及371彼此直接連結之一替代情況相比，其中該第一基板302與該第二基板307藉由連結其等上面分別形成該等絕緣薄膜312a及312b之諸面而彼此接合之本實施例之半導體裝置1之連結性質較優。應注意，在其中僅於該第一基板302之接合面341上形成該絕緣薄膜312a之情況中，該第一基板302側之絕緣薄膜312a與該第二基板307側之接合面371亦連結在一起，且該等基板之連結性質優於其中該等接合面341與371彼此直接連結之替代情況中該等基板之連結性質。 In the manufacturing method of the semiconductor device of the present embodiment, the insulating films 312a and 312b are formed on the first substrate 302 and the second substrate 307, and the first substrate 302 and the second substrate are formed. The substrate 307 is bonded to each other by joining the surfaces of the first substrate 302 and the second substrate 307 on which the insulating films 312a and 312b are formed, respectively. Therefore, compared with the case where the bonding surfaces 341 and 371 which are planarized by the CMP are directly connected to each other, the first substrate 302 and the second substrate 307 are respectively formed by bonding the insulating films thereon. The semiconductor device 1 of the present embodiment in which the surfaces of 312a and 312b are bonded to each other is superior in bonding property. It should be noted that in the case where the insulating film 312a is formed only on the bonding surface 341 of the first substrate 302, the bonding film 371 on the first substrate 302 side and the bonding surface 371 on the second substrate 307 side are also connected. Together, and the bonding properties of the substrates are superior to the bonding properties of the substrates in the alternative where the bonding surfaces 341 and 371 are directly coupled to each other.

例如，存在以下可能性：在CMP步驟處組態藉由該CMP平坦化之接合面341及371之第一絕緣膜335及第二絕緣膜369可含有水。進一步言之，若組態該等接合面341及371之第一絕緣膜335及第二絕緣膜369係由一TEOS膜形成，則該第一絕緣膜335及該第二絕緣膜369形成為歸因於該TEOS膜之形成條件最初具有一高水分含量之膜。因此，在其中依此方式含有水之接合面341與371彼此直接連結之情況中，在該接合後之熱處理中，輸出氣體集中在連結介面上以形成空隙。然而，在本實施例中，因為該等絕緣薄膜312a及312b覆蓋在該等接合面341及371之總體面積上方，所以可防止輸出氣體集中在該連結介面上，以藉此抑制空隙之產生。 For example, there is a possibility that the first insulating film 335 and the second insulating film 369 which configure the bonding faces 341 and 371 which are planarized by the CMP at the CMP step may contain water. Further, if the first insulating film 335 and the second insulating film 369 of the bonding surfaces 341 and 371 are formed of a TEOS film, the first insulating film 335 and the second insulating film 369 are formed as The film has a high moisture content initially due to the formation conditions of the TEOS film. Therefore, in the case where the joint faces 341 and 371 containing water in this manner are directly joined to each other, in the heat treatment after the joining, the output gas is concentrated on the joint interface to form a void. However, in the present embodiment, since the insulating films 312a and 312b cover over the entire area of the bonding faces 341 and 371, it is possible to prevent the output gas from being concentrated on the bonding interface, thereby suppressing the generation of the voids.

尤其係在其中該第一基板302之接合面341上之絕緣薄膜312a及該第二基板307之接合面371上之絕緣薄膜312b係由相同材料之膜組態之情況中，因為該等相同材料膜彼此連結，所以可達成更堅固的連結。因此，可獲得該等基板之連結強度增強且因此可靠性增強之一半導體裝置。 In particular, in the case where the insulating film 312a on the bonding surface 341 of the first substrate 302 and the insulating film 312b on the bonding surface 371 of the second substrate 307 are configured by a film of the same material, because of the same material The membranes are joined to each other so that a stronger bond can be achieved. Therefore, it is possible to obtain a semiconductor device in which the bonding strength of the substrates is enhanced and thus the reliability is enhanced.

進一步言之，藉由使用該ALD方法以形成該等絕緣薄膜312a及312b，亦可達成下列優點。 Further, by using the ALD method to form the insulating films 312a and 312b, the following advantages can be achieved.

首先，因為該ALD方法係膜厚度可控性由於以一原子層為一單位之膜形成而良好之一方法。因此，即使運用其中該第一基板302側之第一電極333與該第二基板307之第二電極367彼此以一相對關係安置(其中該絕緣薄膜312內插於該第一電極333與該第二電極307之間)之一結構，因為 該絕緣薄膜312係一極薄膜，所以亦允許在該等第一電極333與該等第二電極367之間進行電連接。 First, since the ALD method is one in which the film thickness controllability is good due to the formation of a film having one atomic layer as a unit. Therefore, even if the first electrode 333 on the side of the first substrate 302 and the second electrode 367 of the second substrate 307 are disposed in an opposing relationship with each other (the insulating film 312 is interposed in the first electrode 333 and the first One of the two electrodes 307), because The insulating film 312 is a one-pole film, so that electrical connection between the first electrodes 333 and the second electrodes 367 is also allowed.

進一步言之，因為該ALD方法係膜厚度均勻性歸因於以一原子層為一單位之膜形成而良好之一方法，所以分別在該第一基板302及該第二基板307上形成該等均勻絕緣薄膜312a及312b，維持藉由CMP平坦化之接合面341及371之平坦度。因為該等絕緣薄膜312a及312b之平坦連結面之間之連結得以達成，所以所得連結之緊密接觸性較優，且可預期連結強度改良之基板之連結。 Further, since the ALD method is one in which the film thickness uniformity is good due to the formation of a film having one atomic layer as a unit, the formation is performed on the first substrate 302 and the second substrate 307, respectively. The uniform insulating films 312a and 312b maintain the flatness of the joint faces 341 and 371 which are flattened by CMP. Since the connection between the flat connecting faces of the insulating films 312a and 312b is achieved, the close contact of the obtained joint is excellent, and the connection of the substrate with improved joint strength can be expected.

進一步言之，因為該ALD方法使用一低溫製程以形成一膜，所以可在該第一基板302側之電極層302c及該第二基板307之電極層307c上形成該等絕緣薄膜312a及312b而不會因高熱而經歷該第一基板302側之電極層302c及該第二基板307側之電極層307c之損害。 Further, since the ALD method uses a low temperature process to form a film, the insulating films 312a and 312b can be formed on the electrode layer 302c on the first substrate 302 side and the electrode layer 307c of the second substrate 307. The damage of the electrode layer 302c on the first substrate 302 side and the electrode layer 307c on the second substrate 307 side is not caused by high heat.

最後，因為該ALD方法係以一原子層為一單位之一膜形成方法，所以所形成之絕緣薄膜312a及312b係精細膜且具有一極低水分含量。因此，因為所形成的具有一低水分含量之絕緣薄膜312a及312b的連結面連結在一起，所以該連結面上不可能出現空隙。 Finally, since the ALD method is a film formation method in which one atomic layer is one unit, the formed insulating films 312a and 312b are fine films and have an extremely low moisture content. Therefore, since the joint faces of the insulating films 312a and 312b having a low moisture content are joined together, voids are unlikely to occur on the joint faces.

因此，其中該等基板之連結強度增加之一半導體裝置達成可靠性之增強。 Therefore, one of the semiconductor devices in which the connection strength of the substrates is increased is increased in reliability.

第三實施例 Third embodiment

<<1.第一工作實例>> <<1. First working example>>

[相關技術中之一Cu-Cu連結技術之問題] [Problems of Cu-Cu Bonding Technology in One of Related Art]

在描述根據本發明之一第三實施例之一第一工作實例之一半導體裝置之前，參考圖12A、圖12B及圖13描述相關技術中之一Cu-Cu連結技術可能發生之問題。圖12A展示兩個半導體部件連結在一起之前半導體部件之一般組態，且圖12B展示該兩個半導體部件在一連結介面附近連結後之一般橫截面。進一步言之，圖13圖解說明在其中該兩個半導體部件接合時發生連結錯位之情況中可能發生之問題。 Before describing a semiconductor device according to one of the first working examples of the third embodiment of the present invention, a problem that may occur in one of the related art Cu-Cu joining techniques will be described with reference to FIGS. 12A, 12B and 13. Figure 12A shows a general configuration of a semiconductor component prior to joining two semiconductor components together, and Figure 12B shows a general cross section of the two semiconductor components joined together in the vicinity of a bonding interface. Further, FIG. 13 illustrates a problem that may occur in the case where a joint misalignment occurs when the two semiconductor components are joined.

在圖12A、圖12B及圖13中，展示一實例，其中包含一第一SiO2層611、一第一Cu電極612及一第一Cu障壁層613之一第一半導體部件610以及包含一第二SiO2層621、一第二Cu電極622及一第二Cu障壁層623之一第二半導體部件620連結在一起。 In FIGS. 12A, 12B and 13, an example is shown in which a first SiO 2 layer 611, a first Cu electrode 612 and a first Cu barrier layer 613 are included in the first semiconductor component 610 and include a first The second SiO 2 layer 621, a second Cu electrode 622, and a second Cu barrier layer 623 are joined together by a second semiconductor component 620.

應注意，在圖12A及圖12B中所示之實例中，以一嵌入式方式在該等半導體部件之SiO2層之一表面上形成該等Cu電極。特定言之，該等Cu電極經形成使得其等曝露於該SiO2層之該一表面，且所曝露面大致上與該SiO2層之該一表面齊平。進一步言之，在一Cu電極與一SiO2層之間設置每一Cu障壁層。進一步言之，該第一Cu電極612側上之第一半導體部件610之表面與該第二Cu電極622側上之第二半導體部件620之表面彼此接合。 It should be noted that in the examples shown in FIGS. 12A and 12B, the Cu electrodes are formed on one surface of one of the SiO 2 layers of the semiconductor components in an embedded manner. In particular, the Cu electrodes are formed such that they are exposed to the surface of the SiO 2 layer, and the exposed surface is substantially flush with the surface of the SiO 2 layer. Further, each Cu barrier layer is disposed between a Cu electrode and a SiO 2 layer. Further, the surface of the first semiconductor component 610 on the first Cu electrode 612 side and the surface of the second semiconductor component 620 on the second Cu electrode 622 side are bonded to each other.

當該第一半導體部件610與該第二半導體部件620彼此接合時，若其等之間發生連結錯位，則如圖12B中所示在一連結介面Si上產生該等半導體部件之一者之一Cu電極與另 一半導體部件之一SiO2層之間之一接觸區域。 When the first semiconductor component 610 and the second semiconductor component 620 are bonded to each other, if a connection misalignment occurs between them, one of the semiconductor components is produced on a bonding interface Si as shown in FIG. 12B. A contact area between the Cu electrode and one of the SiO 2 layers of another semiconductor component.

在此例項中，存在下列可能性：在連結時藉由一退火製程或類似製程，Cu 630可自該等Cu電極擴散至該等SiO2層中直到相鄰Cu電極在如圖13中所示之一連結介面Sj上短路。進一步言之，若該Cu 630自該等Cu電極擴散至該等SiO2層中之量大，則因為該等Cu電極中之Cu量降低，所以(例如)由於接觸電阻之一增加或導電故障發生可發生此一故障。 In this example, there is a possibility that Cu 630 can diffuse from the Cu electrodes into the SiO 2 layers by an annealing process or the like during bonding until the adjacent Cu electrodes are as shown in FIG. A short circuit is shown on one of the connection interfaces Sj. Further, if the amount of the Cu 630 diffused from the Cu electrodes into the SiO 2 layers is large, since the amount of Cu in the Cu electrodes is lowered, for example, one of the contact resistances increases or the conduction failure occurs. This failure can occur.

若如上所述之連結介面Sj上之電特性發生此一故障，則該半導體裝置之效能受到損害。因此，在本工作實例中，描述可消除如上所述之連結介面Sj上之電特性之此等故障之一半導體裝置之組態。 If the electrical characteristics on the bonding interface Sj occur as described above, the performance of the semiconductor device is impaired. Therefore, in the present working example, a configuration of a semiconductor device which can eliminate such a failure of the electrical characteristics on the connection interface Sj as described above is described.

[半導體裝置之組態] [Configuration of Semiconductor Device]

圖14及圖15展示根據該第一工作實例之半導體裝置之一般組態。特定言之，圖14展示一連結介面附近該第一工作實例之半導體裝置之一般橫截面，且圖15展示該連結介面附近之一示意俯視圖並圖解說明下文描述之Cu連結部分與一介面Cu障壁膜之間之一配置關係。應注意，在圖14及圖15中，為簡化描述，僅展示一連結介面之一組態。 14 and 15 show a general configuration of a semiconductor device according to the first working example. In particular, FIG. 14 shows a general cross section of a semiconductor device of the first working example near a bonding interface, and FIG. 15 shows a schematic top view of the vicinity of the bonding interface and illustrates a Cu bonding portion and an interface Cu barrier described below. One configuration relationship between the membranes. It should be noted that in FIGS. 14 and 15, only one configuration of a link interface is shown for simplicity of description.

首先參考圖14，所示之一半導體裝置401包含作為一第一半導體截面之一第一半導體部件410及作為一第二半導體截面之一第二半導體部件420。進一步言之，在本工作實例之半導體裝置401中，該第一半導體部件410在該第一半導體部件410在一第一層間絕緣415側上之一面處連結該 第二半導體部件420在至下文描述之一介面Cu障壁膜428側上之一面。 Referring first to Figure 14, a semiconductor device 401 is shown comprising a first semiconductor component 410 as one of the first semiconductor sections and a second semiconductor component 420 as one of the second semiconductor sections. Further, in the semiconductor device 401 of the working example, the first semiconductor component 410 is coupled to the first semiconductor component 410 at a side of a first interlayer insulating 415 side. The second semiconductor component 420 is on one side of the side of the interface Cu barrier film 428 described below.

該第一半導體部件410包含未展示之一第一半導體基板、一第一SiO2層411、一第一Cu配接線部分412、一第一Cu障壁膜413、一第一Cu擴散防止膜414、該第一層間絕緣膜415、一第一Cu連結部分416及一第一Cu障壁層417。 The first semiconductor component 410 includes a first semiconductor substrate, a first SiO 2 layer 411, a first Cu wiring portion 412, a first Cu barrier film 413, and a first Cu diffusion preventing film 414. The first interlayer insulating film 415, a first Cu connecting portion 416, and a first Cu barrier layer 417.

該第一SiO2層411係形成於該第一半導體基板上。該第一Cu配接線部分412係以一嵌入式狀態形成於該第一SiO2層411在與該第一半導體基板側相對之側上之表面上。應注意，該第一Cu配接線部分412係在如圖15中所示之一預定方向上延伸之一Cu膜且連接至該半導體裝置401中未展示或包含該半導體裝置401之一電子設備中之一預定裝置、一信號處理電路或類似物。 The first SiO 2 layer 411 is formed on the first semiconductor substrate. The first Cu wiring portion 412 is formed in an embedded state on the surface of the first SiO 2 layer 411 on the side opposite to the first semiconductor substrate side. It should be noted that the first Cu wiring portion 412 extends one of the Cu films in a predetermined direction as shown in FIG. 15 and is connected to an electronic device not shown in the semiconductor device 401 or included in the semiconductor device 401. One of the predetermined devices, a signal processing circuit or the like.

該第一Cu障壁膜413係形成於該第一SiO2層411與該第一Cu配接線部分412之間。應注意，該第一Cu障壁膜413係用於防止銅(Cu)自該第一Cu配接線部分412擴散至該第一SiO2層411中之一薄膜，且係由(例如)Ti、Ta、Ru或其等任一者之氮化物(TiN、TaN、RuN)形成。 The first Cu barrier film 413 is formed between the first SiO 2 layer 411 and the first Cu wiring portion 412. It should be noted that the first Cu barrier film 413 is for preventing copper (Cu) from diffusing from the first Cu wiring portion 412 to one of the first SiO 2 layers 411, and is made of, for example, Ti, Ta. Nitride (TiN, TaN, RuN) of Ru, or any of them is formed.

該第一Cu擴散防止膜414形成於除該第一Cu障壁層417之一形成區域外之第一SiO2層411及第一Cu配接線部分412之一區域中。應注意，該第一Cu擴散防止膜414係用於防止Cu自該第一Cu配接線部分412擴散至該第一層間絕緣膜415中之一薄膜，且係由(例如)SiC、SiN或SiCN之一薄膜組態。 The first Cu diffusion preventing film 414 is formed in a region of the first SiO 2 layer 411 and the first Cu wiring portion 412 except for a region where the first Cu barrier layer 417 is formed. It should be noted that the first Cu diffusion preventing film 414 is for preventing diffusion of Cu from the first Cu wiring portion 412 to one of the first interlayer insulating films 415, and is made of, for example, SiC, SiN or One of the SiCN film configurations.

該第一層間絕緣膜415係形成於該第一Cu擴散防止膜414上，且由諸如SiO2膜之氧化物膜組態。 The first interlayer insulating film 415 is formed on the first Cu diffusion preventing film 414, and is configured by an oxide film such as a SiO 2 film.

作為一第一金屬膜之第一Cu連結部分416係以一嵌入式方式設置於該第一層間絕緣膜415在與該第一Cu擴散防止膜414側相對之側上之表面上。應注意，在本工作實例中，該第一Cu連結部分416係由具有如圖15中所示之一正方形形狀之一表面(膜面)之一Cu膜組態。然而，本發明並不限於此，但是考慮諸如一所需接觸電阻及一設計規則之各種條件可適當地改變該第一Cu連結部分416之表面形狀。 The first Cu connecting portion 416 as a first metal film is disposed in an embedded manner on the surface of the first interlayer insulating film 415 on the side opposite to the side of the first Cu diffusion preventing film 414. It should be noted that in the present working example, the first Cu joining portion 416 is configured by a Cu film having one surface (film surface) of one square shape as shown in FIG. However, the present invention is not limited thereto, but the surface shape of the first Cu joining portion 416 can be appropriately changed in consideration of various conditions such as a required contact resistance and a design rule.

該第一Cu障壁層417係以覆蓋該第一Cu連結部分416之一方式設置於該第一Cu連結部分416與該第一Cu配接線部分412、該第一Cu擴散防止膜414與該第一層間絕緣膜415之間。因此，該第一Cu連結部分416透過該第一Cu障壁層417電連接至該第一Cu配接線部分412。應注意，該第一Cu障壁層417係用於防止Cu自該第一Cu連結部分416擴散至該第一層間絕緣膜415中之一薄膜，且係由(例如)Ti、Ta、Ru或其等任一者之氮化物形成。 The first Cu barrier layer 417 is disposed on the first Cu connecting portion 416 and the first Cu bonding portion 412, the first Cu diffusion preventing film 414, and the first covering layer 416. Between the interlayer insulating films 415. Therefore, the first Cu bonding portion 416 is electrically connected to the first Cu wiring portion 412 through the first Cu barrier layer 417. It should be noted that the first Cu barrier layer 417 is for preventing diffusion of Cu from the first Cu bonding portion 416 to one of the first interlayer insulating films 415, and is, for example, Ti, Ta, Ru or The nitride of any of them is formed.

該第二半導體部件420包含未展示之一第二半導體基板、一第二SiO2層421、一第二Cu配接線部分422、一第二Cu障壁膜423、一第二Cu擴散防止膜424、該第二層間絕緣膜425、一第二Cu連結部分426、一第二Cu障壁層427及該介面Cu障壁膜428。 The second semiconductor component 420 includes a second semiconductor substrate, a second SiO 2 layer 421, a second Cu wiring portion 422, a second Cu barrier film 423, and a second Cu diffusion preventing film 424. The second interlayer insulating film 425, a second Cu connecting portion 426, a second Cu barrier layer 427, and the interface Cu barrier film 428.

應注意，該第二半導體部件420之第二半導體基板、第 二SiO2層421及第二Cu配接線部分422具有類似於該第一半導體部件410之第一半導體基板、第一SiO2層411及第一Cu配接線部分412之組態之一組態。進一步言之，該第二半導體部件420之第二Cu障壁膜423、第二Cu擴散防止膜424及第二層間絕緣膜425具有類似於該第一半導體部件410之第一Cu障壁膜413、第一Cu擴散防止膜414及第一層間絕緣膜415之組態之一組態。 It should be noted that the second semiconductor substrate, the second SiO 2 layer 421 and the second Cu wiring portion 422 of the second semiconductor component 420 have a first semiconductor substrate similar to the first semiconductor component 410, and the first SiO 2 layer 411. And one of the configurations of the first Cu distribution wiring portion 412 is configured. Further, the second Cu barrier film 423, the second Cu diffusion preventing film 424, and the second interlayer insulating film 425 of the second semiconductor component 420 have a first Cu barrier film 413 similar to the first semiconductor component 410, One of the configurations of the Cu diffusion preventing film 414 and the first interlayer insulating film 415 is configured.

作為一第二金屬膜之第二Cu連結部分426係以一嵌入式方式設置於呈一絕緣膜之形式之第二層間絕緣膜425在與該第二Cu擴散防止膜424側相對之側上之表面上。應注意，在本工作實例中，該第二Cu連結部分426係由具有如圖15中所示之一正方形形狀之一表面之一Cu膜組態。然而，本發明並不限於此，但是考慮諸如一所需接觸電阻及一設計規則之各種條件可適當地改變該第二Cu連結部分426之表面形狀。 The second Cu connecting portion 426 as a second metal film is disposed in an embedded manner on the side of the second interlayer insulating film 425 in the form of an insulating film on the side opposite to the second Cu diffusion preventing film 424 side. On the surface. It should be noted that in the present working example, the second Cu joining portion 426 is configured by a Cu film having one of the surfaces of one of the square shapes as shown in FIG. However, the present invention is not limited thereto, but the surface shape of the second Cu joining portion 426 can be appropriately changed in consideration of various conditions such as a required contact resistance and a design rule.

進一步言之，在本工作實例中，該第二Cu連結部分426在該連結側上(即，該連結介面Sj側上)之表面面積或該連結側表面之尺寸小於如圖14及圖15中所示之第一Cu連結部分416。此後，該第二Cu連結部分426之大小經設定使得即使發生該第一半導體部件410與該第二半導體部件420之間估計之最大連結錯位，該第二Cu連結部分426與該第一層間絕緣膜415亦不在該連結介面Si上彼此接觸。更特定言之，該第二Cu連結部分426之大小經設定使得(例如)若由如圖14中所示之△a表示該第二Cu連結部分426之一側面與 該第一Cu障壁層417之一側面之間之最小距離，則△a係大於所估計最大連結錯位之一尺寸。 Further, in the working example, the surface area of the second Cu connecting portion 426 on the connecting side (ie, on the side of the connecting interface Sj) or the size of the connecting side surface is smaller than in FIGS. 14 and 15 The first Cu joint portion 416 is shown. Thereafter, the second Cu connecting portion 426 is sized such that even if the estimated maximum misalignment between the first semiconductor component 410 and the second semiconductor component 420 occurs, the second Cu bonding portion 426 and the first layer The insulating film 415 also does not contact each other on the bonding interface Si. More specifically, the size of the second Cu joining portion 426 is set such that, for example, one side of the second Cu joining portion 426 is indicated by Δa as shown in FIG. The minimum distance between one side of the first Cu barrier layer 417, then Δa is greater than one of the estimated maximum connection misalignments.

該第二Cu障壁層427係以覆蓋該第二Cu連結部分426之一方式設置於該第二Cu連結部分426與該第二Cu配接線部分422、該第二Cu擴散防止膜424與該第二層間絕緣膜425之間。因此，該第二Cu連結部分426透過該第二Cu障壁層427電連接至該第二Cu配接線部分422。應注意，類似於該第一Cu障壁層417，該第二Cu障壁層427係用於防止Cu自該第二Cu連結部分426擴散至該第二層間絕緣膜425中之一薄膜，且係由(例如)Ti、Ta、Ru或其等任一者之氮化物形成。 The second Cu barrier layer 427 is disposed on the second Cu connecting portion 426 and the second Cu wiring portion 422, the second Cu diffusion preventing film 424, and the first covering layer 426. Between the two interlayer insulating films 425. Therefore, the second Cu bonding portion 426 is electrically connected to the second Cu wiring portion 422 through the second Cu barrier layer 427. It should be noted that similar to the first Cu barrier layer 417, the second Cu barrier layer 427 is for preventing diffusion of Cu from the second Cu bonding portion 426 to one of the second interlayer insulating films 425, and is Nitride formation of, for example, Ti, Ta, Ru, or the like.

該介面Cu障壁膜428(即，一介面障壁膜或一介面障壁區段)係形成於該第二層間絕緣膜425上。在此例項中，該介面Cu障壁膜428經形成使得該介面Cu障壁膜428之表面與該第二Cu連結部分426之表面在該連結側上可大致上彼此齊平。換言之，該介面Cu障壁膜428係設置於包括自該第一Cu連結部分416在該連結介面Si側上之面區域內開始之未連結至該第二Cu連結部分426之一面區域。藉由在剛剛描述之一區域或位置中設置該介面Cu障壁膜428，可防止Cu自該Cu連結部分透過該連結介面Sj與該第一Cu連結部分416相對之區域擴散至呈一SiO2膜之形式之層間絕緣膜及該第二層間絕緣膜425中。 The interface Cu barrier film 428 (ie, an interface barrier film or an interface barrier layer) is formed on the second interlayer insulating film 425. In this example, the interface Cu barrier film 428 is formed such that the surface of the interface Cu barrier film 428 and the surface of the second Cu bonding portion 426 are substantially flush with each other on the bonding side. In other words, the interface Cu barrier film 428 is disposed on a surface region that is not connected to the second Cu bonding portion 426 from the surface region of the first Cu connecting portion 416 on the bonding interface Si side. By providing the interface Cu barrier film 428 in a region or position just described, it is possible to prevent Cu from diffusing from the Cu bonding portion through the bonding interface Sj and the region opposite to the first Cu bonding portion 416 to a SiO 2 film. In the form of an interlayer insulating film and the second interlayer insulating film 425.

應注意，可使用舉例而言諸如SiN、SiON、SiCN或有機樹脂之材料形成該介面Cu障壁膜428。然而，就增強與一 Cu膜之緊密接觸而言，較佳地特別由SiN形成該介面Cu障壁膜428。 It should be noted that the interface Cu barrier film 428 may be formed using a material such as SiN, SiON, SiCN or an organic resin. However, it is enhanced with one In the case of intimate contact of the Cu film, the interface Cu barrier film 428 is preferably formed particularly of SiN.

[半導體裝置之製造技術] [Manufacturing Technology of Semiconductor Device]

現在，參考圖16A至圖16M描述本工作實例之半導體裝置401之一製造技術。應注意，圖16A至圖16L展示在不同步驟處製造之一半導體部件之Cu連結部分附近之示意橫截面，且圖16M圖解說明該第一半導體部件410與該第二半導體部件420之一連結製程之一方式。 Now, a manufacturing technique of one of the semiconductor devices 401 of the present working example will be described with reference to FIGS. 16A to 16M. It should be noted that FIGS. 16A to 16L show schematic cross sections in the vicinity of a Cu joint portion of a semiconductor component manufactured at different steps, and FIG. 16M illustrates a process of joining the first semiconductor component 410 and the second semiconductor component 420. One way.

首先，參考圖16A至圖16F描述該第一半導體部件410之一製造技術。在本工作實例中，雖然未展示，但是在作為一接地絕緣層之第一SiO2層411之表面之一者之一預定區域中按此順序形成一第一Cu障壁膜413及一第一Cu配接線部分412。此後，該第一Cu配接線部分412係以其嵌入該第一SiO2層411之表面之一者中(即，曝露於該第一SiO2層411之表面)之一方式形成。 First, a manufacturing technique of the first semiconductor component 410 will be described with reference to FIGS. 16A to 16F. In the present working example, although not shown, a first Cu barrier film 413 and a first Cu are formed in this order in a predetermined region of one of the surfaces of the first SiO 2 layer 411 as a ground insulating layer. Wiring portion 412. Thereafter, the first Cu wiring portion 412 is formed in such a manner that it is embedded in one of the surfaces of the first SiO 2 layer 411 (i.e., exposed on the surface of the first SiO 2 layer 411).

接著，如圖16A中所示，在由該第一SiO2層411、該第一Cu配接線部分412及該第一Cu障壁膜413組態之半導體部件之第一Cu配接線部分412側上之表面上形成一第一Cu擴散防止膜414。應注意，可藉由類似於舉例而言諸如日本專利特許公開案第2004-63859號中揭示之相關技術中之一固態影像擷取裝置之一半導體裝置之此一製造方法之一方法形成該第一SiO2層411、該第一Cu配接線部分412、該第一Cu障壁膜413及該第一Cu擴散防止膜414。 Next, as shown in FIG. 16A, on the side of the first Cu wiring portion 412 of the semiconductor component configured by the first SiO 2 layer 411, the first Cu wiring portion 412, and the first Cu barrier film 413 A first Cu diffusion preventing film 414 is formed on the surface. It should be noted that the first method can be formed by one of the manufacturing methods of a semiconductor device which is one of the related art technologies disclosed in Japanese Laid-Open Patent Publication No. 2004-63859, for example. An SiO 2 layer 411, the first Cu wiring portion 412, the first Cu barrier film 413, and the first Cu diffusion preventing film 414.

接著在該第一Cu擴散防止膜414上形成一第一層間絕緣 膜415。特定言之，在該第一Cu擴散防止膜414上形成一厚度為約50奈米至500奈米之一SiO2膜或一含碳氧化矽(SiOC)膜以形成一第一層間絕緣膜415。應注意，可藉由(例如)一化學氣相沈積(CVD)方法或一旋塗方法形成剛剛描述之此第一層間絕緣膜415。 Next, a first interlayer insulating film 415 is formed on the first Cu diffusion preventing film 414. Specifically, a SiO 2 film or a carbon-containing cerium oxide (SiOC) film having a thickness of about 50 nm to 500 nm is formed on the first Cu diffusion preventing film 414 to form a first interlayer insulating film. 415. It should be noted that the first interlayer insulating film 415 just described may be formed by, for example, a chemical vapor deposition (CVD) method or a spin coating method.

此後，如圖16B中所示，在該第一層間絕緣膜415上形成一光阻膜450。接著，使用一光微影技術以對該光阻膜450實施一圖案化製程以移除一第一Cu連結部分416之一形成區域中之光阻膜450以形成一開口450a。 Thereafter, as shown in FIG. 16B, a photoresist film 450 is formed on the first interlayer insulating film 415. Next, a photolithography technique is used to perform a patterning process on the photoresist film 450 to remove the photoresist film 450 in the formation region of one of the first Cu bonding portions 416 to form an opening 450a.

接著，例如，使用磁電管類型之一已知蝕刻設備以在開口450a側上對上面形成該光阻膜450之半導體部件之表面實施一乾式蝕刻製程。因此，蝕刻曝露於該光阻膜450之開口450a之第一層間絕緣膜415之區域。藉由此蝕刻製程，如圖16C中所示，移除該光阻膜450之開口450a之區域中之第一層間絕緣膜415及第一Cu擴散防止膜414以使該第一Cu配接線部分412曝露於該第一層間絕緣膜415之一開口415a。應注意，在本工作實例中，該第一層間絕緣膜415之開口415a之開口直徑係(例如)約4微米至100微米。 Next, for example, an etching apparatus known as one of the magnetron types is used to perform a dry etching process on the surface of the semiconductor member on which the photoresist film 450 is formed on the side of the opening 450a. Therefore, the region exposed to the first interlayer insulating film 415 of the opening 450a of the photoresist film 450 is etched. By the etching process, as shown in FIG. 16C, the first interlayer insulating film 415 and the first Cu diffusion preventing film 414 in the region of the opening 450a of the photoresist film 450 are removed to make the first Cu wiring The portion 412 is exposed to one of the openings 415a of the first interlayer insulating film 415. It should be noted that in the present working example, the opening diameter 415a of the first interlayer insulating film 415 has an opening diameter of, for example, about 4 μm to 100 μm.

此後，對已實施該蝕刻製程之面實施(例如)其中使用氧氣(O2)電漿之一灰化製程及其中使用有機胺基藥物之溶液之一沖洗製程。藉由該等製程，移除留在該第一層間絕緣膜415上之光阻膜450及該蝕刻製程中產生之殘留沈積物。 Thereafter, the surface on which the etching process has been carried out is subjected to, for example, one of a solution in which an oxygen-based (O 2 ) plasma is used in the ashing process and a solution in which the organic amine-based drug is used. By the processes, the photoresist film 450 remaining on the first interlayer insulating film 415 and the residual deposit generated in the etching process are removed.

接著，如圖16D中所示，在該第一層間絕緣膜415及曝露於該第一層間絕緣膜415之開口415a之第一Cu配接線部分 412上形成由Ti、Ta、Ru或其等氮化物之任一者製成之一第一Cu障壁層417。特定言之，使用舉例而言諸如一射頻(RF)濺鍍方法之一技術以在Ar/N2氛圍中於該第一層間絕緣膜415及該第一Cu配接線部分412上形成一厚度為約5奈米至50奈米之第一Cu障壁層417。 Next, as shown in FIG. 16D, Ti, Ta, Ru or the first interlayer insulating film 415 and the first Cu wiring portion 412 exposed to the opening 415a of the first interlayer insulating film 415 are formed. Any of the nitrides is formed into one of the first Cu barrier layers 417. Specifically, a technique such as a radio frequency (RF) sputtering method is used to form a thickness on the first interlayer insulating film 415 and the first Cu wiring portion 412 in an Ar/N 2 atmosphere. It is a first Cu barrier layer 417 of about 5 nm to 50 nm.

接著，如圖16E中所示，使用諸如一濺鍍方法或一電解電鍍方法之技術在該第一Cu障壁層417上形成一Cu膜451。藉由此製程，該Cu膜451嵌入該第一層間絕緣膜415之開口415a之一區域中。 Next, as shown in FIG. 16E, a Cu film 451 is formed on the first Cu barrier layer 417 using a technique such as a sputtering method or an electrolytic plating method. By this process, the Cu film 451 is embedded in a region of the opening 415a of the first interlayer insulating film 415.

此後，在一氮氣氛圍中或真空中使用諸如一加熱板之一加熱設備或一燒結退火設備將上面形成該Cu膜451之半導體部件加熱至約100℃至400℃持續1分鐘至60分鐘。藉由此加熱製程，加固該Cu膜451以形成精細膜品質之一Cu膜451。 Thereafter, the semiconductor member on which the Cu film 451 is formed is heated to about 100 ° C to 400 ° C for 1 minute to 60 minutes using a heating device such as a heating plate or a sintering annealing apparatus in a nitrogen atmosphere or a vacuum. By this heating process, the Cu film 451 is reinforced to form a Cu film 451 which is one of fine film qualities.

此後，如圖16F中所示，藉由一化學機械拋光(CMP)方法移除該Cu膜451及該第一Cu障壁層417之不必要部分。特定言之，藉由一CMP方法拋光該Cu膜451之表面直到該第一層間絕緣膜415曝露於該表面。 Thereafter, as shown in FIG. 16F, unnecessary portions of the Cu film 451 and the first Cu barrier layer 417 are removed by a chemical mechanical polishing (CMP) method. Specifically, the surface of the Cu film 451 is polished by a CMP method until the first interlayer insulating film 415 is exposed to the surface.

在本工作實例中，實施上文參考圖16A至圖16F描述之步驟以製造一第一半導體部件410。現在，參考圖16G至圖16L描述該第二半導體部件420之一製造技術。 In the present working example, the steps described above with reference to FIGS. 16A through 16F are performed to fabricate a first semiconductor component 410. Now, a manufacturing technique of the second semiconductor component 420 will be described with reference to FIGS. 16G to 16L.

首先，類似於該第一半導體部件410之製造(圖16A之步驟)按此順序在一第二SiO2層421之諸面之一者之一預定區域中形成一第二Cu障壁膜423及一第二Cu配接線部分 422。接著，在由該第二SiO2層421、該第二Cu配接線部分422及該第二Cu障壁膜423形成之半導體部件在該第二Cu配接線部分422側上之表面上形成一第二Cu擴散防止膜424。 First, similar to the fabrication of the first semiconductor component 410 (step of FIG. 16A), a second Cu barrier film 423 and a predetermined region are formed in a predetermined region of one of the faces of the second SiO 2 layer 421 in this order. The second Cu is provided with a wiring portion 422. Next, a semiconductor component formed by the second SiO 2 layer 421, the second Cu wiring portion 422, and the second Cu barrier film 423 forms a second surface on the surface of the second Cu wiring portion 422 side. Cu diffusion preventing film 424.

接著在該第二Cu擴散防止膜424上形成一第二層間絕緣膜425。特定言之，例如，在該第二Cu擴散防止膜424上形成一厚度為約50奈米至500奈米之SiO2膜或SiOC膜作為一第二層間絕緣膜425。應注意，可藉由(例如)一CVD方法或一旋塗方法形成剛剛描述之此第二層間絕緣膜425。接著，使用諸如一CVD方法或一旋塗方法之一技術在該第二層間絕緣膜425上形成一厚度為約5奈米至100奈米之一介面Cu障壁膜428。此後，使用諸如一CVD方法或一旋塗方法之一技術在該介面Cu障壁膜428上形成一厚度為約50奈米至200奈米之SiO2膜或SiOC膜，藉此形成一絕緣膜452。 Next, a second interlayer insulating film 425 is formed on the second Cu diffusion preventing film 424. Specifically, for example, a SiO 2 film or a SiOC film having a thickness of about 50 nm to 500 nm is formed as a second interlayer insulating film 425 on the second Cu diffusion preventing film 424. It should be noted that the second interlayer insulating film 425 just described may be formed by, for example, a CVD method or a spin coating method. Next, an interface Cu barrier film 428 having a thickness of about 5 nm to 100 nm is formed on the second interlayer insulating film 425 using a technique such as a CVD method or a spin coating method. Thereafter, a SiO 2 film or a SiOC film having a thickness of about 50 nm to 200 nm is formed on the interface Cu barrier film 428 by using a technique such as a CVD method or a spin coating method, thereby forming an insulating film 452. .

接著，如圖16G中所示，在該絕緣膜452上形成一光阻膜453。接著，使用一光微影技術對該光阻膜453實施一圖案化製程以移除該第二Cu連結部分426之一形成區域中之光阻膜453以形成一開口453a。應注意，設定該開口453a之開口直徑小於於上文參考圖16B描述之步驟處形成之光阻膜450之開口450a之開口直徑。 Next, as shown in FIG. 16G, a photoresist film 453 is formed on the insulating film 452. Next, the photoresist film 453 is subjected to a patterning process using a photolithography technique to remove the photoresist film 453 in a region where the second Cu bonding portion 426 is formed to form an opening 453a. It should be noted that the opening diameter of the opening 453a is set to be smaller than the opening diameter of the opening 450a of the photoresist film 450 formed at the step described above with reference to FIG. 16B.

然而，其中在上述光阻膜453中形成該開口453a之半導體部件之製造步驟並不限於圖16G中所示之實例，且例如，該光阻膜453可直接設置於該介面Cu障壁膜428上且在該光阻膜453中形成該開口453a。圖16H展示藉由剛剛描述 之技術形成該開口453a時該半導體部件之一示意橫截面。 However, the manufacturing step of the semiconductor member in which the opening 453a is formed in the above-mentioned photoresist film 453 is not limited to the example shown in FIG. 16G, and for example, the photoresist film 453 may be directly disposed on the interface Cu barrier film 428. The opening 453a is formed in the photoresist film 453. Figure 16H shows by just describing The technique forms a cross section of one of the semiconductor components when the opening 453a is formed.

然而，若採用圖16H中所示之技術，則透過一第二Cu障壁層427直接在該介面Cu障壁膜428上形成一Cu膜，且接著藉由一CMP製程拋光該Cu膜以形成一第二Cu連結部分426。然而，因為通常該介面Cu障壁膜428係難以藉由一CMP方法拋光之一膜，所以若採用圖16H中所示之技術，則一旦進行CMP處理，該介面Cu障壁膜428上可出現仍未移除之Cu膜之一部分。 However, if the technique shown in FIG. 16H is used, a Cu film is directly formed on the interface Cu barrier film 428 through a second Cu barrier layer 427, and then the Cu film is polished by a CMP process to form a first The second Cu joint portion 426. However, since the interface Cu barrier film 428 is generally difficult to polish one film by a CMP method, if the technique shown in FIG. 16H is employed, once the CMP process is performed, the interface Cu barrier film 428 may still appear. Remove one part of the Cu film.

相比而言，在圖16G中所示之開口453a之形成方法中，因為在該介面Cu障壁膜428上形成該絕緣膜452，所以在CMP處理該Cu膜時亦藉由拋光該絕緣膜452可高度確定地消除仍未移除之Cu膜之該部分。換言之，就形成該第二Cu連結部分426時防止該Cu膜出現一未移除部分而言，圖16G中所示之開口453a之形成技術比圖16H中所示之開口453a之形成技術更佳。 In contrast, in the method of forming the opening 453a shown in FIG. 16G, since the insulating film 452 is formed on the interface Cu barrier film 428, the insulating film 452 is also polished by CMP processing of the Cu film. This portion of the Cu film that has not been removed can be eliminated with a high degree of certainty. In other words, the formation technique of the opening 453a shown in FIG. 16G is better than the formation of the opening 453a shown in FIG. 16H in the case where the Cu-film portion 426 is formed to prevent an unremoved portion of the Cu film. .

接著，在該開口453上使用磁控管類型之一已知蝕刻設備對上面形成該光阻膜453之半導體部件之表面實施一乾式蝕刻製程。因此，蝕刻曝露於該光阻膜453之開口453a之絕緣膜452之一區域。藉由此蝕刻製程，如圖16I中所示般移除該開口453a之區域中之絕緣膜452、介面Cu障壁膜428、第二層間絕緣膜425及第二Cu擴散防止膜424以使該第二Cu配接線部分422曝露於該第二層間絕緣膜425之一開口425a。應注意，該第二層間絕緣膜425之開口425a之開口直徑係(例如)約1微米至95微米。 Next, a dry etching process is performed on the opening 453 on the surface of the semiconductor component on which the photoresist film 453 is formed using an etching apparatus known in the magnetron type. Therefore, a region exposed to the insulating film 452 of the opening 453a of the photoresist film 453 is etched. By the etching process, the insulating film 452, the interface Cu barrier film 428, the second interlayer insulating film 425, and the second Cu diffusion preventing film 424 in the region of the opening 453a are removed as shown in FIG. 16I to make the first The second Cu wiring portion 422 is exposed to one opening 425a of the second interlayer insulating film 425. It should be noted that the opening diameter 425a of the second interlayer insulating film 425 has an opening diameter of, for example, about 1 μm to 95 μm.

此後，對已實施該蝕刻之面實施(例如)其中使用氧氣(O2)電漿之一灰化製程及其中使用有機胺基藥物之溶液之一沖洗製程。藉由該等製程，移除留在該絕緣膜452上之光阻膜453及該蝕刻製程中產生之殘留沈積物。 Thereafter, the surface on which the etching has been performed is subjected to, for example, one of a solution in which an oxygen-based (O 2 ) plasma is used in the ashing process and a solution in which the organic amine-based drug is used. By the processes, the photoresist film 453 remaining on the insulating film 452 and the residual deposit generated in the etching process are removed.

接著，如圖16J中所示，在該絕緣膜452及曝露於該第二層間絕緣膜425之開口425a之第二Cu配接線部分422上形成由Ti、Ta、Ru或其等氮化物之任一者製成之一第二Cu障壁層427。特定言之，使用舉例而言諸如一RF濺鍍方法之一技術以在Ar/N2氛圍中於該絕緣膜452及該第二Cu配接線部分422上形成一厚度為約5奈米至50奈米之第二Cu障壁層427。 Next, as shown in FIG. 16J, a Ti, Ta, Ru or the like is formed on the insulating film 452 and the second Cu wiring portion 422 exposed to the opening 425a of the second interlayer insulating film 425. One of them is made of one of the second Cu barrier layers 427. Specifically, a technique such as an RF sputtering method is used to form a thickness of about 5 nm to 50 on the insulating film 452 and the second Cu wiring portion 422 in an Ar/N 2 atmosphere. The second Cu barrier layer 427 of nano.

接著，如圖16K中所示，使用諸如一濺鍍方法或一電解電鍍方法之技術在該第二Cu障壁層427上形成一Cu膜454。藉由此製程，該Cu膜454嵌入該第二層間絕緣膜425之開口425a之一區域中。 Next, as shown in FIG. 16K, a Cu film 454 is formed on the second Cu barrier layer 427 using a technique such as a sputtering method or an electrolytic plating method. By this process, the Cu film 454 is embedded in a region of the opening 425a of the second interlayer insulating film 425.

此後，在一氮氣氛圍中或真空中使用諸如一加熱板之一加熱設備或一燒結退火設備將上面形成該Cu膜454之半導體部件加熱至約100℃至400℃持續1分鐘至60分鐘。藉由此加熱製程，加固該Cu膜454以形成精細膜品質之一Cu膜454。 Thereafter, the semiconductor member on which the Cu film 454 is formed is heated to about 100 ° C to 400 ° C for 1 minute to 60 minutes in a nitrogen atmosphere or in a vacuum using a heating device such as a heating plate or a sintering annealing device. By this heating process, the Cu film 454 is reinforced to form a Cu film 454 which is one of fine film qualities.

此後，如圖16L中所示，藉由一化學機械拋光(CMP)方法移除該Cu膜454、該第二Cu障壁層427及該絕緣膜452之不必要部分。特定言之，藉由一CMP方法拋光該Cu膜454側之表面直到該介面Cu障壁膜428曝露於該表面。在本工 作實例中，實施上文參考圖16G至圖16L描述之各種步驟以製造該第二半導體部件420。 Thereafter, as shown in FIG. 16L, the Cu film 454, the second Cu barrier layer 427, and unnecessary portions of the insulating film 452 are removed by a chemical mechanical polishing (CMP) method. Specifically, the surface of the Cu film 454 side is polished by a CMP method until the interface Cu barrier film 428 is exposed to the surface. In the work In the example, various steps described above with reference to FIGS. 16G through 16L are performed to fabricate the second semiconductor component 420.

此後，藉由上述程序製造之圖16F中所示之第一半導體部件410及圖16L中所示之第二半導體部件420彼此接合。該接合步驟(即，一連結步驟)之特定處理物質係諸如下文描述之處理物質。 Thereafter, the first semiconductor component 410 shown in FIG. 16F and the second semiconductor component 420 shown in FIG. 16L, which are manufactured by the above-described program, are bonded to each other. The specific treatment material of the joining step (i.e., a joining step) is such as the treating substance described below.

首先，對該第一半導體部件410在該第一Cu連結部分416側上之表面及該第二半導體部件420在第二Cu連結部分426側上之表面實施一還原製程以移除該等Cu連結部分之表面上之氧化物膜(即，移除氧化物)。藉由此移除，使純淨的Cu曝露於該等Cu連結部分之表面。應注意，使用其中使用諸如甲酸之藥物溶液之一濕式蝕刻製程或其中使用(例如)Ar、NH3或H2之電漿之一乾式蝕刻製程作為此例項中之還原製程。 First, a surface of the first semiconductor component 410 on the side of the first Cu bonding portion 416 and a surface of the second semiconductor component 420 on the second Cu bonding portion 426 side are subjected to a reduction process to remove the Cu links. Part of the oxide film on the surface (ie, removing oxide). By this removal, pure Cu is exposed to the surface of the Cu-joining portion. It should be noted that a dry etching process in which one of the drug solutions such as formic acid is used or a plasma in which, for example, Ar, NH 3 or H 2 is used is used as the reduction process in this example.

接著，如圖16M中所示，該第一半導體部件410在該第一Cu連結部分416側上之表面與該第二半導體部件420在第二Cu連結部分426側上之表面彼此接觸或彼此接合。此後，該第一Cu連結部分416與對應的第二Cu連結部分426在其等彼此相對定位後彼此接合。 Next, as shown in FIG. 16M, the surface of the first semiconductor component 410 on the side of the first Cu bonding portion 416 and the surface of the second semiconductor component 420 on the second Cu bonding portion 426 side are in contact with each other or bonded to each other. . Thereafter, the first Cu joining portion 416 and the corresponding second Cu joining portion 426 are joined to each other after they are positioned opposite each other.

接著，在其中該第一半導體部件410與該第二半導體部件420彼此接合之狀態中，使用諸如一加熱板之一加熱設備或一快速熱退火(RTA)設備以使所接合部件退火以使該第一Cu連結部分416與該第二Cu連結部分426彼此連結。特定言之，在(例如)大氣壓力之N2氛圍中或真空中將該等 所接合部件加熱至約100℃至400℃持續約5分鐘至兩個小時。 Next, in a state in which the first semiconductor component 410 and the second semiconductor component 420 are bonded to each other, a heating device such as a heating plate or a rapid thermal annealing (RTA) device is used to anneal the bonded component to make the The first Cu joint portion 416 and the second Cu joint portion 426 are coupled to each other. Specifically, the joined components are heated to about 100 ° C to 400 ° C for about 5 minutes to 2 hours in an N 2 atmosphere of, for example, atmospheric pressure or in a vacuum.

進一步言之，藉由此連結製程，在自該第一Cu連結部分416在該連結介面Sj側上之面區域內開始、包含未連結至該第二Cu連結部分426之面區域之區域中安置一介面Cu障壁膜428。更特定言之，如圖14中所示，在包含其中該第一Cu連結部分416與該第二層間絕緣膜425彼此相對之連結介面Sj之區域之區域中安置一介面Cu障壁膜428。 Further, by the joining process, the first Cu joining portion 416 is disposed in the region of the surface region on the side of the joining interface Sj and includes the region of the surface region not joined to the second Cu joining portion 426. An interface Cu barrier film 428. More specifically, as shown in FIG. 14, an interface Cu barrier film 428 is disposed in a region including a region in which the first Cu bonding portion 416 and the second interlayer insulating film 425 are opposed to each other in the bonding interface Sj.

在本工作實例中，以此方式實施一Cu-Cu連結製程。應注意，惟上述連結步驟除外，用於該半導體裝置401之製造技術可類似於用於諸如一固態影像擷取裝置(例如，參考日本專利特許公開案第2007-234725號)之一半導體裝置之一製造技術。 In this working example, a Cu-Cu joining process was carried out in this manner. It should be noted that, except for the above-described joining step, the manufacturing technique for the semiconductor device 401 can be similar to that used in a semiconductor device such as a solid-state image capturing device (for example, refer to Japanese Patent Laid-Open Publication No. 2007-234725). A manufacturing technique.

如上所述，在本工作實例之半導體裝置401中，在包含其中該第一半導體部件410之第一Cu連結部分416與該第二半導體部件420之第二層間絕緣膜425彼此相對之連結介面區域之區域中設置該介面Cu障壁膜428。因此，在本工作實例中，即使在連結半導體部件時發生連結錯位，該連結介面Sj上亦不會出現該Cu連結部分與該層間絕緣膜之間之一接觸區域，且亦可消除上述連結介面Sj上之電特性之故障。 As described above, in the semiconductor device 401 of the present working example, the connection interface region including the first interlayer insulating portion 416 of the first semiconductor member 410 and the second interlayer insulating film 425 of the second semiconductor member 420 is opposed to each other. The interface Cu barrier film 428 is disposed in the region. Therefore, in the present working example, even if a connection misalignment occurs when the semiconductor component is bonded, a contact area between the Cu connection portion and the interlayer insulating film does not occur on the connection interface Sj, and the connection interface can also be eliminated. The failure of the electrical characteristics on Sj.

進一步言之，在本工作實例中，使該第一Cu連結部分416在該連結側上之表面面積充分大於如上所述之第二Cu連結部分426之表面面積。因此，在本工作實例中，即使 在該第一半導體部件410與該第二半導體部件420彼此連結時發生錯位，亦不會改變該等Cu連結部分之間之接觸面積且因此不會改變其等之間之接觸電阻，且亦可抑制該半導體裝置401之電特性或效能之損害。特定言之，在本工作實例中，因為可抑制該連結介面Sj之接觸電阻之增加，所以可抑制該半導體裝置401之電力消耗之增加及處理速度之下降。 Further, in the present working example, the surface area of the first Cu joining portion 416 on the joining side is sufficiently larger than the surface area of the second Cu joining portion 426 as described above. So in this working example, even When the first semiconductor component 410 and the second semiconductor component 420 are connected to each other, misalignment occurs, and the contact area between the Cu bonding portions is not changed, and thus the contact resistance between the components is not changed, and The damage of the electrical characteristics or performance of the semiconductor device 401 is suppressed. In particular, in the present working example, since the increase in the contact resistance of the connection interface Sj can be suppressed, the increase in power consumption of the semiconductor device 401 and the decrease in the processing speed can be suppressed.

進一步言之，在本工作實例中，因為該介面Cu障壁膜428係設置於該第一Cu連結部分416與該第二層間絕緣膜425之間，所以可增強其等之間之緊密接觸力。因此，在本工作實例中，可增加該第一半導體部件410與該第二半導體部件420之間之連結強度。 Further, in the present working example, since the interface Cu barrier film 428 is disposed between the first Cu bonding portion 416 and the second interlayer insulating film 425, the close contact force between them can be enhanced. Therefore, in the present working example, the strength of the connection between the first semiconductor component 410 and the second semiconductor component 420 can be increased.

就前述而言，根據本工作實例，可設置該半導體裝置401，其中可進一步抑制該連結介面上之一電特性之劣化且具有一較高可靠度之一連結介面Sj。 As described above, according to the present working example, the semiconductor device 401 can be provided in which deterioration of electrical characteristics of one of the connection interfaces can be further suppressed and one of the connection interfaces Sj having a higher reliability can be provided.

<<2.第二工作實例>> <<2. Second working example>>

[半導體裝置之組態] [Configuration of Semiconductor Device]

圖17及圖18展示根據第三實施例之一第二工作實例之一半導體裝置之一般組態。特定言之，圖17展示一連結介面附近根據該第二工作實例之半導體裝置之一示意橫截面，且圖18展示該連結介面附近之一示意俯視圖並圖解說明Cu連結部分與一介面Cu障壁膜之一配置關係。應注意，在圖17及圖18中，為便於簡單描述僅展示一連結介面附近之一組態。進一步言之，在圖17及圖18中所示之本工作實例之 半導體裝置402中，藉由相同的元件符號標示類似於圖14及圖15中所示之第一工作實例之半導體裝置401之元件。 17 and 18 show a general configuration of a semiconductor device according to one of the second working examples of the third embodiment. In particular, FIG. 17 shows a schematic cross section of a semiconductor device according to the second working example in the vicinity of a bonding interface, and FIG. 18 shows a schematic top view of the vicinity of the bonding interface and illustrates a Cu bonding portion and an interface Cu barrier film. One of the configuration relationships. It should be noted that in FIGS. 17 and 18, only one configuration near a link interface is shown for ease of description. Further, in the working example shown in FIGS. 17 and 18 In the semiconductor device 402, elements of the semiconductor device 401 similar to the first working example shown in FIGS. 14 and 15 are denoted by the same component symbols.

首先參考圖17，該半導體裝置402包含作為一第一半導體區段之一第一半導體部件430及作為一第二半導體截面之一第二半導體部件440及作為一介面障壁膜或介面障壁區段之一介面Cu障壁膜450。 Referring first to FIG. 17, the semiconductor device 402 includes a first semiconductor component 430 as one of the first semiconductor segments and a second semiconductor component 440 as a second semiconductor cross section and as a via barrier film or interface barrier segment. An interface of the Cu barrier film 450.

該第一半導體部件430包含未展示之一第一半導體基板、一第一SiO2層411、一第一Cu配接線部分412、一第一Cu障壁膜413、一第一Cu擴散防止膜414、一第一層間絕緣膜415、一第一Cu連結部分416、一第一Cu障壁層417及一第一Cu晶種層431。 The first semiconductor component 430 includes a first semiconductor substrate, a first SiO 2 layer 411, a first Cu wiring portion 412, a first Cu barrier film 413, and a first Cu diffusion preventing film 414. A first interlayer insulating film 415, a first Cu connecting portion 416, a first Cu barrier layer 417, and a first Cu seed layer 431.

如可自圖17與圖14之間之比較認知，本工作實例中之第一半導體部件430經組態使得在該第一工作實例之第一半導體部件410中之第一Cu連結部分416與第一Cu障壁層417之間設置該第一Cu晶種層431。該第一半導體部件430之另一部分之組態類似於上述第一工作實例之第一半導體部件410之組態。因此，下文僅給定對該第一Cu晶種層431之組態之描述。 As can be appreciated from the comparison between FIG. 17 and FIG. 14, the first semiconductor component 430 in this working example is configured such that the first Cu junction portion 416 and the first semiconductor component 410 in the first working example are configured. The first Cu seed layer 431 is disposed between a Cu barrier layer 417. The configuration of the other portion of the first semiconductor component 430 is similar to the configuration of the first semiconductor component 410 of the first working example described above. Therefore, only the description of the configuration of the first Cu seed layer 431 is given below.

作為一晶種層之第一Cu晶種層431係如上所述般設置於該第一Cu連結部分416與該第一Cu障壁層417之間，且經設置以覆蓋該第一Cu連結部分416。 The first Cu seed layer 431 as a seed layer is disposed between the first Cu joint portion 416 and the first Cu barrier layer 417 as described above, and is disposed to cover the first Cu joint portion 416. .

該第一Cu晶種層431係由一Cu層或含有有可能與氧氣發生反應之一金屬材料之一Cu合金層形成。可使用(例如)更可能與氧氣而非氫氣發生反應之一金屬材料作為該第一Cu 晶種層431中含有之金屬材料。特定言之，可使用Fe、Mn、V、Cr、Mg、Si、Ce、Ti、Al等等之金屬材料。應注意，在所提及之金屬材料中，Mn、Mg、Ti或Al係適合用於該半導體裝置之一材料。進一步言之，就該連結介面Sj之配接線電阻之減小而言，特定較佳地使用Mn或Ti作為待包含於該第一Cu晶種層431中之金屬材料。 The first Cu seed layer 431 is formed of a Cu layer or a Cu alloy layer containing one of the metal materials which may react with oxygen. A metal material, for example, which is more likely to react with oxygen than hydrogen, can be used as the first Cu The metal material contained in the seed layer 431. Specifically, a metal material of Fe, Mn, V, Cr, Mg, Si, Ce, Ti, Al, or the like can be used. It should be noted that among the metal materials mentioned, Mn, Mg, Ti or Al is suitable for use as one of the materials of the semiconductor device. Further, in terms of the reduction of the wiring resistance of the bonding interface Sj, Mn or Ti is particularly preferably used as the metal material to be included in the first Cu seed layer 431.

該第二半導體部件440包含未展示之一第二半導體基板、一第二SiO2層421、一第二Cu配接線部分422、一第二Cu障壁膜423、一第二Cu擴散防止膜424、一第二層間絕緣膜425、一第二Cu連結部分426、一第二Cu障壁層427及一第二Cu晶種層441。 The second semiconductor component 440 includes a second semiconductor substrate, a second SiO 2 layer 421, a second Cu wiring portion 422, a second Cu barrier film 423, and a second Cu diffusion preventing film 424. A second interlayer insulating film 425, a second Cu connecting portion 426, a second Cu barrier layer 427, and a second Cu seed layer 441.

如自圖17與圖14明顯地認知，本工作實例中之第二半導體部件440經組態使得該第一工作實例之第二半導體部件420並不包含該介面Cu障壁膜428但包含設置在該第二Cu連結部分426與該第二Cu障壁層427之間之第二Cu晶種層441。該第二半導體部件440之另一部分之組態類似於上述第一工作實例之第二半導體部件420之組態。因此，下文僅描述該第二Cu晶種層441之組態。 As is apparent from FIGS. 17 and 14, the second semiconductor component 440 in this working example is configured such that the second semiconductor component 420 of the first working example does not include the interface Cu barrier film 428 but includes A second Cu seed layer 441 between the second Cu junction portion 426 and the second Cu barrier layer 427. The configuration of the other portion of the second semiconductor component 440 is similar to the configuration of the second semiconductor component 420 of the first working example described above. Therefore, only the configuration of the second Cu seed layer 441 will be described below.

該第二Cu晶種層441係如上所述般設置於該第二Cu連結部分426與該第二Cu障壁層427之間，且經形成以覆蓋該第二Cu連結部分426。類似於該第一Cu晶種層431，該第二Cu晶種層441係由一Cu層或含有有可能與氧氣發生反應之一金屬材料之一Cu合金層形成。進一步言之，該第二Cu晶種層441中含有之金屬材料可適當地選自關於該第一Cu 晶種層431描述之金屬材料。應注意，在本工作實例中，該第二Cu晶種層441中含有之金屬材料與該第一Cu晶種層431中含有之金屬材料相同。 The second Cu seed layer 441 is disposed between the second Cu bonding portion 426 and the second Cu barrier layer 427 as described above, and is formed to cover the second Cu bonding portion 426. Similar to the first Cu seed layer 431, the second Cu seed layer 441 is formed of a Cu layer or a Cu alloy layer containing one of the metal materials which may react with oxygen. Further, the metal material contained in the second Cu seed layer 441 may be appropriately selected from the first Cu The metal material described by the seed layer 431. It should be noted that in the present working example, the metal material contained in the second Cu seed layer 441 is the same as the metal material contained in the first Cu seed layer 431.

該介面Cu障壁膜450係在藉由該等Cu晶種層中含有之金屬材料與有關層間絕緣膜中(主要係該第二層間絕緣膜425中)之氧氣發生反應將該第一半導體部件430與該第二半導體部件440連結在一起時藉由加熱處理(即，藉由一退火製程)製造之一膜。換言之，該介面Cu障壁膜450係一自成形膜。因此，該介面Cu障壁膜450係形成於該連結介面Sj之一區域中(跨該區域該第一半導體部件430之第一Cu連結部分416與該第二半導體部件440之第二層間絕緣膜425彼此相對)，且係由(例如)MnOx、MgOx、TiOx或AlOx之氧化膜組態。 The interface Cu barrier film 450 is formed by reacting a metal material contained in the Cu seed layer with oxygen in an associated interlayer insulating film (mainly in the second interlayer insulating film 425) to bond the first semiconductor component 430. A film is formed by heat treatment (i.e., by an annealing process) when the second semiconductor member 440 is joined together. In other words, the interface Cu barrier film 450 is a self-forming film. Therefore, the interface Cu barrier film 450 is formed in a region of the bonding interface Sj (the first Cu bonding portion 416 of the first semiconductor component 430 and the second interlayer insulating film 425 of the second semiconductor component 440 across the region) Opposite each other, and is configured by an oxide film such as MnOx, MgOx, TiOx or AlOx.

應注意，在圖17中，為清晰地指示該介面Cu障壁膜450之形成位置，展示該介面Cu障壁膜450經形成以自該第二Cu連結部分426之一側面沿該連結介面Sj延伸至該第一Cu障壁層417之一側面。然而，該介面Cu障壁膜450之形成區域並不限於此。 It should be noted that, in FIG. 17, in order to clearly indicate the formation position of the interface Cu barrier film 450, the interface Cu barrier film 450 is formed to extend from the side of the second Cu bonding portion 426 along the bonding interface Sj to One side of the first Cu barrier layer 417. However, the formation region of the interface Cu barrier film 450 is not limited thereto.

該介面Cu障壁膜450係用於防止Cu自一Cu連結部分透過該第一Cu連結部分416與該第二層間絕緣膜425之間之相對區域擴散至一層間絕緣膜之一膜。因此，該介面Cu障壁膜450可沿該連結介面Sj至少形成於該第一Cu連結部分416與該第二層間絕緣膜425之間之相對區域中。應注意，可藉由(例如)調整在該第一半導體部件430與該第二半導體部件 440之間進行一連結製程時之退火條件、每一Cu晶種層中之一金屬材料之含量等等適當地設定該介面Cu障壁膜450之形成區域。 The interface Cu barrier film 450 serves to prevent Cu from diffusing from a Cu-connecting portion through a region between the first Cu connecting portion 416 and the second interlayer insulating film 425 to a film of an interlayer insulating film. Therefore, the interface Cu barrier film 450 can be formed at least in the opposite region between the first Cu bonding portion 416 and the second interlayer insulating film 425 along the bonding interface Sj. It should be noted that the first semiconductor component 430 and the second semiconductor component can be adjusted, for example. The formation condition of the interface Cu barrier film 450 is appropriately set by annealing conditions during a bonding process between 440, the content of one of the metal materials in each of the Cu seed layers, and the like.

[半導體裝置之製造技術] [Manufacturing Technology of Semiconductor Device]

現在，參考圖19A至圖19E描述本工作實例之半導體裝置402之一製造技術。應注意，圖19A至圖19D展示在個別步驟處製造之半導體部件之一Cu連結部分附近之示意橫截面，且圖19E圖解說明該第一半導體部件430與該第二半導體部件440之間之一連結製程之一方式。應注意，在下列描述中，適當地參考圖解說明該第一工作實例中之步驟之圖式(即，圖16A至圖16M)給定類似於用於根據該第一工作實例之一半導體裝置之製造技術之步驟之步驟之描述。 Now, a manufacturing technique of one of the semiconductor devices 402 of the present working example will be described with reference to FIGS. 19A to 19E. It should be noted that FIGS. 19A to 19D show schematic cross sections in the vicinity of a Cu joint portion of one of the semiconductor components manufactured at the individual steps, and FIG. 19E illustrates one of the first semiconductor component 430 and the second semiconductor component 440. One way to link processes. It should be noted that, in the following description, a reference to the diagram illustrating the steps in the first working example (ie, FIGS. 16A to 16M) is given similarly to the semiconductor device according to one of the first working examples. A description of the steps of the manufacturing process steps.

首先，在本工作實例中，類似於上文參考圖16A描述之第一工作實例中之第一半導體部件410之製造製程，按此順序在一第一SiO2層411上形成一第一Cu障壁膜413、一第一Cu配接線部分412及一第一Cu擴散防止膜414。接著，類似於上文參考圖16B及圖16C描述之第一工作實例中之第一半導體部件410之製造製程，在該第一Cu擴散防止膜414上形成作為一第一氧化物膜之一第一層間絕緣膜415及該第一層間絕緣膜415之一開口415a。應注意，在本工作實例中，該第一層間絕緣膜415之開口415a之開口直徑亦係(例如)約4微米至100微米。進一步言之，類似於上文參考圖16D描述之第一工作實例中之第一半導體部件410之製造製程，在該第一層間絕緣膜415及曝露於該第一層間絕 緣膜415之開口415a之第一Cu配接線部分412上形成一第一Cu障壁層417。 First, in the present working example, a first Cu barrier is formed on a first SiO 2 layer 411 in this order, similar to the manufacturing process of the first semiconductor component 410 in the first working example described above with reference to FIG. 16A. The film 413, a first Cu wiring portion 412, and a first Cu diffusion preventing film 414. Next, similar to the manufacturing process of the first semiconductor component 410 in the first working example described above with reference to FIGS. 16B and 16C, a first oxide film is formed on the first Cu diffusion preventing film 414. An interlayer insulating film 415 and one opening 415a of the first interlayer insulating film 415. It should be noted that in the present working example, the opening diameter of the opening 415a of the first interlayer insulating film 415 is also, for example, about 4 to 100 μm. Further, similar to the manufacturing process of the first semiconductor component 410 in the first working example described above with reference to FIG. 16D, the first interlayer insulating film 415 and the opening exposed to the first interlayer insulating film 415 A first Cu barrier layer 417 is formed on the first Cu wiring portion 412 of 415a.

接著，如圖19A中所示，在Ar/N2氛圍中使用(例如)一RF濺鍍方法之一技術在該第一Cu障壁層417上形成一厚度為約5奈米至50奈米之一第一Cu晶種層431。該第一Cu晶種層431可為(例如)一CuMn層、一CuAl層、一CuMg層或一CuTi層。 Next, as shown in FIG. 19A, a thickness of about 5 nm to 50 nm is formed on the first Cu barrier layer 417 using, for example, an RF sputtering method in an Ar/N 2 atmosphere. A first Cu seed layer 431. The first Cu seed layer 431 can be, for example, a CuMn layer, a CuAl layer, a CuMg layer, or a CuTi layer.

接著，如圖19B中所示，使用諸如一濺鍍方法或一電解電鍍方法之一技術在該第一Cu晶種層431上形成一Cu膜455。藉由此製程，該Cu膜455嵌入該第一層間絕緣膜415之開口415a之區域中。 Next, as shown in FIG. 19B, a Cu film 455 is formed on the first Cu seed layer 431 using a technique such as a sputtering method or an electrolytic plating method. By this process, the Cu film 455 is embedded in the region of the opening 415a of the first interlayer insulating film 415.

此後，在一氮氣氛圍中或真空中使用諸如一加熱板之一加熱設備或一燒結退火設備將上面形成該Cu膜455之半導體部件加熱至約100℃至400℃持續1分鐘至60分鐘。藉由此加熱製程，加固該Cu膜455以形成精細膜品質之一Cu膜455。 Thereafter, the semiconductor member on which the Cu film 455 is formed is heated to about 100 ° C to 400 ° C for 1 minute to 60 minutes using a heating device such as a heating plate or a sintering annealing apparatus in a nitrogen atmosphere or in a vacuum. By this heating process, the Cu film 455 is reinforced to form a Cu film 455 which is one of fine film qualities.

接著，如圖19C中所示，藉由一CMP方法移除該Cu膜455、該第一Cu晶種層431及該第一Cu障壁層417之不必要部分。特定言之，藉由一CMP方法拋光該Cu膜455之表面直到該第一層間絕緣膜415曝露於該表面。 Next, as shown in FIG. 19C, unnecessary portions of the Cu film 455, the first Cu seed layer 431, and the first Cu barrier layer 417 are removed by a CMP method. Specifically, the surface of the Cu film 455 is polished by a CMP method until the first interlayer insulating film 415 is exposed to the surface.

在本工作實例中，以如上所述之此一方式製造該第一半導體部件430。進一步言之，在本工作實例中，類似於上述第一半導體部件430製造該第二半導體部件440。 In the present working example, the first semiconductor component 430 is fabricated in the manner described above. Further, in the present working example, the second semiconductor component 440 is fabricated similarly to the first semiconductor component 430 described above.

圖19D展示根據本工作實例製造之第二半導體部件440之 一示意橫截面。然而，在本工作實例中，當在作為製造該半導體部件440中途之一第二氧化物膜之第二層間絕緣膜425中形成一開口時，使該開口之開口直徑小於上文參考圖16C描述之第一層間絕緣膜415中之開口直徑(即，小於約4微米至100微米)。更特定言之，該第二層間絕緣膜425中之開口之開口直徑被設定為約1微米至95微米。 19D shows a second semiconductor component 440 fabricated in accordance with the present working example. A schematic cross section. However, in the present working example, when an opening is formed in the second interlayer insulating film 425 which is one of the second oxide films in the middle of manufacturing the semiconductor member 440, the opening diameter of the opening is made smaller than that described above with reference to FIG. 16C. The opening diameter in the first interlayer insulating film 415 (i.e., less than about 4 micrometers to 100 micrometers). More specifically, the opening diameter of the opening in the second interlayer insulating film 425 is set to be about 1 μm to 95 μm.

此後，類似於該第一工作實例，皆以如上所述之此一方式製造之圖19C中所示之第一半導體部件430及圖19D中所示之第二半導體部件440彼此接合。 Thereafter, similarly to the first working example, the first semiconductor component 430 shown in Fig. 19C and the second semiconductor component 440 shown in Fig. 19D, which are manufactured in such a manner as described above, are bonded to each other.

特定言之，對該第一半導體部件430在該第一Cu連結部分416側上之表面及該第二半導體部件440在該第二Cu連結部分426側上之表面實施一還原製程以移除每一Cu連結部分之表面上之氧化物膜或氧化物以使純淨的Cu曝露於每一Cu連結部分之該表面。應注意，使用其中使用諸如甲酸之藥物溶液之一濕式蝕刻製程或其中使用(例如)Ar、NH3或H2之電漿之一乾式蝕刻製程作為此例項中之還原製程。 Specifically, a surface of the first semiconductor component 430 on the side of the first Cu bonding portion 416 and a surface of the second semiconductor component 440 on the second Cu bonding portion 426 side are subjected to a reduction process to remove each An oxide film or oxide on the surface of a Cu bonding portion to expose pure Cu to the surface of each Cu bonding portion. It should be noted that a dry etching process in which one of the drug solutions such as formic acid is used or a plasma in which, for example, Ar, NH 3 or H 2 is used is used as the reduction process in this example.

接著，如圖19E中所示，該第一半導體部件430在該第一Cu連結部分416側上之表面與該第二半導體部件440在該第二Cu連結部分426側上之表面彼此接觸或彼此接合。接著，在其中該第一半導體部件430與該第二半導體部件440彼此接合之狀態中，使用諸如一加熱板之一加熱設備或一RTA設備以使所接合部件退火以使該第一Cu連結部分416與該第二Cu連結部分426彼此連結。特定言之，在(例如)大氣壓力之N2氛圍中或真空中在約100℃至400℃下加熱所 接合部件持續約5分鐘至兩個小時。 Next, as shown in FIG. 19E, the surface of the first semiconductor component 430 on the side of the first Cu bonding portion 416 and the surface of the second semiconductor component 440 on the side of the second Cu bonding portion 426 are in contact with each other or each other. Engage. Next, in a state in which the first semiconductor component 430 and the second semiconductor component 440 are bonded to each other, a heating device such as a heating plate or an RTA device is used to anneal the bonded component to make the first Cu bonded portion 416 and the second Cu joining portion 426 are coupled to each other. Specifically, the joined component is heated in an N 2 atmosphere of, for example, atmospheric pressure or in a vacuum at about 100 ° C to 400 ° C for about 5 minutes to 2 hours.

進一步言之，當進行上述連結製程時，該等Cu晶種層中之金屬材料(諸如Mn、Mg、Ti或Al)選擇性地與該等層間絕緣膜中(特別係該第二層間絕緣膜425中)之氧氣發生反應。因此，在其中該第一半導體部件430之第一Cu連結部分416與該第二半導體部件440之第二層間絕緣膜425彼此相對之連結介面Sj之一區域中形成一介面Cu障壁膜450。特定言之，藉由上述連結製程，該介面Cu障壁膜450係設置於自該第一Cu連結部分416在該連結介面Si側上之面區域內開始包含其中該第一Cu連結部分416未連結至該第二Cu連結部分426之面區域之一區域中。 Further, when the bonding process is performed, a metal material (such as Mn, Mg, Ti or Al) in the Cu seed layer is selectively associated with the interlayer insulating film (particularly the second interlayer insulating film) Oxygen in 425) reacts. Therefore, an interface Cu barrier film 450 is formed in a region of the bonding interface Sj in which the first Cu bonding portion 416 of the first semiconductor component 430 and the second interlayer insulating film 425 of the second semiconductor component 440 oppose each other. Specifically, the interface Cu barrier film 450 is disposed from the surface region of the first Cu bonding portion 416 on the side of the bonding interface Si, wherein the first Cu bonding portion 416 is not connected. To one of the area regions of the second Cu joint portion 426.

在本工作實例中，以如上所述之此一方式實施一Cu-Cu連結製程。應注意，惟上述連結步驟除外，該半導體裝置402之製造製程可類似於諸如一固態影像擷取裝置之一半導體裝置之一現有製造技術中之製造製程，且類似於(例如)日本專利特許公開案第2007-234725號中揭示之製造技術。 In the present working example, a Cu-Cu joining process is carried out in such a manner as described above. It should be noted that, except for the above-described joining step, the manufacturing process of the semiconductor device 402 can be similar to the manufacturing process in the prior art manufacturing technology of one of the semiconductor devices such as a solid-state image capturing device, and is similar to, for example, Japanese Patent Laid-Open Manufacturing technique disclosed in No. 2007-234725.

如上所述，在本工作實例之半導體裝置402中，類似於上述第一工作實例，亦在其中該第一半導體部件430之第一Cu連結部分416與該第二半導體部件440之第二層間絕緣膜425彼此相對之連結介面Sj之區域中設置該介面Cu障壁膜450。因此，在本工作實例中，亦達成類似於藉由該第一工作實例達成之效果之若干效果。 As described above, in the semiconductor device 402 of the present working example, similar to the first working example described above, the first Cu bonding portion 416 of the first semiconductor component 430 and the second layer of the second semiconductor component 440 are also insulated. The interface Cu barrier film 450 is disposed in a region of the film 425 opposite to the bonding interface Sj. Therefore, in this working example, several effects similar to those achieved by the first working example are also achieved.

進一步言之，在其中設置一Cu晶種層且藉由如本工作實 例中之一電解電鍍方法在該Cu晶種層上形成一Cu連結區段之情況中，該Cu晶種層中之Cu用作一Cu電鍍膜之一核心。因此，在本工作實例中，可增強該Cu連結部分與相關聯之層間絕緣膜之間之緊密接觸力。 Further, a Cu seed layer is disposed therein and In the case where one electrolytic plating method forms a Cu junction portion on the Cu seed layer, Cu in the Cu seed layer serves as a core of a Cu plating film. Therefore, in the present working example, the close contact force between the Cu joint portion and the associated interlayer insulating film can be enhanced.

<<3.第三工作實例>> <<3. Third working example>>

[半導體裝置之組態] [Configuration of Semiconductor Device]

圖20及圖21展示根據本技術之第三實施例之一第三工作實例之一半導體裝置之一般組態。特定言之，圖20展示根據本工作實例之半導體裝置之一連結介面附近之一示意橫截面，且圖21展示該連結介面附近之一示意俯視圖並圖解說明Cu連結部分與下文描述之一第二Cu障壁層之一介面層部分之間之一配置關係。應注意，在圖20及圖21中，為簡化描述，僅展示一連結介面之一組態。進一步言之，在圖20及圖21中所示之本工作實例之半導體裝置403中，藉由相同的元件符號標示類似於上文參考圖14及圖15中描述之第一工作實例之半導體裝置401之元件。 20 and 21 show a general configuration of a semiconductor device according to one of the third working examples of the third embodiment of the present technology. In particular, FIG. 20 shows a schematic cross section of a vicinity of a bonding interface of a semiconductor device according to the present working example, and FIG. 21 shows a schematic top view of the vicinity of the bonding interface and illustrates a Cu bonding portion and one of the following descriptions. One of the arrangement relationships between one of the interface layers of the Cu barrier layer. It should be noted that in FIGS. 20 and 21, only one configuration of a link interface is shown for simplicity of description. Further, in the semiconductor device 403 of the present working example shown in FIGS. 20 and 21, the semiconductor device similar to the first working example described above with reference to FIGS. 14 and 15 is denoted by the same component symbol. 401 components.

首先參考圖20，該半導體裝置403包含作為一第一半導體區段之一第一半導體部件410及作為一第二半導體區段之一第二半導體部件460。應注意，本工作實例之半導體裝置403中之第一半導體部件410具有類似於上文參考圖14描述之第一工作實例之半導體裝置401中之一組態之一組態。因此，本文省略該第一半導體部件410之重疊描述以避免冗餘。 Referring first to Figure 20, the semiconductor device 403 includes a first semiconductor component 410 as one of the first semiconductor segments and a second semiconductor component 460 as one of the second semiconductor segments. It should be noted that the first semiconductor component 410 in the semiconductor device 403 of the present working example has a configuration similar to one of the configurations of the semiconductor device 401 of the first working example described above with reference to FIG. Therefore, overlapping descriptions of the first semiconductor component 410 are omitted herein to avoid redundancy.

該第二半導體部件460包含未展示之一第二半導體基 板、一第二SiO2層421、一第二Cu配接線部分422、一第二Cu障壁膜423、一第二Cu擴散防止膜424、一第二層間絕緣膜425、一第二Cu連結部分426及作為一障壁金屬層之一第二Cu障壁層461。 The second semiconductor component 460 includes a second semiconductor substrate, a second SiO 2 layer 421, a second Cu wiring portion 422, a second Cu barrier film 423, and a second Cu diffusion preventing film 424. A second interlayer insulating film 425, a second Cu connecting portion 426, and a second Cu barrier layer 461 as one of the barrier metal layers.

如自圖20與圖14之間之比較認知，本工作實例中之第二半導體部件460經組態使得在該第一工作實例中之第二半導體部件420並不包含該介面Cu障壁層428但該第二Cu障壁層427之組態改變。該第二半導體部件460之另一部分之組態類似於上述第一工作實例之第二半導體部件420之對應部分之組態。因此，下文僅描述第二Cu障壁層461之組態。 As is apparent from the comparison between FIG. 20 and FIG. 14, the second semiconductor component 460 in this working example is configured such that the second semiconductor component 420 in the first working example does not include the interface Cu barrier layer 428. The configuration of the second Cu barrier layer 427 changes. The configuration of the other portion of the second semiconductor component 460 is similar to the configuration of the corresponding portion of the second semiconductor component 420 of the first working example described above. Therefore, only the configuration of the second Cu barrier layer 461 will be described below.

參考圖20，該第二Cu障壁層461包含經設置以覆蓋該第二Cu連結部分426之一障壁本體部分461a及經形成以沿一連結介面Sj自該連結介面Sj側上之障壁本體部分461a之一端部分延伸之一介面層部分461b(其作為一介面障壁部分)。 Referring to FIG. 20, the second Cu barrier layer 461 includes a barrier body portion 461a disposed to cover the second Cu bonding portion 426 and a barrier body portion 461a formed on the side of the bonding interface Sj along a bonding interface Sj. One end portion extends one of the interface layer portions 461b (which acts as a dielectric barrier portion).

特定言之，在本工作實例中，該第二Cu障壁層461之介面層部分461b被安置在其中該第一半導體部件410之第一Cu連結部分416與該第二半導體部件460之第二層間絕緣膜425彼此相對之連結介面Sj之一區域中。進一步言之，該第二Cu障壁層461之介面層部分461b防止Cu透過該第一Cu連結部分416與該第二層間絕緣膜425之相對區域自該Cu連結部分擴散至該層間絕緣膜中。因此，在本工作實例中，該介面層部分461b在沿該連結介面Sj之一方向上之寬度， 經設定使得即使在連結時發生估計最大錯位，該連結介面Sj上亦不一定出現該第一Cu連結部分416與該第二層間絕緣膜425之間之一接觸區域。應注意，類似於上述第一工作實例，該第二Cu障壁層461係由(例如)Ti、Ta、Ru或其等之氮化物組態。 Specifically, in the working example, the interface layer portion 461b of the second Cu barrier layer 461 is disposed between the first Cu bonding portion 416 of the first semiconductor component 410 and the second layer of the second semiconductor component 460. The insulating film 425 is opposed to each other in a region of the interface Sj. Further, the interface layer portion 461b of the second Cu barrier layer 461 prevents Cu from diffusing from the Cu-joining portion into the interlayer insulating film from the opposite region of the first Cu-bonding portion 416 and the second interlayer insulating film 425. Therefore, in the working example, the interface layer portion 461b is in a width along one of the connection interfaces Sj, It is set such that even if the estimated maximum misalignment occurs at the time of connection, a contact area between the first Cu connection portion 416 and the second interlayer insulating film 425 does not necessarily appear on the connection interface Sj. It should be noted that similar to the first working example described above, the second Cu barrier layer 461 is configured by, for example, a nitride of Ti, Ta, Ru, or the like.

[半導體裝置之製造技術] [Manufacturing Technology of Semiconductor Device]

現在，參考圖22A至圖22H描述本工作實例之半導體裝置403之一製造技術。應注意，圖22A至圖22G展示個別步驟處製造之半導體部件之一Cu連結部分附近之示意橫截面，且圖22H圖解說明第一半導體部件410與第二半導體部件460之一連結製程之一方式。進一步言之，在類似於上述第一工作實例之半導體裝置之製造技術之步驟之步驟描述中，適當地參考該第一工作實例中之步驟處之圖式(即，圖16A至圖16M)。進一步言之，因為本工作實例中之第一半導體部件410之製造技術類似於上文參考圖16A至圖16F描述之第一工作實例中之半導體部件之製造技術，所以此處省略該第一半導體部件410之製造技術之描述以避免冗餘。因此，下文描述該第二半導體部件460之一製造技術及一Cu-Cu連結技術。 Now, a manufacturing technique of one of the semiconductor devices 403 of the present working example will be described with reference to FIGS. 22A to 22H. It should be noted that FIGS. 22A to 22G show schematic cross sections in the vicinity of a Cu joint portion of one of the semiconductor components manufactured at the respective steps, and FIG. 22H illustrates one of the ways in which the first semiconductor component 410 and the second semiconductor component 460 are joined together. . Further, in the description of the steps of the steps of the manufacturing technique of the semiconductor device similar to the above-described first working example, the drawings at the steps in the first working example (i.e., Figs. 16A to 16M) are appropriately referred to. Further, since the manufacturing technique of the first semiconductor component 410 in the present working example is similar to the manufacturing technique of the semiconductor component in the first working example described above with reference to FIGS. 16A to 16F, the first semiconductor is omitted here. The description of the manufacturing techniques of component 410 avoids redundancy. Therefore, a manufacturing technique of the second semiconductor component 460 and a Cu-Cu bonding technique will be described below.

首先，在本工作實例中，以類似於上文參考圖16A描述之第一工作實例之第一半導體部件410之製造步驟之一方式，按此順序在一第二SiO2層421上形成一第二Cu障壁膜423、一第二Cu配接線部分422及一第二Cu擴散防止膜424。接著，以類似於上文參考圖16B描述之第一工作實例 中之第一半導體部件410之製造步驟之一方式，在該第二Cu擴散防止膜424上形成一第二層間絕緣膜425。 First, in the present working example, a first SiO 2 layer 421 is formed in this order in a manner similar to the manufacturing steps of the first semiconductor component 410 of the first working example described above with reference to FIG. 16A. The second Cu barrier film 423, a second Cu wiring portion 422, and a second Cu diffusion preventing film 424. Next, a second interlayer insulating film 425 is formed on the second Cu diffusion preventing film 424 in a manner similar to the manufacturing steps of the first semiconductor member 410 in the first working example described above with reference to FIG. 16B.

接著，如圖22A中所示，在該第二層間絕緣膜425上形成一光阻膜456。接著，使用一光微影技術對該光阻膜456實施一圖案化製程以移除一第二Cu障壁層461之一形成區域中之光阻膜456以形成一開口456a。因此，該第二層間絕緣膜425曝露於該光阻膜456之開口456a。 Next, as shown in FIG. 22A, a photoresist film 456 is formed on the second interlayer insulating film 425. Then, a photoresist process is performed on the photoresist film 456 by using a photolithography technique to remove the photoresist film 456 in a region where the second Cu barrier layer 461 is formed to form an opening 456a. Therefore, the second interlayer insulating film 425 is exposed to the opening 456a of the photoresist film 456.

接著，在該開口456a側上使用磁控管類型之一已知蝕刻設備對上面形成該光阻膜456之半導體部件之表面實施一乾式蝕刻製程。因此，蝕刻曝露於該光阻膜456之開口456a之第二層間絕緣膜425之區域。此後，藉由該蝕刻移除該第二層間絕緣膜425約10奈米至50奈米。因此，如圖22B中所示，在該第二層間絕緣膜425之表面上形成一深度為約10奈米至50奈米之一凹陷部分425b。 Next, a dry etching process is performed on the surface of the semiconductor member on which the photoresist film 456 is formed using an etching apparatus known as one of the magnetron types on the side of the opening 456a. Therefore, the region exposed to the second interlayer insulating film 425 of the opening 456a of the photoresist film 456 is etched. Thereafter, the second interlayer insulating film 425 is removed by the etching by about 10 nm to 50 nm. Therefore, as shown in Fig. 22B, a recessed portion 425b having a depth of about 10 nm to 50 nm is formed on the surface of the second interlayer insulating film 425.

此後，對已實施該蝕刻之面實施(例如)其中使用氧氣(O2)電漿之一灰化製程及其中使用有機胺基藥物之溶液之一沖洗製程。藉由該等製程，移除留在該第二層間絕緣膜425上之光阻膜456及該蝕刻製程中產生之殘留沈積物。 Thereafter, the surface on which the etching has been performed is subjected to, for example, one of a solution in which an oxygen-based (O 2 ) plasma is used in the ashing process and a solution in which the organic amine-based drug is used. By the processes, the photoresist film 456 remaining on the second interlayer insulating film 425 and the residual deposit generated in the etching process are removed.

接著，如圖22C中所示，在該第二層間絕緣膜425上形成一光阻膜457。接著，使用一光微影技術對該光阻膜457實施一圖案化製程以移除一第二Cu障壁層461之一障壁本體部分461a之一形成區域中之光阻膜457以形成一開口457a。因此，該第二層間絕緣膜425之凹陷部分425b之底部曝露於該光阻膜457之開口457a。 Next, as shown in FIG. 22C, a photoresist film 457 is formed on the second interlayer insulating film 425. Then, a photoresist process is performed on the photoresist film 457 by using a photolithography technique to remove the photoresist film 457 in a region of the barrier body portion 461a of the second Cu barrier layer 461 to form an opening 457a. . Therefore, the bottom of the recessed portion 425b of the second interlayer insulating film 425 is exposed to the opening 457a of the photoresist film 457.

此後，在該開口457a側上使用磁控管類型之一已知蝕刻設備對上面形成該光阻膜457之半導體部件之表面實施一乾式蝕刻製程。因此，部分蝕刻曝露於該光阻膜457之開口457a之第二層間絕緣膜425之凹陷部分425b之區域。 Thereafter, a dry etching process is performed on the surface of the semiconductor member on which the photoresist film 457 is formed on the side of the opening 457a using an etching apparatus known in the magnetron type. Therefore, a partial etching is exposed to a region of the recessed portion 425b of the second interlayer insulating film 425 of the opening 457a of the photoresist film 457.

在此蝕刻製程中，如圖22D中所示，移除該開口457a之區域中之第二層間絕緣膜425及第二Cu擴散防止膜424以使該第二Cu配接線部分422曝露於該第二層間絕緣膜425之一開口425a。進一步言之，在本工作實例中，該第二層間絕緣膜425之開口425a之開口直徑被設定為(例如)約1微米至95微米。應注意，在此蝕刻製程中未移除該第二層間絕緣膜425之第二層間絕緣膜425之凹陷部分425b之區域係該第二Cu障壁層461之介面層部分461b之一形成區域。 In this etching process, as shown in FIG. 22D, the second interlayer insulating film 425 and the second Cu diffusion preventing film 424 in the region of the opening 457a are removed to expose the second Cu wiring portion 422 to the first portion. One of the two interlayer insulating films 425 has an opening 425a. Further, in the present working example, the opening diameter of the opening 425a of the second interlayer insulating film 425 is set to, for example, about 1 μm to 95 μm. It should be noted that the region where the recess portion 425b of the second interlayer insulating film 425 of the second interlayer insulating film 425 is not removed in this etching process is one of the formation regions of the interface layer portion 461b of the second Cu barrier layer 461.

此後，對已實施該蝕刻製程之面實施(例如)其中使用氧氣(O2)電漿之一灰化製程及其中使用有機胺基藥物之溶液之一沖洗製程。藉由該等製程，移除留在該第二層間絕緣膜425上之光阻膜457及該蝕刻製程中產生之殘留沈積物。 Thereafter, the surface on which the etching process has been carried out is subjected to, for example, one of a solution in which an oxygen-based (O 2 ) plasma is used in the ashing process and a solution in which the organic amine-based drug is used. By the processes, the photoresist film 457 remaining on the second interlayer insulating film 425 and the residual deposit generated in the etching process are removed.

接著，如圖22E中所示，在該第二層間絕緣膜425及曝露於該第二層間絕緣膜425之開口425a之第二Cu配接線部分422上形成由Ti、Ta、Ru或其等氮化物之任一者製成之一第二Cu障壁層461。特定言之，使用舉例而言諸如一RF濺鍍方法之一技術以在Ar/N2氛圍中於該第二層間絕緣膜425及該第二Cu配接線部分422上形成一厚度為約5奈米至50奈米之一第二Cu障壁層461。藉由此製程，在曝露於該第二層間絕緣膜425之開口425a之第二Cu配接線部分422上及該 第二層間絕緣膜425之一側面上形成一障壁本體部分461a。進一步言之，藉由上述製程，在該第二層間絕緣膜425之凹陷部分425b上形成一介面層部分461b。 Next, as shown in FIG. 22E, Ti, Ta, Ru or the like is formed on the second interlayer insulating film 425 and the second Cu wiring portion 422 exposed to the opening 425a of the second interlayer insulating film 425. Any one of the compounds is made of one of the second Cu barrier layers 461. Specifically, a technique such as an RF sputtering method is used to form a thickness of about 5 nm on the second interlayer insulating film 425 and the second Cu wiring portion 422 in an Ar/N 2 atmosphere. One to 50 nanometers of the second Cu barrier layer 461. By this process, a barrier body portion 461a is formed on the second Cu wiring portion 422 exposed to the opening 425a of the second interlayer insulating film 425 and on one side of the second interlayer insulating film 425. Further, an interface layer portion 461b is formed on the recessed portion 425b of the second interlayer insulating film 425 by the above process.

此後，如圖22F中所示，使用(例如)一濺鍍方法或一電解電鍍方法之一技術在該第二Cu障壁層461上形成一Cu膜458。藉由此製程，該Cu膜458嵌入該第二層間絕緣膜425之開口425a之區域中。 Thereafter, as shown in FIG. 22F, a Cu film 458 is formed on the second Cu barrier layer 461 using, for example, a sputtering method or an electrolytic plating method. By this process, the Cu film 458 is embedded in the region of the opening 425a of the second interlayer insulating film 425.

接著，在氮氣氛圍中或真空中使用諸如一加熱板之一加熱設備或一燒結退火設備在約100℃至400℃下加熱上面形成該Cu膜458之半導體部件持續1分鐘至60分鐘。藉由此加熱製程，加固該Cu膜458以形成精細膜品質之一Cu膜458。 Next, the semiconductor member on which the Cu film 458 is formed is heated at about 100 ° C to 400 ° C for 1 minute to 60 minutes in a nitrogen atmosphere or in a vacuum using a heating apparatus such as a hot plate or a sintering annealing apparatus. By this heating process, the Cu film 458 is reinforced to form a Cu film 458 which is one of fine film qualities.

接著，如圖22G中所示，藉由一化學機械拋光(CMP)方法移除該Cu膜458及該第二Cu障壁層461之不必要部分。此後，該CMP方法之處理條件經調整使得該介面層部分461b仍可留在該第二層間絕緣膜425之凹陷部分425b上。特定言之，藉由一CMP方法拋光該Cu膜458之表面直到該第二層間絕緣膜425曝露於該表面。在本工作實例中，以如上所述之此一方式製造一第二半導體部件460。 Next, as shown in FIG. 22G, unnecessary portions of the Cu film 458 and the second Cu barrier layer 461 are removed by a chemical mechanical polishing (CMP) method. Thereafter, the processing conditions of the CMP method are adjusted so that the interface layer portion 461b can remain on the recessed portion 425b of the second interlayer insulating film 425. Specifically, the surface of the Cu film 458 is polished by a CMP method until the second interlayer insulating film 425 is exposed to the surface. In the present working example, a second semiconductor component 460 is fabricated in the manner described above.

此後，以上述之此一方式製造之圖22G中所示之第二半導體部件460及以類似於上述第一工作實例之一方式製造之圖16F中所示之第一半導體部件410以類似於該第一工作實例中之一方式彼此接合。 Thereafter, the second semiconductor component 460 shown in FIG. 22G fabricated in the above manner and the first semiconductor component 410 shown in FIG. 16F manufactured in a manner similar to the first working example described above are similar to the One of the first working examples is joined to each other.

特定言之，對該第一半導體部件410在該第一Cu連結部 分416側上之表面及該第二半導體部件460在該第二Cu連結部分426側上之表面實施一還原製程以移除每一Cu連結部分之表面上之氧化物膜或氧化物以使純淨的Cu曝露於每一Cu連結部分之表面。應注意，使用其中使用諸如甲酸之藥物溶液之一濕式蝕刻製程或其中使用(例如)Ar、NH3或H2之電漿之一乾式蝕刻製程作為此例項中之還原製程。 Specifically, a surface of the first semiconductor component 410 on the side of the first Cu bonding portion 416 and a surface of the second semiconductor component 460 on the second Cu bonding portion 426 side are subjected to a reduction process to remove each An oxide film or oxide on the surface of a Cu junction portion exposes pure Cu to the surface of each Cu junction portion. It should be noted that a dry etching process in which one of the drug solutions such as formic acid is used or a plasma in which, for example, Ar, NH 3 or H 2 is used is used as the reduction process in this example.

接著，如圖22H中所示，該第一半導體部件410在該第一Cu連結部分416側上之表面與該第二半導體部件460在該第二Cu連結部分426側上之表面彼此接觸或彼此接合。接著，在其中該第一半導體部件410與該第二半導體部件460彼此接合之狀態中，使用諸如一加熱板之一加熱設備或一RTA設備使所接合部件退火以使該第一Cu連結部分416與該第二Cu連結部分426彼此連結。特定言之，在(例如)大氣壓力之N2氛圍中或真空中於約100℃至400℃下加熱所接合部件持續約5分鐘至兩個小時。 Next, as shown in FIG. 22H, the surface of the first semiconductor component 410 on the side of the first Cu bonding portion 416 and the surface of the second semiconductor component 460 on the second Cu bonding portion 426 side are in contact with each other or each other. Engage. Next, in a state in which the first semiconductor component 410 and the second semiconductor component 460 are bonded to each other, the bonded component is annealed using a heating device such as a heating plate or an RTA device to make the first Cu bonding portion 416 The second Cu joining portions 426 are coupled to each other. Specifically, the joined component is heated at about 100 ° C to 400 ° C for about 5 minutes to 2 hours in an N 2 atmosphere of, for example, atmospheric pressure or in a vacuum.

進一步言之，藉由上述連結製程，在自該第一Cu連結部分416在該連結介面Sj側上之一面區域內開始包含未連結至該第二Cu連結部分426之一面區域的區域中安置該第二Cu障壁層461之一介面層部分461b。更特定言之，如圖20中所示，在包含其中該第一Cu連結部分416與該第二層間絕緣膜425彼此相對之連結介面Sj之區域之區域中安置該第二Cu障壁層461之一介面層部分461b。 Further, by the bonding process, the first Cu connecting portion 416 is disposed in a region including a surface region of the second Cu connecting portion 426 from a surface region on the side of the connecting interface Sj. One of the second Cu barrier layers 461 is an interface layer portion 461b. More specifically, as shown in FIG. 20, the second Cu barrier layer 461 is disposed in a region including a region in which the first Cu bonding portion 416 and the second interlayer insulating film 425 are opposed to each other in the bonding interface Sj. An interface layer portion 461b.

在本工作實例中，以如上所述之此一方式實施一Cu-Cu連結製程。應注意，惟上述連結步驟除外，該半導體裝置 402之製造技術可類似於諸如一固態影像擷取裝置之一半導體裝置之一現有製造技術，且類似於(例如)日本專利特許公開案第2007-234725號中揭示之製造技術。 In the present working example, a Cu-Cu joining process is carried out in such a manner as described above. It should be noted that except for the above connection step, the semiconductor device The fabrication technique of 402 can be similar to the prior art fabrication techniques of one of the semiconductor devices such as a solid-state image capture device, and is similar to the fabrication techniques disclosed in, for example, Japanese Patent Laid-Open Publication No. 2007-234725.

如上所述，在本工作實例中，類似於上述第一工作實例，亦在其中該第一半導體部件410之第一Cu連結部分416與該第二半導體部件460之第二層間絕緣膜425彼此相對之連結介面Sj之區域中設置該第二Cu障壁層461之介面層部分461b。因此，在本工作實例中，亦達成類似於藉由該第一工作實例達成之效果之若干效果。 As described above, in the present working example, similar to the first working example described above, the first Cu-bonding portion 416 of the first semiconductor component 410 and the second interlayer insulating film 425 of the second semiconductor component 460 are also opposed to each other. The interface layer portion 461b of the second Cu barrier layer 461 is disposed in a region of the connection interface Sj. Therefore, in this working example, several effects similar to those achieved by the first working example are also achieved.

<<4.各種修改及參考實例>> <<4. Various modifications and reference examples>>

現在，描述上述工作實例之半導體裝置之各種修改。 Now, various modifications of the semiconductor device of the above working example will be described.

[修改1] [Modification 1]

在上文參考圖14描述之第一工作實例之半導體裝置401中，雖然該第二Cu擴散防止膜424、該第二層間絕緣膜425及該介面Cu障壁層428係設置於該第二半導體部件420之第二Cu配接線部分422上，但是本發明並不限於此組態。例如，可使用其中僅設置在該第二Cu配接線部分422上之一介面Cu障壁膜之另一組態。 In the semiconductor device 401 of the first working example described above with reference to FIG. 14, the second Cu diffusion preventing film 424, the second interlayer insulating film 425, and the interface Cu barrier layer 428 are disposed on the second semiconductor component. The second Cu of 420 is assigned to the wiring portion 422, but the invention is not limited to this configuration. For example, another configuration in which only one of the interface Cu barrier films is disposed on the second Cu wiring portion 422 can be used.

圖23中展示該組態之一實例(即，一修改1)。圖23特別展示該連結介面Sj附近之修改1之一半導體裝置404之一示意橫截面。應注意，在該修改1之半導體裝置404中，藉由相同的元件符號標示類似於上文參考圖14描述之第一工作實例之半導體裝置401之元件。 An example of this configuration (i.e., a modification 1) is shown in FIG. Figure 23 particularly shows a schematic cross section of one of the modified semiconductor devices 404 in the vicinity of the bonding interface Sj. It should be noted that in the semiconductor device 404 of the modification 1, the elements of the semiconductor device 401 similar to the first working example described above with reference to FIG. 14 are denoted by the same element symbols.

參考圖23，該半導體裝置404包含一第一半導體部件410 及一第二半導體部件470。應注意，因為本修改1之半導體裝置404之第一半導體部件410具有類似於上文參考圖14描述之第一工作實例之半導體部件之一組態，所以本文省略該第一半導體部件410之描述以避免冗餘。 Referring to FIG. 23, the semiconductor device 404 includes a first semiconductor component 410. And a second semiconductor component 470. It should be noted that since the first semiconductor component 410 of the semiconductor device 404 of the modification 1 has one configuration similar to the semiconductor component of the first working example described above with reference to FIG. 14, the description of the first semiconductor component 410 is omitted herein. To avoid redundancy.

該第二半導體部件470包含未展示之一第二半導體基板、一第二SiO2層421、一第二Cu配接線部分422、一第二Cu障壁膜423、作為一介面障壁膜或介面障壁區段之一介面Cu障壁膜471、一第二Cu連結部分426及一第二Cu障壁層427。應注意，該第二半導體部件470之非介面Cu障壁膜471之另一部分之組態類似於上述第一工作實例中之第二半導體部件420之對應部分。 The second semiconductor component 470 includes a second semiconductor substrate, a second SiO 2 layer 421, a second Cu wiring portion 422, a second Cu barrier film 423, and a barrier film or interface barrier region. One of the segments interfaces a Cu barrier film 471, a second Cu junction portion 426, and a second Cu barrier layer 427. It should be noted that the configuration of the other portion of the non-interface Cu barrier film 471 of the second semiconductor component 470 is similar to the corresponding portion of the second semiconductor component 420 of the first working example described above.

作為一Cu擴散防止膜之介面Cu障壁膜471設置於該第二SiO2層421、該第二Cu配接線部分422及該第二Cu障壁膜423上，且以覆蓋該第二Cu障壁層427之一側部分之一方式設置。因此，在本實例中，該介面Cu障壁膜471不僅防止Cu自該Cu連結部分擴散至該層間絕緣膜中，而且起到類似於上述該第一工作實例之第二半導體部件420之第二Cu擴散防止膜424及第二層間絕緣膜425之作用。 An interface Cu barrier film 471 as a Cu diffusion preventing film is disposed on the second SiO 2 layer 421, the second Cu wiring portion 422, and the second Cu barrier film 423, and covers the second Cu barrier layer 427. One of the side sections is set in one way. Therefore, in the present example, the interface Cu barrier film 471 not only prevents Cu from diffusing into the interlayer insulating film from the Cu bonding portion, but also functions as a second Cu similar to the second semiconductor component 420 of the first working example described above. The diffusion preventing film 424 and the second interlayer insulating film 425 function.

應注意，類似於該第一工作實例中之介面Cu障壁膜428，該介面Cu障壁膜471可由諸如SiN、SiON、SiCN或有機樹脂之一材料形成。 It should be noted that similar to the interface Cu barrier film 428 in the first working example, the interface Cu barrier film 471 may be formed of a material such as SiN, SiON, SiCN or an organic resin.

可以(例如)下方式製造本修改中之第二半導體部件470。首先，以類似於上文參考圖16A描述之第一工作實例之第一半導體部件410之製造步驟處之一方式按此順序在 一第二SiO2層421上形成一第二Cu障壁膜423及一第二Cu配接線部分422。接著，在該第二SiO2層421、該第二Cu配接線部分422及該第二Cu障壁膜423上形成一厚度為約5奈米至500奈米之一介面Cu障壁膜471。 The second semiconductor component 470 of the present modification can be fabricated, for example, in the following manner. First, a second Cu barrier film 423 is formed on the second SiO 2 layer 421 in this order in a manner similar to the manufacturing step of the first semiconductor component 410 of the first working example described above with reference to FIG. 16A. A second Cu is assigned to the wiring portion 422. Next, an interface Cu barrier film 471 having a thickness of about 5 nm to 500 nm is formed on the second SiO 2 layer 421, the second Cu wiring portion 422, and the second Cu barrier film 423.

接著，如圖24中所示，在該介面Cu障壁膜471上形成一光阻膜459。此後，使用一光微影技術以對該光阻膜459實施一圖案化製程以移除該第二Cu連結部分426之一形成區域中之光阻膜459以形成一開口459a。因此，該介面Cu障壁膜471曝露於該光阻膜459之開口459a。此後，實施上文參考圖16I至圖16L描述之第一工作實例中之第二半導體部件420之製造步驟以製造本修改之一第二半導體部件470。 Next, as shown in FIG. 24, a photoresist film 459 is formed on the interface Cu barrier film 471. Thereafter, a photolithography technique is used to perform a patterning process on the photoresist film 459 to remove the photoresist film 459 in the formation region of one of the second Cu bonding portions 426 to form an opening 459a. Therefore, the interface Cu barrier film 471 is exposed to the opening 459a of the photoresist film 459. Thereafter, the manufacturing steps of the second semiconductor component 420 in the first working example described above with reference to FIGS. 16I through 16L are performed to fabricate the second semiconductor component 470 of one of the modifications.

在本修改之組態中，其中該第一Cu連結部分416未連結至該第二Cu連結部分426之該第一Cu連結部分416在該連結介面Sj側上之面區域之一部分被置於其中該部分接觸該介面Cu障壁膜471之一狀態中。因此，在本修改之組態中，該等Cu連結部分之Cu亦並未擴散至一外部氧化物膜中，且因此可達成類似於藉由該第一工作實例達成之效果之若干效果。 In the configuration of the modification, a portion of the surface area of the first Cu joint portion 416 that is not joined to the second Cu joint portion 426 on the side of the joint interface Sj is placed therein. This portion is in contact with one of the interfaces of the Cu barrier film 471. Therefore, in the configuration of the present modification, Cu of the Cu-bonding portions is not diffused into an external oxide film, and thus several effects similar to those achieved by the first working example can be achieved.

[修改2] [Modify 2]

雖然該第二工作實例係其中如上文參考圖17描述般在該第一半導體部件430及該第二半導體部件440二者中設置一Cu晶種層之一實例，但是本發明並不限於此。該Cu晶種層可至少設置於在該Cu連結部分之連結側上具有一較大表面面積之半導體部件之一者中。例如，在圖17中所示之半 導體裝置402中，一Cu晶種層可僅設置於該第一半導體部件430之第一Cu連結部分416與該第一Cu障壁層417之間。 Although this second working example is an example in which a Cu seed layer is disposed in both the first semiconductor component 430 and the second semiconductor component 440 as described above with reference to FIG. 17, the present invention is not limited thereto. The Cu seed layer may be provided at least in one of the semiconductor members having a large surface area on the joined side of the Cu joint portion. For example, the half shown in Figure 17 In the conductor device 402, a Cu seed layer may be disposed only between the first Cu junction portion 416 of the first semiconductor component 430 and the first Cu barrier layer 417.

在此情況中，亦藉由連結時之退火製程，該第一半導體部件430之Cu晶種層中之一金屬材料(諸如Mn、Mg、Ti或Al)與跨該連結介面Sj與該cu晶種層相對之第二半導體部件440之第二層間絕緣膜425中之氧氣發生反應。因此，在本修改中，亦在該連結介面Sj之區域(跨該連結介面Sj之區域該第一半導體部件430之第一Cu連結部分416與該第二半導體部件440之第二層間絕緣膜425彼此相對)中形成一介面障壁膜，且達成類似於藉由該第一工作實例達成之效果之若干效果。 In this case, one of the Cu seed layers of the first semiconductor component 430 (such as Mn, Mg, Ti or Al) and the bonding interface Sj and the cu crystal are also passed through the annealing process at the time of bonding. The seed layer reacts with oxygen in the second interlayer insulating film 425 of the second semiconductor component 440. Therefore, in the present modification, also in the region of the connection interface Sj (the first Cu connection portion 416 of the first semiconductor component 430 and the second interlayer insulation film 425 of the second semiconductor component 440 in the region across the connection interface Sj) An interface barrier film is formed in each other, and several effects similar to those achieved by the first working example are achieved.

[修改3] [edit 3]

雖然上述該第三工作實例經組態使得該第二半導體部件460中之第二Cu障壁層461之介面層部分461b以嵌入該第二層間絕緣膜425之連結側表面中之一方式形成，但是本發明並不限於此。例如，亦可其他方式組態該第二Cu障壁層461使得該介面層部分461b設置於該第二層間絕緣膜425之連結側表面上。 Although the third working example described above is configured such that the interface layer portion 461b of the second Cu barrier layer 461 in the second semiconductor component 460 is formed in one of the bonding side surfaces of the second interlayer insulating film 425, The invention is not limited to this. For example, the second Cu barrier layer 461 may be configured in such a manner that the interface layer portion 461b is disposed on the joint side surface of the second interlayer insulating film 425.

圖25中展示該組態之一實例(即，一修改3)。特定言之，圖25展示該連結介面Sj附近之修改3之一半導體裝置405之一示意橫截面。應注意，在圖25中所示之修改3之半導體裝置405中，藉由相同的元件符號標示類似於上文參考圖20中描述之第三工作實例之半導體裝置403之元件。 An example of this configuration (i.e., a modification 3) is shown in FIG. In particular, Figure 25 shows a schematic cross section of one of the modified semiconductor devices 405 in the vicinity of the bonding interface Sj. It should be noted that in the semiconductor device 405 of Modification 3 shown in FIG. 25, elements similar to the semiconductor device 403 of the third working example described above with reference to FIG. 20 are denoted by the same element symbols.

參考圖25，本修改之半導體裝置405包含一第一半導體 部件410及一第二半導體部件480。應注意，因為本修改之半導體裝置405中之第一半導體部件410之組態類似於上文參考圖20描述之第三工作實例中之半導體部件之組態，所以本文省略該第一半導體部件410之重複描述以避免冗餘。 Referring to FIG. 25, the semiconductor device 405 of the present modification includes a first semiconductor. Component 410 and a second semiconductor component 480. It should be noted that since the configuration of the first semiconductor component 410 in the semiconductor device 405 of the present modification is similar to the configuration of the semiconductor component in the third working example described above with reference to FIG. 20, the first semiconductor component 410 is omitted herein. Repeat the description to avoid redundancy.

該第二半導體部件480包含未展示之一第二半導體基板、一第二SiO2層421、一第二Cu配接線部分422、一第二Cu障壁膜423、一第二Cu擴散防止膜424、一第二層間絕緣膜481、一第二Cu連結部分426、一第二Cu障壁層461及一介面Cu障壁膜482。 The second semiconductor component 480 includes a second semiconductor substrate, a second SiO 2 layer 421, a second Cu wiring portion 422, a second Cu barrier film 423, and a second Cu diffusion preventing film 424. A second interlayer insulating film 481, a second Cu connecting portion 426, a second Cu barrier layer 461, and an interface Cu barrier film 482.

應注意，在本修改之第二半導體部件480中，類似於上述該第三工作實例之第二半導體部件460之對應組件組態未展示之第二半導體基板、第二SiO2層421、第二Cu配接線部分422、第二Cu障壁膜423、及第二Cu擴散防止膜424。進一步言之，類似於上述該第三工作實例之第二半導體部件460之對應組件組態本修改中之第二Cu連結部分426及第二Cu障壁層461。 It should be noted that in the second semiconductor component 480 of the present modification, the second semiconductor substrate, the second SiO 2 layer 421, and the second, which are not shown, are configured similarly to the corresponding components of the second semiconductor component 460 of the third working example described above. The Cu wiring portion 422, the second Cu barrier film 423, and the second Cu diffusion preventing film 424. Further, the second Cu junction portion 426 and the second Cu barrier layer 461 in the present modification are configured similarly to the corresponding components of the second semiconductor component 460 of the third working example described above.

在本修改中，在該第二層間絕緣膜481之連結側表面上設置該第二Cu障壁層461之介面層部分461b。因此，並未在該第二層間絕緣膜481之該表面上形成設置於該第三工作實例中之第二凹陷部分425b。 In the present modification, the interface layer portion 461b of the second Cu barrier layer 461 is provided on the joint side surface of the second interlayer insulating film 481. Therefore, the second recessed portion 425b provided in the third working example is not formed on the surface of the second interlayer insulating film 481.

進一步言之，在本修改中，該介面Cu障壁膜482係以覆蓋該第二Cu障壁層461之介面層部分461b之一側部分或側面之一方式形成於該第二層間絕緣膜481之表面上。進一 步言之，此後，使該介面Cu障壁膜482之膜厚度與該介面層部分461b之膜厚度大致上彼此相等，使得該介面Cu障壁膜482在該連結介面Sj側上之表面與該介面層部分461b在該連結介面Sj側上之表面大致上彼此齊平。應注意，類似於該第一工作實例中之介面Cu障壁膜428，該介面Cu障壁膜482可由舉例而言諸如SiN、SiON、SiCN或有機樹脂之一材料形成。 Further, in the present modification, the interface Cu barrier film 482 is formed on the surface of the second interlayer insulating film 481 in such a manner as to cover one of the side portions or sides of the interface layer portion 461b of the second Cu barrier layer 461. on. Enter one After that, the film thickness of the interface Cu barrier film 482 and the film thickness of the interface layer portion 461b are substantially equal to each other, such that the surface of the interface Cu barrier film 482 on the side of the bonding interface Sj and the interface layer The surfaces of the portions 461b on the side of the joint interface Sj are substantially flush with each other. It should be noted that, similar to the interface Cu barrier film 428 in the first working example, the interface Cu barrier film 482 may be formed of, for example, a material such as SiN, SiON, SiCN, or an organic resin.

在本修改中，在除該第一Cu連結部分416與該第二Cu連結部分426之間之連結區域外之連結介面Sj之一區域中，該第一Cu連結部分416被置於其中其接觸該第二Cu障壁層461之介面層部分461b及/或該介面Cu障壁膜482之一狀態中。因此，在本修改之組態中，亦可防止該等Cu連結部分中之Cu擴散至該層間絕緣膜中，且因此達成類似於藉由該第一工作實例達成之效果之若干效果。 In the present modification, in a region other than the joint interface Sj outside the joint region between the first Cu joint portion 416 and the second Cu joint portion 426, the first Cu joint portion 416 is placed therein in contact In the state of one of the interface layer portion 461b of the second Cu barrier layer 461 and/or the interface Cu barrier film 482. Therefore, in the configuration of the present modification, it is also possible to prevent Cu in the Cu-bonding portions from diffusing into the interlayer insulating film, and thus achieve several effects similar to those achieved by the first working example.

應注意，可進一步修改本修改使得其並不包含該介面Cu障壁膜482。在此例項中，當在該第二Cu障壁層461之介面層部分461b之一側部分周圍形成一氣隙時，因為可藉由該氣隙防止該等Cu連結部分之Cu擴散至該層間絕緣膜中，所以可達成類似於藉由該第一工作實例達成之效果之若干效果。然而，就該連結介面Sj處之連結強度而言，如圖25中所示，較佳地以覆蓋該介面層部分461b之一側部分之一方式設置該介面Cu障壁膜482。 It should be noted that this modification may be further modified such that it does not include the interface Cu barrier film 482. In this example, when an air gap is formed around one side portion of the interface layer portion 461b of the second Cu barrier layer 461, since Cu diffusion of the Cu-bonding portions can be prevented from being diffused to the interlayer insulating layer by the air gap In the film, several effects similar to those achieved by the first working example can be achieved. However, with respect to the joint strength at the joint interface Sj, as shown in FIG. 25, the interface Cu barrier film 482 is preferably provided in such a manner as to cover one of the side portions of the interface layer portion 461b.

[修改4] [Modify 4]

在上述該等工作實例及該等修改中，雖然每一連結部分 之電極膜係由一Cu膜組態，但是本發明並不限於此。該連結部分可以其他方式由由(例如)Al、W、Ti、TiN、Ta、TaN或Ru形成之一金屬膜或此等金屬膜之一層壓膜組態。 In the above working examples and the modifications, although each link portion The electrode film is configured by a Cu film, but the present invention is not limited thereto. The joining portion may be configured in other manner from a metal film formed of, for example, Al, W, Ti, TiN, Ta, TaN or Ru, or a laminated film configuration of one of the metal films.

例如，在該第一工作實例中，可使用鋁(Al)作為該等連結部分之電極材料。在此例項中，類似於上述該第一工作實例，該介面Cu障壁層428可由舉例而言諸如SiN、SiON、SiCN或一樹脂之一材料組態。進一步言之，在此例項中，覆蓋該Al連結部分之金屬障壁層較佳地由藉由自該Al連結部分側(即，自Ti/TiN層壓膜)按此順序層壓Ti膜及TiN膜形成之一多層膜組態。 For example, in the first working example, aluminum (Al) may be used as the electrode material of the joining portions. In this example, similar to the first working example described above, the interface Cu barrier layer 428 can be configured by, for example, one of materials such as SiN, SiON, SiCN, or a resin. Further, in this example, the metal barrier layer covering the Al bonding portion is preferably laminated by laminating the film from the side of the Al bonding portion (ie, from the Ti/TiN laminated film) The TiN film forms a multilayer film configuration.

進一步言之，例如，在上述該第二工作實例之組態中，亦可使用Al作為該等連結部分之電極材料。然而，在此例項中，因為Al係易於與氧氣發生反應之一材料，所以無需設置用於製造一介面障壁膜之一晶種層(即，Cu晶種層)。 Further, for example, in the configuration of the second working example described above, Al may also be used as the electrode material of the connecting portions. However, in this example, since the Al system is apt to react with oxygen as one of the materials, it is not necessary to provide a seed layer (i.e., a Cu seed layer) for fabricating an interface barrier film.

圖26展示在其中在上述該第二工作實例之組態中每一連結部分係由Al形成之情況中之一半導體裝置之連結介面Sj附近之一示意橫截面。應注意，在圖26中，為簡化描述，省略僅Al連結部分附近之一組態同時省略配接線區段之組態。進一步言之，在圖26中所示之半導體裝置406中，藉由相同的元件符號標示類似於圖17中所示之第二工作實例之半導體裝置402之元件。 Figure 26 shows a schematic cross section of the vicinity of the joint interface Sj of one of the semiconductor devices in the case where each of the joint portions is formed of Al in the configuration of the second working example described above. It should be noted that, in FIG. 26, in order to simplify the description, the configuration in which only one of the vicinity of the Al joint portion is omitted while omitting the configuration of the wiring section is omitted. Further, in the semiconductor device 406 shown in Fig. 26, elements of the semiconductor device 402 similar to the second working example shown in Fig. 17 are denoted by the same reference numerals.

參考圖26，本修改之半導體裝置406包含一第一半導體部件491、一第二半導體部件492及一介面障壁膜497。該第一半導體部件491包含一第一層間絕緣膜415、以嵌入該 第一層間絕緣膜415之連結側表面中之一方式形成之一第一Al連結部分493及設置於該第一層間絕緣膜415與該第一Al連結部分493之間之一第一障壁金屬層494。同時，該第二半導體部件492包含一第二層間絕緣膜425、以嵌入該第二層間絕緣膜425之連結側表面中之一方式形成之一第二Al連結部分495及設置於該第二層間絕緣膜425與該第二Al連結部分495之間之一第二障壁金屬層496。 Referring to FIG. 26, the semiconductor device 406 of the present modification includes a first semiconductor component 491, a second semiconductor component 492, and an interface barrier film 497. The first semiconductor component 491 includes a first interlayer insulating film 415 for embedding the One of the joining side surfaces of the first interlayer insulating film 415 forms one of the first Al joining portions 493 and one of the first barriers disposed between the first interlayer insulating film 415 and the first Al joining portion 493 Metal layer 494. At the same time, the second semiconductor component 492 includes a second interlayer insulating film 425 formed in one of the connecting side surfaces of the second interlayer insulating film 425 to form a second Al connecting portion 495 and disposed between the second layer. A second barrier metal layer 496 between the insulating film 425 and the second Al bonding portion 495.

在圖26中所示之修改中，亦藉由在連結該第一半導體部件491與該第二半導體部件492時實施之退火製程，該第一Al連結部分493中之Al之部分與跨該連結介面Sj與該第一Al連結部分493相對之第二半導體部件492之第二層間絕緣膜425中之氧氣發生反應。因此，該介面障壁膜497形成於其中該第一Al連結部分493與該第二層間絕緣膜425彼此相對之連結介面Sj之區域中。因此，在本組態實例中，類似於該第一工作實例亦可增加該第一半導體部件491與該第二半導體部件492之間之連結強度，且所得半導體裝置406具有一較高可靠度之一連結介面。 In the modification shown in FIG. 26, the portion of Al in the first Al connection portion 493 is also connected to the connection by an annealing process performed when the first semiconductor component 491 and the second semiconductor component 492 are joined. The interface Sj reacts with oxygen in the second interlayer insulating film 425 of the second semiconductor member 492 opposite to the first Al bonding portion 493. Therefore, the interface barrier film 497 is formed in a region in which the first Al bonding portion 493 and the second interlayer insulating film 425 are opposed to each other in the bonding interface Sj. Therefore, in the present configuration example, the connection strength between the first semiconductor component 491 and the second semiconductor component 492 can be increased similarly to the first working example, and the resulting semiconductor device 406 has a higher reliability. A link interface.

進一步言之，例如，在該第一工作實例中，可使用(例如)鎢(W)作為該等連結部分之電極材料。在此例項中，類似於該第一工作實例，該介面Cu障壁層428可由舉例而言諸如SiN、SiON、SiCN或一有機樹脂之一材料形成。進一步言之，在此例項中，用於覆蓋該W連結部分之金屬障壁層較佳地由藉由自該W連結部分側(即，自Ti/TiN層壓膜)按此順序層壓Ti膜及TiN膜形成之一多層膜組態。然而， 應注意，因為W係不太易於與氧氣發生反應(即，不太易於自我製造一介面障壁膜)之一金屬材料，所以上述該第二工作實例之組態中之連結部分難以使用W。 Further, for example, in the first working example, for example, tungsten (W) may be used as the electrode material of the joining portions. In this example, similar to the first working example, the interface Cu barrier layer 428 may be formed of a material such as, for example, SiN, SiON, SiCN, or an organic resin. Further, in this example, the metal barrier layer for covering the W-bonding portion is preferably laminated in this order by the side from the W-joining portion (i.e., from the Ti/TiN laminated film). The film and the TiN film form a multilayer film configuration. however, It should be noted that since the W system is less prone to react with oxygen (i.e., it is less likely to self-manufacture an interface barrier film), the joint portion in the configuration of the second working example described above is difficult to use.

[修改5] [Modify 5]

在上述該等工作實例及該等修改中，雖然被供應一信號之金屬膜係沿該連結介面Sj連結在一起，但是本發明並不限於此。在其中未被供應信號之金屬膜連結在一起之情況中，亦可應用結合該等工作實例及該等修改描述之一Cu-Cu連結技術。 In the above-described working examples and the modifications, although the metal film to which a signal is supplied is coupled along the joint interface Sj, the present invention is not limited thereto. In the case where the metal films to which the signals are not supplied are joined together, a Cu-Cu joining technique in combination with the working examples and the modifications may be applied.

例如，在其中虛設電極連結在一起之情況中，亦可應用上文結合該等工作實例及該等修改描述之Cu-Cu連結技術。進一步言之，在其中(例如)在一固態影像擷取裝置中一感測器區段及一邏輯電路區段之金屬膜連結在一起以形成一光攔截膜之情況中，亦可應用結合該等工作實例及該等修改描述之Cu-Cu連結技術。 For example, in the case where the dummy electrodes are joined together, the Cu-Cu joining technique described above in connection with the working examples and the modifications may also be applied. Further, in the case where, for example, in a solid-state image capturing device, a sensor segment and a metal film of a logic circuit segment are joined together to form a light intercepting film, a combination may also be applied. The working examples and the Cu-Cu joining techniques described in the modifications.

[參考實例1] [Reference Example 1]

在上述第二工作實例中，該第一Cu連結部分416在該連結介面Sj側上之表面之尺寸或表面積與該第二Cu連結部分426在該連結介面Sj側上之表面之尺寸或表面積彼此不同。然而，上文結合該第二工作實例描述之Cu-Cu連結技術亦可應用於其中該第一Cu連結部分在該連結介面Sj側上之表面形狀及尺寸與該第二Cu連結部分在該連結介面Sj側上之表面形狀及尺寸彼此相同之一半導體裝置。 In the second working example, the size or surface area of the surface of the first Cu connecting portion 416 on the side of the connecting interface Sj and the surface or surface area of the surface of the second Cu connecting portion 426 on the side of the connecting interface Sj are mutually different. However, the Cu-Cu bonding technique described above in connection with the second working example can also be applied to the surface shape and size of the first Cu connecting portion on the side of the connecting interface Sj and the second Cu connecting portion at the connecting A semiconductor device having the same surface shape and size on the interface Sj side.

圖27展示剛剛描述之此一應用之一實例(即，一參考實 例1)。應注意，圖27展示一連結介面Sj附近本參考實例1之半導體裝置500之一示意橫截面。應注意，在圖27中所示之本參考實例之半導體裝置500中，藉由相同的元件符號標示類似於圖17中所示之第二工作實例之半導體裝置402之元件。 Figure 27 shows an example of such an application just described (i.e., a reference example 1). It should be noted that FIG. 27 shows a schematic cross section of the semiconductor device 500 of the present reference example 1 in the vicinity of a bonding interface Sj. It is to be noted that, in the semiconductor device 500 of the present reference example shown in FIG. 27, elements of the semiconductor device 402 similar to the second working example shown in FIG. 17 are denoted by the same reference numerals.

參考圖27，本參考實例之半導體裝置500包含一第一半導體部件501、一第二半導體部件440及一介面Cu障壁膜505。應注意，本參考實例之半導體裝置500中之第二半導體部件440具有類似於上文參考圖17描述之第二工作實例之一組態，且因此，本文省略該第二半導體部件440之重複描述以避免冗餘。 Referring to FIG. 27, the semiconductor device 500 of the present reference example includes a first semiconductor component 501, a second semiconductor component 440, and an interface Cu barrier film 505. It should be noted that the second semiconductor component 440 in the semiconductor device 500 of the present reference example has a configuration similar to that of the second working example described above with reference to FIG. 17, and thus, a repeated description of the second semiconductor component 440 is omitted herein. To avoid redundancy.

該第一半導體部件501包含未展示之一第一半導體部件、一第一SiO2層411、一第一Cu配接線部分412、一第一Cu障壁膜413、一第一Cu擴散防止膜414、一第一層間絕緣膜415、一第一Cu連結部分502、一第一Cu障壁層503及一第一Cu晶種層504。 The first semiconductor component 501 includes a first semiconductor component, a first SiO 2 layer 411, a first Cu wiring portion 412, a first Cu barrier film 413, and a first Cu diffusion preventing film 414. A first interlayer insulating film 415, a first Cu connecting portion 502, a first Cu barrier layer 503, and a first Cu seed layer 504.

應注意，在本實例中，該第一Cu連結部分502在該連結介面Sj側上之表面形狀及尺寸與該第二Cu連結部分426在該連結介面Sj側上之表面形狀及尺寸相同。該第一半導體部件501之另一部分之組態類似於該第二工作實例中之第一半導體部件430之對應部分之組態。 It should be noted that in the present example, the surface shape and size of the first Cu connecting portion 502 on the side of the connecting interface Sj are the same as the surface shape and size of the second Cu connecting portion 426 on the side of the connecting interface Sj. The configuration of the other portion of the first semiconductor component 501 is similar to the configuration of the corresponding portion of the first semiconductor component 430 in the second working example.

在本實例中，類似於該第二工作實例，該第一半導體部件501在該第一Cu連結部分502側上之表面與該第二半導體部件440在該第二Cu連結部分426側上之表面亦彼此連結以 製造該半導體裝置500。此後，若該兩個Cu連結部分之間發生連結錯位，則諸如每一Cu晶種層中之Mn、Mg、Ti或Al之一金屬材料在連結時在一退火製程中選擇性地與跨該連結介面Sj與該Cu晶種層相對之層間絕緣膜之氧氣發生反應。因此，如圖27中所示，在該連結介面Sj之一區域中(跨該區域該第一Cu連結部分502與該第二層間絕緣膜425彼此相對)及該連結介面Sj之一區域中(跨該區域該第二Cu連結部分426與該第一層間絕緣膜415彼此相對)形成一介面Cu障壁膜505。 In this example, similar to the second working example, the surface of the first semiconductor component 501 on the side of the first Cu bonding portion 502 and the surface of the second semiconductor component 440 on the side of the second Cu bonding portion 426 Also linked to each other The semiconductor device 500 is fabricated. Thereafter, if a joint misalignment occurs between the two Cu joint portions, one of the metal materials such as Mn, Mg, Ti or Al in each Cu seed layer is selectively and cross-linked during the annealing process. The bonding interface Sj reacts with oxygen of the interlayer insulating film opposite to the Cu seed layer. Therefore, as shown in FIG. 27, in a region of the bonding interface Sj (the first Cu bonding portion 502 and the second interlayer insulating film 425 are opposed to each other across the region) and a region of the bonding interface Sj ( The second Cu bonding portion 426 and the first interlayer insulating film 415 are opposed to each other across the region to form an interface Cu barrier film 505.

如上所述，在本實例之半導體裝置500中，亦在該連結介面Sj之區域中(跨該區域該半導體部件及另一半導體部件之層間絕緣膜之一者之Cu連結部分)設置該介面Cu障壁膜505。因此，運用本實例，亦達成類似於藉由該第二工作實例達成之效果之若干效果。 As described above, in the semiconductor device 500 of the present example, the interface Cu is also provided in the region of the connection interface Sj (the Cu connection portion of one of the interlayer insulating films of the semiconductor member and the other semiconductor member across the region). Barrier film 505. Therefore, with this example, several effects similar to those achieved by the second working example are achieved.

[參考實例2] [Reference Example 2]

在該參考實例1中，上文結合該第二工作實例描述之Cu-Cu連結技術應用於其中該第一Cu連結部分在該連結介面Sj側上之表面形狀及尺寸與該第二Cu連結部分在該連結介面Sj側上之表面形狀及尺寸彼此相同之一半導體裝置。因此，描述其中上文結合該第一工作實例描述之Cu-Cu連結技術進一步與該參考實例1之半導體裝置500組合之另一組態實例。 In the reference example 1, the Cu-Cu joining technique described above in connection with the second working example is applied to a surface shape and size of the first Cu joining portion on the side of the joining interface Sj and the second Cu joining portion. A semiconductor device having the same surface shape and size on the side of the connection interface Sj. Therefore, another configuration example in which the Cu-Cu joining technique described above in connection with the first working example is further combined with the semiconductor device 500 of the reference example 1 is described.

圖28展示剛剛描述之此一應用之一實例(即，一參考實例2)。應注意，圖28展示一連結介面Sj附近本參考實例2之 半導體裝置510之一示意橫截面。應注意，在圖28中所示之本參考實例之半導體裝置510中，藉由相同的元件符號標示類似於圖27中所示之參考實例1之半導體裝置500之元件。 FIG. 28 shows an example of such an application just described (ie, a reference example 2). It should be noted that FIG. 28 shows a reference interface 2 near the reference interface 2 One of the semiconductor devices 510 is schematically cross-sectioned. It is to be noted that, in the semiconductor device 510 of the present reference example shown in FIG. 28, elements similar to the semiconductor device 500 of Reference Example 1 shown in FIG. 27 are denoted by the same element symbols.

參考圖28，本實例之半導體裝置510包含一第一半導體部件501、一第二半導體部件520及一第一介面Cu障壁膜521。應注意，本參考實例之半導體裝置510中之第一半導體部件501具有類似於上文參考圖27描述之參考實例1之一組態，且因此，本文省略該第一半導體部件501之重複描述以避免冗餘。 Referring to FIG. 28, the semiconductor device 510 of the present example includes a first semiconductor component 501, a second semiconductor component 520, and a first interface Cu barrier film 521. It should be noted that the first semiconductor component 501 in the semiconductor device 510 of the present reference example has a configuration similar to that of the reference example 1 described above with reference to FIG. 27, and therefore, the repeated description of the first semiconductor component 501 is omitted herein. Avoid redundancy.

該第二半導體部件520包含未展示之一第二半導體基板、一第二SiO2層421、一第二Cu配接線部分422、一第二Cu障壁膜423、一第二Cu擴散防止膜424、一第二層間絕緣膜425、一第二Cu連結部分426、一第二Cu障壁層427及一第二Cu晶種層441。進一步言之，該第二半導體部件520包含一第二介面Cu障壁膜522。 The second semiconductor component 520 includes a second semiconductor substrate, a second SiO 2 layer 421, a second Cu wiring portion 422, a second Cu barrier film 423, and a second Cu diffusion preventing film 424. A second interlayer insulating film 425, a second Cu connecting portion 426, a second Cu barrier layer 427, and a second Cu seed layer 441. Further, the second semiconductor component 520 includes a second interface Cu barrier film 522.

如可自圖28與圖27之間之比較認知，本參考實例中之第二半導體部件520經組態使得在該參考實例1之第二半導體部件440中之第二層間絕緣膜525上設置該第二介面Cu障壁層522。進一步言之，在本實例中，該第二介面Cu障壁層522經形成使得該第二Cu連結部分426在該連結介面Sj側上之表面與該第二介面Cu障壁層522之表面可大致上彼此齊平。應注意，該第二半導體部件520之非該第二介面Cu障壁層522之另一部分之組態類似於上述該參考實例1之第二 半導體部件440之對應部分之組態。 As can be seen from the comparison between FIG. 28 and FIG. 27, the second semiconductor component 520 in the present reference example is configured such that the second interlayer insulating film 525 in the second semiconductor component 440 of the reference example 1 is disposed. The second interface Cu barrier layer 522. Further, in the present example, the second interface Cu barrier layer 522 is formed such that the surface of the second Cu bonding portion 426 on the side of the bonding interface Sj and the surface of the second interface Cu barrier layer 522 can be substantially They are flush with each other. It should be noted that the configuration of the second semiconductor component 520 other than the second interface Cu barrier layer 522 is similar to the second of the reference example 1 described above. Configuration of the corresponding portion of semiconductor component 440.

進一步言之，類似於該第一工作實例中之介面Cu障壁層428，該第二介面Cu障壁膜522可由舉例而言諸如SiN、SiON、SiCN或有機樹脂之一材料形成。然而，就與該Cu膜之緊密接觸而言，較佳地由SiN形成該第二介面Cu障壁膜522。 Further, similar to the interface Cu barrier layer 428 in the first working example, the second interface Cu barrier film 522 can be formed of, for example, a material such as SiN, SiON, SiCN or an organic resin. However, in terms of intimate contact with the Cu film, the second interface Cu barrier film 522 is preferably formed of SiN.

在本實例中，類似於該第二工作實例，亦藉由使該第一半導體部件501在該第一Cu連結部分502側上之表面與該第二半導體部件520在該第二Cu連結部分426側上之表面彼此連結製造該半導體裝置510。此後，若該兩個Cu連結部分之間發生錯位，則藉由連結時之一退火製程，諸如該等Cu晶種層中之Mn、Mg、Ti或Al之一金屬材料選擇性地與跨該連結介面Sj與該等Cu晶種層相對之層間絕緣膜之氧氣發生反應。因此，在該連結介面Sj之一區域中(跨該區域該等半導體部件之一者之Cu連結部分與另一半導體部件之層間絕緣膜彼此相對)形成一第一介面Cu障壁膜521。 In this example, similar to the second working example, the surface of the first semiconductor component 501 on the side of the first Cu bonding portion 502 and the second semiconductor component 520 are in the second Cu bonding portion 426. The surface on the side is bonded to each other to fabricate the semiconductor device 510. Thereafter, if a misalignment occurs between the two Cu joint portions, one of the metal materials of Mn, Mg, Ti or Al in the Cu seed layer is selectively and cross-linked by an annealing process at the time of joining The bonding interface Sj reacts with oxygen of the interlayer insulating film opposite to the Cu seed layers. Therefore, a first interface Cu barrier film 521 is formed in a region of the connection interface Sj (the Cu connection portion of one of the semiconductor members across the region and the interlayer insulation film of the other semiconductor member face each other).

然而，在本實例中，如上所述，該第二介面Cu障壁膜522係設置於該第二半導體部件520在該連結介面Sj側上之表面上。因此，在本實例中，該第一介面Cu障壁膜521係形成於該連結介面Sj之區域(跨該區域該第一Cu連結部分502與該第二層間絕緣膜425彼此相對)及該連結介面Sj之區域(跨該區域該第二Cu連結部分426與該第一層間絕緣膜415彼此相對)之一者中。進一步言之，該第二介面Cu障壁膜522被安置在該連結介面Sj之區域(跨該區域該第一Cu連 結部分502與該第二層間絕緣膜425彼此相對)及該連結介面Sj之區域(跨該區域該第二Cu連結部分426與該第一層間絕緣膜415彼此相對)之另一者中。在圖28中所示之實例中，該第二介面Cu障壁膜522係設置於前一連結介面Sj之區域中，且該第一介面Cu障壁膜521係設置於後一連結介面Sj之區域中。 However, in the present example, as described above, the second interface Cu barrier film 522 is disposed on the surface of the second semiconductor component 520 on the side of the bonding interface Sj. Therefore, in the present example, the first interface Cu barrier film 521 is formed in a region of the bonding interface Sj (the first Cu bonding portion 502 and the second interlayer insulating film 425 are opposed to each other across the region) and the bonding interface One of the regions of Sj (the second Cu bonding portion 426 and the first interlayer insulating film 415 are opposed to each other across the region). Further, the second interface Cu barrier film 522 is disposed in the region of the bonding interface Sj (the first Cu connection across the region) The junction portion 502 and the second interlayer insulating film 425 are opposed to each other and the region of the bonding interface Sj (the second Cu bonding portion 426 and the first interlayer insulating film 415 are opposed to each other across the region). In the example shown in FIG. 28, the second interface Cu barrier film 522 is disposed in a region of the previous bonding interface Sj, and the first interface Cu barrier film 521 is disposed in the region of the subsequent bonding interface Sj. .

如上所述，在本實例之半導體裝置510中，該第一介面Cu障壁膜521或該第二介面Cu障壁膜522亦設置於該連結介面Sj之區域中(跨該區域該等半導體部件之一者之Cu連結部分與另一半導體部件之層間絕緣膜彼此相對)。因此，運用本實例，亦可達成類似於藉由該第一工作實例及該第工作實例達成之效果之若干效果。 As described above, in the semiconductor device 510 of the present example, the first interface Cu barrier film 521 or the second interface Cu barrier film 522 is also disposed in the region of the bonding interface Sj (one of the semiconductor components across the region) The Cu bonding portion and the interlayer insulating film of another semiconductor member are opposed to each other). Therefore, with the present example, several effects similar to those achieved by the first working example and the first working example can be achieved.

<<5.第四工作實例>> <<5. Fourth working example>>

通常，當具有面積彼此不同之Cu連結部分之一第一半導體部件與一第二半導體部件彼此接合以實施Cu-Cu連結時，該半導體部件之一者之Cu連結部分與另一半導體部件之層間絕緣膜彼此接觸。圖29展示剛剛描述之連結之一實例中一連結介面附近之一示意橫截面。應注意，在圖29中所示之半導體裝置650中，藉由相同的元件符號標示類似於上文參考圖14描述之第一工作實例之半導體裝置401之元件。 Generally, when one of the first semiconductor member and the second semiconductor member having the Cu-connecting portions having different areas are bonded to each other to perform Cu-Cu bonding, the Cu-bonding portion of one of the semiconductor members is interposed between the layers of the other semiconductor member. The insulating films are in contact with each other. Figure 29 shows a schematic cross section of a vicinity of a joining interface in one of the examples just described. It is to be noted that, in the semiconductor device 650 shown in FIG. 29, elements of the semiconductor device 401 similar to the first working example described above with reference to FIG. 14 are denoted by the same element symbols.

參考圖29，Cu如圖29中之虛線箭頭標記所示自面積大於一第二Cu連結部分426之面積之一第一Cu連結部分416擴散至一第二層間絕緣膜425中，且藉此損害該連結介面Sj 處之一電特性並使該等Cu連結部分及該半導體裝置650之可靠性降級。相比而言，在上述該等工作實例中，沿該第一Cu連結部分416與該第二層間絕緣膜425之間之連結介面形成一介面障壁膜，且可藉此防止Cu自該第一Cu連結部分416擴散至該第二層間絕緣膜425中。因此，可解決上述問題。 Referring to FIG. 29, Cu is diffused into a second interlayer insulating film 425 from one of the areas larger than a second Cu joining portion 426 as indicated by a broken arrow mark in FIG. 29, and thereby impaired. The link interface Sj One of the electrical characteristics degrades the reliability of the Cu junction portions and the semiconductor device 650. In contrast, in the above working examples, an interface barrier film is formed along the bonding interface between the first Cu connecting portion 416 and the second interlayer insulating film 425, and thereby Cu can be prevented from being the first The Cu joint portion 416 is diffused into the second interlayer insulating film 425. Therefore, the above problem can be solved.

進一步言之，可應用其中一第一半導體部件與一第二半導體部件彼此接合(接合的狀態為其中該層間絕緣膜在該第一半導體部件及該第二半導體部件之至少一者之連結介面側上之表面自該Cu連結部分之連結側面收縮)之一技術作為用於防止Cu透過上述連結介面擴散之另一技術。換言之，亦可應用其中該第一半導體部件與該第二半導體部件彼此接合(接合的狀態為其中該第一半導體部件及該第二半導體部件之至少一者之Cu連結部分朝該連結介面側突出)之一技術。 Further, a first semiconductor component and a second semiconductor component may be bonded to each other (the bonded state is where the interlayer insulating film is on the bonding interface side of at least one of the first semiconductor component and the second semiconductor component One of the techniques for shrinking the upper surface from the joint side of the Cu joint portion is another technique for preventing Cu from diffusing through the joint interface. In other words, the first semiconductor component and the second semiconductor component may be bonded to each other (the bonded state is such that the Cu connecting portion of at least one of the first semiconductor component and the second semiconductor component protrudes toward the bonding interface side) ) One of the technologies.

圖30展示在其中一第一半導體部件及一第二半導體部件彼此接合(接合的狀態為其中該第一半導體部件及該第二半導體部件二者之Cu連結部分朝該連結介面側突出)之情況下一連結介面附近之一示意橫截面。應注意，在圖30中所示之半導體裝置660中，藉由相同的元件符號標示類似於圖14中所示之第一工作實例之半導體裝置401之元件。 FIG. 30 shows a case where one of the first semiconductor member and the second semiconductor member are bonded to each other (the state in which the bonding is performed in which the Cu-bonding portion of both the first semiconductor member and the second semiconductor member protrudes toward the bonding interface side) One of the schematic cross sections near the next joint interface. It is to be noted that, in the semiconductor device 660 shown in FIG. 30, elements of the semiconductor device 401 similar to the first working example shown in FIG. 14 are denoted by the same reference numerals.

在此例項中，沿第一半導體部件661與第二半導體部件662之間(特別係一第一層間絕緣膜663與一第二層間絕緣膜664之間)之連結介面Sj形成一間隙。因此，在該第二層 間絕緣664與該第一Cu連結部分416之間形成一氣隙，且防止Cu自該第一Cu連結部分416擴散至該第二層間絕緣664中。然而，在此例項中，外部空氣如概述箭頭標記所示沿該連結介面Sj進入該間隙，且污染該第一Cu連結部分416之表面。因此，損害該連結介面Sj處之一電特性且該等Cu連結部分及該半導體裝置之可靠性降級。 In this example, a gap is formed along the bonding interface Sj between the first semiconductor component 661 and the second semiconductor component 662 (particularly between the first interlayer insulating film 663 and a second interlayer insulating film 664). So on the second floor An interstitial 664 forms an air gap with the first Cu junction portion 416 and prevents Cu from diffusing from the first Cu junction portion 416 into the second interlayer insulation 664. However, in this example, the outside air enters the gap along the joint interface Sj as indicated by the outline arrow mark, and contaminates the surface of the first Cu joint portion 416. Therefore, one of the electrical characteristics of the connection interface Sj is damaged and the reliability of the Cu connection portion and the semiconductor device is degraded.

因此，在該第四工作實例中，其中在一第二層間絕緣膜與一第一Cu連結部分之間形成一氣隙之一半導體裝置經組態使得其可防止如上所述之外部空氣之此一影響。 Therefore, in the fourth working example, a semiconductor device in which an air gap is formed between a second interlayer insulating film and a first Cu connecting portion is configured such that it can prevent the outside air as described above. influences.

[半導體裝置之組態] [Configuration of Semiconductor Device]

圖31及圖32展示根據一第四工作實例之一半導體裝置之一般組態。特定言之，圖31展示一連結介面附近根據該第四工作實例之半導體裝置之一示意橫截面，且圖32展示該連結介面附近之一示意俯視圖並圖解說明Cu連結部分與沿該連結介面界定之一氣隙之一配置關係。應注意，在圖31及圖32中，為簡化描述，僅展示一連結介面附近之一組態。進一步言之，在圖31中所示之本工作實例之半導體裝置530中，藉由相同的元件符號標示類似於圖14中所示之第一工作實例之半導體裝置401之元件。 31 and 32 show a general configuration of a semiconductor device according to a fourth working example. Specifically, FIG. 31 shows a schematic cross section of a semiconductor device according to the fourth working example in the vicinity of a bonding interface, and FIG. 32 shows a schematic top view of the vicinity of the bonding interface and illustrates that the Cu bonding portion is defined along the bonding interface. One of the air gap configuration relationships. It should be noted that in FIGS. 31 and 32, to simplify the description, only one configuration near a link interface is shown. Further, in the semiconductor device 530 of the present working example shown in FIG. 31, elements of the semiconductor device 401 similar to the first working example shown in FIG. 14 are denoted by the same reference numerals.

首先參考圖31，該半導體裝置530包含作為一第一半導體區段之一第一半導體部件531及作為一第二半導體區段之一第二半導體部件532。 Referring first to FIG. 31, the semiconductor device 530 includes a first semiconductor component 531 as one of the first semiconductor segments and a second semiconductor component 532 as one of the second semiconductor segments.

該第一半導體部件531包含未展示之一第一半導體基板、一第一SiO2層411、一第一Cu配接線部分412、一第一 Cu障壁膜413、一第一Cu擴散防止膜414、一第一層間絕緣膜415、一第一Cu連結部分533及一第一Cu障壁層417。 The first semiconductor component 531 includes a first semiconductor substrate, a first SiO 2 layer 411, a first Cu wiring portion 412, a first Cu barrier film 413, and a first Cu diffusion preventing film 414. A first interlayer insulating film 415, a first Cu connecting portion 533, and a first Cu barrier layer 417.

如自圖31與圖14之間之比較認知，本工作實例中之第一半導體部件531經組態使得在該第一實例之第一半導體部件410在該連結介面Sj側上之表面積上，於該第一Cu連結部分416與該第二層間絕緣膜425相對之表面區域中設置一凹陷部分。該第一半導體部件531之非剛剛描述之組態的另一部分的組態類似於上述第一工作實例之第一半導體部件410之對應部分之組態。 As is apparent from the comparison between FIG. 31 and FIG. 14, the first semiconductor component 531 in this working example is configured such that the surface area of the first semiconductor component 410 of the first example on the side of the bonding interface Sj is A recessed portion is formed in a surface area of the first Cu connecting portion 416 opposite to the second interlayer insulating film 425. The configuration of the other portion of the first semiconductor component 531 that is not just described is similar to the configuration of the corresponding portion of the first semiconductor component 410 of the first working example described above.

該第二半導體部件532包含未展示之一第二半導體基板、一第二SiO2層421、一第二Cu配接線部分422、一第二Cu障壁膜423、一第二Cu擴散防止膜424、一第二層間絕緣膜425及一第二Cu連結部分426。 The second semiconductor component 532 includes a second semiconductor substrate, a second SiO 2 layer 421, a second Cu wiring portion 422, a second Cu barrier film 423, and a second Cu diffusion preventing film 424. A second interlayer insulating film 425 and a second Cu connecting portion 426.

如自圖31與圖14之間之比較認知，本工作實例中之第二半導體部件532經組態使得該第一工作實例中之第二半導體部件420並不包含該介面Cu障壁膜428。該第二半導體部件532之除此之外的另一部分之組態類似於該第一工作實例中之第二半導體部件420之對應部分之組態。 As is apparent from the comparison between FIG. 31 and FIG. 14, the second semiconductor component 532 in this working example is configured such that the second semiconductor component 420 in the first working example does not include the interface Cu barrier film 428. The configuration of the other portion of the second semiconductor component 532 other than this is similar to the configuration of the corresponding portion of the second semiconductor component 420 of the first working example.

如圖31中所示，在本工作實例中之半導體裝置530中，在該第一半導體部件531在該連結介面Sj側上之表面區域中，於該第一Cu連結部分533與該第二半導體部件532之第二層間絕緣膜425相對之表面區域中設置一凹陷部分534。因此，可形成一結構，其中沿該連結介面Sj在一區域中形成一氣隙，跨該區域該第一半導體部件531之第一Cu連結 部分533與該第二半導體部件532之第二層間絕緣膜531彼此相對且該第一Cu連結部分533並未直接接觸該第二層間絕緣膜425。 As shown in FIG. 31, in the semiconductor device 530 of this working example, in the surface region of the first semiconductor component 531 on the side of the bonding interface Sj, the first Cu bonding portion 533 and the second semiconductor A second recessed portion 534 is disposed in the surface area of the second interlayer insulating film 425 of the member 532. Therefore, a structure can be formed in which an air gap is formed in a region along the bonding interface Sj, and the first Cu junction of the first semiconductor component 531 is spanned across the region The portion 533 and the second interlayer insulating film 531 of the second semiconductor member 532 are opposed to each other and the first Cu connecting portion 533 does not directly contact the second interlayer insulating film 425.

特定言之，在本工作實例中之半導體裝置530中，一介面障壁部分由該第一Cu連結部分533之凹陷部分534及該第二半導體部件532與該凹陷部分534相對之連結介面Sj側上之表面區域部分(即，面區域部分)組態。進一步言之，在本工作實例中，藉由該第一Cu連結部分533之凹陷部分534及該第二層間絕緣膜425在該連結介面Sj側上之表面界定之氣隙被置於其中該氣隙如圖31中所示藉由該氣隙周圍之各種膜密封之一狀態中。 Specifically, in the semiconductor device 530 of the present working example, a dielectric barrier portion is formed by the recessed portion 534 of the first Cu connecting portion 533 and the second semiconductor member 532 opposite to the recessed portion 534 on the side of the connecting interface Sj. The surface area portion (ie, the area area portion) is configured. Further, in the working example, the air gap defined by the concave portion 534 of the first Cu joint portion 533 and the surface of the second interlayer insulating film 425 on the joint interface Sj side is placed therein. The gap is sealed in one of the states by various films around the air gap as shown in FIG.

[半導體裝置之製造技術] [Manufacturing Technology of Semiconductor Device]

現在，參考圖33A至圖33D描述本實施例中之半導體裝置530之一製造技術。應注意，圖33A及圖33B展示於不同步驟處製造之半導體部件之一Cu連結部分附近之橫截面，且圖33C及圖33D圖解說明該第一半導體部件531與該第二半導體部件532之一連結製程之一方式。 Now, a manufacturing technique of one of the semiconductor devices 530 in the present embodiment will be described with reference to FIGS. 33A to 33D. It should be noted that FIGS. 33A and 33B show cross sections near the Cu junction portion of one of the semiconductor components fabricated at different steps, and FIGS. 33C and 33D illustrate one of the first semiconductor component 531 and the second semiconductor component 532. One way to link processes.

首先，在本工作實例中，如圖33A中所示以類似於上文參考圖16A至圖16F描述之第一工作實例中之第一半導體部件410之製造步驟處之一方式製造一第一半導體部件531。 First, in the present working example, a first semiconductor is fabricated in a manner similar to that of the first semiconductor component 410 in the first working example described above with reference to FIGS. 16A to 16F as shown in FIG. 33A. Component 531.

進一步言之，在本工作實例中，如圖33B中所示以類似於上文參考圖16A至圖16F描述之第一工作實例中之第一半導體部件410之製造步驟處之一方式製造一第二半導體部件532。然而，應注意，在此例項中，在對應於圖16C之步 驟之第二層間絕緣膜425中形成對應於該第二Cu連結部分426及該第二Cu障壁層427之一形成區域之一開口之步驟處，將該開口之開口直徑設定為約1微米至95微米。 Further, in the present working example, as shown in FIG. 33B, a method is manufactured in a manner similar to the manufacturing step of the first semiconductor component 410 in the first working example described above with reference to FIGS. 16A to 16F. Two semiconductor components 532. However, it should be noted that in this example, the step corresponding to Figure 16C a step of forming an opening corresponding to one of the second Cu-connecting portion 426 and the second Cu barrier layer 427 forming region in the second interlayer insulating film 425, and setting the opening diameter of the opening to about 1 μm to 95 microns.

接著，對該第一半導體部件531在該第一Cu連結部分533側上之表面及該第二半導體部件532在該第二Cu連結部分426側上之表面實施一還原製程以移除該等Cu連結部分之表面上之氧化物膜或氧化物以使純淨的Cu曝露於該等Cu連結部分之該表面。應注意，使用其中使用舉例而言諸如甲酸之藥物溶液之一濕式蝕刻製程或其中使用(例如)Ar、NH3或H2之電漿之一乾式蝕刻製程作為此例項中之還原製程。 Next, a surface of the first semiconductor component 531 on the first Cu-connecting portion 533 side and a surface of the second semiconductor component 532 on the second Cu-bonding portion 426 side are subjected to a reduction process to remove the Cu. An oxide film or oxide on the surface of the joint portion is used to expose pure Cu to the surface of the Cu joint portion. It should be noted that a dry etching process in which one of the drug solutions such as formic acid is used, or a plasma in which, for example, Ar, NH 3 or H 2 is used, is used as the reduction process in this example.

此後，如圖33C中所示，該第一半導體部件531在該第一Cu連結部分533側上之表面與該第二半導體部件532在該第二Cu連結部分426側上之表面彼此接觸或彼此接合。 Thereafter, as shown in FIG. 33C, the surface of the first semiconductor component 531 on the side of the first Cu bonding portion 533 and the surface of the second semiconductor component 532 on the side of the second Cu bonding portion 426 are in contact with each other or each other. Engage.

接著，如圖33D中所示，在其中該第一半導體部件531與該第二半導體部件532彼此接合之狀態中，使用舉例而言諸如一加熱板之一加熱設備或退火設備或一RTA設備以使所接合部件退火以使該第一Cu連結部分533與該第二Cu連結部分426彼此連結。特定言之，在(例如)大氣壓力之N2氛圍中或真空中在約100℃至400℃下加熱所接合部件持續約5分鐘至兩個小時。 Next, as shown in FIG. 33D, in a state in which the first semiconductor component 531 and the second semiconductor component 532 are bonded to each other, using, for example, a heating device or an annealing device or an RTA device such as a heating plate The joined member is annealed to connect the first Cu joining portion 533 and the second Cu joining portion 426 to each other. Specifically, the joined component is heated in an N 2 atmosphere of, for example, atmospheric pressure or in a vacuum at about 100 ° C to 400 ° C for about 5 minutes to 2 hours.

在本工作實例中，藉由圖33D中所示之退火製程進一步加固該第一Cu連結部分533之Cu膜。應注意，在該連結介面Sj上，該第一Cu連結部分533與該第二層間絕緣膜425之 間之接觸區域與另一區域相比在緊密接觸力方面有所降低。因此，藉由圖33D中所示之退火製程，該接觸區域中之第一Cu連結部分533收縮且該第一Cu連結部分533之表面在其中其經間隔遠離該連結介面Sj之一方向上後移。因此，如圖33D中所示，在該第一半導體部件531在該連結介面Sj上之表面區域中，在該第一Cu連結部分533與該第二層間絕緣膜425相對之表面區域中形成一凹陷部分534。 In the present working example, the Cu film of the first Cu joining portion 533 is further reinforced by the annealing process shown in Fig. 33D. It should be noted that the first Cu connecting portion 533 and the second interlayer insulating film 425 are on the bonding interface Sj. The contact area between the two has a lower contact force than the other area. Therefore, by the annealing process shown in FIG. 33D, the first Cu joint portion 533 in the contact region contracts and the surface of the first Cu joint portion 533 moves backward in a direction in which it is spaced apart from the joint interface Sj. . Therefore, as shown in FIG. 33D, in the surface region of the first semiconductor component 531 on the bonding interface Sj, a surface region is formed in a surface region of the first Cu bonding portion 533 opposite to the second interlayer insulating film 425. The recessed portion 534.

特定言之，藉由圖33D中所示之退火製程，形成一結構，其中沿該第一Cu連結部分533與該第二層間絕緣膜425之間之連結介面Sj形成一氣隙，且該氣隙藉由該氣隙周圍之各種膜密封在該半導體裝置530中。應注意，為藉由圖33D中所示之退火製程形成該凹陷部分534，較佳地在(例如)高於經實施以在製造該等半導體部件時形成精細膜品質之Cu連結部分之退火製程之退火溫度之一溫度下實施該退火。 Specifically, a structure is formed by the annealing process shown in FIG. 33D, wherein an air gap is formed along the bonding interface Sj between the first Cu connecting portion 533 and the second interlayer insulating film 425, and the air gap is formed. The semiconductor device 530 is sealed by various films around the air gap. It should be noted that the recessed portion 534 is formed by the annealing process illustrated in FIG. 33D, preferably, for example, above an annealing process that is performed to form a Cu-junction portion of a fine film quality when the semiconductor components are fabricated. The annealing is performed at one of the annealing temperatures.

在本工作實例中，以如上所述之此一方式實施一Cu-Cu連結製程。應注意，該半導體裝置530之製造製程之除上述該連結步驟外的另一部分可類似於舉例而言諸如一固態影像擷取裝置(參考(例如)日本專利特許公開案第2007-234725號)之一當前可用半導體裝置之製造技術。 In the present working example, a Cu-Cu joining process is carried out in such a manner as described above. It should be noted that another portion of the manufacturing process of the semiconductor device 530 other than the above-described bonding step may be similar to, for example, a solid-state image capturing device (refer to, for example, Japanese Patent Laid-Open Publication No. 2007-234725). A manufacturing technique of currently available semiconductor devices.

如上所述，本工作實例中之半導體裝置530經結構化使得沿該第一Cu連結部分533與該第二層間絕緣膜425之間之連結介面Sj形成一氣隙使得該第一Cu連結部分533與該第二層間絕緣膜425彼此不直接接觸。因此，在本工作實例 中，類似於該第一工作實例中，亦可防止Cu自該第一Cu連結部分533擴散至該第二層間絕緣膜425中。應注意，因為沿該連結介面Sj形成之氣隙之區域與該連結介面Sj之總體面積相比足夠小，所以本工作實例之組態中該連結介面Sj之緊密接觸效能類似於上述該等工作實例中之緊密接觸效能。 As described above, the semiconductor device 530 in the working example is structured such that an air gap is formed along the bonding interface Sj between the first Cu connecting portion 533 and the second interlayer insulating film 425 such that the first Cu connecting portion 533 and The second interlayer insulating films 425 are not in direct contact with each other. Therefore, in this working example In the first working example, it is also possible to prevent Cu from diffusing into the second interlayer insulating film 425 from the first Cu bonding portion 533. It should be noted that since the area of the air gap formed along the joint interface Sj is sufficiently smaller than the total area of the joint interface Sj, the close contact performance of the joint interface Sj in the configuration of the working example is similar to the above work. The close contact performance in the examples.

進一步言之，在本工作實例之半導體裝置530中，沿該第一Cu連結部分533與該第二層間絕緣膜425之間之連結介面Sj形成之氣隙被置於其中該氣隙藉由該氣隙周圍的各種膜密封之一狀態中。因此，在本工作實例中，可防止外部空氣侵入該等Cu連結部分，且可保證該半導體裝置530之可靠性。 Further, in the semiconductor device 530 of the present working example, an air gap formed along the bonding interface Sj between the first Cu connecting portion 533 and the second interlayer insulating film 425 is placed therein, wherein the air gap is A variety of membrane seals around the air gap are in one state. Therefore, in the present working example, external air can be prevented from intruding into the Cu-bonding portions, and the reliability of the semiconductor device 530 can be ensured.

<<6.第五工作實例>> <<6. Fifth working example>>

描述其中沿一第一半導體部件之一第一Cu連結部分與一第二半導體部件之一第二層間絕緣膜之間之一連結介面設置一氣隙之一半導體裝置之另一組態實例作為一第五工作實例。 Another configuration example in which a semiconductor device is disposed along a connection interface between a first Cu-bonding portion and a second interlayer insulating film of a second semiconductor component is provided as a first Five working examples.

[半導體裝置之組態] [Configuration of Semiconductor Device]

圖34及圖35展示根據一第五工作實例之一半導體裝置之一般組態。特定言之，圖34展示一連結介面附近根據該第五工作實例之半導體裝置之一示意橫截面，且圖35展示該連結介面附近之一示意俯視圖並圖解說明Cu連結部分及介面Cu障壁膜與沿該連結介面界定之一氣隙之一配置關係。應注意，在圖34及圖35中，為簡化描述，僅展示一連結介 面附近之一組態。進一步言之，在圖34中所示之本工作實例之半導體裝置540中，藉由相同的元件符號標示類似於圖31中之第四工作實例之半導體裝置530之元件。 34 and 35 show a general configuration of a semiconductor device according to a fifth working example. In particular, FIG. 34 shows a schematic cross section of a semiconductor device according to the fifth working example in the vicinity of a bonding interface, and FIG. 35 shows a schematic top view of the vicinity of the bonding interface and illustrates the Cu bonding portion and the interface Cu barrier film and One of the air gaps is defined along the joint interface. It should be noted that in FIG. 34 and FIG. 35, in order to simplify the description, only one link is shown. One configuration near the face. Further, in the semiconductor device 540 of the present working example shown in FIG. 34, elements of the semiconductor device 530 similar to the fourth working example in FIG. 31 are denoted by the same reference numerals.

首先參考圖34，該半導體裝置540包含作為一第一半導體區段之一第一半導體部件531及作為一第二半導體區段之一第二半導體部件420。 Referring first to FIG. 34, the semiconductor device 540 includes a first semiconductor component 531 as one of the first semiconductor segments and a second semiconductor component 420 as one of the second semiconductor segments.

該第一半導體部件531之組態類似於上文參考圖31描述之第四工作實例中之組態。特定言之，該第一半導體部件531經組態使得在上文參考圖14描述之第一工作實例中該第一半導體部件410之連結介面Sj側上之表面區域中，於該第一Cu連結部分533與該第二半導體部件420之第二層間絕緣膜425相對之表面區域中設置一凹陷部分534。同時，該第二半導體部件420具有類似於上文參考圖14描述之第一工作實例中之組態，相似之處在於：該介面Cu障壁膜428係設置於該第二層間絕緣膜425在該連結介面Sj側上之表面上。 The configuration of the first semiconductor component 531 is similar to the configuration in the fourth working example described above with reference to FIG. In particular, the first semiconductor component 531 is configured such that in the surface region on the side of the bonding interface Sj of the first semiconductor component 410 in the first working example described above with reference to FIG. 14, the first Cu bonding A concave portion 534 is disposed in a surface region of the portion 533 opposite to the second interlayer insulating film 425 of the second semiconductor member 420. Meanwhile, the second semiconductor component 420 has a configuration similar to that in the first working example described above with reference to FIG. 14, similarly in that the interface Cu barrier film 428 is disposed on the second interlayer insulating film 425. Connected to the surface on the side of the interface Sj.

在本工作實例中之半導體裝置540中，在該第一半導體部件531在該連結介面Sj上之表面區域中，該凹陷部分534如上所述般設置於該第一Cu連結部分533與該第二半導體部件420之介面Cu障壁膜428相對之表面區域中。因此，沿該連結介面Sj形成於一氣隙，跨該連結介面Sj該第一半導體部件531之第一Cu連結部分533與該第二半導體部件420之介面Cu障壁膜428彼此相對。進一步言之，在本工作實例中，如圖34中所示，藉由該第一Cu連結部分533之凹陷 部分534及該介面Cu障壁膜428在該連結介面Sj側上之表面界定之氣隙被置於其中該氣隙藉由該氣隙周圍的各種膜密封之一狀態中。 In the semiconductor device 540 of the working example, in the surface region of the first semiconductor component 531 on the bonding interface Sj, the recessed portion 534 is disposed on the first Cu bonding portion 533 and the second as described above. The interface of the semiconductor component 420 is in the opposite surface region of the Cu barrier film 428. Therefore, the connection interface Sj is formed in an air gap, and the first Cu connection portion 533 of the first semiconductor component 531 and the interface Cu barrier film 428 of the second semiconductor component 420 are opposed to each other across the connection interface Sj. Further, in the present working example, as shown in FIG. 34, the depression of the first Cu joint portion 533 The portion 534 and the air gap defined by the surface of the interface Cu barrier film 428 on the side of the joint interface Sj are placed in a state in which the air gap is sealed by various films around the air gap.

特定言之，在本工作實例中，一介面障壁部分亦由該第一Cu連結部分533之凹陷部分534及該第二半導體部件420與該凹陷部分534相對之連結介面Sj側上之表面區域部分或面區域部分組態。進一步言之，在本工作實例中，藉由形成於該表面障壁部分中之氣隙及亦藉由該介面Cu障壁膜428防止Cu自該第一Cu連結部分533擴散至該第二層間絕緣膜425中。 Specifically, in the working example, the interface barrier portion is also formed by the recessed portion 534 of the first Cu connecting portion 533 and the surface portion of the second semiconductor member 420 opposite to the recessed portion 534 on the side of the joint interface Sj. Partial area configuration. Further, in the present working example, the diffusion of Cu from the first Cu bonding portion 533 to the second interlayer insulating film is prevented by the air gap formed in the surface barrier portion and also by the interface Cu barrier film 428. 425.

[半導體裝置之製造技術] [Manufacturing Technology of Semiconductor Device]

現在，參考圖36A至圖36D描述本工作實例中之半導體裝置540之一製造技術。應注意，圖36A及圖36B展示於不同步驟處製造之半導體部件之一Cu連結部分附近之示意橫截面，且圖36C及圖36D圖解說明該第一半導體部件531與該第二半導體部件420之間之一連結製程之一方式。 Now, a manufacturing technique of one of the semiconductor devices 540 in the present working example will be described with reference to FIGS. 36A to 36D. It should be noted that FIGS. 36A and 36B show schematic cross sections near the Cu junction portion of one of the semiconductor components fabricated at different steps, and FIGS. 36C and 36D illustrate the first semiconductor component 531 and the second semiconductor component 420. One of the ways to link the process.

首先，在本工作實例中，如圖36A中所示以類似於上文參考圖16A至圖16F描述之第一工作實例中之第一半導體部件410之製造步驟處之一方式製造一第一半導體部件531。 First, in the present working example, a first semiconductor is fabricated in a manner similar to that of the first semiconductor component 410 in the first working example described above with reference to FIGS. 16A to 16F as shown in FIG. 36A. Component 531.

進一步言之，在本工作實例中，如圖36B中所示以類似於上文參考圖16G至圖16L描述之第一工作實例中之第二半導體部件420之製造步驟處之一方式製造一第二半導體部件420。然而，在本工作實例中，可為(例如)SiN膜或SiCN膜之介面Cu障壁膜428之膜厚度係約10奈米至100奈 米，且藉由一CVD方法或一旋塗方法形成一介面Cu障壁膜428。進一步言之，在本工作實例中，在對應於圖16I之步驟之第二層間絕緣膜425中形成對應於該第二Cu連結部分426及該第二Cu障壁層427之一形成區域之一開口之步驟處，將該開口之開口直徑設定為約4微米至100微米。 Further, in the present working example, as shown in FIG. 36B, one of the manufacturing steps of the second semiconductor component 420 in the first working example described above with reference to FIGS. 16G to 16L is manufactured. Two semiconductor components 420. However, in this working example, the film thickness of the interface Cu barrier film 428 which may be, for example, a SiN film or a SiCN film is about 10 nm to 100 nm. And an interface Cu barrier film 428 is formed by a CVD method or a spin coating method. Further, in the present working example, an opening corresponding to one of the second Cu bonding portion 426 and the second Cu barrier layer 427 is formed in the second interlayer insulating film 425 corresponding to the step of FIG. 16I. At the step, the opening diameter of the opening is set to be about 4 to 100 μm.

接著，對該第一半導體部件531在該第一Cu連結部分533側上之表面及該第二半導體部件420在該第二Cu連結部分426側上之表面實施一還原製程以移除該等Cu連結部分之表面上之氧化物膜或氧化物以使純淨的Cu曝露於該等Cu連結部分之該表面。應注意，使用其中使用舉例而言諸如甲酸之藥物溶液之一濕式蝕刻製程或其中使用(例如)Ar、NH3或H2之電漿之一乾式蝕刻製程作為此例項中之還原製程。 Next, a surface of the first semiconductor component 531 on the first Cu-connecting portion 533 side and a surface of the second semiconductor component 420 on the second Cu-bonding portion 426 side are subjected to a reduction process to remove the Cu. An oxide film or oxide on the surface of the joint portion is used to expose pure Cu to the surface of the Cu joint portion. It should be noted that a dry etching process in which one of the drug solutions such as formic acid is used, or a plasma in which, for example, Ar, NH 3 or H 2 is used, is used as the reduction process in this example.

此後，如圖36C中所示，該第一半導體部件531在該第一Cu連結部分533側上之表面與該第二半導體部件420在該第二Cu連結部分426側上之表面彼此接觸或彼此接合。 Thereafter, as shown in FIG. 36C, the surface of the first semiconductor component 531 on the side of the first Cu bonding portion 533 and the surface of the second semiconductor component 420 on the side of the second Cu bonding portion 426 are in contact with each other or each other. Engage.

接著，如圖36D中所示，在其中該第一半導體部件531與該第二半導體部件420彼此接合之狀態中，使用舉例而言諸如一加熱板之一加熱設備或退火設備或一RTA設備以使所接合部件退火以使該第一Cu連結部分533與該第二Cu連結部分426彼此連結。特定言之，在(例如)大氣壓力之N2氛圍中或真空中在約100℃至400℃下加熱所接合部件持續約5分鐘至兩個小時。 Next, as shown in FIG. 36D, in a state in which the first semiconductor component 531 and the second semiconductor component 420 are bonded to each other, using, for example, a heating device or an annealing device or an RTA device such as a heating plate The joined member is annealed to connect the first Cu joining portion 533 and the second Cu joining portion 426 to each other. Specifically, the joined component is heated in an N 2 atmosphere of, for example, atmospheric pressure or in a vacuum at about 100 ° C to 400 ° C for about 5 minutes to 2 hours.

在本工作實例中，類似於上述該第四工作實例中，藉由 圖36D中所示之退火製程進一步加固該第一Cu連結部分533之Cu膜。此後，在該連結介面Sj上之第一Cu連結部分533與介面Cu障壁膜428之間之接觸區域中，該第一Cu連結部分533收縮且該第一Cu連結部分533之表面在其中其經間隔遠離該連結介面Sj之一方向上後移。因此，如圖36D中所示，在該第一半導體部件531在該連結介面Sj上之表面區域中，在該第一Cu連結部分533與該介面Cu障壁膜428相對之表面區域中形成一凹陷部分534。 In this working example, similar to the fourth working example described above, by The annealing process shown in Fig. 36D further reinforces the Cu film of the first Cu joining portion 533. Thereafter, in the contact region between the first Cu bonding portion 533 and the interface Cu barrier film 428 on the bonding interface Sj, the first Cu bonding portion 533 is shrunk and the surface of the first Cu bonding portion 533 is in the The interval is shifted back in a direction away from one of the connection interfaces Sj. Therefore, as shown in FIG. 36D, in the surface region of the first semiconductor component 531 on the bonding interface Sj, a recess is formed in a surface region of the first Cu bonding portion 533 opposite to the interface Cu barrier film 428. Part 534.

特定言之，藉由圖36D中所示之退火製程，形成一結構，其中沿該第一Cu連結部分533與該介面Cu障壁膜428之間之連結介面Sj形成一氣隙，且該氣隙藉由該氣隙周圍之各種膜密封在該半導體裝置540中。應注意，為藉由圖36D中所示之退火製程形成該凹陷部分534，較佳地在(例如)高於經實施以在製造該等半導體部件時形成精細膜品質之Cu連結部分之退火製程之退火溫度之一溫度下實施該退火。 Specifically, a structure is formed by the annealing process shown in FIG. 36D, wherein an air gap is formed along the bonding interface Sj between the first Cu connecting portion 533 and the interface Cu barrier film 428, and the air gap is borrowed. Various films around the air gap are sealed in the semiconductor device 540. It should be noted that the recessed portion 534 is formed by the annealing process illustrated in FIG. 36D, preferably at, for example, an annealing process that is higher than a Cu-bonded portion that is formed to form a fine film quality when the semiconductor components are fabricated. The annealing is performed at one of the annealing temperatures.

在本工作實例中，以如上所述之此一方式實施一Cu-Cu連結製程。應注意，該半導體裝置540之製造製程除上述連結步驟外之其他部分類似於舉例而言諸如一固態影像擷取裝置(參考(例如)日本專利特許公開案第2007-234725號)之一當前可用半導體裝置之製造技術。 In the present working example, a Cu-Cu joining process is carried out in such a manner as described above. It should be noted that the manufacturing process of the semiconductor device 540 is currently available except for the above-described joining step, such as, for example, one of the solid-state image capturing devices (refer to, for example, Japanese Patent Laid-Open Publication No. 2007-234725). Manufacturing technology of semiconductor devices.

如上所述，本工作實例中之半導體裝置540經結構化使得在沿該第一Cu連結部分533與該介面Cu障壁膜428之間之連結介面Sj之一區域中形成一氣隙使得該第一Cu連結部 分533與該介面Cu障壁膜428彼此不直接接觸。進一步言之，在本工作實例中，該介面Cu障壁膜428形成於與該第一Cu連結部分533之凹陷部分534相對之區域中。因此，在本工作實例中，可較高肯定地防止Cu自該第一Cu連結部分533擴散至該第二層間絕緣膜425中。 As described above, the semiconductor device 540 in the present working example is structured such that an air gap is formed in a region along the bonding interface Sj between the first Cu bonding portion 533 and the interface Cu barrier film 428 such that the first Cu Linkage The minute 533 and the interface Cu barrier film 428 are not in direct contact with each other. Further, in the present working example, the interface Cu barrier film 428 is formed in a region opposing the recessed portion 534 of the first Cu bonding portion 533. Therefore, in the present working example, Cu can be prevented from diffusing into the second interlayer insulating film 425 from the first Cu bonding portion 533 with higher certainty.

進一步言之，在本工作實例之半導體裝置540中，沿該第一Cu連結部分533與該介面Cu障壁膜428之間之連結介面Sj形成之氣隙被置於其中該氣隙藉由該氣隙周圍的各種膜密封之一狀態中。因此，在本工作實例中，類似於上述該第四工作實例中，可防止外部空氣侵入該等Cu連結部分，且可保證該半導體裝置540之可靠性。 Further, in the semiconductor device 540 of the working example, an air gap formed along the bonding interface Sj between the first Cu connecting portion 533 and the interface Cu barrier film 428 is placed therein, wherein the air gap is obtained by the gas A variety of membrane seals around the gap are in one state. Therefore, in the present working example, similar to the fourth working example described above, external air can be prevented from intruding into the Cu-bonding portions, and the reliability of the semiconductor device 540 can be ensured.

應注意，在本工作實例中，雖然上文結合該第四工作實例描述之一介面障壁部分之形成技術應用於上文參考圖14描述之第一工作實例之半導體裝置401，但是本發明並不限於此。例如，上文結合該第四工作實例描述之一介面障壁部分之形成技術亦可應用於上文參考圖17描述之第二工作實例之半導體裝置402或上文參考圖20描述之第三工作實例之半導體裝置403。進一步言之，上文結合該第四工作實例描述之一介面障壁部分之形成技術亦可應用於(例如)上文參考圖23至圖26等等描述之修改之各種半導體裝置。 It should be noted that in the present working example, although the formation technique of one of the interface barrier portions described above in connection with the fourth working example is applied to the semiconductor device 401 of the first working example described above with reference to FIG. 14, the present invention is not Limited to this. For example, the formation technique of one of the interface barrier portions described above in connection with the fourth working example can also be applied to the semiconductor device 402 of the second working example described above with reference to FIG. 17 or the third working example described above with reference to FIG. Semiconductor device 403. Further, the formation technique of one of the interface barrier portions described above in connection with the fourth working example can also be applied to, for example, various semiconductor devices modified as described above with reference to FIGS. 23 to 26 and the like.

進一步言之，上文結合該第四工作實例描述之一介面障壁部分之形成技術亦可應用於上文參考圖27及圖34描述之各種參考實例之半導體裝置。然而，在此例項中，不僅在 該第一Cu連結部分與該第二層間絕緣膜相對之表面區域上而且在該第二Cu連結部分與該第一層間絕緣膜相對之表面區域中沿該連結介面Sj形成一凹陷部分。 Further, the formation technique of one of the interface barrier portions described above in connection with the fourth working example can also be applied to the semiconductor devices of the various reference examples described above with reference to FIGS. 27 and 34. However, in this example, not only A surface of the first Cu connecting portion opposite to the second interlayer insulating film and a surface portion of the second Cu connecting portion opposite to the first interlayer insulating film form a recessed portion along the connecting interface Sj.

<<7.應用>> <<7. Application>>

上文結合各種工作實例及修改描述之半導體裝置及用於該半導體裝置之製造技術(即，該等Cu-Cu連結技術)可應用於需要接合兩個基板以在製造時實施一Cu-Cu連結製程之各種電子設備。特定言之，上述該等工作實例及修改之Cu-Cu連結技術可適當地應用於(例如)一固態影像擷取裝置之製造。 The semiconductor device described above in connection with various working examples and modifications, and the manufacturing technique for the semiconductor device (ie, the Cu-Cu bonding technique) can be applied to the need to bond two substrates to implement a Cu-Cu connection at the time of manufacture. Various electronic devices of the process. In particular, the above-described working examples and modified Cu-Cu joining techniques can be suitably applied to, for example, the manufacture of a solid-state image capturing device.

[應用1] [Application 1]

圖37展示可應用上文結合各種工作實例及修改描述之半導體裝置及用於半導體裝置之製造技術之一半導體影像感測器模組之一組態之一實例。參考圖37，半導體影像感測器模組700係由連結在一起之一第一半導體晶片701及一第二半導體晶片702組態。 37 shows an example of one configuration of a semiconductor image sensor module to which the semiconductor device and one of the manufacturing techniques for the semiconductor device described above can be applied in combination with various working examples and modifications. Referring to FIG. 37, the semiconductor image sensor module 700 is configured by a first semiconductor wafer 701 and a second semiconductor wafer 702 joined together.

該第一半導體晶片701具有一光電二極體形成區域703、一電晶體形成區域704及建立在該第一半導體晶片701中之一類比/數位轉換器陣列705。該電晶體形成區域704及該類比/數位轉換器陣列705係按順序層壓在該光電二極體形成區域703上。 The first semiconductor wafer 701 has a photodiode forming region 703, a transistor forming region 704, and an analog/digital converter array 705 built in the first semiconductor wafer 701. The transistor forming region 704 and the analog/digital converter array 705 are laminated in this order on the photodiode forming region 703.

在該類比/數位轉換器陣列705中形成滲透接觸部分706。該等滲透接觸部分706之各者經形成使得其在其之一端部分處曝露於該類比/數位轉換器陣列705在該第二半導 體晶片702側上之表面。 A permeable contact portion 706 is formed in the analog/digital converter array 705. Each of the permeable contact portions 706 is formed such that it is exposed at one of its end portions to the analog/digital converter array 705 at the second semiconductor The surface on the side of the bulk wafer 702.

同時，該第二半導體晶片702由一記憶體陣列組態且具有形成於其內部之接觸部分707。該等接觸部分707之各者經形成使得其在其之一端部分處曝露於該第二半導體晶片702在該第一半導體晶片701側上之表面。 At the same time, the second semiconductor wafer 702 is configured by a memory array and has a contact portion 707 formed therein. Each of the contact portions 707 is formed such that it is exposed at one end portion thereof to the surface of the second semiconductor wafer 702 on the side of the first semiconductor wafer 701.

接著，該等滲透接觸部分706與該等接觸部分707經加熱且彼此接觸接合，接合的狀態為其等彼此鄰接以使該第一半導體晶片701與該第二半導體晶片702彼此連結，以藉此製造該半導體影像感測器模組700。運用具有如上所述之此一組態之半導體影像感測器模組700，可增加每一單位面積之像素數目並可減小厚度。 Then, the permeable contact portions 706 and the contact portions 707 are heated and brought into contact with each other, and the joined state is adjacent to each other to connect the first semiconductor wafer 701 and the second semiconductor wafer 702 to each other, thereby The semiconductor image sensor module 700 is fabricated. With the semiconductor image sensor module 700 having such a configuration as described above, the number of pixels per unit area can be increased and the thickness can be reduced.

在本應用之半導體影像感測器模組700中，上述該等工作實例及該等修改之Cu-Cu連結技術可應用於(例如)該第一半導體晶片701與該第二半導體晶片702之間之連結步驟。在此例項中，可進一步改良該第一半導體晶片701與該第二半導體晶片702之間之連結介面之可靠性。 In the semiconductor image sensor module 700 of the present application, the above-described working examples and the modified Cu-Cu bonding techniques can be applied, for example, between the first semiconductor wafer 701 and the second semiconductor wafer 702. The linking step. In this example, the reliability of the connection interface between the first semiconductor wafer 701 and the second semiconductor wafer 702 can be further improved.

[應用2] [Application 2]

圖38展示可應用上文結合各種工作實例及修改描述之半導體裝置及用於半導體裝置之製造技術(即，該等Cu-Cu連結技術)之背側照明類型之一固態影像擷取裝置之部分之一示意橫截面。 38 shows portions of a solid-state image capturing device that can be applied to the semiconductor device of the various working examples and modifications described above, and the backside illumination type of the semiconductor device manufacturing technology (ie, the Cu-Cu bonding technology). One shows a cross section.

參考圖38，藉由使呈包含一像素陣列之一部分製造物品之形式之一第一半導體基板810及呈包含一邏輯電路之一部分製造物品之形式之一第二半導體基板820彼此連結組 態所示之固態影像擷取裝置800。應注意，在圖38中所示之固態影像擷取裝置800中，按順序在該第一半導體基板810與該第二半導體基板820相對之一面上層壓一平坦膜830、一晶片上彩色濾光片831及一晶片上微透鏡陣列832。 Referring to FIG. 38, a first semiconductor substrate 810 in the form of an article comprising a portion of a pixel array and a second semiconductor substrate 820 in the form of an article comprising a portion of a logic circuit are connected to each other. The solid state image capturing device 800 shown in the state. It should be noted that, in the solid-state image capturing device 800 shown in FIG. 38, a flat film 830 and a color filter on a wafer are laminated on one surface of the first semiconductor substrate 810 and the second semiconductor substrate 820 in sequence. Sheet 831 and a wafer on microlens array 832.

該第一半導體基板810包含P型之一半導體井區域811及一多層配接線層812。該半導體井區域811被安置在該平坦膜830側上之第一半導體基板810上。在該半導體井區域811中，形成(例如)一光電二極體(PD)、一浮動擴散區(FD)、組態一像素之MOS電晶體(Tr1及Tr2)及組態一控制電路之MOS電晶體(Tr3及Tr4)。同時，在該多層配接線層812中，複數個金屬配接線814被形成為一層間絕緣膜813內插於該多層配接線層812與該複數個金屬配接線814之間，且在該層間絕緣膜813中形成連接導體815以使該等金屬配接線814與對應的MOS電晶體彼此連接。 The first semiconductor substrate 810 includes a P-type semiconductor well region 811 and a multilayer wiring layer 812. The semiconductor well region 811 is disposed on the first semiconductor substrate 810 on the side of the flat film 830. In the semiconductor well region 811, for example, a photodiode (PD), a floating diffusion (FD), a MOS transistor (Tr1 and Tr2) configuring a pixel, and a MOS configuring a control circuit are formed. Transistors (Tr3 and Tr4). Meanwhile, in the multilayer wiring layer 812, a plurality of metal wirings 814 are formed as an interlayer insulating film 813 interposed between the multilayer wiring layer 812 and the plurality of metal wirings 814, and insulated between the layers. Connecting conductors 815 are formed in the film 813 to connect the metal wiring wires 814 and the corresponding MOS transistors to each other.

同時，該第二半導體基板820包含形成於(例如)矽基板之表面中之一半導體井區域821及形成於該第一半導體基板810側上之半導體井區域821中之一多層配接線層822。在該半導體井區域821中，形成組態一邏輯電路之MOS電晶體(Tr6、Tr7及Tr8)。同時，在該多層配接線層822中，複數個金屬配接線824被形成為一層間絕緣膜823內插於該多層配接線層822與該複數個金屬配接線824之間，且在該層間絕緣膜823中形成連接導體825以將該等金屬配接線824連接至對應的MOS電晶體。 Meanwhile, the second semiconductor substrate 820 includes a semiconductor well region 821 formed on, for example, a surface of the germanium substrate, and a multilayer wiring layer 822 formed in the semiconductor well region 821 formed on the first semiconductor substrate 810 side. . In the semiconductor well region 821, MOS transistors (Tr6, Tr7, and Tr8) configuring a logic circuit are formed. Meanwhile, in the multilayer wiring layer 822, a plurality of metal wirings 824 are formed as an interlayer insulating film 823 interposed between the multilayer wiring layer 822 and the plurality of metal wirings 824, and insulated between the layers. A connection conductor 825 is formed in the film 823 to connect the metal distribution wires 824 to the corresponding MOS transistors.

根據上述本發明之工作實例及修改之Cu-Cu連結技術亦可應用於上述組態之背側照明類型之固態影像擷取裝置800。 The working example of the present invention and the modified Cu-Cu joining technique can also be applied to the solid-state image capturing device 800 of the backside illumination type of the above configuration.

第四實施例 Fourth embodiment

<<1.半導體裝置之概述>> <<1. Overview of Semiconductor Devices>>

描述一半導體裝置之一連結電極之一組態之一概述。 An overview of one of the configurations of one of the connection electrodes of a semiconductor device is described.

圖39展示一連結電極之一般組態且特別展示包含一連結電極之一連結部分之一橫截面組態。 Figure 39 shows a general configuration of a joint electrode and in particular shows a cross-sectional configuration of one of the joint portions of a joint electrode.

在未展示之一半導體基板上形成一第一連結部分910。該第一連結部分910包含一第一配接線層912及透過一通孔913連接至該第一配接線層912之一第一連結電極911。 A first joint portion 910 is formed on one of the semiconductor substrates not shown. The first connecting portion 910 includes a first wiring layer 912 and a first connecting electrode 911 connected to the first wiring layer 912 through a through hole 913.

該第一配接線層912形成於一層間絕緣層919中。在該層間絕緣層919上形成一層間絕緣層917，其中一中間層918內插於其等之間。在該層間絕緣層917上設置另一層間絕緣層915，其中一中間層916內插於其等之間。 The first wiring layer 912 is formed in an interlayer insulating layer 919. An interlayer insulating layer 917 is formed on the interlayer insulating layer 919, and an intermediate layer 918 is interposed between them. Another interlayer insulating layer 915 is disposed on the interlayer insulating layer 917, and an intermediate layer 916 is interposed between them.

該第一連結電極911形成於該層間絕緣層915中，且該第一連結電極911之表面曝露於該層間絕緣層915之表面。此曝露表面經形成與該層間絕緣層915之表面齊平。 The first connection electrode 911 is formed in the interlayer insulating layer 915, and the surface of the first connection electrode 911 is exposed on the surface of the interlayer insulating layer 915. The exposed surface is formed flush with the surface of the interlayer insulating layer 915.

該第一配接線層912與該第一連結電極911透過延伸穿過該中間層916、該層間絕緣層917及該中間層918之通孔913而彼此電連接。 The first wiring layer 912 and the first connection electrode 911 are electrically connected to each other through a through hole 913 extending through the intermediate layer 916, the interlayer insulating layer 917, and the intermediate layer 918.

在該第一連結電極911與該通孔913及該層間絕緣層915及917與該中間層916之間設置用於防止一電極材料擴散至一絕緣層中之一障壁金屬層914。進一步言之，在該第一 配接線層912與該層間絕緣層919之間設置另一障壁金屬層931。 A barrier metal layer 914 for preventing diffusion of an electrode material into an insulating layer is disposed between the first connection electrode 911 and the via 913 and the interlayer insulating layers 915 and 917 and the intermediate layer 916. Further, at the first Another barrier metal layer 931 is disposed between the wiring layer 912 and the interlayer insulating layer 919.

類似於上述該第一連結部分910，在未展示之一半導體基板上形成一第二連結部分920。該第二連結部分920包含一第二配接線層922及透過一通孔923連接至該第二配接線層922之一第二連結電極921。 Similar to the first joint portion 910 described above, a second joint portion 920 is formed on one of the semiconductor substrates not shown. The second connecting portion 920 includes a second wiring layer 922 and a second connecting electrode 921 connected to the second wiring layer 922 through a through hole 923.

該第二配接線層922形成於一層間絕緣層929中。在該層間絕緣層929上形成另一層間絕緣層927，其中一中間層928內插於其等之間。在該層間絕緣層927上設置又一層間絕緣層925，其中一中間層926內插於其等之間。 The second wiring layer 922 is formed in the interlayer insulating layer 929. Another interlayer insulating layer 927 is formed on the interlayer insulating layer 929, and an intermediate layer 928 is interposed between them. A further interlayer insulating layer 925 is disposed on the interlayer insulating layer 927, and an intermediate layer 926 is interposed between them.

該第二連結電極921形成於該層間絕緣層925中使得其之表面自該層間絕緣層925之表面曝露。此曝露表面經形成與該層間絕緣層925之表面齊平。 The second connection electrode 921 is formed in the interlayer insulating layer 925 such that the surface thereof is exposed from the surface of the interlayer insulating layer 925. The exposed surface is formed to be flush with the surface of the interlayer insulating layer 925.

該第二配接線層922與該第二連結電極921透過延伸穿過該中間層926、該層間絕緣層927及該中間層928之通孔923而彼此電連接。 The second wiring layer 922 and the second connection electrode 921 are electrically connected to each other through a through hole 923 extending through the intermediate layer 926, the interlayer insulating layer 927, and the intermediate layer 928.

在該第二連結電極921與該通孔923及該層間絕緣層925及927與該中間層926之間設置用於防止一電極材料擴散至一絕緣層中之一障壁金屬層924。在該第二配接線層922與該層間絕緣層929之間設置另一障壁金屬層932。 A barrier metal layer 924 for preventing diffusion of an electrode material into an insulating layer is disposed between the second connection electrode 921 and the via hole 923 and the interlayer insulating layers 925 and 927 and the intermediate layer 926. Another barrier metal layer 932 is disposed between the second wiring layer 922 and the interlayer insulating layer 929.

如上所述，該第一連結部分910與該第二連結部分920彼此接合，接合的狀態為其中該第一連結電極911與該第二連結電極921連結在一起。 As described above, the first connecting portion 910 and the second connecting portion 920 are joined to each other in a state in which the first connecting electrode 911 and the second connecting electrode 921 are coupled together.

進一步言之，該第一連結電極911及該第二連結電極921 經設計使得其等之一者之面積大於其等之另一者之面積，使得即使其等之間之連結位置移位，其等之間之連結面積亦未發生差別以保證高連結可靠性。運用圖39中所示之組態，因為該第二連結電極921具有較大面積，所以克服位置移位之連接可靠性得以保證。 Further, the first connection electrode 911 and the second connection electrode 921 It is designed such that the area of one of the others is larger than the area of the other one, so that even if the joint position between them is shifted, the joint area between them is not different to ensure high connection reliability. With the configuration shown in Fig. 39, since the second joint electrode 921 has a large area, the connection reliability against the positional displacement is ensured.

如上所述，在圖39所示之組態中，因為該第一連結電極911及該第二連結電極912在其等之間具有一面積差，所以具有一較大面積之第二連結電極921在其之表面上具有直接接觸該第一連結部分910之層間絕緣膜915之一接觸部分933。 As described above, in the configuration shown in FIG. 39, since the first connection electrode 911 and the second connection electrode 912 have an area difference therebetween, the second connection electrode 921 having a large area is provided. One of the contact portions 933 of the interlayer insulating film 915 having direct contact with the first joint portion 910 is provided on the surface thereof.

此接觸部分933在Cu或其類似物之一金屬層處直接接觸該層間絕緣層915。 This contact portion 933 directly contacts the interlayer insulating layer 915 at a metal layer of Cu or the like.

進一步言之，因為組態該層間絕緣層915等等之SiO2一般具有易於吸收水分之一本質，所以該等層中易於包含水(H2O)。進一步言之，近年來用於高效能裝置之一低k材料(k<2.4)具有一更高的水分吸收性質。 Further, since SiO 2 configuring the interlayer insulating layer 915 or the like generally has an essence of easily absorbing moisture, it is easy to contain water (H 2 O) in the layers. Furthermore, in recent years, a low-k material (k < 2.4) for high-performance devices has a higher moisture absorption property.

因此，在上面該第二連結電極921與該層間絕緣層915彼此直接接觸之接觸部分933上，包含於該層間絕緣層915中等等中之水930與該第二連結電極921彼此接觸。在此例項中，存在諸如組態該第二連結電極921之Cu之金屬可能腐蝕之可能性。 Therefore, on the contact portion 933 where the second connection electrode 921 and the interlayer insulating layer 915 are in direct contact with each other, the water 930 included in the interlayer insulating layer 915 or the like and the second connection electrode 921 are in contact with each other. In this example, there is a possibility that a metal such as Cu configuring the second connection electrode 921 may corrode.

如上所述，在其中半導體基板在其等之金屬連結電極處彼此接觸之組態之一半導體裝置中，該等連結電極被包含於該等層間絕緣層中之水發生腐蝕。若水腐蝕該等連結電 極，則此增加電阻、連結產生故障等等，從而妨礙該等半導體裝置之一正常功能。 As described above, in one semiconductor device in which the semiconductor substrates are in contact with each other at the metal connection electrodes thereof, the connection electrodes are corroded by water contained in the interlayer insulating layers. If the water corrodes the connected electricity Extremely, this increases the resistance, the connection creates a fault, etc., thereby preventing one of the semiconductor devices from functioning properly.

因此，對於在該等連結電極處連結在一起之半導體裝置，要求用於防止包含於該等層間絕緣層中之水腐蝕該等連結電極之一組態。 Therefore, for a semiconductor device that is bonded together at the connection electrodes, it is required to prevent the water contained in the interlayer insulating layers from corroding one of the connection electrodes.

<<2.半導體裝置之實施例>> <<2. Embodiment of Semiconductor Device>>

在下文中，描述根據本實施例之具有一連結電極之一半導體裝置。 Hereinafter, a semiconductor device having one of the connection electrodes according to the present embodiment will be described.

圖40A及圖40B展示包含根據本實施例之一連結電極之一半導體裝置之一般組態。特定言之，圖40A展示本實施例之半導體裝置之一連結電極區域附近該半導體裝置之一般組態，且圖40B展示圖40A中所示之一第一連結部分940之一連結面950之一俯視圖。應注意，圖40A及圖40B僅展示一連結電極之一形成區域附近之一般組態，同時省略設置在上面形成該等連結電極之半導體基板及該等連結電極周圍之組件。 40A and 40B show a general configuration of a semiconductor device including one of the bonding electrodes according to the present embodiment. Specifically, FIG. 40A shows a general configuration of the semiconductor device in the vicinity of one of the connection electrode regions of the semiconductor device of the present embodiment, and FIG. 40B shows one of the connection faces 950 of one of the first connection portions 940 shown in FIG. 40A. Top view. It should be noted that FIGS. 40A and 40B only show a general configuration of a vicinity of one of the connection regions of the connection electrode, and the semiconductor substrate on which the connection electrodes are formed and the components around the connection electrodes are omitted.

首先參考圖40A，形成一半導體裝置，其中一第一連結部分940與一第二連結部分960連結在一起，其中其等之電極形成面彼此相對。 Referring first to FIG. 40A, a semiconductor device is formed in which a first joint portion 940 is joined to a second joint portion 960, wherein the electrode forming faces thereof are opposed to each other.

該第一連結部分940包含一連結面950上之一第一連結電極941、一第二連結電極942及一第三連結電極943。同時，該第二連結部分960包含該連結面950上之一第四連結電極961、一第五連結電極962及一第六連結電極963。 The first connecting portion 940 includes a first connecting electrode 941 , a second connecting electrode 942 and a third connecting electrode 943 on a connecting surface 950 . At the same time, the second connecting portion 960 includes a fourth connecting electrode 961, a fifth connecting electrode 962 and a sixth connecting electrode 963 on the connecting surface 950.

該第一連結部分940之第一連結電極941與該第二連結部 分960之第四連結電極961連結在一起。進一步言之，該第二連結電極942與該第五連結電極962連結在一起，且該第三連結電極943與該第六連結電極963連結在一起。 a first connecting electrode 941 of the first connecting portion 940 and the second connecting portion The fourth joining electrode 961 of the minute 960 is joined together. Further, the second connection electrode 942 is coupled to the fifth connection electrode 962, and the third connection electrode 943 is coupled to the sixth connection electrode 963.

[絕緣層] [Insulation]

該第一連結部分940及該第二連結部分960之各者係由彼此層壓之複數個配接線層及絕緣層組態。 Each of the first joint portion 940 and the second joint portion 960 is configured by a plurality of wiring layers and insulation layers laminated to each other.

該第一連結部分940之絕緣層包含按此順序自該連結面950側層壓之一第一層間絕緣層951、一第一中間層952、一第二層間絕緣層953、一第二中間層954及一第三層間絕緣層955。同時，該第二連結部分960之絕緣層包含按此順序自該連結面950側層壓之一第四層間絕緣層971、一第三中間層972、一第五層間絕緣層973、一第四中間層974及一第六層間絕緣層975。 The insulating layer of the first connecting portion 940 includes a first interlayer insulating layer 951, a first intermediate layer 952, a second interlayer insulating layer 953, and a second intermediate layer laminated from the connecting surface 950 side in this order. A layer 954 and a third interlayer insulating layer 955. Meanwhile, the insulating layer of the second connecting portion 960 includes a fourth interlayer insulating layer 971, a third intermediate layer 972, a fifth interlayer insulating layer 973, and a fourth layer laminated from the side of the connecting surface 950 in this order. The intermediate layer 974 and a sixth interlayer insulating layer 975.

[導體層：第一連結部分] [Conductor layer: first joint part]

該第一連結部分940之第一連結電極941、第二連結電極942及第三連結電極943形成於該第一層間絕緣膜951中。該第一連結電極941、該第二連結電極942及該第三連結電極943在其等之表面處曝露於該連結面950且經形成與該第一層間絕緣膜951齊平。 The first connection electrode 941, the second connection electrode 942, and the third connection electrode 943 of the first connection portion 940 are formed in the first interlayer insulating film 951. The first connection electrode 941, the second connection electrode 942, and the third connection electrode 943 are exposed to the connection surface 950 at the surface thereof and are formed flush with the first interlayer insulating film 951.

在與該第二中間層954呈一接觸關係之第三層間絕緣層955中之位置處形成一第一配接線946、一第二配接線947及一第三配接線948。 A first wiring 946, a second wiring 947 and a third wiring 948 are formed at a position in the third interlayer insulating layer 955 in a contact relationship with the second intermediate layer 954.

該第一連結電極941與該第一配接線946透過延伸穿過該第一中間層952、該第二層間絕緣層953及該第二中間層 954之一第一通孔956而彼此電連接。類似地，該第二連結電極942與該第二配接線947透過一第二通孔957而彼此電連接。該第三連結電極943與該第三配接線948透過一第三通孔958而彼此電連接。 The first connecting electrode 941 and the first connecting wire 946 are transmitted through the first intermediate layer 952, the second interlayer insulating layer 953 and the second intermediate layer. One of the first through holes 956 of 954 is electrically connected to each other. Similarly, the second connecting electrode 942 and the second connecting wire 947 are electrically connected to each other through a second through hole 957. The third connecting electrode 943 and the third connecting wire 948 are electrically connected to each other through a third through hole 958.

進一步言之，在該第一連結電極941與該第一層間絕緣層951之間設置用於防止該第一連結電極941擴散至該第一層間絕緣層951中之一障壁金屬層941A。同時，在該第二連結電極942及該第三連結電極943與該第一層間絕緣層951之間設置障壁金屬層942A及943A。進一步言之，在該第一配接線946與該第三層間絕緣層955之間設置一障壁金屬層946A；在該第二配接線947與該第三層間絕緣層955之間設置一障壁金屬層947A；且在該第三配接線948與該第三層間絕緣層955之間設置一障壁金屬層948A。 Further, between the first connection electrode 941 and the first interlayer insulating layer 951, a barrier metal layer 941A for preventing the first connection electrode 941 from diffusing into the first interlayer insulating layer 951 is provided. At the same time, barrier metal layers 942A and 943A are provided between the second connection electrode 942 and the third connection electrode 943 and the first interlayer insulating layer 951. Further, a barrier metal layer 946A is disposed between the first wiring 946 and the third interlayer insulating layer 955; a barrier metal layer is disposed between the second wiring 947 and the third interlayer insulating layer 955 947A; and a barrier metal layer 948A is disposed between the third wiring 948 and the third interlayer insulating layer 955.

進一步言之，分別在該第一通孔956、該第二通孔957及該第三通孔958與該第一中間層952、該第二層間絕緣層953及該第二中間層954之間設置障壁金屬層956A、957A及958A。該第一通孔956、該第二通孔957及該第三通孔958分別透過該等障壁金屬層956A、957A及958A連接至該第一配接線946、該第二配接線947及該第三配接線948。 Further, between the first through hole 956, the second through hole 957 and the third through hole 958 and the first intermediate layer 952, the second interlayer insulating layer 953 and the second intermediate layer 954 Barrier metal layers 956A, 957A, and 958A are provided. The first through hole 956, the second through hole 957 and the third through hole 958 are respectively connected to the first connecting wire 946, the second connecting wire 947 and the first through the barrier metal layers 956A, 957A and 958A. Three distribution wiring 948.

[導體層：第二連結部分] [Conductor layer: second joint portion]

該第二連結部分960之第四連結電極961、第五連結電極962及第六連結電極963形成於該第四層間絕緣膜971中。該第四連結電極961、該第五連結電極962及該第六連結電極963在其等之表面處曝露於該連結面950且經形成與該第 四層間絕緣膜971齊平。 The fourth connection electrode 961, the fifth connection electrode 962, and the sixth connection electrode 963 of the second connection portion 960 are formed in the fourth interlayer insulating film 971. The fourth connection electrode 961, the fifth connection electrode 962, and the sixth connection electrode 963 are exposed to the connection surface 950 at the surface thereof and are formed and The four-layer insulating film 971 is flush.

在與該第四中間層974呈一接觸關係之第六層間絕緣層975中之位置處形成一第四配接線966、一第五配接線967及一第六配接線968。 A fourth distribution line 966, a fifth distribution line 967 and a sixth distribution line 968 are formed at a position in the sixth interlayer insulating layer 975 in a contact relationship with the fourth intermediate layer 974.

該第四連結電極961與該第四配接線966透過延伸穿過該第三中間層972、該第五層間絕緣層973及該第四中間層974之一第四通孔976而彼此電連接。類似地，該第五連結電極962與該第五配接線967透過一第五通孔977而彼此電連接。該第六連結電極963與該第六配接線968透過一第六通孔978而彼此電連接。 The fourth connecting electrode 961 and the fourth connecting wire 966 are electrically connected to each other through a fourth through hole 976 extending through the third intermediate layer 972, the fifth interlayer insulating layer 973 and the fourth intermediate layer 974. Similarly, the fifth connecting electrode 962 and the fifth connecting wire 967 are electrically connected to each other through a fifth through hole 977. The sixth connection electrode 963 and the sixth connection line 968 are electrically connected to each other through a sixth through hole 978.

進一步言之，在該第四連結電極961與該第四層間絕緣層971之間設置用於防止該第四連結電極961擴散至該第四層間絕緣層971中之一障壁金屬層961A。進一步言之，分別在該第五連結電極962及該第六連結電極963與該第四層間絕緣層971之間設置障壁金屬層962A及963A。進一步言之，在該第四配接線966與該第六層間絕緣層975之間設置一障壁金屬層966A；在該第五配接線967與該第六層間絕緣層975之間設置一障壁金屬層967A；且在該第六配接線968與該第六層間絕緣層975之間設置一障壁金屬層968A。 Further, between the fourth connection electrode 961 and the fourth interlayer insulating layer 971, a barrier metal layer 961A for preventing the fourth connection electrode 961 from diffusing into the fourth interlayer insulating layer 971 is provided. Further, barrier metal layers 962A and 963A are provided between the fifth connection electrode 962 and the sixth connection electrode 963 and the fourth interlayer insulating layer 971, respectively. Further, a barrier metal layer 966A is disposed between the fourth wiring 966 and the sixth interlayer insulating layer 975; a barrier metal layer is disposed between the fifth wiring 967 and the sixth interlayer insulating layer 975. 967A; and a barrier metal layer 968A is disposed between the sixth wiring 968 and the sixth interlayer insulating layer 975.

在該第四通孔976、該第五通孔977及該第六通孔978與該第三中間層972、該第五層間絕緣層973及該第四中間層974之間亦分別設置障壁金屬層976A、977A及978A。該第四通孔976、該第五通孔977及該第六通孔978分別透過該等障壁金屬層976A、977A及978A連接至該第四配接線 966、該第五配接線967及該第六配接線968。 A barrier metal is also disposed between the fourth through hole 976, the fifth through hole 977, the sixth through hole 978, the third intermediate layer 972, the fifth interlayer insulating layer 973, and the fourth intermediate layer 974. Layers 976A, 977A and 978A. The fourth through hole 976, the fifth through hole 977 and the sixth through hole 978 are respectively connected to the fourth matching wire through the barrier metal layers 976A, 977A and 978A. 966. The fifth distribution line 967 and the sixth distribution line 968.

[材料] [material]

該第一配接線946、該第二配接線947、該第三配接線948、該第四配接線966、該第五配接線967及該第六配接線968係由普遍用於一半導體裝置之配接線之一材料(舉例而言諸如Al或Cu)形成。 The first distribution line 946, the second distribution line 947, the third distribution line 948, the fourth distribution line 966, the fifth distribution line 967, and the sixth distribution line 968 are commonly used in a semiconductor device. A material of the wiring, such as, for example, Al or Cu, is formed.

同時，該第一連結電極941、該第二連結電極942、該第三連結電極943、該第四連結電極961、該第五連結電極962及該第六連結電極963係由容許連結一半導體基板之一介電材料(舉例而言諸如Cu)形成。 At the same time, the first connection electrode 941, the second connection electrode 942, the third connection electrode 943, the fourth connection electrode 961, the fifth connection electrode 962, and the sixth connection electrode 963 are allowed to be connected to a semiconductor substrate. One dielectric material, such as, for example, Cu, is formed.

該等障壁金屬層係由普遍用於一半導體裝置中之障壁金屬層之一材料(舉例而言諸如Ta、Ti、Ru、TaN或TiN)形成。 The barrier metal layers are formed of a material commonly used in a barrier metal layer in a semiconductor device, such as, for example, Ta, Ti, Ru, TaN, or TiN.

該第一層間絕緣膜951、該第二層間絕緣膜953、該第三層間絕緣膜955、該第四層間絕緣膜971、該第五層間絕緣膜973及該第六層間絕緣膜975係由(例如)SiO2、由含氟氧化矽(FSG)或聚芳醚(PAE)表示之有機矽基聚合物、由氫化矽倍半氧烷(HSQ)或甲基矽倍半氧烷(MSQ)表示之一無機材料形成，且特別係由具有約2.7或更小之一相對介電常數之一低介電常數(低k)材料形成。 The first interlayer insulating film 951, the second interlayer insulating film 953, the third interlayer insulating film 955, the fourth interlayer insulating film 971, the fifth interlayer insulating film 973, and the sixth interlayer insulating film 975 are (for example) SiO 2 , an organic fluorenyl polymer represented by fluorinated yttrium oxide (FSG) or polyarylene ether (PAE), hydrogenated heptapropane oxide (HSQ) or methyl sesquioxanes (MSQ) It is meant that one of the inorganic materials is formed, and in particular is formed of a low dielectric constant (low k) material having one of the relative dielectric constants of about 2.7 or less.

如圖40A中所示，該第一層間絕緣層至該第六層間絕緣層951、953、955、971、973及975由於該等絕緣層之水分吸收而易於包含水(H2O)970。 As shown in FIG. 40A, the first interlayer insulating layer to the sixth interlayer insulating layer 951, 953, 955, 971, 973, and 975 easily contain water (H 2 O) 970 due to moisture absorption of the insulating layers. .

該第一中間層952、該第二中間層954、該第三中間層 972及該第四中間層974係由普遍用於組態一半導體裝置中之配接線等等之一金屬材料之一擴散防止層之一材料組態。進一步言之，該等中間層係不太可能容許包含於該等層間絕緣層中之水970滲透之高密度絕緣層。進一步言之，用作剛剛描述之擴散防止層之此等高密度絕緣層係由藉由(例如)一旋塗方法或一CVD方法形成之一相對介電常數4至7之P-SiN或一相對介電常數等於或小於4之SiCN(含有C)或類似物組態。 The first intermediate layer 952, the second intermediate layer 954, and the third intermediate layer The 972 and the fourth intermediate layer 974 are configured by one of the diffusion preventing layers of one of the metal materials commonly used for configuring a wiring in a semiconductor device or the like. Further, the intermediate layers are less likely to allow the high density insulating layer that the water 970 contained in the interlayer insulating layers penetrate. Further, the high-density insulating layers used as the diffusion preventing layer just described are formed of P-SiN or a relative dielectric constant of 4 to 7 by, for example, a spin coating method or a CVD method. A SiCN (with C) or similar configuration with a relative dielectric constant of 4 or less.

[連結部分] [link section]

如上所述，組態一半導體裝置，其中半導體基板連結在一起，連結的狀態為其中該第一連結電極941、該第二連結電極942及該第三連結電極943與該第四連結電極961、該第五連結電極962及該第六連結電極963連結在一起。 As described above, a semiconductor device is configured in which the semiconductor substrates are connected together, and the connected state is the first connection electrode 941, the second connection electrode 942, the third connection electrode 943, and the fourth connection electrode 961, The fifth connection electrode 962 and the sixth connection electrode 963 are coupled together.

進一步言之，如圖40A中所示，該第一連結部分940之連結電極及該第二連結部分960之連結電極經組態使得其等之一者之面積較大以保證連結可靠性。藉由此組態，當連結位置移位時該等電極之間之連結面積亦不會改變。 Further, as shown in FIG. 40A, the connection electrode of the first connection portion 940 and the connection electrode of the second connection portion 960 are configured such that the area of one of them is large to ensure connection reliability. With this configuration, the joint area between the electrodes does not change when the joint position is shifted.

在圖40A中所示之組態中，該第二連結電極942、該第四連結電極961及該第六連結電極963經形成具有大於各自相對連結電極之一面積。因此，在該第二連結電極942上，形成直接接觸該第四層間絕緣層971之一接觸部分949。進一步言之，在該第四連結電極961及該第六連結電極963之表面上，分別形成直接接觸該第一層間絕緣層951之接觸部分969及979。 In the configuration shown in FIG. 40A, the second connection electrode 942, the fourth connection electrode 961, and the sixth connection electrode 963 are formed to have an area larger than one of the respective opposite connection electrodes. Therefore, on the second connection electrode 942, a contact portion 949 which directly contacts the fourth interlayer insulating layer 971 is formed. Further, on the surfaces of the fourth connection electrode 961 and the sixth connection electrode 963, contact portions 969 and 979 that directly contact the first interlayer insulating layer 951 are formed, respectively.

[保護層] [The protective layer]

該第一連結部分940包含該第一連結電極941周圍之一第一保護層944。該第一連結部分940進一步包含包圍該第二連結電極942及該第三連結電極943之周邊之一第二保護層945。 The first connecting portion 940 includes a first protective layer 944 around the first connecting electrode 941. The first connecting portion 940 further includes a second protective layer 945 surrounding one of the second connecting electrode 942 and the third connecting electrode 943.

如圖40B中所示，該第一保護層944及該第二保護層945係由包圍該第一連結電極941之周邊之一單層形成。進一步言之，如圖40A中所示，該第一保護層944係形成於其透過該第一層間絕緣層951自該第一連結部分940之連結面950延伸至該第一中間層952之一深度之一凹陷部分中。該第二保護層945形成於其透過該第一層間絕緣層951、該第一中間層952及該第二層間絕緣層953自該第一連結部分940之連結面950延伸至該第二中間層954之一深度之一凹陷部分中。 As shown in FIG. 40B, the first protective layer 944 and the second protective layer 945 are formed by a single layer surrounding a periphery of the first connection electrode 941. Further, as shown in FIG. 40A, the first protective layer 944 is formed to extend from the connecting surface 950 of the first connecting portion 940 to the first intermediate layer 952 through the first interlayer insulating layer 951. One of the depths is in one of the recessed portions. The second protective layer 945 is formed through the first interlayer insulating layer 951, the first intermediate layer 952 and the second interlayer insulating layer 953 extending from the connecting surface 950 of the first connecting portion 940 to the second intermediate portion. One of the depths of one of the layers 954 is in the recessed portion.

進一步言之，如圖40A中所示，該第二連結部分960具有設置於其上對應於上述該第一保護層944之一位置處之一第三保護層964。進一步言之，該第二連結部分960具有設置於其上對應於上述該第二保護層945之一位置處之一第四保護層965。 Further, as shown in FIG. 40A, the second joint portion 960 has a third protective layer 964 disposed thereon at a position corresponding to one of the first protective layers 944 described above. Further, the second joint portion 960 has a fourth protective layer 965 disposed thereon at a position corresponding to one of the second protective layers 945 described above.

該第三保護層964形成於其包圍該第四連結電極961之周邊且透過該第四層間絕緣層971自該第二連結部分960之連結面950延伸至該第三中間層972之一深度之一凹陷部分中。 The third protective layer 964 is formed at a periphery thereof surrounding the fourth connecting electrode 961 and extends from the connecting surface 950 of the second connecting portion 960 to a depth of the third intermediate layer 972 through the fourth interlayer insulating layer 971. In a recessed part.

該第四保護層965形成於其包圍該第五連結電極962及該 第六連結電極963之周邊且透過該第四層間絕緣層971自該第二連結部分960之連結面950延伸至該第三中間層972之一深度之一凹陷部分中。 The fourth protective layer 965 is formed on the fifth connecting electrode 962 and the The periphery of the sixth connection electrode 963 and the fourth interlayer insulating layer 971 extend from the joint surface 950 of the second joint portion 960 to a recessed portion of one of the depths of the third intermediate layer 972.

該第一保護層944及該第三保護層964設置於其等沿該連結面950彼此接觸之位置處。藉由此組態，該第一連結電極941與該第四連結電極961之連結部分係藉由該第一保護層944、該第三保護層964、該第一中間層952及該第三中間層972包圍。 The first protective layer 944 and the third protective layer 964 are disposed at positions where the connecting surfaces 950 are in contact with each other. By this configuration, the connecting portion of the first connecting electrode 941 and the fourth connecting electrode 961 is formed by the first protective layer 944, the third protective layer 964, the first intermediate layer 952, and the third intermediate portion. Layer 972 is surrounded.

進一步言之，該第二保護層945及該第四保護層965設置於其等沿該連結面950彼此接觸之位置處。因此，該第二連結電極942與該第五連結電極962之連結部分及該第三連結電極943與該第六連結電極963之連結部分係藉由該第二保護層945、該第四保護層965、該第二中間層954及該第三中間層972包圍。 Further, the second protective layer 945 and the fourth protective layer 965 are disposed at positions where the connecting surfaces 950 are in contact with each other. Therefore, the connection portion between the second connection electrode 942 and the fifth connection electrode 962 and the connection portion between the third connection electrode 943 and the sixth connection electrode 963 are provided by the second protective layer 945 and the fourth protective layer. 965, the second intermediate layer 954 and the third intermediate layer 972 are surrounded.

該第一保護層944、該第二保護層945、該第三保護層964及該第四保護層965係由類似於上述該等障壁金屬層之材料之一材料形成，且係由(例如)Ti、Ru、TaN或TiN形成。 The first protective layer 944, the second protective layer 945, the third protective layer 964, and the fourth protective layer 965 are formed of a material similar to the material of the barrier metal layer described above, and are, for example, Ti, Ru, TaN or TiN are formed.

[保護層：作用] [Protection layer: role]

如上所述，應用於該第一層間絕緣層951、該第四層間絕緣層971或類似物之SiO2、一低k材料或類似物具有易於吸收水分之一本質。特別係若使用一電漿連結方法將層間絕緣層連結在一起，則藉由該等絕緣層之表面處理及加熱處理在該等連結面上產生水。因此，水(H2O)970由於絕緣 層材料之水分吸收而易於包含在該第一層間絕緣層951、該第四層間絕緣層971或類似物中。 As described above, SiO 2 , a low-k material or the like applied to the first interlayer insulating layer 951, the fourth interlayer insulating layer 971 or the like has an essence of easily absorbing moisture. In particular, if the interlayer insulating layers are joined together by a plasma bonding method, water is generated on the connecting surfaces by surface treatment and heat treatment of the insulating layers. Therefore, water (H 2 O) 970 is easily contained in the first interlayer insulating layer 951, the fourth interlayer insulating layer 971 or the like due to moisture absorption of the insulating layer material.

在本實施例之半導體裝置之組態中，該第一保護層944、該第二保護層945、該第三保護層964及該第四保護層965設置於該等連結電極周圍。若該等保護層係由類似於該等障壁金屬層之材料之一材料組態，則可防止包含於該等絕緣層中之水970滲透。進一步言之，該第一中間層952及該第三中間層972係由不太容易容許水970滲透之P-SiN之一高密度絕緣層或類似物組態。 In the configuration of the semiconductor device of the embodiment, the first protective layer 944, the second protective layer 945, the third protective layer 964, and the fourth protective layer 965 are disposed around the connecting electrodes. If the protective layers are configured of a material similar to the material of the barrier metal layers, the water 970 contained in the insulating layers can be prevented from penetrating. Further, the first intermediate layer 952 and the third intermediate layer 972 are configured by a high-density insulating layer or the like of P-SiN which is less likely to allow water 970 to penetrate.

因此，可藉由該第一保護層944、該第三保護層964、該第一中間層952及該第三中間層972攔截包含於該第一層間絕緣層951或該第四層間絕緣層971中之水970。 Therefore, the first interlayer insulating layer 944, the third interlayer 952, the first intermediate layer 952, and the third intermediate layer 972 can be intercepted by the first interlayer insulating layer 951 or the fourth interlayer insulating layer. Water 970 in 971.

進一步言之，可藉由該第二保護層945、該第四保護層965、該第二中間層954及該第三中間層972攔截包含於該第一層間絕緣層951或該第四層間絕緣層971中之水970。 Further, the second protective layer 945, the fourth protective layer 965, the second intermediate layer 954, and the third intermediate layer 972 may be interposed between the first interlayer insulating layer 951 or the fourth layer. Water 970 in insulating layer 971.

藉由上述組態，可藉由該第一連結電極941與該第四連結電極961之連結部分抑制水970與該第四連結電極961與該第一層間絕緣層951之間之接觸部分969之接觸。類似地，可藉由該第二連結電極942與該第五連結電極962之連結部分抑制水970與該第二連結電極942與該第四層間絕緣層971之間之接觸部分949之接觸。進一步言之，可藉由該第三連結電極943與該第六連結電極963之連結部分抑制水970與該第六連結電極963與該第一層間絕緣層951之間之接觸部分979之接觸。 With the above configuration, the contact portion 969 between the water 970 and the fourth connecting electrode 961 and the first interlayer insulating layer 951 can be suppressed by the connecting portion of the first connecting electrode 941 and the fourth connecting electrode 961. Contact. Similarly, the contact between the water 970 and the contact portion 949 between the second connecting electrode 942 and the fourth interlayer insulating layer 971 can be suppressed by the connecting portion of the second connecting electrode 942 and the fifth connecting electrode 962. Further, the contact between the water 970 and the contact portion 979 between the sixth connection electrode 963 and the first interlayer insulating layer 951 can be suppressed by the connection portion of the third connection electrode 943 and the sixth connection electrode 963. .

應注意，在上述組態中，該第四連結電極961之接觸部分969在藉由該第一保護層944、該第三保護層964、該第一中間層952及該第三中間層972包圍之一區域中接觸包含於該第一層間絕緣層951中之水970。因此，較佳地將該第一連結電極941與該第一保護層944之間之距離及該第四連結電極961與該第三保護層964之間之距離設定為儘可能短。例如，將該等距離設定為用於佈線之設計規則中允許之最小距離，使得其中可存在一絕緣層之區域在藉由該第一保護層944、該第三保護層964等等包圍之一區域內係最小的。可將一連結電極與一保護層之間之最小距離之最小值設定為約50奈米，且可在一普遍半導體裝置的設計規則中將其設定為2微米至4微米。 It should be noted that in the above configuration, the contact portion 969 of the fourth connection electrode 961 is surrounded by the first protection layer 944, the third protection layer 964, the first intermediate layer 952, and the third intermediate layer 972. Water 970 included in the first interlayer insulating layer 951 is contacted in one of the regions. Therefore, it is preferable to set the distance between the first connection electrode 941 and the first protective layer 944 and the distance between the fourth connection electrode 961 and the third protection layer 964 to be as short as possible. For example, the equidistance is set to a minimum distance allowed in the design rule for wiring such that an area in which an insulating layer may exist is surrounded by the first protective layer 944, the third protective layer 964, and the like. The area is the smallest. The minimum distance between the minimum distance between a bonding electrode and a protective layer can be set to about 50 nm, and can be set to 2 micrometers to 4 micrometers in a general semiconductor device design rule.

該第二連結電極942之接觸部分949或該第六連結電極963之接觸部分979在該第三保護層964、該第四保護層965等等之區域中亦接觸包含於該第一層間絕緣層951及該第四層間絕緣層971中之水970。因此，根據用於配線之設計規則，較佳地將該第二保護層945及該第四保護層965定位儘可能分別接近該第二連結電極942及該第六連結電極963。 The contact portion 949 of the second connection electrode 942 or the contact portion 979 of the sixth connection electrode 963 is also in contact with the first interlayer insulating layer 964, the fourth protective layer 965, and the like. The water 970 in the layer 951 and the fourth interlayer insulating layer 971. Therefore, according to the design rule for wiring, the second protective layer 945 and the fourth protective layer 965 are preferably positioned as close as possible to the second connecting electrode 942 and the sixth connecting electrode 963, respectively.

進一步言之，需要包圍待以此一方式形成之一連結電極之一保護層屏蔽由易於吸收水分之一材料製成之至少一絕緣層。因此，該保護層較佳地形成於自其中設置該連結電極之一層間絕緣層之表面(即，自連結面)至該層間絕緣層上之一絕緣層(即，至一中間層)之一深度。 Further, it is necessary to surround one of the bonding electrodes to be formed in such a manner that the protective layer shields at least one insulating layer made of a material which is easy to absorb moisture. Therefore, the protective layer is preferably formed on one surface (ie, self-joining surface) from which an interlayer insulating layer of the connecting electrode is disposed to one of insulating layers (ie, to an intermediate layer) on the interlayer insulating layer depth.

進一步言之，一保護層可形成於比其中形成一連結電極之一層間絕緣層更深之一位置。例如，一保護層可經形成以透過該第一層間絕緣層951、該第一中間層952及該第二層間絕緣層953自該連結面950延伸至該保護層如該第二保護層945一樣接觸該第二中間層954之一位置。根據該第二保護層945之組態，因為可攔截該第二層間絕緣層953中之水，所以可防止可自該第二層間絕緣層953滲透該第一中間層952之水970。 Further, a protective layer may be formed at a position deeper than an interlayer insulating layer in which one of the connection electrodes is formed. For example, a protective layer may be formed to extend from the bonding surface 950 to the protective layer such as the second protective layer 945 through the first interlayer insulating layer 951, the first intermediate layer 952, and the second interlayer insulating layer 953. The position of one of the second intermediate layers 954 is similarly contacted. According to the configuration of the second protective layer 945, since the water in the second interlayer insulating layer 953 can be intercepted, the water 970 which can penetrate the first intermediate layer 952 from the second interlayer insulating layer 953 can be prevented.

進一步言之，因為彼此接觸之保護層之一者之寬度被設定為大於另一保護層沿該連結面950之寬度，所以即使該等半導體基板之連結位置發生移位，亦可保證該等保護層之間之連接可靠性。在如圖40A中所示之本實施例之半導體裝置之組態中，在該連結面上該第三保護層964及該第四保護層965之寬度大於該第一保護層944及該第二保護層945之寬度。 Further, since the width of one of the protective layers contacting each other is set to be larger than the width of the other protective layer along the connecting surface 950, the protection can be ensured even if the connection position of the semiconductor substrates is shifted. Connection reliability between layers. In the configuration of the semiconductor device of the embodiment shown in FIG. 40A, the width of the third protective layer 964 and the fourth protective layer 965 on the bonding surface is greater than the first protective layer 944 and the second The width of the protective layer 945.

特定言之，該第三保護層964及該第一保護層944經組態使得該第三保護層964之連結電極側(即，內側)經定位比該第一保護層944更接近該連結電極，且與該第三保護層964之連結電極相對之側(即，該第三保護層964之外側)經定位比該第一保護層944更遠離該連結電極。依此方式，藉由設定該第三保護層964之寬度為較大，即使在該連結位置發生移位時，該第一保護層944亦在該第三保護層964之寬度內接觸該第三保護層964。 In particular, the third protective layer 964 and the first protective layer 944 are configured such that the connecting electrode side (ie, the inner side) of the third protective layer 964 is positioned closer to the connecting electrode than the first protective layer 944. And the side opposite to the connecting electrode of the third protective layer 964 (ie, the outer side of the third protective layer 964) is positioned farther away from the connecting electrode than the first protective layer 944. In this manner, by setting the width of the third protective layer 964 to be large, the first protective layer 944 contacts the third within the width of the third protective layer 964 even when the joint position is displaced. Protective layer 964.

進一步言之，該第四保護層965及該第二保護層945經組 態使得該第四保護層965之連結電極側(即，內側)經定位比該第二保護層945更接近該連結電極，且與該第四保護層965之連結電極相對之側(即，該第四保護層965之外側)經定位比該第二保護層945更遠離該連結電極。依此方式，藉由設定該第四保護層965之寬度為較大，即使在該連結位置發生移位時，該第二保護層945亦在該第四保護層965之寬度內接觸該第四保護層965。 Further, the fourth protective layer 965 and the second protective layer 945 are grouped The state in which the connecting electrode side (ie, the inner side) of the fourth protective layer 965 is positioned closer to the connecting electrode than the second protective layer 945 and opposite to the connecting electrode of the fourth protective layer 965 (ie, the The outer side of the fourth protective layer 965 is positioned farther away from the connecting electrode than the second protective layer 945. In this manner, by setting the width of the fourth protective layer 965 to be large, the second protective layer 945 contacts the fourth within the width of the fourth protective layer 965 even when the joint position is displaced. Protective layer 965.

藉由上述組態，可保證克服位置移位之連接可靠性。 With the above configuration, the connection reliability that overcomes the position shift can be ensured.

[保護層：效果] [Protection layer: effect]

運用上述本實施例之半導體裝置之組態，因為形成包圍一連結電極之一保護層，所以可將水的接觸(造成該連結部分及該連結電極被腐蝕的因素)抑制到最小程度。因此，可抑制該連結電極之腐蝕，且可給半導體裝置提供一良好的電特性及可靠性。 With the configuration of the semiconductor device of the present embodiment described above, since the protective layer surrounding one of the connection electrodes is formed, the contact of water (the factor causing the connection portion and the connection electrode to be corroded) can be suppressed to a minimum. Therefore, corrosion of the connection electrode can be suppressed, and a good electrical characteristic and reliability can be provided to the semiconductor device.

因此，可提供電特性及可靠性改良之半導體裝置。進一步言之，因為可抑制由腐蝕引起的電阻值增加，所以可預期半導體裝置之處理速度增強且功率消耗減小。 Therefore, a semiconductor device with improved electrical characteristics and reliability can be provided. Further, since the increase in the resistance value caused by the corrosion can be suppressed, it is expected that the processing speed of the semiconductor device is enhanced and the power consumption is reduced.

進一步言之，因為該等連結電極藉由該等保護層包圍，所以亦可減小流過該電極連結部分之一電信號之外部干擾。因此，可預期半導體裝置之雜訊減小。 Further, since the connection electrodes are surrounded by the protective layers, external interference flowing through an electrical signal of one of the electrode connection portions can also be reduced. Therefore, it is expected that the noise of the semiconductor device is reduced.

應注意，該等連結電極及該等保護層之形狀並不限於上文結合本實施例描述之形狀。該等保護層之形狀並不限於圖40B中所示之圓形形狀，而是僅在其等與該等連結電極具有包圍該等保護層之連結面上之一連結電極之一連續形 狀之情況下可為任何其他形狀。該等連結電極之形狀亦不限於如圖40B中所示之一圓形形狀，而是可為任何其他形狀。 It should be noted that the shapes of the connecting electrodes and the protective layers are not limited to the shapes described above in connection with the embodiment. The shape of the protective layer is not limited to the circular shape shown in FIG. 40B, but is continuous only in one of the connecting electrodes of the connecting surface and the connecting electrode having the protective layer. In the case of a shape, it can be any other shape. The shape of the connecting electrodes is also not limited to one circular shape as shown in Fig. 40B, but may be any other shape.

<<3.半導體裝置之製造方法>> <<3. Manufacturing method of semiconductor device>>

現在描述本實施例之半導體裝置之一製造方法之一實例。應注意，在該製造方法之下列描述中，僅描述關於上文參考圖40A及圖40B描述之第一連結電極941與第四連結電極961之間之連結部分之半導體裝置之一製造方法，同時省略半導體裝置之其他部分之組態之一製造方法之描述。可以類似於關於該第一連結電極941與該第四連結電極961之間之連結部分之半導體裝置之製造方法製造該第二連結電極942與該第五連結電極962之間之連結部分、該第三連結電極943與該第六連結電極963之間之連結部分等等。進一步言之，省略半導體基板、配接線層、其他各種電晶體及各種元件之一製造方法之描述，此係因為其等可以已知方法製造。 An example of a method of manufacturing one of the semiconductor devices of the present embodiment will now be described. It should be noted that in the following description of the manufacturing method, only one manufacturing method of the semiconductor device regarding the joint portion between the first connection electrode 941 and the fourth connection electrode 961 described above with reference to FIGS. 40A and 40B is described, while Description of a manufacturing method that omits the configuration of other parts of the semiconductor device. The connection portion between the second connection electrode 942 and the fifth connection electrode 962 can be manufactured similarly to the method of manufacturing a semiconductor device in which the connection portion between the first connection electrode 941 and the fourth connection electrode 961 is A connecting portion between the third connecting electrode 943 and the sixth connecting electrode 963, and the like. Further, descriptions of a semiconductor substrate, a wiring layer, various other transistors, and a manufacturing method of one of various elements are omitted because they can be manufactured by a known method.

進一步言之，藉由相同的元件符號標示類似於上文參考圖40A及圖40B描述之本實施例之半導體裝置之元件，且本文省略其等之重複詳細描述以避免冗餘。 Further, elements of the semiconductor device of the present embodiment similar to those described above with reference to FIGS. 40A and 40B are denoted by the same element symbols, and repeated detailed descriptions thereof are omitted herein to avoid redundancy.

首先，如圖41A中所示形成連接至一接地裝置且包含一障壁金屬層946A及一第一配接線946之一第三層間絕緣層955。可使用應用於一半導體裝置之一普遍製造方法或一相同技術之一鑲嵌製程(參考(例如)日本專利特許公開案第2004-63859號)形成包含該第一配接線946之第三層間絕緣 層955。接著，在該第一配接線946及該第三層間絕緣層955上形成10奈米至100奈米厚之一第二中間層954。 First, a third interlayer insulating layer 955 connected to a grounding device and including a barrier metal layer 946A and a first wiring 946 is formed as shown in FIG. 41A. The third interlayer insulation including the first wiring 946 can be formed using a general manufacturing method applied to one of the semiconductor devices or a damascene process (refer to, for example, Japanese Patent Laid-Open Publication No. 2004-63859). Layer 955. Next, a second intermediate layer 954 of 10 nm to 100 nm thick is formed on the first wiring 946 and the third interlayer insulating layer 955.

接著，如圖41B中所示在該第二中間層954上形成20奈米至200奈米厚之呈SiO2層、SiOC層或類似物形式之一第二層間絕緣層953。接著，在該二層間絕緣層953上形成10奈米至100奈米厚之呈SiN層、SiCN層或類似物形式之一第一中間層952。在該第一中間層952上形成20奈米至200奈米厚之呈SiO2層、SiOC層形式之一第一層間絕緣層951。 Next, a second interlayer insulating layer 953 of 20 nm to 200 nm thick in the form of a SiO 2 layer, an SiOC layer or the like is formed on the second intermediate layer 954 as shown in FIG. 41B. Next, a first intermediate layer 952 of a thickness of 10 nm to 100 nm in the form of a SiN layer, a SiCN layer or the like is formed on the two interlayer insulating layer 953. A first interlayer insulating layer 951 of a thickness of 20 nm to 200 nm in the form of an SiO 2 layer or an SiOC layer is formed on the first intermediate layer 952.

可使用(例如)一CVD方法或一旋塗方法形成上述該第一層間絕緣層951、該第一中間層952、該二層間絕緣層953、該第二中間層954及該第三層間絕緣層955。 The first interlayer insulating layer 951, the first intermediate layer 952, the second interlayer insulating layer 953, the second intermediate layer 954, and the third interlayer insulating layer may be formed by, for example, a CVD method or a spin coating method. Layer 955.

進一步言之，如圖41B中所示在該第一層間絕緣層951上形成一光阻層991。該光阻層991形成於一圖案中，其中該光阻層991在其之一形成位置處朝一第一通孔956等等開口以連接一下層配接線結構(諸如該第一配接線946)。 Further, a photoresist layer 991 is formed on the first interlayer insulating layer 951 as shown in FIG. 41B. The photoresist layer 991 is formed in a pattern in which the photoresist layer 991 is opened at a position where it is formed toward a first via 956 or the like to connect a layer wiring structure (such as the first wiring 946).

接著，如圖41C中所示使用磁控管類型之一普遍蝕刻設備藉由一乾式蝕刻方法自該光阻層991上方蝕刻該第一層間絕緣層951、該第一中間層952及該第二層間絕緣層953。 Next, as shown in FIG. 41C, the first interlayer insulating layer 951, the first intermediate layer 952, and the first layer are etched from the photoresist layer 991 by a dry etching method using one of the magnetron type universal etching apparatuses. A two-layer insulating layer 953.

在蝕刻該第一層間絕緣層951、該第一中間層952及該第二層間絕緣層953後，實施基於氧氣(O2)電漿之一灰化製程及藉由有機胺基藥物之溶液之一製程。藉由該等製程，完全移除該光阻層991及該蝕刻製程中產生之殘留沈積物。 After etching the first interlayer insulating layer 951, the first intermediate layer 952 and the second interlayer insulating layer 953, performing an ashing process based on oxygen (O 2 ) plasma and a solution by an organic amine-based drug One process. By the processes, the photoresist layer 991 and residual deposits generated in the etching process are completely removed.

接著，如圖41D中所示藉由一旋塗方法塗敷50奈米至1微米厚之一有機樹脂，且藉由一塗敷設備中設置之一加熱器在30℃至200℃下煆燒該有機樹脂以形成一有機材料層992。接著，藉由一CVD方法或一旋塗方法在該有機材料層992上形成20奈米至200奈米厚之SiO2層以形成氧化物層993。 Next, an organic resin of 50 nm to 1 μm thick is applied by a spin coating method as shown in FIG. 41D, and is calcined at 30 ° C to 200 ° C by a heater provided in a coating apparatus. The organic resin forms an organic material layer 992. Next, a SiO 2 layer of 20 nm to 200 nm thick is formed on the organic material layer 992 by a CVD method or a spin coating method to form an oxide layer 993.

此後，如圖41E中所示在該氧化物層993上形成一光阻層994。該光阻層994形成於一圖案中，其中該光阻層994在待形成連結部分之第一連結電極941及第一保護層944之一位置處開口。 Thereafter, a photoresist layer 994 is formed on the oxide layer 993 as shown in FIG. 41E. The photoresist layer 994 is formed in a pattern in which the photoresist layer 994 is opened at a position of the first connection electrode 941 and the first protective layer 944 where the connection portion is to be formed.

接著，使用磁控管類型之一普遍蝕刻設備藉由一乾式蝕刻方法自該光阻層994上方蝕刻該氧化物層993。接著，使用所蝕刻氧化物層993以使用磁控管類型之一普遍蝕刻設備藉由一乾式蝕刻方法蝕刻該有機材料層992及該第一層間絕緣層951。 Next, the oxide layer 993 is etched from above the photoresist layer 994 by a dry etching method using one of the magnetron type universal etching devices. Next, the etched oxide layer 993 is used to etch the organic material layer 992 and the first interlayer insulating layer 951 by a dry etching method using one of the magnetron type universal etching devices.

此後，實施基於氧氣(O2)電漿之一灰化製程及藉由有機胺基藥物之溶液之一製程以完全移除該氧化物層993、該有機材料層992及該蝕刻製程中產生之殘留沈積物。藉由此製程，同時蝕刻該第一配接線946上之第二中間層954以曝露該第一配接線946以獲得如圖41G中所示之此一形狀。 Thereafter, a process based on one of an oxygen (O 2 ) plasma ashing process and a solution of an organic amine-based drug is performed to completely remove the oxide layer 993, the organic material layer 992, and the etching process. Residual deposits. By this process, the second intermediate layer 954 on the first wiring 946 is simultaneously etched to expose the first wiring 946 to obtain such a shape as shown in FIG. 41G.

接著，如圖41H中所示形成用於形成一障壁金屬層956A及該第一保護層944之一障壁材料層995。在Ar/N2氛圍中藉由一RF濺鍍製程由Ti、Ta、Ru或其等之氮化物之任一者形成一厚度為5奈米至50奈米之障壁材料層995。 Next, a barrier material layer 995 for forming a barrier metal layer 956A and the first protective layer 944 is formed as shown in FIG. 41H. A barrier material layer 995 having a thickness of 5 nm to 50 nm is formed from any of nitrides of Ti, Ta, Ru or the like by an RF sputtering process in an Ar/N 2 atmosphere.

接著，如圖41I中所示使用一電解電鍍方法或一濺鍍方法在該障壁材料層995上形成由Cu或類似物製成之一電極材料層996。形成該電極材料層996以填滿形成於該第一層間絕緣層951、該第一中間層952、該第二層間絕緣層953及該第二中間層954中之開口。在形成該電極材料層996後，使用一加熱板或一燒結退火設備以在100℃至400℃下實施熱處理持續約1分鐘至60分鐘。 Next, an electrode material layer 996 made of Cu or the like is formed on the barrier material layer 995 using an electrolytic plating method or a sputtering method as shown in FIG. 41I. The electrode material layer 996 is formed to fill the openings formed in the first interlayer insulating layer 951, the first intermediate layer 952, the second interlayer insulating layer 953, and the second intermediate layer 954. After the electrode material layer 996 is formed, heat treatment is performed at 100 ° C to 400 ° C for about 1 minute to 60 minutes using a hot plate or a sintering annealing apparatus.

接著，如圖41J中所示藉由一化學機械拋光(CMP)方法移除並非佈線圖案必需之所沈積障壁材料層995及電極材料層996之部分。藉由此步驟，形成透過該第一通孔956連接至該第一配接線946之一第一連結電極941。同時，形成一障壁金屬層941A及一障壁金屬層956A。 Next, a portion of the deposited barrier material layer 995 and the electrode material layer 996 which are not necessary for the wiring pattern is removed by a chemical mechanical polishing (CMP) method as shown in FIG. 41J. By this step, one of the first connection electrodes 941 connected to the first distribution line 946 is formed through the first through hole 956. At the same time, a barrier metal layer 941A and a barrier metal layer 956A are formed.

進一步言之，由留在該第一層間絕緣層951之開口中之障壁材料層995形成一第一保護層944。 Further, a first protective layer 944 is formed by the barrier material layer 995 remaining in the opening of the first interlayer insulating layer 951.

藉由上述該等步驟形成一第一連結部分940。 A first joint portion 940 is formed by the above steps.

進一步言之，重複類似於上文參考圖41A至圖41J描述之方法之步驟以製備具有一第二連結部分960之一半導體裝置。 Further, the steps similar to those described above with reference to FIGS. 41A through 41J are repeated to prepare a semiconductor device having a second joint portion 960.

接著，對藉由上述該製程形成之兩個半導體基板之表面(即，對該第一連結部分940與該第二連結部分960之表面)實施(例如)使用甲酸之一濕式製程或使用Ar、NH3或類似物之電漿之一乾式製程。藉由該製程，移除該第一連結電極941與該第四連結電極961之表面上之氧化物膜以曝露純淨的金屬面。 Next, the surface of the two semiconductor substrates formed by the above process (ie, the surface of the first joint portion 940 and the second joint portion 960) is subjected to, for example, a wet process using formic acid or using Ar A dry process of plasma of NH 3 or the like. By the process, the oxide film on the surfaces of the first connection electrode 941 and the fourth connection electrode 961 is removed to expose a pure metal surface.

接著，如圖41K中所示，在該兩個半導體基板之表面彼此相對後其等彼此接觸以使該第一連結部分940與該第二連結部分960彼此連結。 Next, as shown in FIG. 41K, after the surfaces of the two semiconductor substrates are opposed to each other, they are in contact with each other to connect the first joint portion 940 and the second joint portion 960 to each other.

此後，在(例如)大氣壓力之N2氛圍中或真空中藉由諸如一加熱板之一退火設備或一RTA在100℃至400℃下實施加熱處理持續約5分鐘至兩個小時。 Thereafter, the heat treatment is carried out at 100 ° C to 400 ° C for about 5 minutes to 2 hours in an atmosphere of N 2 such as atmospheric pressure or in a vacuum by an annealing apparatus such as a hot plate or an RTA.

進一步言之，當連結上述該第一連結部分940與該第二連結部分960時，可使用一電漿連結方法以使該第一層間絕緣層951與該第四層間絕緣層971彼此連結。例如，氧氣電漿輻照在該第一層間絕緣層951與該第四層間絕緣層971之表面上以修改其等之表面。在該修改後，用純淨水清洗該第一層間絕緣層951與該第四層間絕緣層971之表面持續30秒以在該表面上形成矽烷醇基(Si-OH基團)。接著，上面形成矽烷醇基之諸面彼此相對且部分彼此抵靠按壓以藉由范德華力連結在一起。此後，為進一步增加連結介面處之緊密接觸力，應用(例如)400℃/60分鐘之加熱處理以使該等矽烷醇基發生一脫水凝結反應。 Further, when the first connecting portion 940 and the second connecting portion 960 are joined, a plasma bonding method may be used to connect the first interlayer insulating layer 951 and the fourth interlayer insulating layer 971 to each other. For example, oxygen plasma is irradiated on the surface of the first interlayer insulating layer 951 and the fourth interlayer insulating layer 971 to modify the surface thereof. After this modification, the surface of the first interlayer insulating layer 951 and the fourth interlayer insulating layer 971 was washed with pure water for 30 seconds to form a stanol group (Si-OH group) on the surface. Next, the faces on which the stanol groups are formed are opposed to each other and partially pressed against each other to be joined together by van der Waals force. Thereafter, in order to further increase the close contact force at the joint interface, a heat treatment of, for example, 400 ° C / 60 minutes is applied to cause a dehydration coagulation reaction of the stanol groups.

藉由上述該等步驟，可製造圖41K中所示之本實施例之一半導體裝置。 By the above steps, a semiconductor device of the present embodiment shown in Fig. 41K can be manufactured.

藉由上述該製造方法，可同時形成該障壁金屬層956A及該第一保護層944。進一步言之，用於形成該第一保護層944之第一層間絕緣層951之凹陷部分可與用於形成該第一連結電極941之凹陷部分同時形成。 With the above manufacturing method, the barrier metal layer 956A and the first protective layer 944 can be simultaneously formed. Further, the recessed portion of the first interlayer insulating layer 951 for forming the first protective layer 944 may be formed simultaneously with the recessed portion for forming the first connection electrode 941.

因此，在不增加用於形成一保護層之一步驟之情況下可 藉由用於一半導體裝置之一普遍製造方法製造本實施例之半導體裝置。 Therefore, without increasing the step of forming a protective layer, The semiconductor device of the present embodiment is fabricated by a general manufacturing method for a semiconductor device.

下文給定圖41K中所示之半導體裝置之組件之一大小之一實例。 An example of one of the sizes of the components of the semiconductor device shown in Fig. 41K is given below.

分別連接至該第一配接線946及該第四配接線966之第一通孔956及第四通孔976之開口直徑係50奈米至200奈米。該第一連結電極941及該第四連結電極961之開口直徑係200奈米至20微米。分別形成於該第一連結電極941及該第四連結電極961周圍並包圍該等連結部分之第一保護層944及第三保護層964之開口寬度係10奈米至20微米。 The first through hole 956 and the fourth through hole 976 respectively connected to the first distribution line 946 and the fourth distribution line 966 have an opening diameter of 50 nm to 200 nm. The opening diameters of the first connection electrode 941 and the fourth connection electrode 961 are 200 nm to 20 μm. The opening widths of the first protective layer 944 and the third protective layer 964 formed around the first connecting electrode 941 and the fourth connecting electrode 961 and surrounding the connecting portions are 10 nm to 20 μm.

<<4.半導體裝置之修改1>> <<4. Modification of semiconductor device 1>>

現在描述本實施例之半導體裝置之一修改1。圖42A及圖42B展示該修改1之半導體裝置之一組態。應注意，在圖42A及圖42B中所示之半導體裝置中，藉由相同的元件符號標示類似於上述實施例之半導體裝置之元件，且本文省略其等之重複詳細描述以避免冗餘。進一步言之，惟非保護層之另一部分之組態外，圖42A及圖42B中所示之修改1之半導體裝置之組態類似於上述實施例之半導體裝置。因此，本文省略除該等保護層外之組件之組態之描述以避免冗餘。 Modification 1 of one of the semiconductor devices of the present embodiment will now be described. 42A and 42B show a configuration of one of the semiconductor devices of Modification 1. It is to be noted that, in the semiconductor device shown in FIG. 42A and FIG. 42B, elements similar to those of the semiconductor device of the above-described embodiment are denoted by the same reference numerals, and repeated detailed descriptions thereof are omitted herein to avoid redundancy. Further, the configuration of the semiconductor device of Modification 1 shown in Figs. 42A and 42B is similar to the semiconductor device of the above embodiment except for the configuration of another portion other than the protective layer. Therefore, the description of the configuration of components other than the protective layers is omitted herein to avoid redundancy.

[保護層] [The protective layer]

首先參考圖42A，該第一連結部分940包含該第一連結電極941周圍之一第一保護層981。該第一連結部分940進一步包含包圍該第二連結電極942及該第三連結電極943之一 第二保護層982。 Referring first to FIG. 42A, the first joint portion 940 includes a first protective layer 981 around the first joint electrode 941. The first connecting portion 940 further includes one of the second connecting electrode 942 and the third connecting electrode 943 Second protective layer 982.

參考圖42B，該第一保護層981係由包圍該第一連結電極941之一單一連續層形成。該第二保護層982係由包圍該第二連結電極942及第三連結電極943之一單一連續層形成。 Referring to FIG. 42B, the first protective layer 981 is formed by a single continuous layer surrounding one of the first connection electrodes 941. The second protective layer 982 is formed by a single continuous layer surrounding one of the second connection electrode 942 and the third connection electrode 943.

返回參考圖42A，該第一保護層981包含覆蓋形成於該第一層間絕緣層951中之一凹陷部分之內面之一障壁金屬層981B及經形成以填滿該障壁金屬層981B之一導體層981A。 Referring back to FIG. 42A, the first protective layer 981 includes a barrier metal layer 981B covering an inner surface of a recessed portion formed in the first interlayer insulating layer 951 and formed to fill one of the barrier metal layers 981B. Conductor layer 981A.

該第一保護層981經形成具有其透過該第一層間絕緣層951自該第一連結部分940之連結面950延伸至該第一中間層952之此一深度。 The first protective layer 981 is formed to have such a depth that it extends from the bonding surface 950 of the first connecting portion 940 to the first intermediate layer 952 through the first interlayer insulating layer 951.

同時，該第二保護層982包含覆蓋形成於該第一層間絕緣層951、該第一中間層952及該第二層間絕緣層953中之一凹陷部分之內面之一障壁金屬層982B及經形成以填滿該障壁金屬層982B之一導體層982A。該第二保護層982經形成具有其透過該第一層間絕緣層951、該第一中間層952及該第二層間絕緣層953自該第一連結部分940之連結面950延伸至該第二中間層954之此一深度。 At the same time, the second protective layer 982 includes a barrier metal layer 982B covering the inner surface of one of the first interlayer insulating layer 951, the first intermediate layer 952 and the second interlayer insulating layer 953. A conductor layer 982A is formed to fill the barrier metal layer 982B. The second protective layer 982 is formed to extend through the first interlayer insulating layer 951, the first intermediate layer 952 and the second interlayer insulating layer 953 from the connecting surface 950 of the first connecting portion 940 to the second This depth of the intermediate layer 954.

進一步言之，如圖42A中所示，在該第二連結部分960上在對應於上述該第一保護層981之一位置處設置一第三保護層964。進一步言之，在該第二連結部分960上在對應於該第二保護層982之一位置處設置一第四保護層965。該第三保護層964及該第四保護層965具有類似於上文參考圖40A及圖40B描述之實施例中之組態之一組態。 Further, as shown in FIG. 42A, a third protective layer 964 is disposed on the second joint portion 960 at a position corresponding to one of the first protective layers 981 described above. Further, a fourth protective layer 965 is disposed on the second joint portion 960 at a position corresponding to the second protective layer 982. The third protective layer 964 and the fourth protective layer 965 have a configuration similar to one of the configurations in the embodiment described above with reference to FIGS. 40A and 40B.

在該連結面950上，該第一保護層981及該第三保護層964設置於其等彼此接觸之位置處。進一步言之，在該連結面950上，該第二保護層982及該第四保護層965設置於其等彼此接觸之位置處。 On the joint surface 950, the first protective layer 981 and the third protective layer 964 are disposed at positions where they are in contact with each other. Further, on the joint surface 950, the second protective layer 982 and the fourth protective layer 965 are disposed at positions where they are in contact with each other.

藉由剛剛描述之組態，在藉由該第一保護層981、該第三保護層964、該第一中間層952及該第三中間層972包圍之一區域中形成該第一連結電極941與該第四連結電極961之間之一連結部分。同時，在藉由該第二保護層982、該第四保護層965、該第二中間層954及該第三中間層972包圍之一區域中形成該第二連結電極942與該第五連結電極962之間之一連結部分及該第三連結電極943與該第六連結電極963之間之一連結部分。 The first connection electrode 941 is formed in a region surrounded by the first protective layer 981, the third protective layer 964, the first intermediate layer 952, and the third intermediate layer 972 by the configuration just described. One of the connection portions with the fourth connection electrode 961. At the same time, the second connecting electrode 942 and the fifth connecting electrode are formed in a region surrounded by the second protective layer 982, the fourth protective layer 965, the second intermediate layer 954 and the third intermediate layer 972. One of the connecting portions between 962 and one of the connecting portions between the third connecting electrode 943 and the sixth connecting electrode 963.

該第一保護層981、該第二保護層982之障壁金屬層981B及982B由類似於上述該等障壁金屬層之材料之一材料(諸如Ta、Ti、Ru、TaN或TiN)形成。進一步言之，該第一保護層981、該第二保護層982之導體層981A及982A由類似於上述該等連結電極之材料之一材料(舉例而言諸如Cu)形成。 The first protective layer 981 and the barrier metal layers 981B and 982B of the second protective layer 982 are formed of a material similar to the material of the barrier metal layer described above, such as Ta, Ti, Ru, TaN or TiN. Further, the first protective layer 981 and the conductor layers 981A and 982A of the second protective layer 982 are formed of a material similar to the material of the connecting electrodes described above, such as, for example, Cu.

[保護層：效果] [Protection layer: effect]

運用圖42A中所示之修改1之半導體裝置之組態，將該第一保護層981與該第二保護層982之間之連結面之寬度設定為大於該第三保護層964及該第四保護層965之寬度以保證克服位置移位之連接可靠性。 The width of the joint surface between the first protective layer 981 and the second protective layer 982 is set larger than the third protective layer 964 and the fourth by using the configuration of the semiconductor device of the modification 1 shown in FIG. 42A. The width of the protective layer 965 is to ensure connection reliability against positional displacement.

該第一保護層981及該第二保護層982之組態係適合的， 其中使彼此連結之保護層之一者之寬度大於另一保護層之寬度以保證該等保護層之連接可靠性。例如，在其中該第一保護層981之開口直徑或寬度係約30奈米至20微米之情況中，僅藉由用該等障壁金屬層981B及982B填充難以填滿形成於該等絕緣層中之開口。因此，在用該等障壁金屬層981B及982B覆蓋該開口之內面後藉由用該等導體層981A及982A填滿該等障壁金屬層981B及982B，可組態其等之間具有該連結面之一大寬度之第一保護層981及第二保護層982。 The configuration of the first protective layer 981 and the second protective layer 982 is suitable, The width of one of the protective layers connected to each other is greater than the width of the other protective layer to ensure the connection reliability of the protective layers. For example, in the case where the opening diameter or width of the first protective layer 981 is about 30 nm to 20 μm, it is difficult to fill the insulating layer only by filling with the barrier metal layers 981B and 982B. The opening. Therefore, after the inner surfaces of the openings are covered by the barrier metal layers 981B and 982B, the barrier metal layers 981B and 982B are filled with the conductor layers 981A and 982A, and the connection can be configured. The first protective layer 981 and the second protective layer 982 having a large width.

<<5.用於半導體裝置之修改1之製造方法>> <<5. Manufacturing Method for Modification 1 of Semiconductor Device>>

現在描述上述用於該修改1之半導體裝置之一製造方法。在該製造方法之下列描述中，僅描述關於上文參考圖42A及圖42B描述之第一連結電極941與第四連結電極961之間之連結部分之半導體裝置之一製造方法，同時省略半導體裝置之另一部分之組態之一製造方法。 A method of manufacturing one of the above-described semiconductor devices for the modification 1 will now be described. In the following description of the manufacturing method, only one manufacturing method of the semiconductor device regarding the connection portion between the first connection electrode 941 and the fourth connection electrode 961 described above with reference to FIGS. 42A and 42B is described, while omitting the semiconductor device One of the other configurations of the manufacturing method.

首先，實施類似於上文參考圖41A至圖41D描述之步驟之步驟以在上面形成一第一配接線946之一第三層間絕緣層955上形成一第二中間層954、一第二層間絕緣層953、一第一中間層952、一第一層間絕緣層951、一有機材料層992及氧化物層993。該第二層間絕緣層953、該第一中間層952及該第一層間絕緣層951具有用於在其中形成一第一通孔956之一開口。 First, a step similar to the steps described above with reference to FIGS. 41A to 41D is performed to form a second intermediate layer 954 and a second interlayer insulating layer on a third interlayer insulating layer 955 on which a first wiring 946 is formed. A layer 953, a first intermediate layer 952, a first interlayer insulating layer 951, an organic material layer 992, and an oxide layer 993. The second interlayer insulating layer 953, the first intermediate layer 952, and the first interlayer insulating layer 951 have openings for forming a first through hole 956 therein.

接著，如圖43A中所示在該氧化物層993上形成一光阻層997。該光阻層997形成於一圖案中，該光阻層997在形成 一連結部分之一第一連結電極941及一第一保護層981之位置處開口。 Next, a photoresist layer 997 is formed on the oxide layer 993 as shown in FIG. 43A. The photoresist layer 997 is formed in a pattern, and the photoresist layer 997 is formed. One of the connecting portions is open at a position of the first connecting electrode 941 and a first protective layer 981.

接著，如圖43B中所示藉由其中使用磁控管類型之一普遍蝕刻設備之一乾式蝕刻方法自該光阻層997上方蝕刻該氧化物層993。接著，使用所蝕刻氧化物層993作為一遮罩以藉由其中使用磁控管類型之一普遍蝕刻設備之一乾式蝕刻方法蝕刻該有機材料層992及該第一層間絕緣層951。 Next, the oxide layer 993 is etched from the photoresist layer 997 by a dry etching method in which one of the magnetron types is used as shown in FIG. 43B. Next, the etched oxide layer 993 is used as a mask to etch the organic material layer 992 and the first interlayer insulating layer 951 by one of dry etching methods in which one of the magnetron types are commonly used.

此後，實施(例如)基於氧氣(O2)電漿之一灰化製程及藉由有機胺基藥物之溶液之一製程以完全移除該氧化物層993、有機材料層992及該蝕刻製程中產生之殘留沈積物。進一步言之，藉由此製程，同時蝕刻該第一配接線946上之第二中間層954以曝露該第一配接線946以藉此獲得如圖43C中所示之此一形狀。 Thereafter, the oxide layer 993, the organic material layer 992, and the etching process are performed, for example, based on one of an oxygen (O 2 ) plasma ashing process and a solution of an organic amine-based drug solution. Residual deposits produced. Further, by the process, the second intermediate layer 954 on the first wiring 946 is simultaneously etched to expose the first wiring 946 to thereby obtain the shape as shown in FIG. 43C.

接著，如圖43D中所示形成用於形成該障壁金屬層956A及該第一保護層981之障壁金屬層981B。在Ar/N2氛圍中藉由一RF濺鍍製程由Ti、Ta、Ru或其等之氮化物之任一者形成一厚度為5奈米至50奈米之障壁材料層998。 Next, a barrier metal layer 981B for forming the barrier metal layer 956A and the first protective layer 981 is formed as shown in FIG. 43D. A barrier material layer 998 having a thickness of 5 nm to 50 nm is formed by any one of Ti, Ta, Ru or a nitride thereof in an Ar/N 2 atmosphere by an RF sputtering process.

接著，如圖43E中所示使用一電解電鍍方法或一濺鍍方法在該障壁材料層998上形成由Cu或類似物製成之一電極材料層999。藉由填滿其中待形成該第一連結電極941之一開口及其中待形成該第一保護層981之一開口形成該電極材料層999。在形成該電極材料層999後，使用一加熱板或一燒結退火設備以在100℃至400℃下實施熱處理持續約1分鐘至60分鐘。 Next, an electrode material layer 999 made of Cu or the like is formed on the barrier material layer 998 using an electrolytic plating method or a sputtering method as shown in Fig. 43E. The electrode material layer 999 is formed by filling an opening in which the first connection electrode 941 is to be formed and an opening in which the first protective layer 981 is to be formed. After the electrode material layer 999 is formed, heat treatment is performed at 100 ° C to 400 ° C for about 1 minute to 60 minutes using a hot plate or a sintering annealing apparatus.

接著，如圖43F中所示藉由一化學機械拋光(CMP)方法移除並非配接線圖案必需之障壁材料層998及電極材料層999之部分。藉由此步驟，形成透過該第一通孔956連接至該第一配接線946之一第一連結電極941。同時，形成一障壁金屬層941A及一障壁金屬層956A。 Next, a portion of the barrier material layer 998 and the electrode material layer 999 which are not necessary for the wiring pattern are removed by a chemical mechanical polishing (CMP) method as shown in FIG. 43F. By this step, one of the first connection electrodes 941 connected to the first distribution line 946 is formed through the first through hole 956. At the same time, a barrier metal layer 941A and a barrier metal layer 956A are formed.

進一步言之，由留在該第一層間絕緣層951之開口中之障壁材料層998及電極材料層999形成一第一保護層981。 Further, a first protective layer 981 is formed by the barrier material layer 998 and the electrode material layer 999 remaining in the opening of the first interlayer insulating layer 951.

藉由上述該等步驟形成一第一連結部分940。 A first joint portion 940 is formed by the above steps.

重複類似於上文參考圖41A至圖41J描述之方法之步驟以製備具有一第二連結部分960之一半導體裝置。 The steps of the method similar to that described above with reference to FIGS. 41A through 41J are repeated to prepare a semiconductor device having a second joint portion 960.

接著，對藉由上述製程形成之兩個半導體部件之表面(即，對該第一連結部分940與該第二連結部分960之表面)實施(例如)使用甲酸之一濕式製程或使用Ar、NH3或類似物之電漿之一乾式製程。藉由該製程，移除該第一連結電極941與該第四連結電極961之表面上之氧化物膜以曝露純淨的金屬面。 Next, the surface of the two semiconductor components formed by the above process (ie, the surface of the first joint portion 940 and the second joint portion 960) is subjected to, for example, a wet process using formic acid or using Ar, One of the plasma processes of NH 3 or the like is a dry process. By the process, the oxide film on the surfaces of the first connection electrode 941 and the fourth connection electrode 961 is removed to expose a pure metal surface.

接著，如圖43G中所示，在該兩個半導體部件之表面彼此相對後其等彼此接觸以使該第一連結部分940與該第二連結部分960彼此連結。 Next, as shown in FIG. 43G, after the surfaces of the two semiconductor members are opposed to each other, they are in contact with each other to connect the first joint portion 940 and the second joint portion 960 to each other.

此後，在(例如)大氣壓力之N2氛圍中或真空中藉由諸如一加熱板之一退火設備或一RTA在100℃至400℃下實施加熱處理持續約5分鐘至兩個小時。 Thereafter, the heat treatment is carried out at 100 ° C to 400 ° C for about 5 minutes to 2 hours in an atmosphere of N 2 such as atmospheric pressure or in a vacuum by an annealing apparatus such as a hot plate or an RTA.

藉由上述該等步驟，可製造圖43G中所示之本修改之一半導體裝置。 By the above steps, a semiconductor device of the present modification shown in Fig. 43G can be manufactured.

<<6.半導體裝置之修改2>> <<6. Modification of semiconductor device 2>>

現在描述本實施例之半導體裝置之一修改2。圖44展示該修改2之半導體裝置之一組態。應注意，在圖44中所示之半導體裝置中，藉由相同的元件符號標示類似於上述實施例之半導體裝置之元件，且本文省略其等之重複詳細描述以避免冗餘。進一步言之，惟非層間絕緣層之另一部分之組態外，圖44中所示之修改2之半導體裝置之組態類似於上述實施例之半導體裝置。因此，本文省略除該等層間絕緣層外之組件之組態之描述以避免冗餘。 Modification 2 of one of the semiconductor devices of the present embodiment will now be described. Figure 44 shows a configuration of one of the semiconductor devices of Modification 2. It is to be noted that, in the semiconductor device shown in FIG. 44, elements similar to those of the above-described embodiment are denoted by the same reference numerals, and repeated detailed descriptions thereof are omitted herein to avoid redundancy. Further, the configuration of the semiconductor device of Modification 2 shown in Fig. 44 is similar to that of the above-described embodiment except that the other portion of the interlayer insulating layer is not configured. Therefore, the description of the configuration of components other than the interlayer insulating layers is omitted herein to avoid redundancy.

[絕緣層] [Insulation]

藉由層壓複數個配接線層及絕緣層形成該第一連結部分940及該第二連結部分960。 The first connecting portion 940 and the second connecting portion 960 are formed by laminating a plurality of wiring layers and insulating layers.

該第一連結部分940之絕緣層自該連結面950側按順序包含一第一層間絕緣層983及一第二層間絕緣層984。同時，該第二連結部分960之絕緣層自該連結面950按順序包含一第三層間絕緣層985及一第四層間絕緣層986。 The insulating layer of the first connecting portion 940 includes a first interlayer insulating layer 983 and a second interlayer insulating layer 984 in this order from the side of the connecting surface 950. At the same time, the insulating layer of the second connecting portion 960 includes a third interlayer insulating layer 985 and a fourth interlayer insulating layer 986 in this order from the connecting surface 950.

在該第一連結部分940中，在該第二層間絕緣層984中形成一第一配接線946、一第二配接線947及一第三配接線948。在該第一層間絕緣層983中，形成該第一連結部分940之一第一連結電極941、一第二連結電極942及一第三連結電極943。該第一連結電極941、該第二連結電極942及該第三連結電極943之表面曝露於該連結面950且鋪設為與該第一層間絕緣層983齊平。 In the first connecting portion 940, a first wiring 946, a second wiring 947 and a third wiring 948 are formed in the second interlayer insulating layer 984. In the first interlayer insulating layer 983, one of the first connection portions 940, a first connection electrode 941, a second connection electrode 942, and a third connection electrode 943 are formed. The surfaces of the first connection electrode 941, the second connection electrode 942, and the third connection electrode 943 are exposed on the connection surface 950 and are laid flush with the first interlayer insulating layer 983.

進一步言之，在該第一層間絕緣層983中形成一第一通 孔956、一第二通孔957及一第三通孔958。 Further, a first pass is formed in the first interlayer insulating layer 983. A hole 956, a second through hole 957 and a third through hole 958.

而且，在該第一層間絕緣層983中設置包圍該第一連結電極941之一第一保護層944及包圍該第二連結電極942及該第三連結電極943之一第二保護層945。 Further, a first protective layer 944 surrounding the first connection electrode 941 and a second protective layer 945 surrounding the second connection electrode 942 and the third connection electrode 943 are provided in the first interlayer insulating layer 983.

在該第二連結部分960中，在該第四層間絕緣層986中形成一第四配接線966、一第五配接線967及一第六配接線968。在該第三層間絕緣層985中，形成一第四連結電極961、一第五連結電極962及一第六連結電極963。該第四連結電極961、該第五連結電極962及該第六連結電極963之表面曝露於該連結面950且鋪設為與該第三層間絕緣層985齊平。 In the second connecting portion 960, a fourth wiring 966, a fifth wiring 967 and a sixth wiring 968 are formed in the fourth interlayer insulating layer 986. In the third interlayer insulating layer 985, a fourth connection electrode 961, a fifth connection electrode 962, and a sixth connection electrode 963 are formed. The surfaces of the fourth connection electrode 961, the fifth connection electrode 962, and the sixth connection electrode 963 are exposed on the connection surface 950 and are laid flush with the third interlayer insulation layer 985.

進一步言之，在該第三層間絕緣層985中形成一第四通孔976、一第五通孔977及一第六通孔978。 Further, a fourth through hole 976, a fifth through hole 977 and a sixth through hole 978 are formed in the third interlayer insulating layer 985.

而且，在該第三層間絕緣層985中設置包圍該第四連結電極961之一第三保護層964及包圍該第五連結電極962及該第六連結電極963之一第四保護層965。 Further, a third protective layer 964 surrounding the fourth connection electrode 961 and a fourth protective layer 965 surrounding the fifth connection electrode 962 and the sixth connection electrode 963 are provided in the third interlayer insulating layer 985.

該第一層間絕緣層983及該第三層間絕緣層985由與上述實施例之半導體裝置之中間層之材料相同之一材料組態。例如，該第一層間絕緣層983及該第三層間絕緣層985係由用於普遍組態一半導體裝置中之配接線等等之一金屬材料之一擴散防止層之一材料組態。進一步言之，該第一層間絕緣層983及該第三層間絕緣層985係不太可能容許包含於該等層間絕緣層中之水970滲透之高密度絕緣層。進一步言之，用作剛剛描述之擴散防止層之此等高密度絕緣層係 由藉由(例如)一旋塗方法或一CVD方法形成之一相對介電常數4至7之P-SiN組態或由一相對介電常數小於4之SiCN或類似物(含有C)組態。 The first interlayer insulating layer 983 and the third interlayer insulating layer 985 are configured by one material identical to the material of the intermediate layer of the semiconductor device of the above embodiment. For example, the first interlayer insulating layer 983 and the third interlayer insulating layer 985 are configured by one of diffusion preventing layers of one of metal materials for universally configuring a wiring line or the like in a semiconductor device. Further, the first interlayer insulating layer 983 and the third interlayer insulating layer 985 are less likely to allow the high-density insulating layer in which the water 970 included in the interlayer insulating layers penetrates. Further, these high-density insulating layers are used as the diffusion preventing layer just described. Forming a P-SiN configuration with a relative dielectric constant of 4 to 7 by, for example, a spin coating method or a CVD method or configuring a SiCN or the like (containing C) having a relative dielectric constant of less than 4 .

進一步言之，該第二層間絕緣層984及該第四層間絕緣層986係由與上述實施例之半導體裝置之層間絕緣層之材料相同之一材料組態。例如，該第二層間絕緣層984及該第四層間絕緣層986係由(例如)SiO2、由含氟氧化矽(FSG)或聚芳醚(PAE)表示之有機矽基聚合物、由氫化矽倍半氧烷(HSQ)或甲基矽倍半氧烷(MSQ)表示之一無機材料組態，且特別係由具有約2.7或更小之一相對介電常數之一低介電常數(低k)材料組態。 Further, the second interlayer insulating layer 984 and the fourth interlayer insulating layer 986 are configured in the same material as the material of the interlayer insulating layer of the semiconductor device of the above embodiment. For example, the second interlayer insulating layer 984 and the fourth interlayer insulating layer 986 are made of, for example, SiO 2 , an organic fluorenyl polymer represented by fluorine-containing cerium oxide (FSG) or polyarylene ether (PAE), and hydrogenated. Hexetane (HSQ) or methyl sesquioxanes (MSQ) represent one of the inorganic material configurations, and in particular by a low dielectric constant having one of the relative dielectric constants of about 2.7 or less ( Low k) material configuration.

在上述修改2之半導體裝置之組態中，形成該連結面950之第一層間絕緣層983及第三層間絕緣層985不太可能容許水滲透。因此，在該第一連結電極941與該第四連結電極961之間之連結部分處，可抑制水970接觸該第四連結電極961與該第一層間絕緣層983之間之接觸部分969。類似地，在該第二連結電極942與該第五連結電極962之間之連結部分處，可抑制水970接觸該第二連結電極942與該第三層間絕緣層985之間之接觸部分949。 In the configuration of the semiconductor device of the above modification 2, the first interlayer insulating layer 983 and the third interlayer insulating layer 985 which form the joint surface 950 are less likely to allow water permeation. Therefore, at the joint portion between the first connection electrode 941 and the fourth connection electrode 961, the water 970 can be prevented from contacting the contact portion 969 between the fourth connection electrode 961 and the first interlayer insulating layer 983. Similarly, at the joint portion between the second joint electrode 942 and the fifth joint electrode 962, the water 970 can be prevented from contacting the contact portion 949 between the second joint electrode 942 and the third interlayer insulating layer 985.

進一步言之，因為設置該第一保護層944、該第二保護層945、該第三保護層964及該第四保護層965，所以可抑制在進行電漿連結時出現在該連結面上之水或包含於該等層間絕緣層中之水遷移至該等電極連結部分。因此，可抑制該連結電極之腐蝕，且可給該半導體裝置提供一良好的 電特性及可靠性。 Further, since the first protective layer 944, the second protective layer 945, the third protective layer 964, and the fourth protective layer 965 are disposed, it can be suppressed from occurring on the joint surface when plasma bonding is performed. Water or water contained in the interlayer insulating layers migrates to the electrode connecting portions. Therefore, corrosion of the connection electrode can be suppressed, and the semiconductor device can be provided with a good Electrical characteristics and reliability.

[製造方法] [Production method]

可藉由在上述實施例之半導體裝置之製造方法中改變待層壓之層間絕緣層之材料及該等層間絕緣層之蝕刻條件製造上文參考圖44描述之修改2之半導體裝置。例如，在形成圖41A及圖41B中所示之一層間絕緣層及一中間層之步驟處形成呈一單層之形式之一層間絕緣層。接著，在該蝕刻步驟處，控制蝕刻時間以形成一凹陷部分至該層間絕緣層之一所要深度。藉由依此方式改變製造製程，可藉由類似於用於上述實施例之半導體裝置之方法之一方法製造該修改2之半導體裝置。 The semiconductor device of the modification 2 described above with reference to FIG. 44 can be manufactured by changing the material of the interlayer insulating layer to be laminated and the etching conditions of the interlayer insulating layers in the manufacturing method of the semiconductor device of the above embodiment. For example, an interlayer insulating layer in the form of a single layer is formed at the step of forming an interlayer insulating layer and an intermediate layer shown in FIGS. 41A and 41B. Next, at the etching step, the etching time is controlled to form a recessed portion to a desired depth of one of the interlayer insulating layers. By changing the manufacturing process in this manner, the semiconductor device of the modification 2 can be manufactured by a method similar to the method for the semiconductor device of the above embodiment.

<<7.電子設備之實施例>> <<7. Examples of electronic devices>>

上述實施例之半導體裝置可應用於其中兩個半導體部件彼此接合以實施配接線連結之一任意電子設備，舉例而言諸如一固態影像擷取裝置、一半導體記憶體或諸如一積體電路(IC)之一半導體邏輯裝置。 The semiconductor device of the above embodiment can be applied to any electronic device in which two semiconductor components are bonded to each other to implement a wiring connection, such as, for example, a solid-state image capturing device, a semiconductor memory, or such as an integrated circuit (IC). One of the semiconductor logic devices.

第五實施例 Fifth embodiment

<<使用該等實施例之半導體裝置之任一者之一電子設備之實例>> <<Example of an electronic device using any one of the semiconductor devices of the embodiments>>

根據上文結合該等實施例描述之本技術之半導體裝置之任一者(諸如一固態影像擷取裝置)可應用於各種電子設備，舉例而言諸如一相機系統(諸如一數位相機或一視訊攝影機)、具有一影像擷取功能之一可攜式電話機或具有一影像擷取功能之任何其他設備。 Any of the semiconductor devices of the present technology described above in connection with the embodiments, such as a solid-state image capture device, can be applied to various electronic devices, such as, for example, a camera system (such as a digital camera or a video camera). Camera), a portable telephone with an image capture function or any other device with an image capture function.

圖45展示其中使用一固態影像擷取裝置作為根據本技術之電子設備之一實例之一相機之一組態。根據本實施例之相機被應用為可擷取一靜態影像或一動態影像之一視訊攝影機。參考圖45，該相機90包含一固態影像擷取裝置91、用於將至其之入射光引入至該固態影像擷取裝置91之一接收光感測器之一光學系統93、一快門設備94、用於驅動該固態影像擷取裝置91之一驅動電路95及用於處理該固態影像擷取裝置91之一輸出信號之一信號處理電路96。 Figure 45 shows a configuration in which one of the cameras using one of the solid state image capture devices as one example of an electronic device in accordance with the present technology is configured. The camera according to the embodiment is applied as a video camera that can capture a still image or a moving image. Referring to FIG. 45, the camera 90 includes a solid-state image capturing device 91 for introducing incident light thereto to one of the solid-state image capturing devices 91, an optical system 93 for receiving a light sensor, and a shutter device 94. A driving circuit 95 for driving the solid-state image capturing device 91 and a signal processing circuit 96 for processing one of the output signals of the solid-state image capturing device 91.

藉由應用上文結合本技術之實施例及修改之半導體裝置之任一者組態該固態影像擷取裝置91。包含一光學透鏡之光學系統93自一影像擷取物體引入影像光(即，入射光)以在該固態影像擷取裝置91之一影像擷取平面上形成一影像。因此，在一固定時間段累積信號電荷至該固態影像擷取裝置91中。如上所述之此一光學系統93可為由複數個光學透鏡組態之一光學透鏡系統。該快門設備94對該固態影像擷取裝置91控制光輻照時間週期及光攔截時間週期。該驅動電路95供應一驅動信號給該固態影像擷取裝置91及該快門設備94，使得根據所供應驅動信號或時序信號實施對該固態影像擷取裝置91至該信號處理電路96之一信號輸出操作及該快門設備94之一快門操作之控制。特定言之，該驅動電路95供應一驅動信號或時序信號以實施自該固態影像擷取裝置91至該信號處理電路96之一信號轉移操作。該信號處理電路96對自該固態影像擷取裝置91供應至該信號處理電路96之信號實施各種信號處理。藉由該等信號處理 之一視訊信號儲存於諸如一記憶體之一儲存媒體中或輸出至一監視器。 The solid-state image capturing device 91 is configured by applying any of the above-described embodiments of the present technology and modified semiconductor devices. An optical system 93 including an optical lens introduces image light (i.e., incident light) from an image capturing object to form an image on an image capturing plane of the solid-state image capturing device 91. Therefore, signal charges are accumulated in the solid-state image capturing device 91 for a fixed period of time. Such an optical system 93 as described above may be one optical lens system configured by a plurality of optical lenses. The shutter device 94 controls the solid-state image capturing device 91 to control the light irradiation time period and the light interception time period. The driving circuit 95 supplies a driving signal to the solid-state image capturing device 91 and the shutter device 94, so that the signal output from the solid-state image capturing device 91 to the signal processing circuit 96 is implemented according to the supplied driving signal or timing signal. Operation and control of shutter operation of one of the shutter devices 94. In particular, the drive circuit 95 supplies a drive signal or timing signal to perform a signal transfer operation from the solid state image capture device 91 to the signal processing circuit 96. The signal processing circuit 96 performs various signal processing on signals supplied from the solid-state image capturing device 91 to the signal processing circuit 96. Processing by these signals One of the video signals is stored in a storage medium such as a memory or output to a monitor.

本申請案含有關於分別在2011年7月5日、2011年8月1日、2011年8月4日、2011年9月27日及2012年1月16日向日本專利局申請之日本優先權專利申請案JP 2011-148883、JP 2011-168021、JP 2011-170666、JP 2011-210142及P 2012-006356中揭示之標的之標的，該等案之全部內容以引用方式併入本文。 This application contains Japanese priority patents filed with the Japanese Patent Office on July 5, 2011, August 1, 2011, August 4, 2011, September 27, 2011 and January 16, 2012, respectively. The subject matter disclosed in the application JP 2011-148883, JP 2011-168021, JP 2011-170666, JP 2011-210142, and P 2012-006356, the entire contents of each of which is incorporated herein by reference.

熟習此項技術者應瞭解可取決於設計需求及其他因數想出各種修改、組合、子組合及變更，只要該等修改、組合、子組合及變更屬於隨附申請專利範圍或其等之等效物之範疇內。 Those skilled in the art should understand that various modifications, combinations, sub-combinations and changes can be made depending on the design requirements and other factors as long as the modifications, combinations, sub-combinations and changes are within the scope of the accompanying claims or equivalent Within the scope of things.

1‧‧‧半導體裝置 1‧‧‧Semiconductor device

1'‧‧‧半導體裝置 1'‧‧‧Semiconductor device

2‧‧‧感測器基板 2‧‧‧Sensor substrate

2a‧‧‧半導體層 2a‧‧‧Semiconductor layer

2b‧‧‧配接線層 2b‧‧‧With wiring layer

2c‧‧‧電極層 2c‧‧‧electrode layer

3‧‧‧像素 3‧‧ ‧ pixels

4‧‧‧像素區域 4‧‧‧Pixel area

5‧‧‧像素驅動線 5‧‧‧Pixel drive line

6‧‧‧垂直信號線 6‧‧‧Vertical signal line

7‧‧‧電路基板 7‧‧‧ circuit board

7a‧‧‧半導體層 7a‧‧‧Semiconductor layer

7b‧‧‧第一配接線層 7b‧‧‧First wiring layer

7c‧‧‧第二配接線層 7c‧‧‧Second wiring layer

7d‧‧‧電極層 7d‧‧‧electrode layer

8‧‧‧垂直驅動電路 8‧‧‧Vertical drive circuit

9‧‧‧行信號處理電路 9‧‧‧ line signal processing circuit

10‧‧‧水平驅動電路 10‧‧‧ horizontal drive circuit

11‧‧‧系統控制電路 11‧‧‧System Control Circuit

15‧‧‧保護膜 15‧‧‧Protective film

17‧‧‧彩色濾光片層 17‧‧‧Color filter layer

19‧‧‧晶片上透鏡 19‧‧‧ wafer on lens

20‧‧‧半導體基板 20‧‧‧Semiconductor substrate

21‧‧‧光電轉換部分 21‧‧‧Photoelectric conversion section

23‧‧‧源極/汲極 23‧‧‧Source/Bungee

25‧‧‧閘極絕緣膜 25‧‧‧gate insulating film

27‧‧‧閘極電極 27‧‧‧ gate electrode

29‧‧‧層間絕緣膜 29‧‧‧Interlayer insulating film

29a‧‧‧溝槽圖案 29a‧‧‧Slot pattern

31‧‧‧嵌入式配接線 31‧‧‧Embedded wiring

31a‧‧‧障壁金屬層 31a‧‧‧ barrier metal layer

31b‧‧‧配接線層 31b‧‧‧With wiring layer

33‧‧‧第一電極 33‧‧‧First electrode

33a‧‧‧第一電極膜 33a‧‧‧First electrode film

35‧‧‧第一絕緣膜 35‧‧‧First insulating film

35a‧‧‧溝槽圖案 35a‧‧‧ Groove pattern

35'‧‧‧第一絕緣膜 35'‧‧‧First insulating film

35-1‧‧‧層間絕緣膜 35-1‧‧‧Interlayer insulating film

35-2‧‧‧擴散防止絕緣膜 35-2‧‧‧Diffusion prevention insulation film

41‧‧‧接合面/連結面 41‧‧‧ joint surface/joining surface

50‧‧‧半導體基板 50‧‧‧Semiconductor substrate

51‧‧‧源極/汲極 51‧‧‧Source/Bungee

53‧‧‧閘極絕緣膜 53‧‧‧gate insulating film

55‧‧‧閘極電極 55‧‧‧gate electrode

57‧‧‧層間絕緣膜 57‧‧‧Interlayer insulating film

57a‧‧‧溝槽圖案 57a‧‧‧ Groove pattern

59‧‧‧嵌入式配接線 59‧‧‧Embedded wiring

59a‧‧‧障壁金屬層 59a‧‧‧Baffle metal layer

59b‧‧‧配接線層 59b‧‧‧Wiring layer

61‧‧‧擴散防止絕緣層 61‧‧‧Diffusion prevention insulation

63‧‧‧層間絕緣膜 63‧‧‧Interlayer insulating film

63a‧‧‧溝槽圖案 63a‧‧‧ Groove pattern

65‧‧‧嵌入式配接線 65‧‧‧Embedded wiring

65a‧‧‧障壁金屬層 65a‧‧‧ barrier metal layer

65b‧‧‧配接線層 65b‧‧‧Wiring layer

67‧‧‧第二電極 67‧‧‧second electrode

67a‧‧‧第二電極膜 67a‧‧‧Second electrode film

69‧‧‧第二絕緣膜 69‧‧‧Second insulation film

69a‧‧‧溝槽圖案 69a‧‧‧ Groove pattern

69'‧‧‧第二絕緣膜 69'‧‧‧Second insulation film

69-1‧‧‧層間絕緣膜 69-1‧‧‧Interlayer insulating film

69-2‧‧‧擴散防止絕緣膜 69-2‧‧‧Diffusion prevention insulation film

71‧‧‧接合面/連結面 71‧‧‧ joint surface/joining surface

90‧‧‧相機 90‧‧‧ camera

91‧‧‧固態影像擷取裝置 91‧‧‧ Solid-state image capture device

93‧‧‧光學系統 93‧‧‧Optical system

94‧‧‧快門設備 94‧‧‧Shutter equipment

95‧‧‧驅動電路 95‧‧‧ drive circuit

96‧‧‧信號處理電路 96‧‧‧Signal Processing Circuit

101‧‧‧第一絕緣膜 101‧‧‧First insulating film

101a‧‧‧溝槽圖案 101a‧‧‧ Groove pattern

102‧‧‧障壁金屬層 102‧‧‧Baffle metal layer

103‧‧‧第一電極 103‧‧‧First electrode

103a‧‧‧第一電極膜 103a‧‧‧First electrode film

201‧‧‧第二絕緣膜 201‧‧‧Second insulation film

201a‧‧‧溝槽圖案 201a‧‧‧ trench pattern

202‧‧‧障壁金屬層 202‧‧‧Baffle metal layer

203‧‧‧第二電極 203‧‧‧second electrode

203a‧‧‧第二電極膜 203a‧‧‧Second electrode film

301‧‧‧半導體裝置 301‧‧‧Semiconductor device

302‧‧‧第一基板 302‧‧‧First substrate

302a‧‧‧半導體層 302a‧‧‧Semiconductor layer

302b‧‧‧配接線層 302b‧‧‧Wiring layer

302c‧‧‧電極層 302c‧‧‧electrode layer

307‧‧‧第二基板 307‧‧‧second substrate

307a‧‧‧半導體層 307a‧‧‧Semiconductor layer

307b‧‧‧配接線層 307b‧‧‧with wiring layer

307c‧‧‧電極層 307c‧‧‧electrode layer

312‧‧‧絕緣薄膜 312‧‧‧Insulation film

312a‧‧‧絕緣薄膜 312a‧‧‧Insulation film

312b‧‧‧絕緣薄膜 312b‧‧‧Insulation film

315‧‧‧保護膜 315‧‧‧Protective film

317‧‧‧彩色濾光片層 317‧‧‧Color filter layer

319‧‧‧晶片上透鏡 319‧‧‧ wafer on lens

320‧‧‧半導體基板 320‧‧‧Semiconductor substrate

321‧‧‧光電轉換部分 321‧‧‧ photoelectric conversion part

323‧‧‧源極/汲極區域 323‧‧‧Source/bungee area

325‧‧‧閘極絕緣膜 325‧‧‧gate insulating film

327‧‧‧閘極電極 327‧‧‧gate electrode

329‧‧‧層間絕緣膜 329‧‧‧Interlayer insulating film

331‧‧‧嵌入式配接線 331‧‧‧Embedded wiring

331a‧‧‧障壁金屬層 331a‧‧‧ barrier metal layer

331b‧‧‧配接線層 331b‧‧‧With wiring layer

332‧‧‧擴散防止絕緣膜 332‧‧‧Diffusion prevention insulation film

333‧‧‧第一電極 333‧‧‧first electrode

333a‧‧‧障壁金屬層 333a‧‧‧ barrier metal layer

333b‧‧‧第一電極膜 333b‧‧‧First electrode film

335‧‧‧第一絕緣膜 335‧‧‧first insulating film

335a‧‧‧溝槽圖案 335a‧‧‧ Groove pattern

341‧‧‧接合面 341‧‧‧ joint surface

350‧‧‧半導體基板 350‧‧‧Semiconductor substrate

351‧‧‧源極/汲極 351‧‧‧Source/Bungee

353‧‧‧閘極絕緣膜 353‧‧‧gate insulating film

355‧‧‧閘極電極 355‧‧‧gate electrode

357‧‧‧層間絕緣膜 357‧‧‧Interlayer insulating film

359‧‧‧嵌入式配接線 359‧‧‧Embedded wiring

359a‧‧‧障壁金屬層 359a‧‧‧Baffle metal layer

359b‧‧‧配接線層 359b‧‧‧Wiring layer

361‧‧‧擴散防止絕緣膜 361‧‧‧Diffusion prevention insulation film

367‧‧‧第二電極 367‧‧‧second electrode

367a‧‧‧障壁金屬層 367a‧‧‧ barrier metal layer

367b‧‧‧第二電極膜 367b‧‧‧Second electrode film

369‧‧‧第二絕緣膜 369‧‧‧Second insulation film

371‧‧‧接合面 371‧‧‧ joint surface

401‧‧‧半導體裝置 401‧‧‧Semiconductor device

402‧‧‧半導體裝置 402‧‧‧Semiconductor device

403‧‧‧半導體裝置 403‧‧‧Semiconductor device

404‧‧‧半導體裝置 404‧‧‧Semiconductor device

405‧‧‧半導體裝置 405‧‧‧Semiconductor device

406‧‧‧半導體裝置 406‧‧‧Semiconductor device

410‧‧‧第一半導體部件 410‧‧‧First semiconductor component

411‧‧‧第一氧化矽(SiO2)層 411‧‧‧First yttrium oxide (SiO 2 ) layer

412‧‧‧第一銅(Cu)配接線部分 412‧‧‧First copper (Cu) wiring part

413‧‧‧第一銅(Cu)障壁膜 413‧‧‧First copper (Cu) barrier film

414‧‧‧第一銅(Cu)擴散防止膜 414‧‧‧First copper (Cu) diffusion preventing film

415‧‧‧第一層間絕緣膜 415‧‧‧First interlayer insulating film

415a‧‧‧第一層間絕緣膜之開口 415a‧‧‧ opening of the first interlayer insulating film

416‧‧‧第一銅(Cu)連結部分 416‧‧‧First copper (Cu) joint

417‧‧‧第一銅(Cu)障壁層 417‧‧‧First copper (Cu) barrier layer

420‧‧‧第二半導體部件 420‧‧‧Second semiconductor components

421‧‧‧第二氧化矽(SiO2)層 421‧‧‧Second yttrium oxide (SiO 2 ) layer

422‧‧‧第二銅(Cu)配接線部分 422‧‧‧Second copper (Cu) wiring part

423‧‧‧第二銅(Cu)障壁膜 423‧‧‧Second copper (Cu) barrier film

424‧‧‧第二銅(Cu)擴散防止膜 424‧‧‧Second copper (Cu) diffusion preventing film

425‧‧‧第二層間絕緣膜 425‧‧‧Second interlayer insulating film

425a‧‧‧第二層間絕緣膜之開口 425a‧‧‧ opening of the second interlayer insulating film

425b‧‧‧凹陷部分 425b‧‧‧ recessed part

426‧‧‧第二銅(Cu)連結部分 426‧‧‧Second copper (Cu) joint

427‧‧‧第二銅(Cu)障壁層 427‧‧‧Second copper (Cu) barrier layer

428‧‧‧介面銅(Cu)障壁膜 428‧‧‧Interface copper (Cu) barrier film

430‧‧‧第一半導體部件 430‧‧‧First semiconductor component

431‧‧‧第一銅(Cu)晶種層 431‧‧‧First copper (Cu) seed layer

440‧‧‧第二半導體部件 440‧‧‧Second semiconductor components

441‧‧‧第二銅(Cu)晶種層 441‧‧‧Second copper (Cu) seed layer

450‧‧‧光阻膜/介面銅(Cu)障壁膜 450‧‧‧Photoresist/Interface Copper (Cu) Barrier Film

450a‧‧‧光阻膜/介面銅(Cu)障壁膜之開口 450a‧‧‧ Opening of the photoresist film/interface copper (Cu) barrier film

451‧‧‧銅(Cu)膜 451‧‧‧copper (Cu) film

452‧‧‧絕緣膜 452‧‧‧Insulation film

453‧‧‧光阻膜 453‧‧‧Photoresist film

453a‧‧‧開口 453a‧‧‧ openings

454‧‧‧銅(Cu)膜 454‧‧‧copper (Cu) film

455‧‧‧銅(Cu)膜 455‧‧‧copper (Cu) film

456‧‧‧光阻膜 456‧‧‧Photoresist film

456a‧‧‧開口 456a‧‧‧ openings

457‧‧‧光阻膜 457‧‧‧Photoresist film

457a‧‧‧開口 457a‧‧‧ openings

458‧‧‧銅(Cu)膜 458‧‧‧copper (Cu) film

459‧‧‧光阻膜 459‧‧‧Photoresist film

459a‧‧‧光阻膜459之開口 459a‧‧‧ openings of photoresist film 459

460‧‧‧第二半導體部件 460‧‧‧Second semiconductor components

461‧‧‧第二銅(Cu)障壁層 461‧‧‧Second copper (Cu) barrier layer

461a‧‧‧障壁本體部分 461a‧‧‧Baffle body part

461b‧‧‧介面層部分 461b‧‧‧Interface layer

470‧‧‧第二半導體部件 470‧‧‧Second semiconductor components

471‧‧‧介面銅(Cu)障壁膜 471‧‧‧Interface copper (Cu) barrier film

480‧‧‧第二半導體部件 480‧‧‧Second semiconductor components

481‧‧‧第二層間絕緣膜 481‧‧‧Second interlayer insulating film

482‧‧‧介面銅(Cu)障壁膜 482‧‧‧Interface copper (Cu) barrier film

491‧‧‧第一半導體部件 491‧‧‧First semiconductor component

492‧‧‧第二半導體部件 492‧‧‧Second semiconductor components

493‧‧‧第一鋁(Al)連結部分 493‧‧‧First aluminum (Al) joint

494‧‧‧第一障壁金屬層 494‧‧‧First barrier metal layer

495‧‧‧第二鋁(Al)連結部分 495‧‧‧Second aluminum (Al) joint

496‧‧‧第二障壁金屬層 496‧‧‧Second barrier metal layer

497‧‧‧介面障壁膜 497‧‧‧Interface barrier film

500‧‧‧半導體裝置 500‧‧‧Semiconductor device

501‧‧‧第一半導體部件 501‧‧‧First semiconductor component

502‧‧‧第一銅(Cu)連結部分 502‧‧‧First copper (Cu) joint

503‧‧‧第一銅(Cu)障壁層 503‧‧‧First copper (Cu) barrier layer

504‧‧‧第一銅(Cu)晶種層 504‧‧‧First copper (Cu) seed layer

505‧‧‧介面銅(Cu)障壁膜 505‧‧‧Interface copper (Cu) barrier film

510‧‧‧半導體裝置 510‧‧‧Semiconductor device

520‧‧‧第二半導體部件 520‧‧‧Second semiconductor components

521‧‧‧第一介面銅(Cu)障壁膜 521‧‧‧First interface copper (Cu) barrier film

530‧‧‧半導體裝置 530‧‧‧Semiconductor device

531‧‧‧第一半導體部件 531‧‧‧First semiconductor component

532‧‧‧第二半導體部件 532‧‧‧Second semiconductor components

533‧‧‧第一銅(Cu)連結部分 533‧‧‧First copper (Cu) link

534‧‧‧凹陷部分 534‧‧‧ recessed part

540‧‧‧半導體裝置 540‧‧‧Semiconductor device

610‧‧‧第一半導體部件 610‧‧‧First semiconductor component

611‧‧‧第一氧化矽(SiO2)層 611‧‧‧first yttrium oxide (SiO 2 ) layer

612‧‧‧第一銅(Cu)電極 612‧‧‧First copper (Cu) electrode

613‧‧‧第一銅(Cu)障壁層 613‧‧‧First copper (Cu) barrier layer

620‧‧‧第二半導體部件 620‧‧‧Second semiconductor components

621‧‧‧第二氧化矽(SiO2)層 621‧‧‧Second yttrium oxide (SiO 2 ) layer

622‧‧‧第二銅(Cu)電極 622‧‧‧Second copper (Cu) electrode

623‧‧‧第二銅(Cu)障壁層 623‧‧‧Second copper (Cu) barrier layer

630‧‧‧銅(Cu) 630‧‧‧Copper (Cu)

650‧‧‧半導體裝置 650‧‧‧Semiconductor device

660‧‧‧半導體裝置 660‧‧‧Semiconductor device

661‧‧‧第一半導體部件 661‧‧‧First semiconductor component

662‧‧‧第二半導體部件 662‧‧‧Second semiconductor components

663‧‧‧第一層間絕緣膜 663‧‧‧First interlayer insulating film

664‧‧‧第二層間絕緣膜 664‧‧‧Second interlayer insulating film

700‧‧‧半導體影像感測器模組 700‧‧‧Semiconductor image sensor module

701‧‧‧第一半導體晶片 701‧‧‧First semiconductor wafer

702‧‧‧第二半導體晶片 702‧‧‧Second semiconductor wafer

703‧‧‧光電二極體形成區域 703‧‧‧Photodiode formation area

704‧‧‧電晶體形成區域 704‧‧‧Optolith formation area

705‧‧‧類比/數位轉換器陣列 705‧‧‧ Analog/Digital Converter Array

706‧‧‧滲透接觸部分 706‧‧‧Infiltration contact

707‧‧‧接觸部分 707‧‧‧Contact section

800‧‧‧固態影像擷取裝置 800‧‧‧ Solid-state image capture device

810‧‧‧第一半導體基板 810‧‧‧First semiconductor substrate

811‧‧‧半導體井區域 811‧‧‧Semiconductor well area

812‧‧‧多層配接線層 812‧‧‧Multilayer wiring layer

813‧‧‧層間絕緣膜 813‧‧‧Interlayer insulating film

814‧‧‧金屬配接線 814‧‧‧Metal wiring

815‧‧‧連接導體 815‧‧‧Connecting conductor

820‧‧‧第二半導體基板 820‧‧‧second semiconductor substrate

821‧‧‧半導體井區域 821‧‧‧Semiconductor well area

822‧‧‧多層配接線層 822‧‧‧Multilayer wiring layer

823‧‧‧層間絕緣膜 823‧‧‧Interlayer insulating film

824‧‧‧金屬配接線 824‧‧‧Metal wiring

825‧‧‧連接導體 825‧‧‧Connecting conductor

830‧‧‧平坦膜 830‧‧‧flat film

831‧‧‧晶片上彩色濾光片 831‧‧‧Color filters on the wafer

832‧‧‧晶片上微透鏡陣列 832‧‧‧Microlens array on wafer

910‧‧‧第一連結部分 910‧‧‧ first link

911‧‧‧第一連結電極 911‧‧‧First connection electrode

912‧‧‧第一配接線層 912‧‧‧First wiring layer

913‧‧‧通孔 913‧‧‧through hole

914‧‧‧障壁金屬層 914‧‧‧Baffle metal layer

915‧‧‧層間絕緣膜/層間絕緣層 915‧‧‧Interlayer insulating film/interlayer insulating layer

916‧‧‧中間層 916‧‧‧Intermediate

917‧‧‧層間絕緣層 917‧‧‧Interlayer insulation

918‧‧‧中間層 918‧‧‧Intermediate

919‧‧‧層間絕緣層 919‧‧‧Interlayer insulation

920‧‧‧第二連結部分 920‧‧‧Second link

921‧‧‧第二連結電極 921‧‧‧Second connection electrode

922‧‧‧第二配接線層 922‧‧‧Second wiring layer

923‧‧‧通孔 923‧‧‧through hole

924‧‧‧障壁金屬層 924‧‧‧Baffle metal layer

925‧‧‧層間絕緣層 925‧‧‧Interlayer insulation

926‧‧‧中間層 926‧‧‧Intermediate

927‧‧‧層間絕緣層 927‧‧‧Interlayer insulation

928‧‧‧中間層 928‧‧‧Intermediate

929‧‧‧層間絕緣層 929‧‧‧Interlayer insulation

930‧‧‧水 930‧‧‧ water

931‧‧‧障壁金屬層 931‧‧‧ barrier metal layer

932‧‧‧障壁金屬層 932‧‧‧ barrier metal layer

933‧‧‧接觸部分 933‧‧‧Contact section

940‧‧‧第一連結部分 940‧‧‧ first link

941‧‧‧第一連結電極 941‧‧‧First connection electrode

941A‧‧‧障壁金屬層 941A‧‧‧ barrier metal layer

942‧‧‧第二連結電極 942‧‧‧Second connection electrode

942A‧‧‧障壁金屬層 942A‧‧‧Baffle metal layer

943‧‧‧第三連結電極 943‧‧‧ Third connecting electrode

943A‧‧‧障壁金屬層 943A‧‧‧ barrier metal layer

944‧‧‧第一保護層 944‧‧‧First protective layer

945‧‧‧第二保護層 945‧‧‧Second protective layer

946‧‧‧第一配接線 946‧‧‧First wiring

946A‧‧‧障壁金屬層 946A‧‧‧ barrier metal layer

947‧‧‧第二配接線 947‧‧‧Second wiring

947A‧‧‧障壁金屬層 947A‧‧‧ barrier metal layer

948‧‧‧第三配接線 948‧‧‧ Third wiring

948A‧‧‧障壁金屬層 948A‧‧‧ barrier metal layer

949‧‧‧接觸部分 949‧‧‧Contact section

950‧‧‧連結面 950‧‧‧ link

951‧‧‧第一層間絕緣層 951‧‧‧First interlayer insulation

952‧‧‧第一中間層 952‧‧‧First intermediate layer

953‧‧‧第二層間絕緣層 953‧‧‧Second interlayer insulation

954‧‧‧第二中間層 954‧‧‧Second intermediate layer

955‧‧‧第三層間絕緣層 955‧‧‧3rd interlayer insulation

956‧‧‧第一通孔 956‧‧‧ first through hole

956A‧‧‧障壁金屬層 956A‧‧‧Baffle metal layer

957‧‧‧第二通孔 957‧‧‧second through hole

957A‧‧‧障壁金屬層 957A‧‧‧ barrier metal layer

958‧‧‧第三通孔 958‧‧‧3rd through hole

958A‧‧‧障壁金屬層 958A‧‧‧Baffle metal layer

960‧‧‧第二連結部分 960‧‧‧Second link

961‧‧‧第四連結電極 961‧‧‧fourth connection electrode

961A‧‧‧障壁金屬層 961A‧‧‧ barrier metal layer

962‧‧‧第五連結電極 962‧‧‧ fifth connecting electrode

962A‧‧‧障壁金屬層 962A‧‧‧ barrier metal layer

963‧‧‧第六連結電極 963‧‧‧6th connection electrode

963A‧‧‧障壁金屬層 963A‧‧‧ barrier metal layer

964‧‧‧第三保護層 964‧‧‧ third protective layer

965‧‧‧第四保護層 965‧‧‧ fourth protective layer

966‧‧‧第四配接線 966‧‧‧fourth wiring

966A‧‧‧障壁金屬層 966A‧‧‧ barrier metal layer

967‧‧‧第五配接線 967‧‧‧Fixed wiring

967A‧‧‧障壁金屬層 967A‧‧‧Baffle metal layer

968‧‧‧第六配接線 968‧‧‧ sixth wiring

968A‧‧‧障壁金屬層 968A‧‧‧Baffle metal layer

969‧‧‧接觸部分 969‧‧‧Contact section

970‧‧‧水 970‧‧‧ water

971‧‧‧第四層間絕緣層 971‧‧‧4th interlayer insulation

972‧‧‧第三中間層 972‧‧‧The third intermediate layer

973‧‧‧第五層間絕緣層 973‧‧‧5th interlayer insulation

974‧‧‧第四中間層 974‧‧‧ fourth intermediate layer

975‧‧‧第六層間絕緣層 975‧‧‧6th interlayer insulation

976‧‧‧第四通孔 976‧‧‧fourth through hole

976A‧‧‧障壁金屬層 976A‧‧‧ barrier metal layer

977‧‧‧第五通孔 977‧‧‧5th through hole

977A‧‧‧障壁金屬層 977A‧‧‧ barrier metal layer

978‧‧‧第六通孔 978‧‧‧ sixth through hole

978A‧‧‧障壁金屬層 978A‧‧‧ barrier metal layer

979‧‧‧接觸部分 979‧‧‧Contact section

981‧‧‧第一保護層 981‧‧‧First protective layer

981A‧‧‧導體層 981A‧‧‧ conductor layer

981B‧‧‧障壁金屬層 981B‧‧‧Baffle metal layer

982‧‧‧第二保護層 982‧‧‧Second protective layer

982A‧‧‧導體層 982A‧‧‧ conductor layer

982B‧‧‧障壁金屬層 982B‧‧‧Baffle metal layer

983‧‧‧第一層間絕緣層 983‧‧‧First interlayer insulation

984‧‧‧第二層間絕緣層 984‧‧‧Second interlayer insulation

985‧‧‧第三層間絕緣層 985‧‧‧3rd interlayer insulation

986‧‧‧第四層間絕緣層 986‧‧‧4th interlayer insulation

991‧‧‧光阻層 991‧‧‧Photoresist layer

992‧‧‧有機材料層 992‧‧‧Organic material layer

993‧‧‧氧化物層 993‧‧‧Oxide layer

994‧‧‧光阻層 994‧‧‧ photoresist layer

995‧‧‧障壁材料層 995‧‧ ‧ barrier material layer

996‧‧‧電極材料層 996‧‧‧electrode material layer

997‧‧‧光阻層 997‧‧‧ photoresist layer

998‧‧‧障壁材料層 998‧‧‧ barrier material layer

999‧‧‧電極材料層 999‧‧‧electrode material layer

FD‧‧‧浮動擴散區 FD‧‧‧Floating diffusion zone

TG‧‧‧轉移閘極 TG‧‧‧Transfer gate

Tr‧‧‧電晶體 Tr‧‧•O crystal

圖1係展示應用本技術之一實施例之一半導體裝置之一實例之一方塊圖；圖2係展示根據本技術之一第一實施例之一半導體裝置之一組態之一部分截面圖；圖3A至圖3F係圖解說明在製造圖2之半導體裝置中一感測器基板之一製造程序之不同步驟之示意截面圖；圖4A至圖4E係圖解說明在製造圖2之半導體裝置中一電路板之一製造程序之不同步驟之示意截面圖；圖5A及圖5B係圖解說明在製造圖2之半導體裝置中不同接合步驟之示意截面圖；圖6A至圖6C、圖6A'至圖6C'及圖6D係圖解說明作為圖2 之半導體裝置之一比較實例之一半導體裝置之一製造方法之一實例之示意截面圖；圖7係展示圖2之半導體裝置之一修改之一半導體裝置之一組態之一部分示意截面圖；圖8係展示根據本技術之一第二實施例之一半導體裝置之一組態之一部分截面圖；圖9A至圖9E係圖解說明製造根據本技術之第二實施例之一半導體裝置中一第一基板或感測器基板之一製造程序之示意截面圖；圖10A及圖10B係圖解說明在製造根據該第二實施例之半導體裝置中一第二基板或電路基板之一製造程序之示意截面圖；圖11A及圖11B係圖解說明在製造根據該第二實施例之半導體裝置中不同接合步驟之示意截面圖；圖12A及圖12B係圖解說明在Cu-Cu連結時發生之一問題之示意截面圖；圖13係圖解說明在Cu-Cu連結時發生之另一問題之一示意截面圖；圖14係根據本技術之一第三實施例之一第一工作實例之一半導體裝置之一連結介面附近之一示意截面圖；圖15係圖14之半導體裝置之一連結介面附近之一示意俯視平面圖；圖16A至圖16M係圖解說明圖15之半導體裝置之一製造程序之不同步驟之示意截面圖； 圖17係根據本技術之第三實施例之一第二工作實例之一半導體裝置之一連結介面附近之一示意截面圖；圖18係圖17之半導體裝置之一連結介面附近之一示意俯視平面圖；圖19A至圖19E係圖解說明圖17之半導體裝置之一製造程序之不同步驟之示意截面圖；圖20係根據本技術之第三實施例之一第三工作實例之一半導體裝置之一連結介面附近之一示意截面圖；圖21係圖20之半導體裝置之一連結介面附近之一示意俯視平面圖；圖22A至圖22H係圖解說明圖20之半導體裝置之一製造程序之不同步驟之示意截面圖；圖23係根據一修改1之一半導體裝置之一連結介面附近之一示意截面圖；圖24係圖解說明圖23之半導體裝置之一製造程序之一示意截面圖；圖25及圖26係根據修改3及4之半導體裝置之一連結介面附近之示意截面圖；圖27及圖28係根據參考實例1及2之半導體裝置之一連結介面附近之示意截面圖；圖29及圖30係圖解說明在一現有Cu-Cu連結技術中可發生之問題之示意圖；圖31係根據本技術之第三實施例之一第四工作實例之一半導體裝置之一連結介面附近之一示意截面圖； 圖32係圖31之半導體裝置之一連結介面附近之一示意俯視平面圖；圖33A至圖33D係圖解說明圖31之半導體裝置之一製造程序之不同步驟之示意截面圖；圖34係根據本技術之第三實施例之一第五工作實例之一半導體裝置之一連結介面附近之一示意截面圖；圖35係圖34之半導體裝置之一連結介面附近之一示意俯視平面圖；圖36A至圖36D係圖解說明圖34之半導體裝置之一製造程序之不同步驟之示意截面圖；圖37係展示可應用本技術之Cu-Cu連結技術之一應用實例1之一半導體裝置之一組態之一實例之一示意截面圖；圖38係展示可應用本技術之Cu-Cu連結技術之一應用實例2之一半導體裝置之一組態之一實例之一示意截面圖；圖39係展示根據本技術之一第四實施例之一半導體裝置之一連結電極之一般組態之一示意截面圖；圖40A係展示包含圖39之連結電極之半導體裝置之一般組態之一示意截面圖，且圖40B係圖40A中所示之一第一連結部分之一連結面之一平面圖；圖41A至圖41K係圖解說明圖40A之半導體裝置之不同製造步驟之示意圖；圖42A係展示包含對圖39之連結電極之一修改1之一連結電極之一半導體裝置之一般組態之一示意截面圖，且圖42B係圖42A中所示之一第一連結部分之一連結面之一平 面圖；圖43A至圖43G係圖解說明圖42A之半導體裝置之不同製造步驟之示意截面圖；圖44係展示包含對圖39之連結電極之一修改2之一連結電極之一半導體裝置之一般組態之一示意圖；及圖45係展示包含藉由應用本技術獲得之一半導體裝置之一電子設備之一方塊圖。 1 is a block diagram showing an example of a semiconductor device to which one embodiment of the present technology is applied; FIG. 2 is a partial cross-sectional view showing one configuration of a semiconductor device according to a first embodiment of the present technology; 3A to 3F are schematic cross-sectional views illustrating different steps in a manufacturing process of a sensor substrate in the fabrication of the semiconductor device of FIG. 2; and FIGS. 4A to 4E illustrate a circuit in the fabrication of the semiconductor device of FIG. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 5A and FIG. 5B are schematic cross-sectional views illustrating different bonding steps in fabricating the semiconductor device of FIG. 2; FIGS. 6A-6C, 6A' to 6C' And Figure 6D is illustrated as Figure 2 A schematic cross-sectional view of one example of a method of fabricating one of the semiconductor devices of one of the semiconductor devices; FIG. 7 is a partially schematic cross-sectional view showing one of the configurations of one of the semiconductor devices of FIG. 2; 8 is a partial cross-sectional view showing one configuration of a semiconductor device according to a second embodiment of the present technology; and FIGS. 9A to 9E are diagrams illustrating a first one of semiconductor devices in accordance with a second embodiment of the present technology. Schematic cross-sectional view of a manufacturing process of a substrate or a sensor substrate; FIGS. 10A and 10B are schematic cross-sectional views illustrating a manufacturing process of a second substrate or circuit substrate in the semiconductor device according to the second embodiment; 11A and 11B are schematic cross-sectional views illustrating different bonding steps in fabricating a semiconductor device according to the second embodiment; FIGS. 12A and 12B are schematic cross-sectional views illustrating a problem occurring when Cu-Cu is bonded. Figure 13 is a schematic cross-sectional view illustrating another problem occurring when Cu-Cu is joined; Figure 14 is a first working example according to a third embodiment of the present technology. 1 is a schematic cross-sectional view of a vicinity of a bonding interface of a semiconductor device; FIG. 15 is a schematic top plan view of a vicinity of a bonding interface of one of the semiconductor devices of FIG. 14; FIG. 16A to FIG. 16M are diagrams illustrating a manufacturing process of the semiconductor device of FIG. a schematic cross-sectional view of the different steps; 17 is a schematic cross-sectional view showing a vicinity of a connection interface of a semiconductor device according to a second working example of the third embodiment of the present technology; and FIG. 18 is a schematic top plan view showing a vicinity of a connection interface of one of the semiconductor devices of FIG. 19A to 19E are schematic cross-sectional views illustrating different steps of a manufacturing process of one of the semiconductor devices of FIG. 17; FIG. 20 is a connection of one of the semiconductor devices according to one of the third working examples of the third embodiment of the present technology; 1 is a schematic cross-sectional view of a vicinity of a bonding interface of a semiconductor device of FIG. 20; and FIGS. 22A to 22H are schematic cross-sectional views illustrating different steps of a manufacturing process of the semiconductor device of FIG. Figure 23 is a schematic cross-sectional view of a vicinity of a bonding interface of a semiconductor device according to a modification 1; Figure 24 is a schematic cross-sectional view showing one of the manufacturing procedures of the semiconductor device of Figure 23; Figure 25 and Figure 26 A schematic cross-sectional view of a vicinity of a connection interface of one of the semiconductor devices according to Modifications 3 and 4; and FIGS. 27 and 28 are a connection of one of the semiconductor devices according to Reference Examples 1 and 2. A schematic cross-sectional view in the vicinity; FIGS. 29 and 30 are diagrams illustrating a problem that may occur in a conventional Cu-Cu joining technique; FIG. 31 is a semiconductor according to a fourth working example of a third embodiment of the present technology. a schematic cross-sectional view of one of the devices adjacent to the interface; 32 is a schematic top plan view of a vicinity of a bonding interface of one of the semiconductor devices of FIG. 31; FIGS. 33A to 33D are schematic cross-sectional views illustrating different steps of a manufacturing process of the semiconductor device of FIG. 31; A schematic cross-sectional view of one of the semiconductor devices in the vicinity of one of the semiconductor devices; FIG. 35 is a schematic top plan view of one of the vicinity of the bonding interface of the semiconductor device of FIG. 34; FIG. 36A to FIG. 36D A schematic cross-sectional view illustrating different steps of a manufacturing process of one of the semiconductor devices of FIG. 34; FIG. 37 is a diagram showing an example of one of the semiconductor devices of one of the application examples 1 of the Cu-Cu bonding technology to which the present technology can be applied. 1 is a schematic cross-sectional view; FIG. 38 is a schematic cross-sectional view showing one of the configurations of one of the semiconductor devices of one of the application examples 2 of the Cu-Cu bonding technology to which the present technology can be applied; FIG. 39 is a view showing the configuration according to the present technology. A schematic cross-sectional view of a general configuration of a connection electrode of one of the semiconductor devices of a fourth embodiment; FIG. 40A shows a general configuration of a semiconductor device including the connection electrode of FIG. a schematic cross-sectional view, and FIG. 40B is a plan view of one of the joint faces of one of the first joint portions shown in FIG. 40A; and FIGS. 41A to 41K are schematic views illustrating different manufacturing steps of the semiconductor device of FIG. 40A; 42A is a schematic cross-sectional view showing a general configuration of a semiconductor device including one of the connection electrodes of one of the connection electrodes of FIG. 39, and FIG. 42B is one of the first connection portions shown in FIG. 42A. One of the faces FIG. 43A to FIG. 43G are schematic cross-sectional views illustrating different manufacturing steps of the semiconductor device of FIG. 42A; FIG. 44 is a view showing a general semiconductor device including one of the bonding electrodes of one of the bonding electrodes of FIG. A schematic diagram of one of the configurations; and FIG. 45 is a block diagram showing an electronic device including one of the semiconductor devices obtained by applying the present technology.

1‧‧‧半導體裝置 1‧‧‧Semiconductor device

2‧‧‧感測器基板 2‧‧‧Sensor substrate

2a‧‧‧半導體層 2a‧‧‧Semiconductor layer

2b‧‧‧配接線層 2b‧‧‧With wiring layer

2c‧‧‧電極層 2c‧‧‧electrode layer

7‧‧‧電路基板 7‧‧‧ circuit board

7a‧‧‧半導體層 7a‧‧‧Semiconductor layer

7b‧‧‧第一配接線層 7b‧‧‧First wiring layer

7c‧‧‧第二配接線層 7c‧‧‧Second wiring layer

7d‧‧‧電極層 7d‧‧‧electrode layer

15‧‧‧保護膜 15‧‧‧Protective film

17‧‧‧彩色濾光片層 17‧‧‧Color filter layer

19‧‧‧晶片上透鏡 19‧‧‧ wafer on lens

20‧‧‧半導體基板 20‧‧‧Semiconductor substrate

21‧‧‧光電轉換部分 21‧‧‧Photoelectric conversion section

23‧‧‧源極/汲極 23‧‧‧Source/Bungee

25‧‧‧閘極絕緣膜 25‧‧‧gate insulating film

27‧‧‧閘極電極 27‧‧‧ gate electrode

29‧‧‧層間絕緣膜 29‧‧‧Interlayer insulating film

31‧‧‧嵌入式配接線 31‧‧‧Embedded wiring

31a‧‧‧障壁金屬層 31a‧‧‧ barrier metal layer

31b‧‧‧配接線層 31b‧‧‧With wiring layer

33‧‧‧第一電極 33‧‧‧First electrode

35‧‧‧第一絕緣膜 35‧‧‧First insulating film

35a‧‧‧溝槽圖案 35a‧‧‧ Groove pattern

50‧‧‧半導體基板 50‧‧‧Semiconductor substrate

51‧‧‧源極/汲極 51‧‧‧Source/Bungee

53‧‧‧閘極絕緣膜 53‧‧‧gate insulating film

55‧‧‧閘極電極 55‧‧‧gate electrode

57‧‧‧層間絕緣膜 57‧‧‧Interlayer insulating film

59‧‧‧嵌入式配接線 59‧‧‧Embedded wiring

59a‧‧‧障壁金屬層 59a‧‧‧Baffle metal layer

59b‧‧‧配接線層 59b‧‧‧Wiring layer

61‧‧‧擴散防止絕緣層 61‧‧‧Diffusion prevention insulation

63‧‧‧層間絕緣膜 63‧‧‧Interlayer insulating film

65‧‧‧嵌入式配接線 65‧‧‧Embedded wiring

65a‧‧‧障壁金屬層 65a‧‧‧ barrier metal layer

65b‧‧‧配接線層 65b‧‧‧Wiring layer

67‧‧‧第二電極 67‧‧‧second electrode

69‧‧‧第二絕緣膜 69‧‧‧Second insulation film

69a‧‧‧溝槽圖案 69a‧‧‧ Groove pattern

FD‧‧‧浮動擴散區 FD‧‧‧Floating diffusion zone

TG‧‧‧轉移閘極 TG‧‧‧Transfer gate

Tr‧‧‧電晶體 Tr‧‧•O crystal

Claims (43)

一種半導體裝置，其包括：一第一基板，其包含：一第一電極，及一第一絕緣膜，其由該第一電極之一擴散防止材料組態並覆蓋該第一電極之一周邊，該第一電極與該第一絕緣膜彼此協調以組態一接合面；及一第二基板，其接合至該第一基板並設置於該第一基板上，且包含：一第二電極，其連結至該第一電極，及一第二絕緣膜，其由該第二電極之一擴散防止材料組態並覆蓋該第二電極之一周邊，該第二電極與該第二絕緣膜彼此協調以組態至該第一基板的一接合面。 A semiconductor device comprising: a first substrate comprising: a first electrode, and a first insulating film configured by a diffusion preventing material of the first electrode and covering a periphery of the first electrode The first electrode and the first insulating film are coordinated with each other to configure a bonding surface; and a second substrate is bonded to the first substrate and disposed on the first substrate, and includes: a second electrode Connecting to the first electrode, and a second insulating film configured by one diffusion preventing material of the second electrode and covering a periphery of one of the second electrodes, wherein the second electrode and the second insulating film are coordinated with each other Configuring to a joint surface of the first substrate. 如請求項1之半導體裝置，其中該第一電極及該第二電極之各者係由一單一材料層組態。 The semiconductor device of claim 1, wherein each of the first electrode and the second electrode is configured by a single material layer. 如請求項1之半導體裝置，其中該第一基板之該接合面及該第二基板之該接合面之各者係組態為一平坦面。 The semiconductor device of claim 1, wherein each of the bonding surface of the first substrate and the bonding surface of the second substrate is configured as a flat surface. 如請求項1之半導體裝置，其中該第一電極嵌入形成於該第一絕緣膜上之一溝槽圖案中，及該第二電極嵌入形成於該第二絕緣膜上之一溝槽圖案中。 The semiconductor device of claim 1, wherein the first electrode is embedded in a trench pattern formed on the first insulating film, and the second electrode is embedded in a trench pattern formed on the second insulating film. 如請求項1之半導體裝置，其中該第一基板之該接合面 係僅由該第一電極及該第一絕緣膜組態，及該第二基板之該接合面係僅由該第二電極及該第二絕緣膜組態。 The semiconductor device of claim 1, wherein the bonding surface of the first substrate The first electrode and the first insulating film are configured only, and the bonding surface of the second substrate is configured only by the second electrode and the second insulating film. 如請求項1之半導體裝置，其中該第一絕緣膜係由組態該第二電極以及該第一電極之一材料之一擴散防止材料組態，及該第二絕緣膜係由組態該第一電極以及該第二電極之一材料之一擴散防止材料組態。 The semiconductor device of claim 1, wherein the first insulating film is configured by a diffusion preventing material configuring one of the second electrode and a material of the first electrode, and the second insulating film is configured by the first One of the electrodes and one of the materials of the second electrode is diffusion-preventing material configuration. 如請求項1之半導體裝置，其中該第一電極及該第二電極係由一相同材料組態。 The semiconductor device of claim 1, wherein the first electrode and the second electrode are configured by a same material. 如請求項1之半導體裝置，其中該第一絕緣膜及該第二絕緣膜係由一相同材料組態。 The semiconductor device of claim 1, wherein the first insulating film and the second insulating film are configured by a same material. 一種用於一半導體裝置之製造方法，其包括：在兩個基板之各者上形成由一電極材料之一擴散防止材料組態之一絕緣膜且在該絕緣膜上形成一溝槽圖案；在該等基板之各者之該絕緣膜上形成由該電極材料組態之一電極膜，形成的狀態為該電極膜填滿形成於該絕緣膜上之該溝槽圖案；拋光該等基板之各者之該電極膜直到曝露該絕緣膜以形成一電極圖案使得該電極膜嵌入該溝槽圖案中；及接合該兩個基板，該電極形成在該兩個基板之各者上，接合的狀態為該等電極連結在一起。 A manufacturing method for a semiconductor device, comprising: forming an insulating film of a diffusion preventing material configuration of one of electrode materials on each of two substrates and forming a groove pattern on the insulating film; An electrode film configured by the electrode material is formed on the insulating film of each of the substrates, and the electrode film is filled with the groove pattern formed on the insulating film; and each of the substrates is polished The electrode film is exposed to the insulating film to form an electrode pattern such that the electrode film is embedded in the groove pattern; and the two substrates are bonded, and the electrode is formed on each of the two substrates, and the bonding state is The electrodes are joined together. 如請求項9之用於一半導體裝置之製造方法，其中當形成該電極圖案時，實施其中使用該絕緣膜作為一止擋件 之化學機械拋光。 A method for manufacturing a semiconductor device according to claim 9, wherein when the electrode pattern is formed, the insulating film is used as a stopper Chemical mechanical polishing. 如請求項9之用於一半導體裝置之製造方法，其中當形成該電極圖案時，開始於周圍藉由拋光該電極膜而曝露該絕緣膜使得該拋光自動停止之該電極膜之一部分，按順序實施化學機械拋光。 A method for manufacturing a semiconductor device according to claim 9, wherein when the electrode pattern is formed, a portion of the electrode film that is automatically stopped by polishing the electrode film by polishing the electrode film is started, in order Perform chemical mechanical polishing. 一種半導體裝置，其包括：一第一基板，其具有曝露一第一電極及一第一絕緣膜之一接合面；一絕緣薄膜，其經組態以覆蓋該第一基板之該接合面；及一第二基板，其具有曝露一第二電極及一第二絕緣膜之一接合面且接合至該第一基板，接合的狀態為該絕緣薄膜夾置在該第二基板之該接合面與該第一基板之該接合面之間，且該第一電極與該第二電極透過該絕緣薄膜而彼此電連接。 A semiconductor device comprising: a first substrate having a bonding surface exposing a first electrode and a first insulating film; an insulating film configured to cover the bonding surface of the first substrate; a second substrate having a bonding surface exposing a second electrode and a second insulating film and bonding to the first substrate, wherein the bonding state is that the insulating film is sandwiched between the bonding surface of the second substrate and the The first electrode and the second electrode are electrically connected to each other through the insulating film. 如請求項12之半導體裝置，其中該絕緣薄膜係氧化物膜。 The semiconductor device of claim 12, wherein the insulating film is an oxide film. 如請求項12之半導體裝置，其中該絕緣薄膜係氮化物膜。 The semiconductor device of claim 12, wherein the insulating film is a nitride film. 如請求項12之半導體裝置，其中該絕緣薄膜具有一層壓結構。 The semiconductor device of claim 12, wherein the insulating film has a laminated structure. 如請求項12之半導體裝置，其中該絕緣薄膜係設置成其中該絕緣薄膜覆蓋該等接合面之各者之一總體面積之一狀態。 The semiconductor device of claim 12, wherein the insulating film is disposed in a state in which the insulating film covers one of a total area of each of the bonding faces. 如請求項12之半導體裝置，其中該第一基板之該接合面及該第二基板之該接合面係平坦面。 The semiconductor device of claim 12, wherein the bonding surface of the first substrate and the bonding surface of the second substrate are flat surfaces. 一種用於一半導體裝置之製造方法，其包括：製備各具有曝露一電極及一絕緣膜之一接合面之兩個基板；形成一絕緣薄膜，形成的狀態為其中該絕緣薄膜覆蓋該兩個基板之至少一者之該接合面；及安置該兩個基板使得其等之該等接合面跨該絕緣薄膜而彼此相對、將該兩個基板定位成其中其等之該等電極透過該絕緣薄膜而彼此電連接之一狀態，且在該定位狀態下接合該兩個基板。 A manufacturing method for a semiconductor device, comprising: preparing two substrates each having a bonding surface exposing an electrode and an insulating film; forming an insulating film in a state in which the insulating film covers the two substrates The bonding surface of at least one of the substrates; and the two substrates are disposed such that the bonding faces are opposite to each other across the insulating film, and the two substrates are positioned such that the electrodes thereof pass through the insulating film One state is electrically connected to each other, and the two substrates are joined in the positioned state. 如請求項18之用於一半導體裝置之製造方法，其中在該兩個基板二者上形成該絕緣薄膜。 A method of manufacturing a semiconductor device according to claim 18, wherein the insulating film is formed on both of the substrates. 如請求項18之用於一半導體裝置之製造方法，其中在該兩個基板二者上形成一相同材料之該絕緣薄膜。 A method of manufacturing a semiconductor device according to claim 18, wherein the insulating film of the same material is formed on both of the substrates. 如請求項18之用於一半導體裝置之製造方法，其中藉由一原子層沈積方法形成該絕緣薄膜。 A method of manufacturing a semiconductor device according to claim 18, wherein the insulating film is formed by an atomic layer deposition method. 如請求項18之用於一半導體裝置之製造方法，其中藉由一平坦化製程形成該兩個基板之該等接合面。 A method of fabricating a semiconductor device according to claim 18, wherein the bonding faces of the two substrates are formed by a planarization process. 一種半導體裝置，其包括：一第一半導體部分，其在一接合介面側上具有形成於其表面上之一第一金屬膜；一第二半導體部分，其在該接合介面上具有連結至該第一金屬膜之一第二金屬膜且在該連結介面側上具有小 於該連結介面側上之該第一金屬膜之一表面積之一表面積，且設置為其中在該連結介面上該第二半導體部分接合至該第一半導體部分之一狀態；及一介面障壁部分，其設置在該連結介面側上之該第一金屬膜之一面區域之一部分中，該部分包含其中該第一金屬膜未連結至該第二金屬膜之一面區域。 A semiconductor device comprising: a first semiconductor portion having a first metal film formed on a surface thereof on a bonding interface side; and a second semiconductor portion having a bonding to the bonding interface a second metal film of a metal film and having a small on the side of the bonding interface One surface area of one surface area of the first metal film on the side of the bonding interface, and is disposed in a state in which the second semiconductor portion is bonded to one of the first semiconductor portions on the bonding interface; and an interface barrier portion, The portion is disposed in a portion of the one surface region of the first metal film on the side of the bonding interface, wherein the portion includes a surface region in which the first metal film is not bonded to the second metal film. 如請求項23之半導體裝置，其中該第二半導體部分具有設置在該連結介面側上之該第一金屬膜之該面區域之該部分中之一介面障壁膜，該部分包含其中該第一金屬膜未連結至該第二金屬膜之該面區域。 The semiconductor device of claim 23, wherein the second semiconductor portion has one of the interface barrier films disposed in the portion of the surface region of the first metal film on the bonding interface side, the portion including the first metal The film is not bonded to the face region of the second metal film. 如請求項24之半導體裝置，其中該第二半導體部分包含經設置以覆蓋該第二金屬膜之一側部分之一絕緣膜，及該介面障壁膜形成於該絕緣膜在該連結介面側上之該表面上。 The semiconductor device of claim 24, wherein the second semiconductor portion comprises an insulating film disposed to cover one of the side portions of the second metal film, and the interface barrier film is formed on the bonding interface side of the insulating film On the surface. 如請求項24之半導體裝置，其中該介面障壁膜由SiN、SiON、SiCN及一有機樹脂材料之一者形成。 The semiconductor device of claim 24, wherein the interface barrier film is formed of one of SiN, SiON, SiCN, and an organic resin material. 如請求項24之半導體裝置，其中該第一半導體部分包含：一第一氧化物膜，其經設置以覆蓋該第一金屬膜之一側部分，及一晶種層，其設置於該第一氧化物膜與該第一金屬膜之間且含有一預定金屬材料；該第二半導體部分包含：一第二氧化物膜，其經設置以覆蓋該第二金屬膜之 一側部分；及該介面障壁膜係由該預定金屬材料之氧化物膜組態。 The semiconductor device of claim 24, wherein the first semiconductor portion comprises: a first oxide film disposed to cover a side portion of the first metal film, and a seed layer disposed on the first Between the oxide film and the first metal film and comprising a predetermined metal material; the second semiconductor portion comprising: a second oxide film disposed to cover the second metal film a side portion; and the interface barrier film is configured by an oxide film of the predetermined metal material. 如請求項27之半導體裝置，其中該預定金屬材料係Mn、Mg、Ti及Al之一者。 The semiconductor device of claim 27, wherein the predetermined metal material is one of Mn, Mg, Ti, and Al. 如請求項24之半導體裝置，其中該第二半導體部分包含：一障壁金屬層，其具有：一障壁本體部分，其經設置以覆蓋該第二金屬膜之一側部分及該第二金屬膜在與該連結介面相對之側上之一表面，及一介面層部分，其經形成以沿該連結介面自該障壁本體部分在該連結介面側上之一端部分延伸；及該介面障壁部分係由該障壁金屬層之該介面層部分組態。 The semiconductor device of claim 24, wherein the second semiconductor portion comprises: a barrier metal layer having: a barrier body portion disposed to cover a side portion of the second metal film and the second metal film a surface on a side opposite to the connection interface, and an interface layer portion formed to extend from the connection interface from the end portion of the barrier body portion on the side of the connection interface; and the interface barrier portion is Partial configuration of the interface layer of the barrier metal layer. 如請求項29之半導體裝置，其中該障壁金屬層由Ti、Ta、Ru、TiN、TaN及RuN之一者形成。 The semiconductor device of claim 29, wherein the barrier metal layer is formed of one of Ti, Ta, Ru, TiN, TaN, and RuN. 如請求項23之半導體裝置，其中在該第一導體部分在該連結介面側上之該面區域之一部分處設置一凹陷部分，在該部分中該第一金屬膜未連結至該第二金屬膜；及該介面障壁部分係由以下各者組態：該第一金屬膜之該凹陷部分，及該連結介面側上與該凹陷部分相對之該第二半導體部分之一面區域部分，且該介面障壁部分具有藉由該介面障壁部分中之該凹陷 部分及該面區域部分界定之一密封氣隙。 The semiconductor device of claim 23, wherein a recessed portion is provided at a portion of the first conductor portion on the side of the bonding interface side, wherein the first metal film is not bonded to the second metal film And the interface barrier portion is configured by: the recessed portion of the first metal film, and a portion of the second semiconductor portion opposite to the recessed portion on the side of the joint interface, and the interface barrier Part having the depression in the barrier portion of the interface The portion and the surface region portion define a sealed air gap. 如請求項31之半導體裝置，其中該第二半導體部分具有：一絕緣膜，其經設置以覆蓋該第二金屬膜之一側部分；且該連結介面側上與該凹陷部分相對之該第二半導體部分之一面區域部分係由該絕緣膜組態。 The semiconductor device of claim 31, wherein the second semiconductor portion has: an insulating film disposed to cover a side portion of the second metal film; and the second side of the bonding interface side opposite to the recess portion One of the surface portions of the semiconductor portion is configured by the insulating film. 如請求項31之半導體裝置，其中該第二半導體部分具有：一介面障壁膜，其設置於該第一金屬膜在該連結介面側上之該面區域之一部分處，該部分包含其中該第一金屬膜未連結至該第二金屬膜之一面區域；且該連結介面側上與該凹陷部分相對之該第二半導體部分之該面區域部分係由該介面障壁膜組態。 The semiconductor device of claim 31, wherein the second semiconductor portion has: an interface barrier film disposed at a portion of the first metal film on the side of the bonding interface, the portion including the first portion The metal film is not bonded to a surface area of the second metal film; and the surface area of the second semiconductor portion opposite to the recessed portion on the side of the connection interface is configured by the interface barrier film. 如請求項23之半導體裝置，其中該第一金屬膜及該第二金屬膜之各者係Cu膜。 The semiconductor device of claim 23, wherein each of the first metal film and the second metal film is a Cu film. 一種電子設備，其包括：一半導體裝置，其包含：一第一半導體部分，其在一接合介面側上具有形成於其表面上之一第一金屬膜；一第二半導體部分，其在該接合介面上具有連結至該第一金屬膜之一第二金屬膜且在該連結介面側上具有小於該連結介面側上之該第一金屬膜之一表面積之一表面積，且設置成其中在該連結介面上該第二半導體部分 接合至該第一半導體部分之一狀態；及一介面障壁部分，其設置於該連結介面側上之該第一金屬膜之一面區域之一部分中，該部分包含其中該第一金屬膜未連結至該第二金屬膜之一面區域；及一信號處理電路，其經組態以處理該半導體裝置之一輸出信號。 An electronic device comprising: a semiconductor device comprising: a first semiconductor portion having a first metal film formed on a surface thereof on a bonding interface side; and a second semiconductor portion at the bonding The interface has a second metal film coupled to the first metal film and has a surface area on a side of the bonding interface that is smaller than a surface area of the first metal film on the side of the bonding interface, and is disposed therein. The second semiconductor portion Bonding to a state of one of the first semiconductor portions; and a dielectric barrier portion disposed in a portion of the first metal film on a side of the bonding interface, the portion including the first metal film not being bonded to a surface area of the second metal film; and a signal processing circuit configured to process an output signal of the semiconductor device. 一種用於一半導體裝置之製造方法，其包括：製造一第一半導體部分，該第一半導體部分在一接合介面側上具有形成於其之一表面上之一第一金屬膜；製造一第二半導體部分，該第二半導體部分具有一第二金屬膜，該第二金屬膜在該連結介面側上具有小於該連結介面側上之該第一金屬膜之一表面積之一表面積；及使該第一半導體部分在該第一金屬膜側上之表面與該第二半導體部分在該第二金屬膜側上之表面彼此接合以使該第一金屬膜與該第二金屬膜彼此連結，且在該連結介面側上之該第一金屬膜之該面區域之一部分處設置一介面障壁部分，該部分包含其中該第一金屬膜未連結至該第二金屬膜之面區域。 A manufacturing method for a semiconductor device, comprising: fabricating a first semiconductor portion having a first metal film formed on one surface thereof on a bonding interface side; and manufacturing a second a semiconductor portion, the second semiconductor portion having a second metal film having a surface area on a side of the connection interface that is smaller than a surface area of the first metal film on the side of the connection interface; a surface of the semiconductor portion on the first metal film side and a surface of the second semiconductor portion on the second metal film side are bonded to each other to connect the first metal film and the second metal film to each other, and A portion of the surface region of the first metal film on the side of the bonding interface is provided with a dielectric barrier portion including a surface region in which the first metal film is not bonded to the second metal film. 一種半導體裝置，其包括：一半導體基板；一絕緣層，其形成於該半導體基板上；一連結電極，其形成於該絕緣層之一表面上；及一保護層，其形成於該絕緣層之一表面上且包圍該連 結電極，其中該絕緣層內插於該保護層與該連結電極之間。 A semiconductor device comprising: a semiconductor substrate; an insulating layer formed on the semiconductor substrate; a bonding electrode formed on a surface of the insulating layer; and a protective layer formed on the insulating layer On the surface and surrounding the company a junction electrode, wherein the insulating layer is interposed between the protective layer and the connection electrode. 如請求項37之半導體裝置，其中曝露於上面形成該連結電極之表面之該保護層經組態含有選自Ta、Ti、Ru、TaN及TiN之至少一者。 The semiconductor device of claim 37, wherein the protective layer exposed to the surface on which the bonding electrode is formed is configured to contain at least one selected from the group consisting of Ta, Ti, Ru, TaN, and TiN. 如請求項37之半導體裝置，其中該保護層由以下各者組態：一覆蓋層，其含有選自Ta、Ti、Ru、TaN及TiN之至少一者且經組態以覆蓋該絕緣層之一凹陷部分之一內面；及一導體層，其形成於該覆蓋層上且由組態該連結電極之一材料製成。 The semiconductor device of claim 37, wherein the protective layer is configured by: a cap layer comprising at least one selected from the group consisting of Ta, Ti, Ru, TaN, and TiN and configured to cover the insulating layer An inner surface of one of the recessed portions; and a conductor layer formed on the cover layer and made of a material configuring one of the connection electrodes. 如請求項37之半導體裝置，其中該保護層包圍該一連結電極或複數個此連結電極之一周邊。 The semiconductor device of claim 37, wherein the protective layer surrounds a connection electrode or a periphery of one of the plurality of connection electrodes. 如請求項37之半導體裝置，其中該連結電極及上面形成該保護層之該絕緣層由SiN製成。 The semiconductor device of claim 37, wherein the connecting electrode and the insulating layer on which the protective layer is formed are made of SiN. 一種用於一半導體裝置之製造方法，其包括：在一半導體基板上形成一絕緣層；在該絕緣層之一表面上形成一連結電極；及在該絕緣層之該表面之一位置處形成一保護層，在該位置處該保護層包圍該連結電極，其中該絕緣層內插於該保護層與該連結電極之間。 A manufacturing method for a semiconductor device, comprising: forming an insulating layer on a semiconductor substrate; forming a bonding electrode on a surface of the insulating layer; and forming a portion at a position of the surface of the insulating layer a protective layer at which the protective layer surrounds the connecting electrode, wherein the insulating layer is interposed between the protective layer and the connecting electrode. 一種電子設備，其包括：一半導體裝置，其包含： 一半導體基板，一絕緣層，其形成於該半導體基板上，一連結電極，其形成於該絕緣層之一表面上，及一保護層，其形成於該絕緣層之一表面上且包圍該連結電極，其中該絕緣層內插於該保護層與該連結電極之間；及一信號處理電路，其用於處理該半導體裝置之一輸出信號。 An electronic device comprising: a semiconductor device comprising: a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a connecting electrode formed on a surface of the insulating layer, and a protective layer formed on a surface of the insulating layer and surrounding the connecting layer An electrode, wherein the insulating layer is interposed between the protective layer and the connecting electrode; and a signal processing circuit for processing an output signal of the semiconductor device.
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