TW201301562A - 具有再分配用於覆晶安裝的垂直接觸件的發光二極體 - Google Patents

具有再分配用於覆晶安裝的垂直接觸件的發光二極體 Download PDF

Info

Publication number
TW201301562A
TW201301562A TW101108520A TW101108520A TW201301562A TW 201301562 A TW201301562 A TW 201301562A TW 101108520 A TW101108520 A TW 101108520A TW 101108520 A TW101108520 A TW 101108520A TW 201301562 A TW201301562 A TW 201301562A
Authority
TW
Taiwan
Prior art keywords
layer
conductive layer
metal
led
dielectric
Prior art date
Application number
TW101108520A
Other languages
English (en)
Inventor
Ji-Pu Lei
Kwong-Hin Henry Choy
ya-jun Wei
Stefano Schiaffino
Daniel Alexander Steigerwald
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Publication of TW201301562A publication Critical patent/TW201301562A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0093Wafer bonding; Removal of the growth substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0095Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/06102Disposition the bonding areas being at different heights
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008Processes
    • H01L2933/0016Processes relating to electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008Processes
    • H01L2933/0033Processes relating to semiconductor body packages
    • H01L2933/0066Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Devices (AREA)
  • Led Device Packages (AREA)

Abstract

本發明揭示一種發光二極體(LED)結構,其具有半導體層,該等半導體層包含一p型層、一作用層及一n型層。該p型層具有一底面,且該n型層具有一頂面,光發射通過該頂面。一銅層具有一第一部分,該第一部分電連接至該p型層之該底面且與該p型層之該底面相對。一介電壁延伸通過該銅層以隔離該銅層之一第二部分與該第一部分。一金屬分流器將該銅層之該第二部分電連接至該n型層之該頂面。P金屬電極電連接至該第一部分,且n金屬電極電連接至該第二部分,其中該LED結構形成一覆晶。亦描述方法及結構之其他實施例。

Description

具有再分配用於覆晶安裝的垂直接觸件的發光二極體
本發明係關於發光二極體(LED),且更特定言之關於一種用於形成LED作為覆晶之技術,一底面上之兩個電極直接接合至基台(submount)電極。
在許多應用中想要覆晶LED,此係因為其等不使用打線接合。兩個電極定位於LED之一底面上以直接接合至一基台上之金屬墊。接合可藉由超音波接合、焊料、導電黏附劑或其他手段而完成。光從與電極相對的LED之表面離開。
在一典型LED覆晶中,磊晶p型層係底層且接觸底部陽極電極。p型層及作用層之一部分必須蝕除以暴露磊晶n型層的下側以接觸底部陰極電極。此蝕刻產生穿過p型層暴露n型層之底面之分配的通孔。通孔開口接著被絕緣,且金屬沈積在開口中以接觸n型層。
此拓撲通常藉由在具有活性離子物種之一電漿環境中乾式蝕刻半導體材料而達成。使此結構存在於一薄膜裝置中需要精確控制電漿蝕刻。此外,待與接觸金屬介接之乾式蝕刻磊晶表面對由電漿中之高能離子物種之碰撞致使的損壞敏感。自熱觀點及機械觀點觀之,此一步階結構之角隅易於因夾置膜內之應力分配而變為故障起始中心。台面或通孔結構上方之膜生長通常需要一最小步階覆蓋,從而導致較高設備成本且需要更密集的線內程序控制。
據此,將想要避免此通孔蝕刻而形成覆晶LED。
在本發明之一實施例中,一LED具有形成在一藍寶石生長基板上之一n型層,繼之生長一作用層及一p型層。各層可係複數個層。許多LED生長在相同基板晶圓上且隨後將被單切。本文描述的程序係一晶圓級程序。下文發明內容描述一實施例。亦預想實施本發明之其他方式。
一銅晶種層經形成上覆於p型層之頂面。
一第一介電壁形成在將有鋸線之在晶圓中之各LED周圍。同時,沿著各LED之一邊緣形成一內介電壁。壁之間的區域將最終填充有銅以對各LED之n型層提供底部陰極電極與一頂部接觸件之間的一電連接。
晶種層鍍有一第一銅層,該第一銅層覆蓋p型層及介電壁之間的區域。
接著,一介電層部分形成在自內介電壁延伸之銅層之底面上。此介電層部分將最終支撐電連接至n型層之金凸塊。
接著,藍寶石基板被移除且暴露的n型層被薄化。
接著,在介電壁上方及周圍蝕刻n型層以暴露介電壁之間的第一銅層,該第一銅層作為一優異蝕刻停止層。接著,可藉由濕式蝕刻而移除銅層以電隔離p接觸件。n型層之蝕刻亦分開晶圓上之多種LED之n型層,從而跨晶圓形成隔離的LED裝置單元。
接著,一介電層將經圖案化以保護側壁且完全覆蓋各 LED單元之暴露的p接觸件金屬。
一合適的n接觸件金屬(例如,TiN)及黏附層及銅晶種層形成在晶圓之頂面上以覆蓋暴露的n型層、介電部分及介電壁之間的銅,且一光阻劑形成在n型層之中央發光區域上但是不在其邊緣及介電部分上。接著,暴露的晶種層(在各LED區域周邊形成一環)用一第二銅層電鍍,以形成一n接觸件,因此隔離在介電壁之間的在底面上之第一銅層之部分接觸接觸n層之頂部邊緣之第二銅層。
暴露的n型層經粗糙化以增大光提取,且一層磷光體沈積在n型層上。
因此,底部第一銅層分成接觸p型層之區段及接觸n型層之區段。接著,金凸塊形成在n銅區段及p銅區段上以接合至基台電極。
接著,沿著環繞各LED區域之外介電壁對晶圓刻劃並斷裂或鋸切。
據此,相比於先前技術之LED覆晶(其中n金屬電極接觸藉由蝕刻一通孔穿過p型層而暴露的n型層下側),本發明中之n金屬電極接觸n型層(如一垂直LED)之頂面。
可藉由每個LED僅形成一介電壁以致使第二銅層接觸一LED之n型層以形成至接觸一相鄰LED之p型層之第一銅層之一電連接而串聯連接多個LED。
亦描述用於藉由電接觸n型層之頂面而非透過p型層中之一蝕刻開口接觸n型層而形成覆晶之其他製造技術。取決於用以生長LED層之技術,層之導電類型可相反。
亦描述方法及結構之其他實施例。
在多個圖中用相同數字標記的元件可相同或等效。
圖通常係展示一LED之右邊緣及一相鄰LED之左邊緣之形成之一LED晶圓之一部分之橫截面。圖20至圖22圖解說明晶圓之一更大部分。圖僅圖解說明本發明之一實施例且可刪除特定步驟。
圖1圖解說明磊晶生長在一藍寶石基板12上方之習知LED半導體GaN層10且以層生長次序表示一成核層、應力釋放層、n層、作用層(發射光),繼之p層及用以形成LED之任何其他半導體層。為了簡便,複數個GaN層將在後文中稱為一單個半導體GaN層10。與藍寶石基板12接觸的層10之頂部係LED之n表面。層10之底面(與頂面相對)係LED之p表面。電流在LED之n表面與p表面之間流動以操作LED。取決於所要峰值波長,LED可係AlInGaN LED。替代地,LED無需基於GaN且可係使用任何類型的生長基板之任何其他類型的LED。本發明適用於形成任何LED作為一覆晶。
圖2圖解說明沈積在GaN層10之p表面上方之一金屬p接觸件14。p接觸件14較佳係反射性的,諸如金或其他高導電反射層。p接觸件14與下伏p層形成一歐姆接觸。接著,使用習知微影技術來圖案化p接觸件14以暴露相鄰LED區域之間的GaN層10。
圖3圖解說明沈積在p接觸件14上方以緩和自p接觸件14 之Au電子遷移之一金屬防護片層18。此等防護片材料係熟知的。在一實施例中,防護片層18含有鎳且可由複數個層形成。防護片層18之圖案可藉由沈積及蝕刻或藉由一電鍍程序而形成。
圖4圖解說明使用數種熟知技術(諸如CVD、濺鍍等)之任何者而沈積在整個晶圓上方之一銅晶種層20。晶種層20接觸且覆蓋由金屬p接觸件14覆蓋的區域之間的GaN層10之p表面之區域。
圖5圖解說明形成在暴露的GaN層10上方之介電壁21/22。至少沿著晶圓上之各LED區域之一側形成內壁21,其中一銅互連將與GaN層10中之n層之頂面接觸。外壁22經形成以沿著鋸線環繞各LED區域。介電壁21/22可沈積為氧化物、光阻劑或任何其他類型的有機介電質,且以一習知方式圖案化。介電壁21/22之高度稍微高於下文描述的一銅板層之一希望高度。介電壁21/22之間的區域將最終填充有銅以對GaN層10之頂部n表面提供一導電路徑。
圖6圖解說明鍍有銅24並至小於介電壁21/22之厚度之一厚度之晶種層20。可使用多種熟知電鍍技術。銅24有利於p接觸件14上方之熱擴散及電流擴散。可使用其他金屬及沈積技術。
圖7圖解說明經圖案化以在銅24上方對n金屬電極提供一絕緣墊之一第二介電層26。介電層26可係用以形成介電壁21/22之相同材料。介電層26可僅沿著正方形LED區域之一邊緣延伸。在另一實施例中,取決於預期的LED電流及其 他因素,用於支撐n金屬電極之介電層26差不多形成在底面上方。
圖8圖解說明藍寶石基板12已被移除且GaN層10被薄化。可藉由雷射提升、機械拋光、蝕刻或任何其他合適技術而移除基板12。相似地,可藉由機械拋光、蝕刻或任何其他合適技術而薄化GaN層10。
圖9圖解說明使用習知技術在介電壁21/22上方蝕除GaN層10。此隔離各LED之GaN層10。晶種層20及任何障壁層保持在開口中且需要被蝕刻。
圖10圖解說明使用習知技術蝕除暴露的晶種層20及任何障壁層,使得介電壁21/22使介電壁21/22之間的銅24與經由防護片層18電接觸p接觸件14之銅24絕緣。銅40係現在隔離在介電壁21/22之間的銅24之部分。
圖11圖解說明在電接觸p接觸件14之暴露的銅24部分上方沈積且圖案化的SiNx 30之一介電層。SiNx 30在將形成一銅n金屬之所有區域上方延伸。對於一正方形LED,對於均勻電流擴散較佳的是n金屬在LED晶片之整個周邊周圍延伸。據此,SiNx 30將在LED區域之周邊周圍形成一窄的正方形。在其他實施例中,n金屬可係用於電流擴散之其他圖案。
圖12圖解說明形成在GaN層10之n表面、SiNx 30、介電壁21/22及暴露的銅24上方之一銅晶種層32(包含任何合適金屬障壁層)。
圖13圖解說明經圖案化以覆蓋將不電鍍銅之所有區域 (其等為將不是n金屬之部分之所有區域)之一光阻劑層34。
圖14圖解說明鍍有一層銅38使得該銅38在左側LED之GaN層10之n表面與介電壁21/22之間的銅40之間形成一連接。一正方形銅環形成在晶圓中之各LED周圍,其中該環沿著其右側電連接至介電壁21/22之間的銅40。繼電鍍之後,光阻劑34剝落,且GaN層10上方之暴露的晶種層32經回蝕以允許光通過。
圖15圖解說明藉由光電化學(PEC)蝕刻而粗糙化以改良光提取之GaN層10表面42之n表面之暴露部分及諸如藉由電泳或任何其他沈積技術而沈積在晶圓上方之一磷光體44。
圖16圖解說明形成在晶圓之底部p表面上方包含在介電材料上方之一金屬障壁層/晶種層48。
圖17圖解說明在晶種層48上圖案化以界定一金凸塊電極圖案之一層光阻劑50。光阻劑50覆蓋介電層26之邊緣以防止一後續鍍銅使p電極及n電極短路且覆蓋最右邊的介電壁22以防止沿著一鋸線/單切線定位鍍銅。
圖18圖解說明鍍有金(或多層多種金屬)以形成一金凸塊陣列54以連接至一基台之金屬墊之暴露的晶種層48。
圖19圖解說明光阻劑50剝落及介電層26之左邊緣附近的晶種層48經蝕除以使形成n電極之在介電層26上方之金凸塊54與形成p電極之金凸塊54電絕緣。最右邊介電壁22上方之晶種層48(其外接各LED區域)亦經蝕刻以避免任何金屬沿著一鋸線(避免金屬撕裂及雜散金屬邊緣)。
圖20圖解說明展示通過環繞各LED之介電壁22之切割線/鋸線58之LED晶圓之一更大部分。圖20亦展示p接觸件/電極區域60及n接觸件/電極區域62。n接觸件/電極區域62可僅沿著LED之一側延伸,此係因為外接GaN層10之銅具有一非常高的導電性。
圖21係展示在GaN層10之n表面之周邊周圍形成一環、電接觸一LED之n型GaN層10之銅38的兩個LED之晶圓之一部分之一簡化的自上而下圖。沿著LED之至少一側之互連銅40(在銅38下方)將「頂部」銅38電連接至底面上之n接觸件/電極金凸塊54。可存在形成在一單個晶圓上之數千個相同LED,其中各LED可係1 mm2等級。
圖22圖解說明圖20之結構之一變動,其中圖5至圖20中之右介電壁22未形成,因此在一LED之頂部銅38(其連接至該LED之n型GaN層10)與一相鄰LED之底部銅24(其連接至該相鄰LED之p型GaN層10)之間存在用以串聯連接LED之一導電路徑。由虛線66展示電子流動。可串聯連接任何數目個LED。接著,串聯連接的LED被單切為一單個群組。該群組可視需要被相似於圖20中之壁22之一介電壁環繞,其中介電壁界定上方未形成金屬以避免鋸穿金屬之一鋸線。
圖23圖解說明一晶圓中之覆晶LED之一不同實施例。在一晶圓中展示一LED及一相鄰LED之一部分。多個程序步驟相同於先前描述的程序步驟,且不重複此等細節。GaN n型層70、GaN作用層72及GaN p型層74磊晶生長在一藍寶 石基板(未展示)上。該基板已被移除。一反射性、金屬p接觸件76(例如,金)形成在p型層74上,且一金屬防護層78形成在p接觸件76上方。接著,晶圓經蝕刻以在LED區域中形成溝渠80用於隔離LED。
一介電層82(諸如氮化矽)沈積在晶圓表面上方且經圖案化以暴露導電防護層78之部分。一銅晶種層86形成在介電層82及暴露的防護層78上方。
接著,為了繼隨後沈積一銅層之後隔離p型層與n型層而形成介電壁88。假定LED係正方形,則與各LED相關聯的壁88形成為一正方形。
晶種層86鍍有銅90並至稍小於介電壁88之高度之一厚度。銅90之底面具有形成在其上方之一金屬障壁層(未展示)。金接觸件/電極墊94及96或金屬凸塊分別沈積在p覆晶接觸件及n覆晶接觸件之障壁層上。墊94及96可直接接合至一基台之墊。
圖24圖解說明繼介電層82經蝕刻以暴露環繞n型層70之銅90之後以及一鋁層98經沈積及圖案化以將n型層70連接至銅90之後圖23之結構。經圖案化鋁層98充當一分流器以在n電極墊96與n型層70之間引導電流。因此,底部銅90提供至p型層74及n型層70之一覆晶連接而無任何通孔形成在p型層74中以獲得對n型層70下側之接達。因此,避免與在p型層74中形成通孔相關聯的問題。
圖25圖解說明一層磷光體100形成在LED之發光表面上方之圖24之結構。
圖26至圖28相同於圖23至圖25,惟介電壁102不完全隔離各LED之n型層與p型層但是僅隔離相鄰LED之p型層74除外。鋁層98及銅90在一LED之n型層70與相鄰LED之p型層74之間形成一串聯路徑。經圖案化鋁層98可沿著相鄰於下一串聯LED之LED之任何側形成一條帶。可以此方式串聯連接一晶圓中之任何數目個覆晶LED。接著,串聯LED單切為一群組。串聯LED可呈任何配置,諸如一正方形群組或一條帶。
據此,已描述形成覆晶LED而無需形成穿過p型層之通孔以獲得對n型層下側之接達之多種技術。在多種實施例中對n型層之接達係經由n型層之頂面藉由電連接至n型層之底部電極之一金屬分流器。
已詳細描述本發明,熟習此項技術者將明白在本揭示內容之情況下,可在不背離本文描述的本發明概念之精神之情況下作出修改。因此,不希望本發明之範疇限於闡釋及描述的特定實施例。
10‧‧‧發光二極體(LED)半導體GaN層
12‧‧‧藍寶石基板
14‧‧‧金屬p接觸件
18‧‧‧金屬防護片層
20‧‧‧銅晶種層
21‧‧‧介電壁
22‧‧‧介電壁
24‧‧‧銅
26‧‧‧第二介電層
30‧‧‧SiNx
32‧‧‧銅晶種層
34‧‧‧光阻劑層
38‧‧‧銅
40‧‧‧銅
42‧‧‧GaN層10表面
44‧‧‧磷光體
48‧‧‧金屬障壁層/晶種層
50‧‧‧光阻劑
54‧‧‧n接觸件/電極金凸塊
58‧‧‧切割線/鋸線
60‧‧‧p接觸件/電極區域
62‧‧‧n接觸件/電極區域
66‧‧‧電子流動
70‧‧‧GaN n型層
72‧‧‧GaN作用層
74‧‧‧GaNp型層
76‧‧‧金屬p接觸件
78‧‧‧金屬防護層
80‧‧‧溝渠
82‧‧‧介電層
86‧‧‧銅晶種層
88‧‧‧介電壁
90‧‧‧銅
94‧‧‧金接觸件/電極墊
96‧‧‧金接觸件/電極墊
98‧‧‧鋁層
100‧‧‧磷光體
102‧‧‧介電壁
圖1至圖19係根據本發明之一實施例之經歷用以形成覆晶LED之一程序之相同LED晶圓部分之橫截面圖,其中該等圖圖解說明一LED之右邊緣及一相鄰LED之左邊緣。
圖20圖解說明晶圓之一更大部分。
圖21係展示兩個LED之晶圓之一部分之一簡化的自上而下圖。
圖22圖解說明圖20之結構之一變動,其中在一LED之陰 極與一相鄰LED之陽極之間存在用以串聯連接LED之一導電路徑。
圖23至圖25係在多個製造階段一晶圓中之覆晶LED之另一實施例之橫截面圖。
圖26至圖28相似於圖23至圖25但是使用一介電圖案變動以串聯連接相鄰LED。
10‧‧‧發光二極體(LED)半導體GaN層
22‧‧‧介電壁
38‧‧‧銅
40‧‧‧銅
54‧‧‧n接觸件/電極金凸塊
58‧‧‧切割線/鋸線
60‧‧‧p接觸件/電極區域
62‧‧‧n接觸件/電極區域

Claims (20)

  1. 一種發光二極體(LED)結構,其包括:半導體層,其等包含一第一導電層、一作用層及一第二導電層,該第一導電層具有一底面,且該第二導電層具有一頂面,光發射通過該頂面;一第一金屬層,其具有一第一部分,該第一部分電連接至該第一導電層之該底面且與該第一導電層之該底面相對;一第一介電部分,其延伸通過該第一金屬層以隔離該第一金屬層之一第二部分與該第一部分;一金屬分流器,其將該第一金屬層之該第二部分電連接至該第二導電層之該頂面;一或多個第一電極,其電連接至該第一金屬層之該第一部分;及一或多個第二電極,其電連接至該第一金屬層之該第二部分使得該LED結構形成一覆晶。
  2. 如請求項1之結構,其進一步包括一第二介電部分,該第二介電部分隔離該金屬分流器與該第二導電層之該頂面。
  3. 如請求項2之結構,其進一步包括:一第三介電部分,其沿著該第一金屬層之該第一部分之一區段延伸;及該等第二電極之該一或多者,其形成在該第三介電部分上方且與該第一金屬層之該第二部分電接觸。
  4. 如請求項1之結構,其中已自該第一介電部分及該第一金屬之該第二部分上方移除該第一導電層、該作用層及該第二導電層。
  5. 如請求項1之結構,其中已自至少該第一金屬之該第二部分上方移除該第一導電層、該作用層及該第二導電層。
  6. 如請求項1之結構,其中該第一金屬層係一第一鍍銅層。
  7. 如請求項6之結構,其中該金屬分流器係一第二鍍銅層。
  8. 如請求項1之結構,其進一步包括一第二介電部分,該第二介電部分沿著該第二導電層之至少一邊緣形成且隔離該金屬分流器與該第二導電層之該頂面。
  9. 如請求項8之結構,其中該金屬分流器上覆於該第二介電部分且電接觸該第二導電層之該頂面,其中該金屬分流器形成在該第二導電層之該頂面之一周邊周圍。
  10. 如請求項1之結構,其中該第一導電層係一p型層且該第二導電層係一n型層。
  11. 如請求項10之結構,其中該LED結構係一基於GaN之LED結構。
  12. 一種形成一覆晶LED結構之方法,其包括:提供一生長基板;在該生長基板上磊晶生長半導體層,該等半導體層包含一第一導電層、一作用層及一第二導電層,該第一導 電層具有一底面,且該第二導電層具有一頂面,光發射通過該頂面;形成一第一介電部分,該第一介電部分與該第一導電層之該底面相對;在該第一導電層之該底面上沈積一第一金屬層,該第一金屬層被封鎖而不沈積在定位該第一介電部分之該第一導電層之該底面上;移除該生長基板;至少蝕除該第一導電層、該作用層及上覆於該第一介電部分之該第二導電層,使得該第一介電部分電隔離該第一金屬層之一第一部分與該第一金屬層之一第二部分,其中該第一金屬層之該第一部分與該第一導電層相對且與該第一導電層電接觸;形成一金屬分流器,該金屬分流器將該第一金屬層之該第二部分連接至該第二導電層之該頂面;形成一或多個第一電極,該一或多個第一電極電連接至該第一金屬層之該第一部分;及形成一或多個第二電極,該一或多個第二電極電連接至該第一金屬層之該第二部分使得該LED結構形成一覆晶。
  13. 如請求項12之方法,其中該生長基板係一晶圓,其支撐複數個LED結構,該方法進一步包括:沿著界定使該複數個LED結構彼此分開之單切線之區域形成一第二介電部分,該第一介電部分及該第二介電 部分形成在其等之間具有該第一金屬層之該第二部分之相對壁。
  14. 如請求項12之方法,其中在該生長基板上形成複數個LED結構,該金屬分流器接觸與一相鄰LED結構之該第一金屬層之該第一部分電連接之一LED結構之該第二導電層之該頂面使得該LED結構及該相鄰LED結構串聯地電連接。
  15. 如請求項12之方法,其進一步包括形成一第二介電部分,該第二介電部分自該第一介電部分延伸至至少該第二導電層之該頂面,該第二介電部分隔離該金屬分流器與該第二導電層之該頂面。
  16. 如請求項15之方法,其進一步包括:形成一第三介電部分,該第三介電部分沿著該第一金屬層之該第一部分之一區段延伸;及在該第三介電部分上方形成該等第二電極之該一或多者且使之與該第一金屬層之該第二部分電接觸。
  17. 如請求項12之方法,其中沈積該第一金屬層包括電鍍一銅層。
  18. 如請求項12之方法,其進一步包括:形成一第二介電部分,該第二介電部分自該第一介電部分延伸至至少該第二導電層之該頂面,該第二介電部分隔離該金屬分流器與該第二導電層之該頂面;且其中形成該金屬分流器包括在該第二介電部分上方及該第二導電層之該頂面之一周邊周圍形成該金屬分流 器。
  19. 如請求項12之方法,其中該第一導電層係一p型層且該第二導電層係一n型層。
  20. 如請求項12之方法,其中該LED結構係一基於GaN之LED結構。
TW101108520A 2011-03-14 2012-03-13 具有再分配用於覆晶安裝的垂直接觸件的發光二極體 TW201301562A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201161452181P 2011-03-14 2011-03-14

Publications (1)

Publication Number Publication Date
TW201301562A true TW201301562A (zh) 2013-01-01

Family

ID=45937460

Family Applications (3)

Application Number Title Priority Date Filing Date
TW101108520A TW201301562A (zh) 2011-03-14 2012-03-13 具有再分配用於覆晶安裝的垂直接觸件的發光二極體
TW106136319A TWI683457B (zh) 2011-03-14 2012-03-13 發光二極體(led)結構及形成覆晶led結構之方法
TW105114215A TWI612696B (zh) 2011-03-14 2012-03-13 發光二極體(led)結構及形成覆晶led結構之方法

Family Applications After (2)

Application Number Title Priority Date Filing Date
TW106136319A TWI683457B (zh) 2011-03-14 2012-03-13 發光二極體(led)結構及形成覆晶led結構之方法
TW105114215A TWI612696B (zh) 2011-03-14 2012-03-13 發光二極體(led)結構及形成覆晶led結構之方法

Country Status (7)

Country Link
US (3) US9246061B2 (zh)
EP (1) EP2686892B1 (zh)
JP (1) JP5932851B2 (zh)
KR (1) KR101933001B1 (zh)
CN (2) CN106058028B (zh)
TW (3) TW201301562A (zh)
WO (1) WO2012123840A1 (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102013103079A1 (de) * 2013-03-26 2014-10-02 Osram Opto Semiconductors Gmbh Optoelektronischer Halbleiterchip und Verfahren zur Herstellung eines optoelektronischen Halbleiterchips
TWI548124B (zh) * 2013-05-27 2016-09-01 崴發控股有限公司 覆晶式發光二極體元件及其封裝結構
DE102013107531A1 (de) * 2013-07-16 2015-01-22 Osram Opto Semiconductors Gmbh Optoelektronischer Halbleiterchip
US20160155901A1 (en) * 2013-07-18 2016-06-02 Koninklijke Philips N.V. Highly reflective flip chip led die
WO2015074880A1 (en) * 2013-11-19 2015-05-28 Koninklijke Philips N.V. A solid state light emitting device and method of manufacturing a solid state light emitting device
WO2015165048A1 (zh) * 2014-04-29 2015-11-05 陈振贤 一种结合led外延结构与led封装基板为一体的垂直式led阵列元件
US9343633B1 (en) 2014-10-31 2016-05-17 Mikro Mesa Technology Co., Ltd. Light-emitting diode lighting device
US9601659B2 (en) * 2015-01-06 2017-03-21 Apple Inc. LED structures for reduced non-radiative sidewall recombination
US9484492B2 (en) * 2015-01-06 2016-11-01 Apple Inc. LED structures for reduced non-radiative sidewall recombination
US9865772B2 (en) * 2015-01-06 2018-01-09 Apple Inc. LED structures for reduced non-radiative sidewall recombination
US10270008B2 (en) 2015-03-16 2019-04-23 Seoul Viosys Co., Ltd. Light emitting element including metal bulk
DE102015114587A1 (de) * 2015-09-01 2017-03-02 Osram Opto Semiconductors Gmbh Optoelektronisches Halbleiterbauelement und Verfahren zu dessen Herstellung
US10898725B2 (en) 2018-11-26 2021-01-26 International Business Machines Corporation Integrated optogenetic device with light-emitting diodes and glass-like carbon electrodes
CN113594321B (zh) * 2021-04-05 2023-12-01 常州纵慧芯光半导体科技有限公司 一种半导体光源及其驱动电路

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6791119B2 (en) * 2001-02-01 2004-09-14 Cree, Inc. Light emitting diodes including modifications for light extraction
TW492202B (en) 2001-06-05 2002-06-21 South Epitaxy Corp Structure of III-V light emitting diode (LED) arranged in flip chip configuration having structure for preventing electrostatic discharge
WO2004010509A2 (en) * 2002-07-22 2004-01-29 Cree, Inc. Light emitting diode including barrier layers and manufacturing methods therefor
US6995032B2 (en) * 2002-07-19 2006-02-07 Cree, Inc. Trench cut light emitting diodes and methods of fabricating same
TW577184B (en) 2002-12-26 2004-02-21 Epistar Corp Light emitting layer having voltage/resistance interdependent layer
US7592207B2 (en) * 2003-11-14 2009-09-22 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device and method for manufacturing the same
TWI347022B (en) * 2004-02-20 2011-08-11 Osram Opto Semiconductors Gmbh Optoelectronic component, device with several optoelectronic components and method to produce an optoelectronic component
JP4116587B2 (ja) * 2004-04-13 2008-07-09 浜松ホトニクス株式会社 半導体発光素子及びその製造方法
US20050274970A1 (en) * 2004-06-14 2005-12-15 Lumileds Lighting U.S., Llc Light emitting device with transparent substrate having backside vias
TWI244748B (en) 2004-10-08 2005-12-01 Epistar Corp A light-emitting device with a protecting structure
CN1909238B (zh) * 2005-08-03 2010-11-03 三星电机株式会社 具有保护元件的发光装置及该发光装置的制造方法
EP1750309A3 (en) 2005-08-03 2009-07-29 Samsung Electro-mechanics Co., Ltd Light emitting device having protection element
US7994514B2 (en) 2006-04-21 2011-08-09 Koninklijke Philips Electronics N.V. Semiconductor light emitting device with integrated electronic components
JP2008135694A (ja) * 2006-10-31 2008-06-12 Hitachi Cable Ltd Ledモジュール
US9159888B2 (en) * 2007-01-22 2015-10-13 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US7759670B2 (en) * 2007-06-12 2010-07-20 SemiLEDs Optoelectronics Co., Ltd. Vertical LED with current guiding structure
US8536584B2 (en) * 2007-11-14 2013-09-17 Cree, Inc. High voltage wire bond free LEDS
US8878219B2 (en) * 2008-01-11 2014-11-04 Cree, Inc. Flip-chip phosphor coating method and devices fabricated utilizing method
JP5123269B2 (ja) * 2008-09-30 2013-01-23 ソウル オプト デバイス カンパニー リミテッド 発光素子及びその製造方法
KR101017395B1 (ko) * 2008-12-24 2011-02-28 서울옵토디바이스주식회사 복수개의 발광셀들을 갖는 발광 소자 및 그것을 제조하는 방법
JP5588882B2 (ja) * 2008-12-28 2014-09-10 有限会社Mtec 発光ダイオードモジュール
TWI414088B (zh) * 2009-12-16 2013-11-01 Epistar Corp 發光元件及其製造方法
KR101106151B1 (ko) * 2009-12-31 2012-01-20 서울옵토디바이스주식회사 발광 소자 및 그것을 제조하는 방법
US8653542B2 (en) * 2011-01-13 2014-02-18 Tsmc Solid State Lighting Ltd. Micro-interconnects for light-emitting diodes

Also Published As

Publication number Publication date
JP2014508426A (ja) 2014-04-03
CN106058028A (zh) 2016-10-26
CN103415935B (zh) 2016-09-14
US9246061B2 (en) 2016-01-26
US20180019370A1 (en) 2018-01-18
EP2686892B1 (en) 2019-10-02
KR20140013029A (ko) 2014-02-04
CN103415935A (zh) 2013-11-27
WO2012123840A1 (en) 2012-09-20
TWI612696B (zh) 2018-01-21
EP2686892A1 (en) 2014-01-22
KR101933001B1 (ko) 2018-12-27
TW201631810A (zh) 2016-09-01
JP5932851B2 (ja) 2016-06-08
TWI683457B (zh) 2020-01-21
TW201826576A (zh) 2018-07-16
US9722137B2 (en) 2017-08-01
US20160126408A1 (en) 2016-05-05
CN106058028B (zh) 2019-03-29
US20130334563A1 (en) 2013-12-19

Similar Documents

Publication Publication Date Title
US9722137B2 (en) LED having vertical contacts redistributed for flip chip mounting
US11563152B2 (en) Light emitting diode package and method of manufacturing the same
CN100416877C (zh) 用于制造垂直结构的发光二极管的方法
US8236584B1 (en) Method of forming a light emitting diode emitter substrate with highly reflective metal bonding
EP2221873B1 (en) Light emitting device
JP6023660B2 (ja) 半導体発光素子及び半導体発光装置
TWI569469B (zh) 用於覆晶發光二極體之p-n分離金屬填充
CN111446343B (zh) 一种半导体发光器件
RU2523777C2 (ru) Продолжение контактных площадок до края кристалла с электрической изоляцией
TWM511125U (zh) 發光二極體晶片及發光裝置
TWI466327B (zh) 晶圓級發光二極體結構之製造方法
KR20110085726A (ko) 반도체 발광소자 및 이를 제조하는 방법
KR102217128B1 (ko) 발광 다이오드 및 그 제조 방법
KR20180098197A (ko) 발광 다이오드 패키지
KR20120073396A (ko) 발광 다이오드 및 그의 제조 방법