TW201301391A - 利用碳電漿浸入以修復低介電常數材料之方法 - Google Patents

利用碳電漿浸入以修復低介電常數材料之方法 Download PDF

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TW201301391A
TW201301391A TW101117617A TW101117617A TW201301391A TW 201301391 A TW201301391 A TW 201301391A TW 101117617 A TW101117617 A TW 101117617A TW 101117617 A TW101117617 A TW 101117617A TW 201301391 A TW201301391 A TW 201301391A
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substrate
conformal oxide
carbon
oxide layer
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Daping Yao
Peter I Porshnev
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Applied Materials Inc
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Abstract

本案提供利用電漿浸入式碳摻雜製程修復低介電常數材料之方法。在某些實施例中，在基板上配置低介電常數材料，且該基板具有一或多個特徵配置成貫穿該低介電常數材料，修復該低介電常數材料的方法可包含在該低介電常數材料上和該一或多個特徵內沉積共形氧化物層；及利用電漿摻雜製程以碳摻雜該共形氧化物層。

Description

利用碳電漿浸入以修復低介電常數材料之方法
本發明之實施例大致關於基板處理法。
半導體製造過程中，諸如化學機械研磨及蝕刻等製程可能造成配置在基板上之低介電常數介電層內的碳損失，而導致該介電層的介電常數或k值升高。
因此，本案發明人提供用以修復低介電常數材料的改善方法。
本案提供利用電漿浸入式碳摻雜製程修復低介電常數材料之方法。在某些實施例中，在基板上配置低介電常數材料，且該基板具有一或多個特徵配置成貫穿該低介電常數材料，修復該低介電常數材料的方法可包含在該低介電常數材料上和該一或多個特徵內沉積共形氧化物層；及利用電漿摻雜製程以碳摻雜該共形氧化物層。
在某些實施例中，提供一種修復配置在基板上之低介電常數材料的方法，其中該基板包含導電層、配置在該導電層上的硬遮罩層及配置在該硬遮罩層上的低介電常數介電層，其中該一或多個特徵係配置成貫穿該低介電常數介電層和該硬遮罩層，藉以暴露出該硬遮罩層之表 面。該方法可包含在該低介電常數材料上及在該一或多個特徵內沉積含有二氧化矽之共形氧化物層；在電漿摻雜腔室中利用碳摻雜該共形氧化物層；去除該一或多個特徵之底表面上的共形氧化物層；及以導電材料填充該一或多個特徵。
在某些實施例中，本案所述之新穎方法可具體實施成電腦可讀媒體。該電腦可讀媒體內儲存有多個指令，當執行該等指令時，可依據本案所述方法中之任一種方法使製程腔室執行冷卻製程腔室部件的方法。
以下內容說明本發明之其他和進一步實施例。
本發明之實施例提供利用碳電漿浸入以修復低介電常數材料的改善方法。本發明之實施例可有利提供改善共形性(conformality)和減小厚度之共形氧化物層。此外，本發明之實施例可使超低介電常數材料能夠用於例如小於2x奈米技術節點中。
第1圖圖示根據本發明某些實施例利用碳電漿浸入以修復低介電常數材料之方法100。根據本發明之某些實施例，第2A圖至第2E圖係基板在第1圖所示方法之不同階段中的示意剖面圖。根據本發明實施例，該方法100可在任何適於進行碳電漿浸入法的設備中執行，例如可在以下參照第3圖所論述的電漿浸入式離子佈植製程腔 室300中執行。
如第2A圖所示，方法100通常始於步驟102，在步驟102中提供基板200。基板200可為任何適當之基板，例如矽基板、III-V族化合物基板、矽鍺(SiGe)基板、磊晶基板、絕緣層上覆矽(SOI)基板、顯示器基板(例如，液晶顯示器(LCD)、電漿顯示器、電致發光(EL)燈顯示器)、發光二極體(LED)基板、太陽能電池陣列、太陽能面板或諸如此類者。在某些實施例中，基板200可為半導體晶圓，例如200 mm、300 mm或諸如此類之矽晶圓。
在某些實施例中，基板200可包含一或多層。基板200包含至少一低介電常數介電層202，且將根據本發明之方法對該至少一低介電常數介電層202進行處理。當用於本案中，「低介電常數(low-k)」意指範圍介於約3.0至約2.0間的介電常數。當用於本案中，「超低介電常數材料(extreme low-k)」係具有低於2.4之介電常數的材料。在某些實施例中，如第2A圖所示般，低介電常數介電層202可形成於硬遮罩204上方。硬遮罩204可形成於導電層206上方。在某些實施例中，該介電層202可為層間介電層(interlayer dielectric layer)。在介電層202為層間介電層的實施例中，該介電層202通常將下方的導電層206與即將配置在該介電層202上方的導電層或導電特徵(圖中未圖示出)隔開。
在某些實施例中，介電層202可包含碳且可進一步為多孔性。合適的介電材料實例包括摻雜碳之氧化矽 (SiOC)、氮碳化矽(SiCN)、低介電常數材料或諸如此類者。該低介電常數材料可為摻雜碳之介電材料(例如，購自美國加州聖塔克拉拉市之應用材料公司的BLACK DIAMOND®介電材料或諸如此類材料)、有機聚合物(例如，聚醯亞胺、聚對二甲苯(parylene)或諸如此類聚合物)、有機摻雜矽玻璃(OSG)，等等。
在某些實施例中，該導電層206可由任何適合用於例如製造積體電路或其他半導體元件的導電材料所製成。在某些實施例中，導電層206可由金屬製成，例如由銅、鋁或諸如此類金屬、此等金屬之合金或組合物所製成。
在某些實施例中，基板200可具有一或多個配置在基板中或配置在基板上的特徵。例如，在某些實施例中且如第2A圖所示，可提供貫穿該層間介電層202的開孔208，藉以暴露硬遮罩204的上表面。通常藉由一或多個側壁210和底表面212界定該開孔208。開孔208可為任何適用於基板製造的特徵，舉例言之，例如介層窗、溝渠、雙鑲嵌特徵或諸如此類特徵，且可藉由任何適當製程(例如，蝕刻製程)形成該開孔208。雖然第2A圖至第2E圖中僅圖示出一個開孔208，但該基板中可同時出現多個特徵。開孔208通常可具有任意尺寸。例如，在某些實施例中，開孔208可具有至少約2：1的特徵高度與特徵寬度之比例。在某些實施例中，開孔208可具有高的高寬比之特徵。在此等實施例中，開孔208可具有至少約4：1的特徵高度與特徵寬度之比例。在某些實施 例中，開孔208可具有約5 nm至約50 nm的寬度。
可藉由習知方法形成該開孔，例如可藉由圖案化並蝕刻該介電層202以形成開孔208。於步驟102提供該基板之前，亦可在基板200上執行其他製程。例如，可執行化學機械研磨(CMP)製程以使介電層202的上表面平坦。CMP製程或該開孔208之蝕刻步驟任一者或兩者皆可能不當地去除介電層202中的碳(例如可能具有碳空乏效應)而導致介電層202之介電常數或k值不當地升高。此外，諸如清洗基板等其他製程亦可能導致介電層202之介電常數或k值不當地升高。
接著於步驟104中，如第2B圖所示般在基板200頂部沉積共形氧化物層214。在某些實施例中，共形氧化物層214可能包含氧化矽(SiO2)、摻雜碳之氧化物(SiOC)或諸如此類者。共形氧化物層214可具有相對高的k值(例如，層214之k值可高於下方介電層202之k值)，例如約為4或介於約2.8至約3.4之範圍內。在某些實施例中，共形氧化物層214具有小於約100Å之厚度，例如具有小於約50Å或約20Å至約40Å之厚度。可利用任何合適之方法沉積該共形氧化物層214，該方法例如化學氣相沉積法(CVD)、電漿增強原子層沉積法(PEALD)或諸如此類方法。亦可利用其他製程形成該共形氧化物層。共形氧化物層214可形成在介電層202之表面上方，包括形成在該開孔208之側壁210和底表面212上。共形氧化物層214有利於去除使用低介電常數材料塗覆該介 電層202的需要。
在某些實施例中，可使用PEALD製程沉積共形氧化物層214，從而提供高共形性，且允許精確控制該共形氧化物層之厚度，精確控制厚度有助於達到該介電層202之最低可能積分k值。例如，在某些實施例中，PEALD製程可先使基板200暴露於一或多種含有前驅物蒸汽的製程氣體中。該前驅物蒸汽可為有機矽化合物，例如，八甲基環四矽氧烷([(CH3)2SiO-]4)、甲基二乙氧基矽烷(C5H14O2Si)或諸如此類化合物。將該前驅物蒸汽連同氦氣一同沖洗至CVD腔室(圖中未圖示出)中的基板上。該前驅物流率可為例如約1克/分鐘至約8克/分鐘，且氦氣流率可為例如約400 sccm至約2000 sccm。可利用具有13.56 MHz頻率之20 W至約100 W的射頻(RF)功率使該前驅物氣體形成電漿。隨後利用淨化氣體清洗該CVD腔室，該淨化氣體係例如惰性氣體，例如，氦氣。在某些實施例中，該淨化氣體可與含碳氣體組合，該含碳氣體係例如甲烷(CH4)、乙烯(C2H4)、乙烷(C2H6)或丙烷(C3H8)之其中一或多者。該惰性氣體流率可為例如約400 sccm至約2000 sccm。該含碳氣體流率可為約0 sccm至約4000 sccm。於該清洗步驟之後接著使用惰性氣體(例如氦氣)或氧化性氣體(oxidizing gas，例如氧氣)進行RF電漿處理。該惰性氣體流率可為例如約400 sccm至約2000 sccm。該氧化性器體流率可為例如約0 sccm至1000 sccm。該製程腔室之清洗期間可使用頻率為13.56 MHz 之200 W至約1000 W的高頻RF功率。在某些實施例中，該製程腔室之清洗期間可使用頻率約200 kHz至約400 kHz且最高約150 W的低頻RF功率。最後，再次使用惰性氣體(例如氦氣或氬氣)沖洗該CVD腔室。該惰性氣體流率可為例如約400 sccm至約2000 sccm。在某些實施例中，可以相同順序重複上述步驟以達到期望的膜厚。可例如在約2托耳(Torr)至約8托耳之腔室壓力及約150℃至約400℃(例如約200℃至約300℃)之溫度下執行該PEALD製程。
接著，在步驟106中，可如第2C圖所示般在電漿摻雜腔室內使用碳對該共形氧化物層214進行摻雜。該碳電漿摻雜製程將基板200暴露於含碳之電漿222下，藉以將碳原子佈植或摻雜至該基板200的暴露表面(例如佈植或摻雜至共形氧化物層214，及隨意地佈植或摻雜至配置於該共形氧化物層214下方的其他層)。可在任何適當之製程腔室中執行該碳電漿摻雜製程，該製程腔室係例如，但不限於，可購自美國加州聖塔克拉拉市之應用材料公司(Applied Materials,Inc.,of Santa Clara,California)的電漿離子浸入式佈植反應器。在同樣受讓予本發明之受讓人的美國專利第7,166,524號中說明此適用之反應器及該反應器之操作方法。該碳電漿摻雜製程產生恢復該低介電常數介電層202中之碳的有利結果，且進一步提供碳給該共形氧化物層214。
參閱第3圖，適合執行碳電漿摻雜製程之例示性環形 源電漿浸入式離子佈植(「P3i」)反應器300可包含圓筒狀真空腔室302，該腔室302係由圓筒狀側壁304及碟狀頂壁306界定而成。位於該腔室之底板處的基板支撐基座308支撐著欲接受處理之基板310。位在頂壁306上之氣體分配板或噴淋頭312的氣體歧管314接收來自氣體分配面板316的製程氣體，該氣體分配面板316輸出的氣體可為來自一或多個各別氣體供應器318之任一種氣體或氣體混合物。泵送環孔322界定在基板支撐基座308與側壁304之間，且真空幫浦320耦接至該泵送環孔322。處理區域324係界定在基板310與氣體分配板312之間。
一對外部重入導管326、328建立重入環狀路徑以供電漿流行經該處理區域324，該等環狀路徑在該處理區域324內相交。該等導管326、328各自具有一對末端330，該等末端330耦接至該腔室的相反兩側。導管326、328各為中空導電管。導管326、328各自具有直流(D.C.)絕緣環332，直流絕緣環332係用以防止在該導管的兩末端之間形成封閉迴路式導電路徑。
環狀磁性核334環繞著導管326、328各自之環狀部位。環繞著磁性核334的激發線圈336係透過阻抗匹配器340而耦接至射頻(RF)電源338。各自與該等線圈336之其中一者耦接的該兩個射頻電源338可採用兩種稍有不同的頻率。由該等射頻功率產生器338耦接而來的射頻功率在延伸穿過各別導管326、328及穿過處理區域 324的封閉環狀路徑中產生電漿離子流。這些離子流以該各自之射頻電源338的頻率振蕩。利用偏壓功率產生器342透過阻抗匹配電路344對該基板支撐基座308施加偏壓功率。在某些實施例中，所提供的偏壓功率高達約5000 W且可具有例如約2 MHz之頻率。該偏壓功率可用以驅趕碳進入該一或多個特徵的平坦表面和側表面中。例如，可利用施加於基板表面的能量大小(例如，利用偏壓功率控制)有利地控制該介電層202及該共形氧化物層中的碳含量深度及碳含量之分佈輪廓。
藉由氣體分配板312將製程氣體或多種製程氣體之混合物導入該腔室324中且由射頻電源338施加足夠的源功率給該等重入導管326、328而進行電漿生成反應，藉以在該等導管中和該處理區域324內建立環形電漿流。例如，該源功率可高達約1000 W且頻率為約2 MHz至約50 MHz以供形成電漿。在某些實施例中，在該偏壓射頻啟動之後可使該源功率降至0。可控制該源功率以提供期望之電漿密度或離子通量。離子通量係取決於射頻功率；射頻功率越高，得到的離子通量或電漿密度越大。與源功率相較之下，該偏壓功率越高，碳量出現在共形氧化物層214中的越深處。相較於該偏壓功率而言，該源功率越高，越多的碳將出現在共形氧化物層214的表面處。
該製程氣體包括含碳氣體，例如具有低碳數的碳氫化合物(carbon hydride)。例如，該含碳氣體可包含甲烷 (CH4)、乙烯(C2H4)、乙烷(C2H6)或丙烷(C3H8)之其中一或多者。可加入惰性氣體(例如，氦氣或氬氣)以稀釋該含碳氣體。控制該含碳氣體的稀釋有利於幫助控制該共形氧化物層214和介電層202中的碳分佈輪廓。在某些實施例中，可使用碳對該共形氧化物層214進行摻雜，藉以在該共形氧化物層214中達到約25原子百分比至約40原子百分比之碳濃度。該等含碳氣體提供含碳離子，可將含碳離子植入該共形氧化物層214中深達某一厚度(例如約100Å)且具有相當高的濃度。由於該電漿浸入製程的緣故，使得第一部分(例如約50Å)具有最高的碳濃度及相對平緩的碳分佈輪廓。藉著添加稀釋氣體可使電漿中具有較低的含碳氣體分壓，在電漿中提供較低的含碳氣體分壓能提供深度稍深的高度集中(highly concentrated)之碳層。
利用射頻偏壓功率產生器342施加晶圓偏壓電壓以決定靠近晶圓表面處的離子通量。可利用該射頻源功率產生器338所施加的射頻功率大小控制該電漿密度，並藉由電漿密度決定該電漿流率或通量(每秒從每平方公分之晶圓表面所取樣到的離子數目)。藉由該電漿通量及該電漿通量持續的總時間兩者可決定在該晶圓310處的累計離子劑量(離子/平方公分)。
若晶圓支撐基座308為靜電吸盤，則在該晶圓支撐基座之絕緣板348內部設置有埋入式電極346，且該埋入式電極346經由阻抗匹配電路344耦接至偏壓功率產生 器342。透過控制該吸盤可控制晶圓溫度使該晶圓溫度介於約5℃至約100℃。若使用經加熱之靜電吸盤，可將基板溫度控制在約80℃至約800℃間，或約25℃至約350℃間。
操作時，例如可將該基板310放置在基板支撐基座308上，並將一或多種製程氣體導入該腔室302中以點燃該等製程氣體而生成電漿。在某些實施例中，可在該反應器300內部使用該等製程氣體產生電漿，藉以如上述般選擇性地修飾基板310之表面。依據上述製程，藉著由該等產生器338施加足夠的源功率給該等重入導管326、328以在該等導管326、328內及在該處理區域324內建立電漿離子流，而在該處理區域324中形成電漿。在某些實施例中，可調整該射頻偏壓功率產生器342所輸送的晶圓偏壓電壓，藉以控制流向該晶圓表面的離子通量，且進而可能控制下列一或多者：在該晶圓上所生成之層厚度或嵌入晶圓表面中之電漿物種濃度。
接著，在步驟108中，如第2D圖所示，從開孔208中去除共形氧化物層。可利用任何合適之製程(例如，蝕刻法)去除該共形氧化物層。
在某些實施例中，例如在該一或多個特徵是介層窗以在基板200上之導電特徵之間提供接觸的實施例中，接著於步驟110中，使用導電材料220填充該開孔208。在某些實施例中，如第2E圖所示般，亦可在開孔208內沉積阻障層216和晶種層218。阻障層216可沉積在 基板200頂部上。若有阻障層時，阻障層216可作為該基板與後續沉積於該開孔中之層之間的電性及/或物理性阻障層，及/或可於下述沉積製程期間作為可供附著的表面，此阻障層216作為可供附著的表面係優於基板之原生表面。阻障層216可包含任何適於執行上述功能的材料。例如，在某些實施例中，阻障層216可包含鈦(Ti)、鉭(Ta)、鈦(Ti)或鉭(Ta)之氧化物或氮化物，或諸如此類者。阻障層216可沉積達任何適當厚度，例如約0.5 nm至約10 nm。可利用任何合適之方法沉積該阻障層216，該方法係例如化學氣相沉積法(CVD)、物理氣相沉積法(PVD)或諸如此類之方法。
晶種層218可沉積在開孔208中。晶種層218提供可供附著之較佳表面且可作為後續沉積材料(例如下述導電材料)的模板。晶種層218可包含任何適於提供上述功能的材料。例如，在某些實施例中，該晶種層可包含下述之一者：銅(Cu)、釕(Ru)、鈷(Co)或諸如此類金屬及此等金屬之合金，例如銅鋁合金(Cu-Al)、銅錳合金(Cu-Mn)、銅鎂合金(Cu-Mg)或諸如此類之合金。可藉由任何適於形成具有期望分佈輪廓之晶種層的沉積製程以沉積晶種層218，舉例言之，該合適之沉積製程係例如PVD、CVD、ALD、PEALD或諸如此類者。
導電材料220可沉積於晶種層218頂部上以填充開孔208。在晶種層218非形成連續層(圖中未圖示出)的實施例中，可將多個部份的導電材料220直接沉積在阻障層 216頂部上。可採任意方法(例如，電化學沉積法或電化學電鍍法或諸如此類者)沉積導電材料220。導電材料220可為任何合適之導電材料，例如鋁(Al)、銅(Cu)或諸如此類之材料。
使用導電材料220填充開孔208之後，可利用化學機械研磨法(CMP)或其他合適技術去除位在該開孔208(及任何其他特徵，例如其他介層窗、溝渠、雙鑲嵌結構或諸如此類者)外部的多餘導電材料220。沉積導電材料220以填充開孔208之後，該方法通常終止於此，且基板200可進行進一步處理，例如沉積、蝕刻、退火或諸如此類處理。在某些實施例中，可沉積附加層，例如沉積附加之介電層，及/或在該已填充之開孔208上形成的金屬化結構。
因此，本案提供利用碳電漿浸入以修復低介電常數材料的方法。雖然上述內容提到本發明之多個具體實施例，但在不偏離本發明基本範圍下當可作出本發明之其他及進一步之實施例。
100‧‧‧方法
102、104、106、108、110‧‧‧步驟
200‧‧‧基板
202‧‧‧低介電常數介電層
204‧‧‧硬遮罩
206‧‧‧導電層
208‧‧‧開孔
210‧‧‧側壁
212‧‧‧底表面
214‧‧‧共形氧化物層
216‧‧‧阻障層
218‧‧‧晶種層
220‧‧‧導電材料
222‧‧‧電漿
300‧‧‧製程腔室/反應器
302‧‧‧圓筒狀真空腔室
304‧‧‧圓筒狀側壁
306‧‧‧頂壁
308‧‧‧支撐基座
310‧‧‧基板/晶圓
312‧‧‧氣體分配板/噴淋頭
314‧‧‧氣體歧管
316‧‧‧氣體分配面板
318‧‧‧氣體供應器
320‧‧‧真空幫浦
322‧‧‧泵送環孔
324‧‧‧處理區域/腔室
326、328‧‧‧重入導管
330‧‧‧末端
332‧‧‧直流絕緣環
334‧‧‧環狀磁性核
336‧‧‧激發線圈
338‧‧‧射頻電源/射頻功率產生器
340‧‧‧阻抗匹配器
342‧‧‧偏壓功率產生器
344‧‧‧阻抗匹配電路
346‧‧‧埋入式電極
348‧‧‧絕緣板
藉由參照附圖中所繪之例示性本發明實施例，可理解上述概要整理和更詳細論述之本發明實施例。然而應注意，該等附圖僅圖示本發明之代表性實施例，且因此該等附圖不應視為本發明範圍之限制，本發明可允許做出 其他等效實施例。
第1圖係根據本發明某些實施例利用碳電漿浸入法修復低介電常數材料之方法的流程圖。
第2A圖至第2E圖圖示根據本發明某些實施例於不同製造階段中的示意基板剖面圖。
第3圖圖示根據本發明某些實施例之電漿浸入式離子佈植製程腔室。
為幫助理解，盡可能使用相同元件符號標示該等圖式中共有的相同元件。該等圖式未按比例繪製且可能經過簡化以求清晰。無需進一步詳述即可思及一實施例的元件和特徵可有利地併入其他實施例中。
100‧‧‧方法
102、104、106、108、110‧‧‧步驟

Claims (15)

  1. 一種修復配置在一基板上之一介電材料的方法，且該基板具有一或多個特徵配置成貫穿該介電材料，該方法包含以下步驟：在該介電材料上和該一或多個特徵內沉積一共形氧化物層；及利用一電漿摻雜製程以碳摻雜該共形氧化物層。
  2. 如請求項1之方法，其中該共形氧化物層包含二氧化矽或摻雜碳的氧化矽。
  3. 如請求項1之方法，其中沉積該共形氧化物層之步驟進一步包含以下步驟：於一化學氣相沉積(CVD)製程或電漿增強原子層沉積製程(PEALD)中沉積該共形氧化物層，及其中該共形氧化物層之厚度為約20Å至約70Å。
  4. 如請求項1之方法，其中摻雜該共形氧化物層之步驟進一步包含以下步驟：使該基板暴露於一含碳之感應生成電漿下；及對該基板施加一偏壓電壓。
  5. 如請求項4之方法，其中摻雜該共形氧化物層之步驟 係於一電漿浸入式離子佈植反應器中執行。
  6. 如請求項4之方法，其中使該基板暴露於該感應生成電漿下的步驟包含以下步驟：提供一含碳製程氣體至一處理腔室且該處理腔室內配置有該基板，及由該製程氣體形成一電漿。
  7. 如請求項6之方法，其中該製程氣體包含至少一種含碳氣體，該至少一種含碳氣體包含甲烷(CH4)、乙烯(C2H4)、乙烷(C2H6)或丙烷(C3H8)。
  8. 如請求項6之方法，其中該製程氣體進一步包含一惰性氣體。
  9. 如請求項4之方法，其中使該基板暴露於該感應生成電漿下的步驟包含以下步驟：提供高達約1000 W且一頻率約13.56 MHZ之射頻(RF)功率以形成該電漿。
  10. 如請求項4之方法，其中摻雜該共形氧化物層之步驟進一步包含下述步驟中之至少一者：以高達約5000 W且一頻率約2 MHz之射頻功率偏壓該基板；或使該基板溫度維持在約5℃至約100℃之範圍中。
  11. 如請求項4之方法，其中摻雜該共形氧化物層之步驟進一步包含以下步驟：在該共形氧化物層中佈植約25原子%至約40原子%的碳。
  12. 如請求項1至11項任一項之方法，其中該基板進一步包含一含有該介電材料之介電層、一配置在該介電層下方的硬遮罩層及一配置在該硬遮罩層下方的導電層，且其中該一或多個特徵進一步包含一配置成貫穿該介電層及該硬遮罩層的介層窗，藉以暴露該導電層之一表面，及進一步包含以下步驟：去除該一或多個特徵之一底表面上的該共形氧化物層，藉以暴露該導電層之一部分；及使用一導電材料填充該一或多個特徵。
  13. 如請求項12之方法，其中該介電材料具有範圍介於約2.2至約2.5間的一介電常數值。
  14. 如請求項1至11項任一項之方法，該方法進一步包含以下步驟：在沉積該共形氧化物層之前，以能消耗該介電材料中之至少一些碳的方式處理該基材。
  15. 一種於媒體上儲存有多個指令之電腦可讀媒體，當執行該等指令時，能使一製程腔室執行一修復配置在一基 板上之一低介電常數材料的方法，其中該基板包含一低介電常數介電層，且該低介電常數介電層具有一或多個配置成貫穿該低介電常數介電層的特徵，該方法係如前述請求項任一項所述之方法。
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