TWI467067B - 改善間隙填充窗的銅表面電漿處理方法 - Google Patents
改善間隙填充窗的銅表面電漿處理方法 Download PDFInfo
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Description
本發明實施例大致係關於在製造半導體過程中用以處理一基材之方法,更明確地說,本發明實施例是關於在電化學沈積製程前,處理一導電晶種層的方法。
可靠地生產奈米尺寸的特徵結構是下一代半導體元件的一項關鍵技術。線路及元件尺寸縮小也對製程能力造成額外的挑戰。積體電路技術的核心-多層次內部連接,需要能精準地處理高寬深比特徵結構,例如,通孔及其他內部連接。可靠地形成這些內連線,對於未來成功以及持續提升個別基材的電路密度與品質是非常重要的。
形成於基材上之金屬化特徵結構長久以來聚焦於各式的鍍膜製程上,包括電鍍。將具有欲填充金屬之開口的基材曝露在一電解質溶液中,同時施加一電位偏壓。電解質與偏壓基材反應,而在其上沈積金屬。
最近,因為奈米尺寸的內連線技術,使銅及銅合金成為更勝於鋁的金屬選擇。相較於鋁,銅具有較低的電阻(大約1.7μΩ-cm,相較於鋁的3.1μΩ-cm)較高的電流承載量、明顯更高的電遷移阻抗。這些特徵在支援高度整合及提高元件速度所必須要有的高電流密度是非常重要的。再者,銅的熱傳導性佳且能以高純度形式取得。
第1圖為根據習知製程所處理之基材100的結構視圖。基材100具有場區102以及場區中之開口,例如溝槽104。通常填充開口以形成具有高深寬比幾何形狀的特徵結構。溝槽104進行先前技術的電鍍製程而在其中沈積金屬106,同時也沈積金屬以覆蓋場區102。先前技術的電鍍製程會在沈積於溝槽104內之填充特徵結構中產生空隙108。出現空隙108是因為當電鍍進行時,金屬沈積在場區以及靠近場區開口處側壁上的沈積速率,高於金屬沉積在溝槽底部的沈積速率。這將形成突出物,其最終將跨連過溝槽,並形成空隙以及阻礙溝槽中的金屬填充。
當電流密度增加時,通孔、穿孔、溝槽、觸點與其他開口以及其間的介電層的寬度減少到奈米的維度,但是介電層的厚度本質上維持不變。因此,這些特徵結構的深寬比通常隨著電流密度增加而增加。當深寬比超過4:1時,許多一般的沈積製程並無法用來填充奈米尺寸開口,且特別是當深寬比超過10:1時。因此,有更多的努力朝向形成大致上無空隙、奈米尺寸之高深寬比幾何形狀的特徵結構。
本發明之實施例大致係提供一種處理基材的方法,該基材之場區(field region)中具有多個開口,此方法包括沈積一導電晶種層於該基材上,在射頻功率存在下,將該導電晶種層暴露在一摻質前驅物下,以及將摻質併入至該導電晶種層內,其中在場區中具有高濃度的摻質,且在溝槽中具有低濃度的摻質。摻質可降低導電晶種層的導電率,使得隨後的電化學沈積製程在場區上沈積物質的速率低於在場該些開口處的沈積速率,造成很少或沒有空隙形成的特徵結構。較佳地,是以感應耦合(inductive coupling)的射頻功率產生電漿,雖然也可施加一弱偏壓。
本發明之實施例亦提供一種增進一基材場區中多個開口內之電鍍金屬成分的方法,包括提供一圖案化基材(其之場區中具有多個開口)至一或多個製程腔室,形成一保形阻障層於該圖案化基材上;形成一保形導電層於該保形阻障層上,以一摻質前驅物電漿處理該保形導電層,使該摻質主要被併入至該場區上之該保形導電層內,透過電鍍製程填入金屬於該場區之該些開口中,以及平坦化該基材。
以上僅為簡短概括說明,為使上述所記載本發明特徵結構之內容可詳細地被理解,可參照實施例使本發明的敘述更明確,其中某些實施例呈現在附圖中。然而,應注意的是隨後的附圖僅說明本發明之典型實施例,不應被視為本發明的限制,因為本發明能夠有其他等效的實施例。
為使容易理解,在可能的範圍內,以相同標號表示圖示中共同的相同元件。應可預期在一實施例揭露之元件可以有益地被利用在其他實施例中而無須明確的記載。
本發明實施例係一般性地提供於電鍍製程中控制基材上沈積速率的方法。將場區(field region)中具有多個欲填充金屬之開口的基材置入一或多個處理腔室中。如果需要及方便的話,在此敘述的處理或製程可以在單一腔室或多腔室中進行。若需要的話,在鍍膜處理前,可先對基材進行除氣及清洗。在基材表面上方沈積阻障層(barrier layer),隨後沈積金屬晶種層(metal seed layer)。最常用在晶種層及後續間隙填充(gap fill)之金屬為銅(Cu),但是諸如鋁或金屬合金之其他金屬也可用於間隙填充或晶種層中。在沈積晶種層之後,將基材表面暴露在使用氮氣的電漿處理中,其可為本質上純的氮或是與載送氣體(例如氬氣或氦氣)混合的氣體。選擇電漿處理條件使得基材的場區接受主要處理,而溝渠之底部及側壁僅輕微處理或根本未處理。電漿處理可選擇性地降低場區的導電率,在接續的製程中造成場區上較慢的初始沈積,而不影響場區中開口內的沈積速率。場區上較慢的初始沈積使得開口的填充速率加快,並使金屬特徵結構中有較少的空隙形成。
第2圖為根據本發明一實施例繪示之製程200的處理流程圖。在步驟202,場區(例如溝槽或空隙)中具有多個開口之基材係設置於處理腔室內之基材支撐件上。在步驟204,在基材之一表面上沈積阻障層。阻障層一般包括一能夠抑制導電物質擴散的材料。能達成此目的之一些示範性阻障材料為鉭(tantalum)、鈦(titanium)、氮化鉭(tantalum nitride)、氮化矽(silicon nitride)、氧化矽(silicon oxide)、氮氧化矽(silicon oxynitrides)、碳化矽(silicon carbide)、以及碳氧化矽(silicon oxycarbide)。可以使用任何習知的適當處理來沈積阻障層,例如物理或化學氣相沈積,或例如原子層沈積的磊晶製程,上述之全部均可利用電漿輔助(plasma-enhanced)。阻障層一般是很薄的,通常厚度介於100埃至500埃。
在步驟206中,沈積導電晶種層於阻障層上方。導電晶種層可為一金屬或金屬合金,例如銅、鋁、鎳、其混合物。它將為溝槽中的電化學沈積金屬提供導電路徑。可以利用任何習知的製程沈積導電晶種層,包括上述的製程。在一實施例中,例如,可以在氬電漿中藉由濺鍍銅靶材而沈積銅晶種層。可使用例如氦或氖之其他電漿濺鍍來形成晶種層。晶種層一般是很薄的,通常厚度介於100埃至400埃。
在步驟208,將基材進行電漿處理。電漿處理包括暴露基材至一離子化摻質前驅物(ionized dopant precursor)。在這一實施例中電漿處理所使用之物質是氮,但是依所欲之結果可以使用其他物質,例如氨(ammonia)或聯胺(hydrazine)。以如上所述之含氮化合物的電漿沈積的摻質為氮。可用以降低表面導電率之摻質,例如碳、硼、矽、鹵素,且低導電率金屬也可為摻質,例如鈦、錫或釕。
在一實施例中,較佳是以氮氣電漿使摻質主要並併入至場區上之導電晶種層表面。可以藉由提供氮氣到製程腔室、施加射頻功率至該腔室以產生一震盪電場、以及將氮氣離子化而產生氮氣電漿。腔室可維持在介於0.1至1000mTorr的壓力,以及可以使用介於約250至約2000瓦的射頻功率。雖然可以利用電容式地或感應式地方式耦接電漿,在這一實施例中並未對基材施加偏壓(bias)。在一些實施例中,一般能藉由施加射頻功率至一感應芯(氮氣可流經此)而產生氮氣電漿。圍繞感應芯之電流所生的震盪電場可將氮氣離子化,但不會在腔室內產生偏壓電位(voltage bias),雖然也可以單獨產生一微弱的電位偏壓以促使電漿更為接觸基材而非腔室硬體。電漿中的離子將向基材的場區移動,且因為沒有偏壓電位,因此一般不會穿過場區內的該些開口。藉由施加介於約5至約200瓦之間的功率到一與電極(如,嵌埋在基材支撐件內的電極)耦接的直流偏壓產生器或基材支撐件上方的氣體分配板(gas distribution plate),可產生一微弱偏壓,以驅使更多的離子靠向基材,但是也會導致基材場區中該些開口側壁上出現一些沈積。為此,若使用偏壓,較佳是使用微弱的偏壓。
在場區晶種層表面上形成一摻雜層。在使用氮氣電漿的實施例中,此摻雜層是一含氮層。5至60秒的處理將導致一單層的摻質被併入至場區上之晶種層表面。若氮為摻質,表面濃度約為2原子百分比的氮。若使用一微弱偏壓來促使更快的摻質沈積,將發生更多的摻質沈積在場區該些開口內的晶種層上。較佳是場區表面上晶種層中的摻質濃度高於場區中該些開口之底部及側壁上晶種層中的摻質濃度。併入摻質可降低受影響區域表面之導電率,在隨後的電化學沈積製程中,可減慢導電物種的初始沈積速率。在此提供的處理可減慢在電鍍過程中場區上金屬沈積的初始速率,而不影響場區中該些開口之底部及側壁上之金屬沈積速率
較佳為在暴露於電漿後隨即形成晶種層,而不在中間過程中暴露於氧氣下。暴露於氧氣將形成一氧化層表面,而阻礙隨後之摻質的吸收。若需要的話,可以藉由氦氣電漿的處理移除不想要的氧層,或是在摻質電漿處理晶種層之前,以一清洗製程中將它移除。
在步驟210中,於一電鍍製程中,以導電物質填充例如溝槽或空隙之開口。因為場區上摻雜的晶種層的導電率被所併入的摻質降低,場區上金屬的初始沈積速率將低於開口中金屬的沈積速率。因此,在場區可能形成任何會阻礙開口中沈積的突出物之前,該些開口就已經被填充了金屬。據此方法,可形成本質上無空隙之導電物質的特徵結構。在某些實施例中,導電物質可為一含有銅的金屬。在一平坦化製程中將基材平坦化而完成製程,例如化學機械研磨、電化學機械研磨、電拋光或類似方法。
第3圖為一製造流程,其繪示根據本發明另一實施例之製程300。於一製程腔室中放置一基材,然後在步驟302-306中形成阻障層及晶種層。在步驟308中,提供一摻質前驅物氣體至該製程腔室,並同時沈積導電晶種層。在步驟310中,將該前驅物氣體離子化成為電漿。在基材表面上形成導電晶種層的同時,使摻質主要被併入至場區表面。利用濺鍍所沈積的導電物質將會保形地沈積,因為它們是以中性粒子形式沈積,因此並不會被選擇性地吸引至場區;反之,帶電電漿粒子將會傾向沈積在場區上。電漿處理可與晶種層形成步驟一部分重疊,例如在晶種層步驟的最後。
在步驟312中,可施加一選擇性之微弱直流偏壓至基材支撐件上的電極或是位於基材支撐件上方的頂部電極。偏壓可以促使電漿離子較快地沈積在基材之場區上,但導致更多的離子進入開口而沈積在開口的側壁上。在此實施例中,偏壓的功率是小於約200瓦。
在步驟314中摻質被併入至基材場區上的晶種層之後,在步驟316對基材進行後處理以移除任何可能已經沈積的過量摻質。可利用熱處理將摻質揮發,或是可使用一化學或電漿蝕刻製程,或是化學或電漿清洗製程。
在步驟318中,以電鍍填充開口。改良前述步驟之場區表面可提高場區的電阻率,使得這些區域的初始鍍膜速率相較於場區中開口的初始鍍膜速率為慢。當場區上一開始只有些微鍍膜形成時,該些開口上就不會形成突出物,且開口內可被迅速地填入金屬。金屬化之後,可在步驟320中研磨基材使其表面平坦。
第4圖為本發明另一實施例之製造流程圖。製程400由步驟402之具有如上所述之場區、場區中開口、阻障層以及晶種層之基材開始。然後於步驟404將基材暴露於摻質前驅物電漿(dopant precursor plasma),以明顯地將摻質吸收進入基材之場區上的晶種層的表面。在某些實施例中,可能吸收過量的摻質。可以藉由如步驟406之步驟以移除過量的摻質,其中是以非反應性電漿濺鍍基材,例如氬氣或氦氣。藉由電漿中高能但非反應性的碰撞,電漿濺鍍造成摻質由該表面被物理性移除。移除過量的摻質後,可藉由電鍍填充場區中該些開口。如上所述,相較於場區中開口之金屬沈積初始速率,併入至場區晶種層表面的摻質可減緩金屬沈積的初始速率。電鍍製程之後,可利用任何適當的製程平坦化基材,包括上述的那些。
表1列出發明人在填充金屬前,所進行之個別晶種層表面處理製程的處理條件:
在每一例子中,藉由在表面中併入可降低導電率的摻質,因而降低了場區的初始導電率,而達成無空隙的間隙填充。
雖上述乃指本發明之實施例,然在未脫離本發明的基本範疇下是可以設計出本發明其他或更多的實施例,本發明的範疇是由隨後的申請專利範圍所決定。
100...基材
102...場區
104...溝槽
106...金屬
108...空隙
200...製程
202、204、206、208、210...步驟
300...製程
302、304、306、308、310、312、314、316、318、320...步驟
400...製程
402、404、406、408、410...步驟
第1圖為根據先前技術製程處理之基材的結構視圖;
第2圖為根據本發明一實施例之製造流程圖;
第3圖為根據本發明另一實施例之製造流程圖;及
第4圖為根據本發明另一實施例之製造流程圖。
200...製程/處理
202、204、206、208、210、212...步驟
Claims (19)
- 一種控制多個開口內的電化學沈積製程之速率的方法,該些開口係形成在一基材上之多個場區中,該方法依序包括:沈積一導電晶種層於該些開口中以及該基材之該些場區上;將該基材暴露在一含氮電漿中,以使氮被併入至該些場區上之該導電晶種層的一表面內,其中併入至該些場區上之該導電晶種層的該表面內之氮濃度高於併入至該些開口中之該導電晶種層的氮濃度;且其中該基材具有介於約5瓦至200瓦之間的一微弱偏壓;以及執行一後處理以移除過量的摻質。
- 如請求項1所述之方法,其中該含氮電漿包括一氮氣之電漿。
- 如請求項1所述之方法,其中該導電晶種層包括一金屬。
- 如請求項3所述之方法,其中該金屬包括銅。
- 一種增進多個開口內之電鍍金屬成分的方法,該些開口係形成在一基材上之多個場區中,該方法依序包括:提供一圖案化基材至一或多個處理腔室中,該圖案化基材具有多個開口,該些開口在該些場區中;形成一保形阻障層於該圖案化基材上;形成一保形導電層於該保形阻障層上;以一摻質前驅物電漿來處理該保形導電層,以使該摻質主要被併入至該些場區上之該保形導電層內,其中該基材具有介於約5瓦至200瓦之間的一微弱偏壓,且其中該摻質是以高濃度沉積在該些場區上且以低濃度沉積在該些場區中的該些開口中;執行一後處理以移除過量的摻質藉由一電鍍製程,以金屬填充該些場區中之該些開口;以及平坦化該基材。
- 如請求項5所述之方法,其中該摻質降低該基材表面上之該導電晶種層之導電率。
- 如請求項6所述之方法,其中該摻質為氮。
- 如請求項5所述之方法,其中該摻質是以一單層沈積。
- 一種以導電材料來填充一基材中之一或多個開口的方法,依序包括:在一保形沈積製程中,藉由沈積一第一導電材料將一保形導電層形成於該基材上;透過併入多個可降低導電率之成分至形成在該基材之一場區上方的該保形導電層之一表面中,來降低在該基材之該場區上方形成之該保形導電層之一部分的最初導電率,其中該基材具有介於約5瓦至200瓦之間的一微弱偏壓,且其中該些可降低導電率之成分是以高濃度沉積在該些場區上且以低濃度沉積在該些場區中的該些開口中;執行一後處理以移除過量的可降低導電率之成分;以及在一電化學製程中,以一第二導電材料來填充該一或多個開口。
- 如請求項9所述之方法,其中該併入多個可降低導電率之成分至該保形導電層之表面中的步驟包括將該基材暴露在一摻質前驅物電漿下。
- 如請求項9所述之方法,其中該併入多個可降低導電率之成分至該保形導電層之表面中的步驟包括將該基材暴露在一含氮電漿下。
- 如請求項9所述之方法,更包括移除被併入至該保形導電層之表面中之過量的該些可降低導電率之成分。
- 如請求項11所述之方法,其中該併入多個可降低導電率之成分至該保形導電層之表面中的步驟包括選擇性地沈積一摻質單層於該基材之該場區上方所形成之該保形導電層之該表面上。
- 如請求項13所述之方法,其中該選擇性地沈積該摻質單層的步驟包括提供一摻質前驅物至容置該基材的一處理腔室中,以及藉由施加一射頻功率至該摻質前驅物而形成一電漿。
- 如請求項13所述之方法,其中該摻質包含氮。
- 如請求項9所述之方法,其中該電偏壓為一直流偏壓,功率位準介於約5瓦至約200瓦間。
- 如請求項9所述之方法,其中該併入多個可降低導電率之成分至該保形導電層之表面中的步驟包括將該基材暴露在一含摻質電漿下並處理5至60秒。
- 如請求項17所述之方法,其中該電漿係藉由提供氮氣至容置有該基材之一製程腔室內以及施加一介於約250瓦至約2000瓦之射頻功率至該氮氣而產生。
- 如請求項9所述之方法,更包括形成一阻障層於該基材上。
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Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20100032644A (ko) * | 2008-09-18 | 2010-03-26 | 삼성전자주식회사 | 선택적 플라즈마 처리를 이용한 반도체 소자의 금속배선 형성방법 |
US8357599B2 (en) * | 2011-02-10 | 2013-01-22 | Applied Materials, Inc. | Seed layer passivation |
WO2017075162A1 (en) * | 2015-10-27 | 2017-05-04 | Applied Materials, Inc. | Methods for reducing copper overhang in a feature of a substrate |
CN113939896A (zh) * | 2019-06-08 | 2022-01-14 | 应用材料公司 | 具有自成型阻挡层的低k电介质 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6440854B1 (en) * | 2001-02-02 | 2002-08-27 | Novellus Systems, Inc. | Anti-agglomeration of copper seed layers in integrated circuit metalization |
TW200634982A (en) * | 2005-02-22 | 2006-10-01 | Asm Inc | Plasma pre-treating surfaces for atomic layer deposition |
US7247252B2 (en) * | 2002-06-20 | 2007-07-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of avoiding plasma arcing during RIE etching |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6136654A (en) * | 1996-06-07 | 2000-10-24 | Texas Instruments Incorporated | Method of forming thin silicon nitride or silicon oxynitride gate dielectrics |
WO1998040910A1 (en) | 1997-03-10 | 1998-09-17 | Asahi Kasei Kogyo Kabushiki Kaisha | Wiring forming method for semiconductor device and semiconductor device |
US5837598A (en) * | 1997-03-13 | 1998-11-17 | Lsi Logic Corporation | Diffusion barrier for polysilicon gate electrode of MOS device in integrated circuit structure, and method of making same |
US5969422A (en) * | 1997-05-15 | 1999-10-19 | Advanced Micro Devices, Inc. | Plated copper interconnect structure |
US6077780A (en) * | 1997-12-03 | 2000-06-20 | Advanced Micro Devices, Inc. | Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure |
US6331468B1 (en) * | 1998-05-11 | 2001-12-18 | Lsi Logic Corporation | Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers |
US6319728B1 (en) * | 1998-06-05 | 2001-11-20 | Applied Materials, Inc. | Method for treating a deposited film for resistivity reduction |
US7136173B2 (en) * | 1998-07-09 | 2006-11-14 | Acm Research, Inc. | Method and apparatus for end-point detection |
US6228754B1 (en) * | 1999-01-05 | 2001-05-08 | Advanced Micro Devices, Inc. | Method for forming semiconductor seed layers by inert gas sputter etching |
US6046108A (en) * | 1999-06-25 | 2000-04-04 | Taiwan Semiconductor Manufacturing Company | Method for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured thereby |
US8696875B2 (en) * | 1999-10-08 | 2014-04-15 | Applied Materials, Inc. | Self-ionized and inductively-coupled plasma for sputtering and resputtering |
KR100387257B1 (ko) | 1999-12-28 | 2003-06-11 | 주식회사 하이닉스반도체 | 반도체 소자의 금속배선 형성방법 |
US6605534B1 (en) * | 2000-06-28 | 2003-08-12 | International Business Machines Corporation | Selective deposition of a conductive material |
US6642146B1 (en) * | 2001-03-13 | 2003-11-04 | Novellus Systems, Inc. | Method of depositing copper seed on semiconductor substrates |
WO2002084724A1 (fr) * | 2001-04-09 | 2002-10-24 | Matsushita Electric Industrial Co., Ltd. | Procede de traitement de surface et systeme de fabrication d'un dispositif a semi-conducteur |
US6534865B1 (en) * | 2001-06-12 | 2003-03-18 | Advanced Micro Devices, Inc. | Method of enhanced fill of vias and trenches |
US7067424B2 (en) * | 2001-12-19 | 2006-06-27 | Koninklijke Philips Electronics N.V. | Method of manufacturing an electronic device |
KR100465063B1 (ko) * | 2002-04-01 | 2005-01-06 | 주식회사 하이닉스반도체 | 반도체 소자의 금속배선 형성방법 |
JP2004063556A (ja) * | 2002-07-25 | 2004-02-26 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
US7405163B1 (en) * | 2003-12-17 | 2008-07-29 | Novellus Systems, Inc. | Selectively accelerated plating of metal features |
US6727175B2 (en) * | 2002-08-02 | 2004-04-27 | Micron Technology, Inc. | Method of controlling metal formation processes using ion implantation, and system for performing same |
US6806192B2 (en) * | 2003-01-24 | 2004-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of barrier-less integration with copper alloy |
KR100546209B1 (ko) * | 2003-07-09 | 2006-01-24 | 매그나칩 반도체 유한회사 | 반도체 소자의 구리 배선 형성 방법 |
US6872657B2 (en) * | 2003-08-08 | 2005-03-29 | Agency For Science, Technology And Research | Method to form copper seed layer for copper interconnect |
US7265038B2 (en) * | 2003-11-25 | 2007-09-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming a multi-layer seed layer for improved Cu ECP |
US7235487B2 (en) * | 2004-05-13 | 2007-06-26 | International Business Machines Corporation | Metal seed layer deposition |
US7476618B2 (en) * | 2004-10-26 | 2009-01-13 | Asm Japan K.K. | Selective formation of metal layers in an integrated circuit |
KR100609049B1 (ko) | 2004-12-06 | 2006-08-09 | 주식회사 하이닉스반도체 | 반도체 소자의 금속배선 형성방법 |
US20080029400A1 (en) * | 2005-05-13 | 2008-02-07 | Stephen Mazur | Selective electroplating onto recessed surfaces |
US7387962B2 (en) * | 2005-10-17 | 2008-06-17 | Samsung Electronics Co., Ltd | Physical vapor deposition methods for forming hydrogen-stuffed trench liners for copper-based metallization |
US20080149490A1 (en) * | 2006-12-26 | 2008-06-26 | Bonhote Christian R | Electroplating on ultra-thin seed layers |
-
2008
- 2008-10-22 US US12/256,418 patent/US8764961B2/en not_active Expired - Fee Related
-
2009
- 2009-01-14 WO PCT/US2009/031002 patent/WO2009091830A2/en active Application Filing
- 2009-01-15 TW TW98101438A patent/TWI467067B/zh not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6440854B1 (en) * | 2001-02-02 | 2002-08-27 | Novellus Systems, Inc. | Anti-agglomeration of copper seed layers in integrated circuit metalization |
US7247252B2 (en) * | 2002-06-20 | 2007-07-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of avoiding plasma arcing during RIE etching |
TW200634982A (en) * | 2005-02-22 | 2006-10-01 | Asm Inc | Plasma pre-treating surfaces for atomic layer deposition |
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MM4A | Annulment or lapse of patent due to non-payment of fees |