CN113939896A - 具有自成型阻挡层的低k电介质 - Google Patents

具有自成型阻挡层的低k电介质 Download PDF

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CN113939896A
CN113939896A CN202080041895.7A CN202080041895A CN113939896A CN 113939896 A CN113939896 A CN 113939896A CN 202080041895 A CN202080041895 A CN 202080041895A CN 113939896 A CN113939896 A CN 113939896A
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dopant gas
dielectric layer
barrier layer
layer
plasma
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丁祎
S·慕克吉
B·谢
K·S·伊姆
D·帕德希
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Applied Materials Inc
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Applied Materials Inc
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Abstract

公开了一种形成具有阻挡性质的低k介电层的方法。所述方法包括通过PECVD形成掺杂有硼、氮或磷中的一者或多者的介电层。一些实施例的掺杂剂气体可在沉积期间与其他反应物共同流动。

Description

具有自成型阻挡层的低K电介质
技术领域
本公开的实施例总体涉及形成具有低介电常数的阻挡层的方法。
背景技术
在半导体领域中，防止元素由电子器件中的一种材料移动到另一种材料中已经是长期公认的问题。已经开发出扩散阻挡层以防止大原子(如金属)的扩散。
半导体中的互连结构通常含有阻挡层以防止金属扩散到电介质中。典型的互连可包含Cu/Ta/TaN/SiO2的堆叠，其中Ta/TaN层是阻挡层，在功能上防止Cu扩散到电介质中。
随着节点尺寸的减小，阻挡层制造中的增加的难度与复杂性需要新颖材料以简化互连制造工艺。当前的最先进技术工艺涉及金属阻挡层(例如，Ta/TaN)的PVD，这在较小的节点尺寸中变得越来越困难。对于较小的尺寸，需要新颖材料，所述新颖材料允许移除中间阻挡层，而不是改变金属与电介质的扩散性质。在没有中介阻挡层情况下，可能形成较小的互连。类似地，中介阻挡层的移除将简化生产方案。
因此，本领域中需要具有增加的阻挡性质的电介质材料。
发明内容
本公开的一个或多个实施例涉及用于形成介电阻挡层的方法，包含以下步骤：将其上具有金属表面的基板暴露于掺杂剂气体以在金属表面上提供掺杂剂层。掺杂剂气体包含具有III族或V族元素的原子的至少一种物质。通过将基板暴露于硅前驱物、掺杂剂气体与等离子体来沉积经掺杂介电层以形成经掺杂介电层。对经掺杂介电层进行退火以形成介电阻挡层。
本公开的附加实施例涉及用于形成介电阻挡层的方法，包含以下步骤：通过将其上具有铜表面的基板暴露于硅前驱物、掺杂剂气体与等离子体来在基板上沉积介电层以形成经掺杂介电层。掺杂剂气体包含硼原子、磷原子或氮原子中的一者或多者。在分子氮(N2)气氛中以小于约500℃的温度对经掺杂介电层进行退火达约60分钟至约120分钟范围内的时间段以形成介电阻挡层。
本公开的进一步实施例涉及用于形成介电阻挡层的方法，包含以下步骤：将其上具有铜表面的基板暴露于包含乙硼烷的掺杂剂气体以形成经处理表面。掺杂剂气体具有在约50sccm至约100sccm范围内的流率。通过将基板暴露于硅前驱物、掺杂剂气体与等离子体来在经处理表面上沉积介电层以形成经掺杂介电层。在分子氮(N2)气氛中以小于约500℃的温度对经掺杂介电层进行退火达约90分钟至约120分钟范围内的时间段以形成介电阻挡层。将介电阻挡层暴露于包含氨的处理等离子体。
附图说明
为了能够详细理解本公开的上述特征的方式，可以通过参考实施例来获得以上简要概括的本公开的更具体的描述，所述实施例中的一些实施例在附图中图示。然而，应注意，附图仅图示本公开的典型实施例，并且因此不应被认为是对本公开范围的限制，因为本公开可允许其他等效实施例。
图1是根据本公开的一个或多个实施例的形成介电层的方法的流程图；
图2图示根据本公开的一个或多个实施例的示例电子器件；以及
图3图示根据本公开的一个或多个实施例的群集工具。
具体实施方式
在描述本公开的若干示例性实施例之前，应理解，本公开并不限于以下描述中阐述的架构或处理步骤的细节。本公开能够有其他实施例并且可以以各种方式实践或执行。
如本说明书与所附权利要求中所使用的，术语“基板”是指表面或表面的部分，在所述表面或表面的部分上进行处理。本领域技术人员也将理解，对基板的引用可也仅指基板的一部分，除非在上下文中另有明确指示。此外，对在基板上沉积的引用可意指在裸基板与具有沉积或形成在其上的一个或多个膜或特征的基板两者。
如本文中所使用的“基板”是指在制造处理期间在其上执行膜处理的任何基板或形成在基板上的材料表面。例如，可在其上执行处理的基板表面包括材料，诸如硅、氧化硅、应变硅、绝缘体上硅(SOI)、碳掺杂氧化硅、非晶硅、掺杂硅、锗、砷化镓、玻璃、蓝宝石、以及任何其他材料，诸如金属、金属氮化物、金属合金、以及其他导电材料，这取决于应用。基板包括但不限于半导体晶片。基板可暴露于预处理工艺以抛光、蚀刻、还原、氧化、羟基化、退火、UV固化、电子束固化和/或烘烤基板表面。除了直接在基板表面本身上进行的膜处理之外，在本公开中，如下文更详细公开的，所公开的膜处理步骤中的任一者也可在形成在基板上的底层(underlayer)上执行，并且术语“基板表面”旨在包括如上下文所指示的这种底层。因此，例如，在膜/层或部分膜/层已沉积到基板表面上的位置处，新沉积的膜/层的暴露表面成为基板表面。
本公开的一些实施例涉及用于形成用作阻挡层的低k介电层的方法。本公开的一些方法有利地提供通过消除PVD步骤来简化阻挡层制造工艺的方法。本公开的一些方法有利地提供了提供用作具有高硬度与刚性的层间电介质的低k介电阻挡层的方法。
将在下文参照可使用任何合适的薄膜沉积系统执行的PECVD工艺来描述本文所述的实施例。合适的系统的示例包括可使用
Figure BDA0003394818230000031
处理腔室的
Figure BDA0003394818230000032
系统、PRECISION
Figure BDA0003394818230000033
系统、
Figure BDA0003394818230000034
系统、
Figure BDA0003394818230000035
GTTM系统、
Figure BDA0003394818230000036
XP PrecisionTM系统、
Figure BDA0003394818230000037
SETM系统、
Figure BDA0003394818230000038
处理腔室、以及MesaTM处理腔室，所有这些系统都可从加利福尼亚州圣克拉拉市的应用材料公司商购。能够执行PECVD工艺的其他工具也可适配成从本文所述的实施例获益。此外，可以有利地使用能够进行本文所述的PECVD工艺的任何系统。本文所述的设备描述是说明性的，并且不应被解释或诠释为限制本公开的范围。
参照图1和图2，在一些实施例中，形成低k介电阻挡层240的方法100开始于操作104，通过在基板210的金属表面220上沉积经掺杂介电层230。金属表面220可具有任何合适的金属种类。在一些实施例中，金属表面220的金属包含铜。
通过将基板210暴露于硅前驱物、掺杂剂气体与由等离子体气体形成的等离子体来沉积经掺杂介电层230。硅前驱物、掺杂剂气体与等离子体全部同时地暴露于基板。换言之，操作104可被称为等离子体增强化学气相沉积(PECVD)工艺。在一些实施例中，硅前驱物、掺杂剂气体与等离子体中的一者或多者可以一起共同流入处理腔室。
本公开的实施例提供低k介电阻挡层240，低k介电阻挡层240限制或防止来自金属表面220的金属扩散进入介电阻挡层240。不受理论的束缚，防止金属扩散进入介电阻挡层240消除或最小化电气短路与器件故障。
掺杂剂气体提供在经掺杂介电层230中的III族或V族元素的原子源。如本说明书中所使用的，III族元素选自周期表中以硼(B)起始的栏，而V族元素选自以氮(N)起始的栏。
在一些实施例中，掺杂剂气体包含硼(B)、磷(P)或氮(N)中的一者或多者。在一些实施例中，掺杂剂气体包含硼原子。在一些实施例中，掺杂剂气体包含乙硼烷(B2H6)或基本上由乙硼烷(B2H6)组成。在一些实施例中，掺杂剂气体包含磷原子。在一些实施例中，掺杂剂气体包含膦(PH3)或基本上由膦(PH3)组成。在一些实施例中，掺杂剂气体包含氮原子。在一些实施例中，掺杂剂气体包含分子氮(N2)、氨(NH3)、二氧化氮(NO2)、一氧化氮(NO)、以及一氧化二氮(N2O)中的一者或多者。在一些实施例中，掺杂剂气体基本上由氮(N2)、氨、NO2、或N2O组成。在此使用时，术语“基本上由…组成”意指排除任何载体或稀释气体，在摩尔基础上掺杂剂气体由大于或等于约95％、大于或等于约98％、大于或等于约99％、或大于或等于约99.5％的掺杂剂气体组成。
掺杂剂气体可以以任何合适的流率供应至处理腔室。在一些实施例中，掺杂剂气体以相对低的流率供应。在一些实施例中，掺杂剂气体以高达约500sccm的流率流动。在一些实施例中，掺杂剂气体以在约10sccm至约500sccm、约20sccm至约200sccm、或约50sccm至约100sccm范围内的流率流动。
硅前驱物可以是任何合适的硅前驱物。等离子体气体可以是任何合适的等离子体气体并且用于产生任何合适的等离子体。在一些实施例中，稀释或载体气体也与硅前驱物、等离子体气体或掺杂剂气体中的一者或多者一起提供。在一些实施例中，硅前驱物包含碳，而等离子体气体包含氧。在这些实施例中，经掺杂介电层230可包含经掺杂碳氧化硅(SiOC)层。本领域技术人员将认识到使用诸如SiOC之类的化学式来描述薄膜材料并不暗示任何特定的原子化学计量比。化学式仅提供对构成膜的主要成分(即，膜的大于90％、95％、98％、99％或99.5％)的原子的标识。
可控制经掺杂介电层230的沉积速率。在一些实施例中，经掺杂介电层的沉积速率被控制在约
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/分钟至约
Figure BDA0003394818230000052
/分钟的范围内。
在控制经掺杂介电层230的沉积速率时，还可控制经掺杂介电层230与介电阻挡层240的厚度。在一些实施例中，经掺杂介电层和/或介电阻挡层的厚度在约150nm至300nm的范围内。在一些实施例中，经掺杂介电层和/或介电阻挡层的厚度小于或等于约300nm、小于或等于约250nm、小于或等于约200nm、小于或等于约150nm、或小于或等于约100nm。
在一些实施例中，基板在暴露于硅前驱物与等离子体之前暴露于掺杂剂气体。再次参照图1与图2，方法100可以可选地开始于操作102，通过将包括金属表面220的基板210暴露于掺杂剂气体。换言之，在沉积经掺杂介电层230之前，基板210可浸泡在掺杂剂气体中。
方法100在操作106处继续，通过对经掺杂介电层230进行退火以形成介电阻挡层240。在一些实施例中，经掺杂介电层在包含分子氮(N2)的气氛中退火。
在一些实施例中，操作106处的退火工艺可被描述为低温退火。在一些实施例中，经掺杂介电层230在小于或等于约500℃、小于或等于约450℃、小于或等于约400℃、或小于或等于约350℃的温度退火。
在一些实施例中，操作106处的退火工艺可被描述为长退火。在一些实施例中，对经掺杂介电层230进行退火达约1分钟至约120分钟、约60分钟至约120分钟、或约90分钟至约120分钟范围内的时间段。在一些实施例中，对经掺杂介电层进行退火达大于或等于约1分钟、大于或等于约10分钟、大于或等于约30分钟、大于或等于约60分钟、或大于或等于约90分钟的时间段。
方法100可在106之后结束。在一些实施例中，方法100以可选操作108继续。在操作108处，介电阻挡层240可暴露于处理等离子体以改善弹性或硬度中的至少一者。在一些实施例中，处理等离子体改善介电阻挡层240的弹性。在一些实施例中，处理等离子体改善介电阻挡层240的硬度。
处理等离子体的成分与参数可根据介电阻挡层240的成分而改变。在一些实施例中，处理等离子体包含氮原子。在一些实施例中，处理等离子体包含氨或基本上由氨组成。在一些实施例中，以在约1500sccm至约2000sccm范围内的流率将氨提供至处理腔室。在一些实施例中，以约1600sccm的流率将氨提供至处理腔室。
在一些实施例中，处理等离子体具有在约250W至约500W范围内或在约350W至约450W范围内的功率。在一些实施例中，处理等离子体具有约400W的功率。
在一些实施例中，介电阻挡层暴露于处理等离子体达小于或等于约30秒、小于或等于约20秒、小于或等于约15秒、或小于或等于约10秒的时间段。
介电阻挡层240能够限制或防止来自金属表面220的金属原子扩散进入介电阻挡层。类似地，在附加层被沉积到介电阻挡层240上的情况下，介电阻挡层能够限制或防止金属原子扩散进入这些附加层。消除传统阻挡层(例如，Ta/TaN)有利地简化生产工艺流程并提供具有减小厚度的电子器件。
图2图示通过方法100的处理期间的示例性基板210。参照图1与图2，方法100开始于具有金属表面220的基板210。在操作104处，经掺杂介电层230被沉积在金属表面220上。在操作106处，对经掺杂介电层230进行退火以形成介电阻挡层240。
在一些实施例中，操作104与操作106(以及可选地，操作102与操作108)在群集工具中被群集在一起。在一些实施例中，在连续操作之间不破坏真空的情况下执行操作104和操作106和可选的操作102和操作108。在一些实施例中，操作102、操作104、操作106与操作108在单个处理环境内执行。
本公开的附加实施例涉及用于本文所述的方法的处理工具，如图3所示。群集工具900包括至少一个中央传送站921、931，中央传送站921、931具有多个侧面。机器人925、935定位在中央传送站921、931内并且被配置成将机械叶片和晶片移动至多个侧面中的每一者。
群集工具900包含连接至中央传送站921、931的多个处理腔室902、904、906、908、910、912、914、916和918，也被称为处理站。各种处理腔室提供与相邻处理腔室隔离的单独处理区域。处理腔室可为任何合适腔室，包括但不限于，预清洗腔室、缓冲腔室、(多个)传送空间、晶片定向/除气腔室、低温冷却腔室、沉积腔室、退火腔室、蚀刻腔室、热处理(RTP)腔室、等离子体处理腔室、原子层沉积(ALD)腔室。处理腔室与部件的具体布置可根据群集工具而改变并且不应视为限制本公开的范围。
在一个或多个实施例中，群集工具900包括沉积腔室以沉积经掺杂介电层230。一些实施例的沉积腔室包含PECVD沉积腔室。在一个或多个实施例中，群集工具900包括连接至中央传送站的浸泡腔室。
在图3所示的实施例中，工厂界面950连接至群集工具900的前部。工厂界面950包括在工厂界面950的前部951上的装载腔室954与卸载腔室956。虽然装载腔室954示出在左边而卸载腔室956示出在右边，但本领域技术人员将理解这仅表示一种可能的配置。
装载腔室954与卸载腔室956的尺寸与形状可根据例如在群集工具900中处理的基板而改变。在所示出的实施例中，装载腔室954与卸载腔室956被尺寸设计为固持晶片盒，所述晶片盒具有定位在盒内的多个晶片。
机器人952在工厂界面950内并且可在装载腔室954与卸载腔室956之间移动。机器人952能够将晶片从装载腔室954中的盒中通过工厂界面950传送至负载锁定腔室960。机器人952也能够将晶片从负载锁定腔室962通过工厂界面950传送至卸载腔室956中的盒。如本领域技术人员将理解的，工厂界面950可具有多于一个机器人952。例如，工厂界面950可具有第一机器人与第二机器人，第一机器人在装载腔室954与负载锁定腔室960之间传送晶片，而第二机器人在负载锁定腔室962与卸载腔室956之间传送晶片。
群集工具900示出为具有第一区段920与第二区段930。第一区段920通过负载锁定腔室960、962连接至工厂界面950。第一区段920包括第一传送腔室921，第一传送腔室921具有定位在其中的至少一个机器人925。机器人925也被称为机器人晶片传送机构。第一传送腔室921相对于负载锁定腔室960、962、处理腔室902、904、916、918、以及缓冲腔室922、924居中定位。一些实施例的机器人925是能够一次独立地移动多于一个晶片的多臂机器人。在一个或多个实施例中，第一传送腔室921包含多于一个机器人晶片传送机构。第一传送腔室921中的机器人925配置成在围绕第一传送腔室921的腔室之间移动晶片。各个晶片被承载在晶片传送叶片上，晶片传送叶片位在第一机器人机构的远端。
在第一区段920中处理晶片之后，晶片可通过穿通(pass-through)腔室被传递至第二区段930。例如，腔室922、924可为单向或双向穿通腔室。穿通腔室922、924可例如用于在第二区段930中进行处理之前低温冷却晶片，或允许在移动回到第一区段920之前进行晶片冷却或后处理。
系统控制器990与第一机器人925、第二机器人935、第一多个处理腔室902、904、916、918以及第二多个处理腔室906、908、910、912、914通信。系统控制器990可以是可控制处理腔室与机器人的任何合适部件。例如，系统控制器990可以是包括中央处理单元、存储器、合适的电路与存储的计算机。
工艺通常可作为软件例程存储在系统控制器990的存储器中，当由处理器执行时使处理腔室执行本公开的工艺。软件例程也可由远离处理器所控制的硬件定位的第二处理器(未示出)来存储和/或执行。本公开的方法中的一些或全部也可在硬件中执行。因此，工艺可实现在软件中并使用计算机系统在硬件中执行，作为例如专用集成电路或其他类型的硬件实现，或作为软件与硬件的组合。软件例程在由处理器执行时将通用计算机转变成控制腔室操作的专用计算机(控制器)，使得工艺被执行。
为了便于描述，在本文中可使用诸如“之下”、“下方”、“下部”、“上方”、“上部”等的空间相关术语来描述如附图所图示的一个要素或特征相对于另一个(多个)要素或特征的关系。将理解，空间相对术语旨在涵盖除了附图中描绘的定向之外的使用或操作中的装置的不同定向。例如，如果附图中的装置被翻转，则被描述为在其他要素或特征“下方”或“之下”的要素将随后被定向为在其他要素或特征“上方”。因此，示例性术语“下方”可涵盖上方与下方的定向两者。装置可以以其他方式定向(旋转90度或处于其他定向)并且本文使用的空间相关描述符也被相应地诠释。
在描述本文讨论的材料与方法的上下文中(尤其是在以下权利要求书的上下文中)使用术语“一(a)”和“一个(an)”和“所述”以及类似称谓旨在解释为涵盖单数和复数两者，除非在本文中另外说明或明显与上下文矛盾。本文的值的范围的记载仅旨在记载用作单独引用落在该范围内的每一单独值的速记方法，除非在本文中另外说明，并且每一单独值被结合到本说明书中，好比它在本文中单独记载的一样。本文描述的所有方法可以以任何合适顺序执行，除非在本文中另外说明或明显与上下文矛盾。使用本文所提供的任何和所有示例或示例性语言(例如，“诸如”)仅旨在更好地阐明材料与方法，而不施加对范围施加限制，除非另外要求。本说明书中的语言不应被解释为指示任何未被要求保护的要素对于所公开的材料与方法的实践是必要的。
贯穿本说明书，对“一个实施例”、“某些实施例”、“一个或多个实施例”、或“实施例”的引用意指结合此实施例描述的特定特征、结构、材料或特性被包括在本公开的至少一个实施例中。因此，贯穿本说明书在各个地方出现的诸如“在一个或多个实施例中”、“在某些实施例中”、“在一个实施例中”、或“在实施例中”之类的短语不一定是指本公开的同一实施例。在一个或多个实施例中，特定特征、结构、材料、或特性以任何合适方式组合。
虽然已参照特定实施例描述了本文的公开，但应理解，这些实施例仅是对本公开的原理与应用的说明。对于本领域技术人员将显而易见的是，在不背离本公开的精神与范围的情况下，可对本公开的方法与设备做出各种修改和变化。因此，本公开旨在包括在所附权利要求书与其等效物的范围内的修改与变化。

Claims (20)

1.一种用于形成介电阻挡层的方法，包含以下步骤：
将其上具有金属表面的基板暴露于掺杂剂气体，以在所述金属表面上提供掺杂剂层，所述掺杂剂气体包含具有III族或V族元素的原子的至少一种物质；
通过将所述基板暴露于硅前驱物、所述掺杂剂气体与等离子体来沉积经掺杂介电层以形成经掺杂介电层；以及
对所述经掺杂介电层进行退火以形成介电阻挡层。
2.如权利要求1所述的方法，其中所述金属表面是铜表面。
3.如权利要求1所述的方法，其中所述掺杂剂气体以高达约500sccm的流率流动。
4.如权利要求1所述的方法，其中所述掺杂剂气体包含硼原子。
5.如权利要求4所述的方法，其中所述掺杂剂气体基本上由乙硼烷组成。
6.如权利要求1所述的方法，其中所述掺杂剂气体包含磷原子。
7.如权利要求6所述的方法，其中所述掺杂剂气体基本上由膦组成。
8.如权利要求1所述的方法，其中所述掺杂剂气体包含氮原子。
9.如权利要求8所述的方法，其中所述掺杂剂气体包含氮(N2)、氨、NO2与N2O中的一者或多者。
10.如权利要求1所述的方法，其中通过利用包含碳的硅前驱物与包含氧的等离子体气体的等离子体增强化学气相沉积工艺来执行沉积所述经掺杂介电层。
11.如权利要求10所述的方法，其中所述经掺杂介电层包含经掺杂SiOC层。
12.如权利要求1所述的方法，其中在包含N2的气氛中执行对所述经掺杂介电层进行退火。
13.如权利要求1所述的方法，其中在小于约500℃的温度对所述经掺杂介电层进行退火。
14.如权利要求1所述的方法，其中对所述经掺杂介电层进行退火达在约1分钟至约120分钟范围内的时间段。
15.如权利要求1所述的方法，进一步包含将所述介电阻挡层暴露于处理等离子体以改善弹性与硬度中的至少一者。
16.如权利要求15所述的方法，其中所述处理等离子体包含氨。
17.如权利要求15所述的方法，其中所述处理等离子体具有在约250W至约500W范围内的功率，并且将所述介电阻挡层暴露达小于或等于约20秒。
18.一种用于形成介电阻挡层的方法，包含以下步骤：
通过将其上具有铜表面的基板暴露于硅前驱物、掺杂剂气体与等离子体来在所述基板上沉积介电层以形成经掺杂介电层，所述掺杂剂气体包含硼原子、磷原子或氮原子中的一者或多者；以及
在氮(N2)气氛中以小于约500℃的温度对所述经掺杂介电层进行退火达在约60分钟至约120分钟范围内的时间段以形成介电阻挡层。
19.如权利要求18所述的方法，进一步包含将所述介电阻挡层暴露于包含氨的处理等离子体以改善弹性与硬度中的至少一者。
20.一种用于形成介电阻挡层的方法，包含以下步骤：
将其上具有铜表面的基板暴露于包含乙硼烷的掺杂剂气体以形成经处理表面，所述掺杂剂气体具有在约50sccm至约100sccm范围内的流率；
通过将所述基板暴露于硅前驱物、所述掺杂剂气体与等离子体来在所述经处理表面上沉积介电层以形成经掺杂介电层；以及
在氮(N2)气氛中以小于约500℃的温度对所述经掺杂介电层进行退火达在约90分钟至约120分钟范围内的时间段以形成介电阻挡层；以及
将所述介电阻挡层暴露于包含氨的处理等离子体。
CN202080041895.7A 2019-06-08 2020-06-08 具有自成型阻挡层的低k电介质 Pending CN113939896A (zh)

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