TW554477B - Method for improving filling metal in deep trench - Google Patents

Abstract

A type of method for improving filling metal in deep trench is disclosed, which comprises performing a sputtering process on a copper seed layer and a metal barrier layer on the side wall of a deep trench, in which the deep trench is in the dielectric layer and above the substrate; placing the test wafer in a pre-sputtering reaction chamber and performing two alternating steps: a sputter deposition step and a sputter etching step, in which the reaction chamber proceeds the sputter etching step when the operation powder is low to prevent arcing issue on the surface of the test wafer, and proceeds a sputter deposition step when the operation powder is high to incur effective bombardment on the target and to prevent any plasma damage from occurring; making the copper seed layer and the barrier layer homogeneously covering the side wall of the deep trench, so that there is no void present in the subsequent process of filling metal into the deep trench.

Description

554477 V. Description of the invention (1) 5-1 Field of invention: The present invention relates to a method for forming a deep trench, and more particularly to a method for improving the filling of a metal layer into a deep trench. 5-2 Background of the Invention: In high-density integrated circuits, there are many problems with the use of copper interconnect structures. For example, in the oxide layer and the silicon layer, the copper metal has a high degree of diffusion even at room temperature. If copper diffuses from the interconnect structure to electronic components in the active area, these electronic components cannot be operated. Therefore, it is necessary to protect the electronic components in the interconnect structure. In the standard process copper interconnect structure, such as titanium nitride (TiN), group (tantalum, Ta), nitride group (tantalum nitride (TaN), and nitride nitride (WN), etc.) It acts as a barrier layer to prevent copper from diffusing into metal wires. However, this is a challenging task. In terms of the current device structure, in general, the metal barrier layer deposition process provides non-uniform coverage of the dual damascene structure. In addition, the diffusion characteristics of the metal barrier layer in the dual damascene structure of the aspect ratio must be higher than the standard of the device performance. Copper interconnects can be used in microelectronic circuits. However, the other

554477 V. Description of the invention (2) One problem is electromigration (EM). Electromigration will reduce the effectiveness of the entire copper interconnect, for example, voids in the interconnect will increase. Therefore, copper interconnects have more problems. The resistance of electromigration of copper interconnects is related to the structure of copper interconnects. Referring to the first figure, the step of forming a deep trench 14 0 on the substrate 100 is shown. A dielectric layer 120 is deposited on the substrate 1000. Next, a photoresist layer having a trench pattern is deposited, exposed, and developed on the dielectric layer 120 by a conventional lithography technique. Then, a | worming step is performed on the dielectric layer 120 to form a deep trench structure 140 in the dielectric layer 120. The second and second pictures of Cang Kaodi are used as the barrier nitride (tantalum nitride, TaN) of 160. The physical vapor deposition method (physica 1 va ρ 〇 rd ρ 〇 siti ο η, PVD) is deposited on the sidewalls of the trench trench 140 by a sputtering deposition method, and then a conductive seed layer 180 such as a copper seed layer is borrowed. A physical vapor deposition (PVD) is deposited on the barrier layer i60. The nitride button and metallic copper (conductor crystal layer) cannot provide a uniformly covered barrier / conductor crystal layer. This will result in the formation of pores 2 2 0 in the deep trenches 1 40 having an aspect ratio when the metal layer 2 4 is filled in, and back-end-of- line (BE0L) inlaying process is unable to achieve satisfactory quality. And this void 2 2 0 is formed in gold

554477 V. Description of the invention (3) The problem of electromigration will also be caused in the ditch 1 40. 5-3 Purpose and Summary of the Invention: The main object of the present invention is to provide a sputtering etching step in a sputtering reaction chamber to form a uniform covering layer on the side wall of a deep trench. Another object of the present invention is to improve the problem of pores caused by metal filling in deep trenches. In one embodiment, a barrier layer and a copper crystal layer are sequentially deposited on the sidewall of the deep trench. In order to prevent the pores from occurring in the subsequent filling process of the metal layer, the test piece is placed in a pre-sputtering reaction chamber, and there are two alternative processes in the reaction chamber: deposition process and etching process. When the operating power in the reaction is higher than 500 watts, a sputtering deposition process is performed in the reaction chamber. In addition, when the power in the reaction chamber is less than 200 watts, a sputtering etching process is performed in the reaction chamber. At this power, an effective impact will be formed on the test piece and the non-uniformly deposited barrier layer will be etched away. Copper crystal layer, and there will not be any problem of plasma damage. Therefore, the copper crystal layer and the barrier layer can form a uniform coverage on the sidewall of the deep trench, and there will be no pores in the subsequent process of metal filling the trench.

554477 V. Description of the invention (4) 5-4 Detailed description of the invention: Some embodiments of the present invention will be described in detail as follows. However, in addition to the detailed description, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited, which is subject to the scope of subsequent patents. After the present invention provides a method, after the barrier layer / conductor crystal layer deposition process, an additional sputtering etching process is added to obtain a more uniformly covered barrier layer / conductor crystal layer to improve the metal filling ability and metal reliability. Sexual effectiveness. Referring to the fourth figure, the formation steps of the deep trenches 14 on the substrate 10 are shown. A dielectric layer 12 is formed on the substrate 10. Next, a photoresist layer having a deep trench pattern is deposited, exposed, and developed on the dielectric layer 12 by a conventional lithography process. Next, a #etching step is performed on the dielectric layer 12 so that a deep trench structure 14 is formed in the dielectric layer 12. Referring to the fifth figure, the test piece is placed in a pre-sputtering reaction chamber. In general, the most commonly used materials for the barrier layer 16 include titanium / titanium nitride (T i / Ti N), iron nitride (WN), group (T a), and nitride group (T a N) . The reason why the barrier layer 16 is used is to increase the mechanical strength and adhesion of the subsequently deposited conductor, and to prevent the metal conductor material from diffusing into the dielectric layer 12. Then, a conductor nucleus layer 18 is deposited on the barrier layer 16 by a physical vapor deposition method, and then an electrochemical deposition method is used to deposit the

Page 7 554477

V. Description of the invention (5) Deposit a metal layer 24 (shown in the sixth figure). The pre-sputtering reaction chamber is usually used for sputtering etching, and the power at the time of sufficient engraving is less than 2000 watts. In general, when the operating power of the reaction chamber is less than 200 watts, an in-plane sputtering step is performed in the reaction chamber. In this example, when the deposition is performed in a sputtering reaction chamber, the operating power in the counter-attack is less than 200 watts. With this operating power, the discharge effect on the surface of the test piece can be ... And when it is less than 200 watts, no discharge will occur on the surface of the test piece. However, when the operation layer 16 and the copper crystal layer 18 are deposited in a deep trench, the shape of the conformal barrier can not be formed, and there will be a step coverage (step c0vera & 2), and the subsequent metal layer is filled in. In deep trenches, voids are formed at the same time. In order to solve the above-mentioned shortcomings, in the $ f channel. The middle system will use the appropriate operating power to make the plasma with positive electricity. For example, due to the increase in the power supply difference between the plasma and the electrode plate, the ionized ion accelerates and bombards the wafer surface, and the non-uniformly covered ^ w positive 18 is a uniformly covered copper crystal layer. 1 8. '@ 晶 层 Therefore, in order to avoid the problem of step coverage (stepcoverage) created when the metal is filled in the subsequent steps, the reaction

554477 V. Description of the invention (6) Barrier layer 16. However, operating at this power will produce effective bombardment on the test strip without causing any problems of plasma damage. Therefore, by using these two alternate steps of sputtering etching and sputtering deposition under different powers, the metal core layer 18 and the barrier layer 16 can be uniformly covered on the side wall of the deep trench. In the subsequent metal filling process, there will be no formation of pores as in the traditional technology, and a complete and reliable semiconductor device will be obtained. Next, referring to FIG. 6 and FIG. 7, a metal layer 24 is deposited by an electrochemical vapor deposition method to fill the deep trenches 14. Then, chemical mechanical polishing is used to remove the excess metal layer 2 4, so that a metal plug 24 is formed in the deep trench 14. According to the above description, in order to avoid the problem of voids caused by metal filling into deep trenches, the test piece is placed in a pre-sputtering reaction, and the deposited copper crystal layer and the resistance are adjusted by the sputtering etching adjustment. The barrier layer can evenly cover the side wall of the deep trench, so that when the subsequent metal layer is filled in, the thickness of the deep trench will not cause the problem of step coverage and voids will be generated. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

Page 9 554477 The diagram is a simple illustration. The first diagram is based on the traditional technology and illustrates the unintended application of the dielectric layer in the mosaic structure. The second diagram is the intention when the metal layer is filled in the deep trench according to the traditional technology The third diagram is a schematic diagram of the structure of forming a deep trench with pores according to the traditional technology; the fourth diagram is a schematic diagram illustrating the application of a dielectric layer in a surface-embedded structure according to the technology disclosed in the present invention; the fifth diagram is According to the technology disclosed in the present invention, a schematic diagram of forming a non-uniformly covered metal layer by performing a sputtering step after depositing a barrier layer and a metal crystal layer is illustrated. The sixth figure is based on the technology disclosed in the present invention, and illustrates sputtering. A schematic diagram when a uniformly-covered copper crystal layer and a metal layer are filled into a deep trench after etching; and the seventh figure is a schematic diagram of forming a deep trench structure according to the technology disclosed in the present invention. Representative symbols of the main parts:

Page 554477 Simple illustration of the drawing 10 substrate 1 2 dielectric layer 1 4 deep trench 1 6 barrier layer 1 8 conductor crystal layer 2 0 sputtering etching step 24 metal layer 1 0 0 substrate 1 2 0 dielectric layer 1 4 0 Deep trench 1 6 0 Barrier layer 1 8 0 Metal crystal layer 2 2 0 Pore 2 4 0 Metal layer

Claims (1)

554477 6. Scope of patent application 1. A method for forming a conformal layer in a trench, the method at least comprises: providing a substrate having a trench; forming a poor stepped cover layer in the trench; and etching the bad The method of covering the steps to form the conformal layer and covering the steps in the trench is its method. ^ —I-layer barrier barrier Fan Yili Contains special package Please apply less to layer 2 cover 3. If the method of the second item of the patent application, the method further includes a conductor crystal layer on the barrier layer. 4. The method according to item 3 of the patent application, wherein the method for etching the defective step cover layer includes at least a sputtering etching method. 5. The method according to item 4 of the patent application, wherein the power of the sputtering etch is lower than about 200 watts. 6. A method for improving the filling of a metal layer into a deep trench, the method at least comprising: providing a substrate having a deep trench, a barrier layer on a side wall of the deep trench, and a conductive crystal layer on the barrier layer Engraving the conductor crystal layer; filling a metal layer in the deep trench; and grinding the metal layer to remove the excess metal layer on the substrate. Page 12 554477 VI. Application for Patent Scope 7. The method according to item 6 of the patent application scope, wherein the above method for depositing the core layer of the conductor includes at least a physical vapor deposition method. 8. The method according to item 7 of the patent application, wherein the material of the conductor crystal layer includes at least metallic copper. 9. The method according to item 8 of the scope of patent application, wherein the method for etching the conductive crystal layer includes at least a base ore carving method. 10. The method according to item 9 of the scope of patent application, wherein the power of the above-mentioned sputtering etching is lower than about 200 watts. 1 1. The method according to item 6 of the patent application, wherein the material of the metal layer includes at least metal copper. The shaped channel has a layer of dielectric M which can be lifted. It contains as little as the bottom of the material. • A structural barrier. • The channel resistance is deep. The layer is deep in the electrical layer. Layers of resistive electro-sinking photophase—the Yuduo top material of the gas-etched etched Jinhaikou—should go to the inner channel to the depth of the groove, which belongs to the gold •铜 金 械 此 一 机 刻 积 学 # 沈 化 与 以 Page 13 554477 6. Scope of patent application 1 3. The method according to item 12 of the scope of patent application, wherein the etching of the copper crystal layer includes at least one remaining step of inferior ore. 14. The method according to item 13 of the scope of patent application, wherein the power of the sputtering etching step is lower than about 200 watts. 15. The method according to item 12 of the scope of patent application, wherein the material of the metal layer includes at least metal copper. Page 14